drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2
   5  *
   6  *  Copyright (C) 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/mach/flash.h>
  38 #include <asm/arch/gpmc.h>
  39 #include <asm/arch/onenand.h>
  40 #include <asm/arch/gpio.h>
  41 #include <asm/arch/gpmc.h>
  42 #include <asm/arch/pm.h>
  43
  44 #include <linux/dma-mapping.h>
  45 #include <asm/dma-mapping.h>
  46 #include <asm/arch/dma.h>
  47
  48 #include <asm/arch/board.h>
  49
  50 #define ONENAND_IO_SIZE         SZ_128K
  51 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  52
  53 struct omap2_onenand {
  54         struct platform_device *pdev;
  55         int gpmc_cs;
  56         unsigned long phys_base;
  57         int gpio_irq;
  58         struct mtd_info mtd;
  59         struct mtd_partition *parts;
  60         struct onenand_chip onenand;
  61         struct completion irq_done;
  62         struct completion dma_done;
  63         int dma_channel;
  64         int freq;
  65         int (*setup)(void __iomem *base, int freq);
  66 };
  67
  68 static unsigned short omap2_onenand_readw(void __iomem *addr)
  69 {
  70         return readw(addr);
  71 }
  72
  73 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
  74 {
  75         writew(value, addr);
  76 }
  77
  78 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  79 {
  80         struct omap2_onenand *info = data;
  81
  82         complete(&info->dma_done);
  83 }
  84
  85 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  86 {
  87         struct omap2_onenand *info = dev_id;
  88
  89         complete(&info->irq_done);
  90
  91         return IRQ_HANDLED;
  92 }
  93
  94 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
  95 {
  96         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
  97         unsigned int interrupt = 0;
  98         unsigned int ctrl;
  99         unsigned long timeout;
 100         u32 syscfg;
 101
 102         if (state == FL_RESETING) {
 103                 int i;
 104
 105                 for (i = 0; i < 20; i++) {
 106                         udelay(1);
 107                         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 108                         if (interrupt & ONENAND_INT_MASTER)
 109                                 break;
 110                 }
 111                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 112                 if (ctrl & ONENAND_CTRL_ERROR) {
 113                         printk(KERN_ERR "onenand_wait: reset error! ctrl 0x%04x intr 0x%04x\n", ctrl, interrupt);
 114                         return -EIO;
 115                 }
 116                 if (!(interrupt & ONENAND_INT_RESET)) {
 117                         printk(KERN_ERR "onenand_wait: reset timeout! ctrl 0x%04x intr 0x%04x\n", ctrl, interrupt);
 118                         return -EIO;
 119                 }
 120                 return 0;
 121         }
 122
 123         if (state != FL_READING) {
 124                 int result;
 125                 /* Turn interrupts on */
 126                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 127                 syscfg |= ONENAND_SYS_CFG1_IOBE;
 128                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 129
 130                 INIT_COMPLETION(info->irq_done);
 131                 if (info->gpio_irq) {
 132                         result = omap_get_gpio_datain(info->gpio_irq);
 133                         if (result == -1) {
 134                                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 135                                 printk(KERN_ERR "onenand_wait: gpio error, state = %d, ctrl = 0x%04x\n", state, ctrl);
 136                                 return -EIO;
 137                         }
 138                 } else {
 139                         result = 0;
 140                 }
 141                 if (result == 0) {
 142                         int retry_cnt = 0;
 143 retry:
 144                         result = wait_for_completion_timeout(&info->irq_done,
 145                                                     msecs_to_jiffies(20));
 146                         if (result == 0) {
 147                                 /* Timeout after 20ms */
 148                                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 149                                 if (ctrl & ONENAND_CTRL_ONGO) {
 150                                         /* The operation seems to be still going - so give it some more time */
 151                                         retry_cnt += 1;
 152                                         if (retry_cnt < 3)
 153                                                 goto retry;
 154                                         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 155                                         printk(KERN_ERR "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 156                                         return -EIO;
 157                                 }
 158                                 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 159                                 if ((interrupt & ONENAND_INT_MASTER) == 0)
 160                                         printk(KERN_WARNING "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 161                         }
 162                 }
 163         } else {
 164                 /* Turn interrupts off */
 165                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 166                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 167                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 168
 169                 timeout = jiffies + msecs_to_jiffies(20);
 170                 while (time_before(jiffies, timeout)) {
 171                         if (omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT) &
 172                             ONENAND_INT_MASTER)
 173                                 break;
 174                 }
 175         }
 176
 177         /* To get correct interrupt status in timeout case */
 178         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 179         ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 180
 181         if (ctrl & ONENAND_CTRL_ERROR) {
 182                 printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl);
 183                 if (ctrl & ONENAND_CTRL_LOCK)
 184                         printk(KERN_ERR "onenand_erase: Device is write protected!!!\n");
 185                 return -EIO;
 186         }
 187
 188         if (ctrl & 0xFE9F)
 189                 printk(KERN_WARNING "onenand_wait: unexpected controller status = 0x%04x  state = %d  interrupt = 0x%04x\n", ctrl, state, interrupt);
 190
 191         if (interrupt & ONENAND_INT_READ) {
 192                 int ecc = omap2_onenand_readw(info->onenand.base + ONENAND_REG_ECC_STATUS);
 193                 if (ecc) {
 194                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 195                                 printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
 196                                 mtd->ecc_stats.failed++;
 197                                 return -EBADMSG;
 198                         } else if (ecc & ONENAND_ECC_1BIT_ALL)
 199                                 printk(KERN_NOTICE "onenand_wait: correctable ECC error = 0x%04x\n", ecc);
 200                                 mtd->ecc_stats.corrected++;
 201                 }
 202         } else if (state == FL_READING) {
 203                 printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
 204                 return -EIO;
 205         }
 206
 207         return 0;
 208 }
 209
 210 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 211 {
 212         struct onenand_chip *this = mtd->priv;
 213
 214         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 215                 if (area == ONENAND_DATARAM)
 216                         return mtd->writesize;
 217                 if (area == ONENAND_SPARERAM)
 218                         return mtd->oobsize;
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 225                                         unsigned char *buffer, int offset,
 226                                         size_t count)
 227 {
 228         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 229         struct onenand_chip *this = mtd->priv;
 230         dma_addr_t dma_src, dma_dst;
 231         int bram_offset;
 232
 233         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 234         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 235             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 236             (count < 1024) || (count & 3)) {
 237                 memcpy(buffer, (void *)(this->base + bram_offset), count);
 238                 return 0;
 239         }
 240
 241         dma_src = info->phys_base + bram_offset;
 242         dma_dst = dma_map_single(&info->pdev->dev, buffer, count, DMA_FROM_DEVICE);
 243         if (dma_mapping_error(dma_dst)) {
 244                 dev_err(&info->pdev->dev,
 245                         "Couldn't DMA map a %d byte buffer\n",
 246                         count);
 247                 return -1;
 248         }
 249
 250         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 251                                      count / 4, 1, 0, 0, 0);
 252         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 253                                 dma_src, 0, 0);
 254         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 255                                  dma_dst, 0, 0);
 256
 257         INIT_COMPLETION(info->dma_done);
 258         omap2_block_sleep();
 259         omap_start_dma(info->dma_channel);
 260         wait_for_completion(&info->dma_done);
 261         omap2_allow_sleep();
 262
 263         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 264
 265         return 0;
 266 }
 267
 268 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 269                                          const unsigned char *buffer, int offset,
 270                                          size_t count)
 271 {
 272         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 273         struct onenand_chip *this = mtd->priv;
 274         dma_addr_t dma_src, dma_dst;
 275         int bram_offset;
 276
 277         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 278         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 279             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 280             (count < 1024) || (count & 3)) {
 281                 memcpy((void *)(this->base + bram_offset), buffer, count);
 282                 return 0;
 283         }
 284
 285         dma_src = dma_map_single(&info->pdev->dev, (void *) buffer, count,
 286                                  DMA_TO_DEVICE);
 287         dma_dst = info->phys_base + bram_offset;
 288         if (dma_mapping_error(dma_dst)) {
 289                 dev_err(&info->pdev->dev,
 290                         "Couldn't DMA map a %d byte buffer\n",
 291                         count);
 292                 return -1;
 293         }
 294
 295         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 296                                      count / 2, 1, 0, 0, 0);
 297         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 298                                 dma_src, 0, 0);
 299         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 300                                  dma_dst, 0, 0);
 301
 302         INIT_COMPLETION(info->dma_done);
 303         omap_start_dma(info->dma_channel);
 304         wait_for_completion(&info->dma_done);
 305
 306         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 307
 308         return 0;
 309 }
 310
 311 static struct platform_driver omap2_onenand_driver;
 312
 313 static int __adjust_timing(struct device *dev, void *data)
 314 {
 315         int ret = 0;
 316         struct omap2_onenand *info;
 317
 318         info = dev_get_drvdata(dev);
 319
 320         BUG_ON(info->setup == NULL);
 321
 322         /* DMA is not in use so this is all that is needed */
 323         ret = info->setup(info->onenand.base, info->freq);
 324
 325         return ret;
 326 }
 327
 328 int omap2_onenand_rephase(void)
 329 {
 330         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
 331                                       NULL, __adjust_timing);
 332 }
 333
 334 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
 335 {
 336         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 337
 338         /* With certain content in the buffer RAM, the OMAP boot ROM code
 339          * can recognize the flash chip incorrectly. Zero it out before
 340          * soft reset.
 341          */
 342         memset(info->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 343 }
 344
 345 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 346 {
 347         struct omap_onenand_platform_data *pdata;
 348         struct omap2_onenand *info;
 349         int r;
 350
 351         pdata = pdev->dev.platform_data;
 352         if (pdata == NULL) {
 353                 dev_err(&pdev->dev, "platform data missing\n");
 354                 return -ENODEV;
 355         }
 356
 357         info = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 358         if (!info)
 359                 return -ENOMEM;
 360
 361         init_completion(&info->irq_done);
 362         init_completion(&info->dma_done);
 363         info->gpmc_cs = pdata->cs;
 364         info->gpio_irq = pdata->gpio_irq;
 365         info->dma_channel = pdata->dma_channel;
 366         if (info->dma_channel < 0) {
 367                 /* if -1, don't use DMA */
 368                 info->gpio_irq = 0;
 369         }
 370
 371         r = gpmc_cs_request(info->gpmc_cs, ONENAND_IO_SIZE, &info->phys_base);
 372         if (r < 0) {
 373                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 374                 goto err_kfree;
 375         }
 376
 377         if (request_mem_region(info->phys_base, ONENAND_IO_SIZE,
 378                                pdev->dev.driver->name) == NULL) {
 379                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
 380                         info->phys_base, ONENAND_IO_SIZE);
 381                 r = -EBUSY;
 382                 goto err_free_cs;
 383         }
 384         info->onenand.base = ioremap(info->phys_base, ONENAND_IO_SIZE);
 385         if (info->onenand.base == NULL) {
 386                 r = -ENOMEM;
 387                 goto err_release_mem_region;
 388         }
 389
 390         if (pdata->onenand_setup != NULL) {
 391                 r = pdata->onenand_setup(info->onenand.base, info->freq);
 392                 if (r < 0) {
 393                         dev_err(&pdev->dev, "Onenand platform setup failed: %d\n", r);
 394                         goto err_iounmap;
 395                 }
 396                 info->setup = pdata->onenand_setup;
 397         }
 398
 399         if (info->gpio_irq) {
 400                 if ((r = omap_request_gpio(info->gpio_irq)) < 0) {
 401                         dev_err(&pdev->dev,  "Failed to request GPIO%d for OneNAND\n",
 402                                 info->gpio_irq);
 403                         goto err_iounmap;
 404         }
 405         omap_set_gpio_direction(info->gpio_irq, 1);
 406
 407         if ((r = request_irq(OMAP_GPIO_IRQ(info->gpio_irq),
 408                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 409                              pdev->dev.driver->name, info)) < 0)
 410                 goto err_release_gpio;
 411         }
 412
 413         if (info->dma_channel >= 0) {
 414                 r = omap_request_dma(0, pdev->dev.driver->name,
 415                                      omap2_onenand_dma_cb, (void *) info,
 416                                      &info->dma_channel);
 417                 if (r == 0) {
 418                         omap_set_dma_write_mode(info->dma_channel, OMAP_DMA_WRITE_NON_POSTED);
 419                         omap_set_dma_src_data_pack(info->dma_channel, 1);
 420                         omap_set_dma_src_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 421                         omap_set_dma_dest_data_pack(info->dma_channel, 1);
 422                         omap_set_dma_dest_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 423                 } else {
 424                         dev_info(&pdev->dev,
 425                                  "failed to allocate DMA for OneNAND, using PIO instead\n");
 426                         info->dma_channel = -1;
 427                 }
 428         }
 429
 430         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual base %p\n",
 431                  info->gpmc_cs, info->phys_base, info->onenand.base);
 432
 433         info->pdev = pdev;
 434         info->mtd.name = pdev->dev.bus_id;
 435         info->mtd.priv = &info->onenand;
 436         info->mtd.owner = THIS_MODULE;
 437
 438         if (info->dma_channel >= 0) {
 439                 info->onenand.wait = omap2_onenand_wait;
 440                 info->onenand.read_bufferram = omap2_onenand_read_bufferram;
 441                 info->onenand.write_bufferram = omap2_onenand_write_bufferram;
 442         }
 443
 444         if ((r = onenand_scan(&info->mtd, 1)) < 0)
 445                 goto err_release_dma;
 446
 447         switch ((info->onenand.version_id >> 4) & 0xf) {
 448         case 0:
 449                 info->freq = 40;
 450                 break;
 451         case 1:
 452                 info->freq = 54;
 453                 break;
 454         case 2:
 455                 info->freq = 66;
 456                 break;
 457         case 3:
 458                 info->freq = 83;
 459                 break;
 460         }
 461
 462 #ifdef CONFIG_MTD_PARTITIONS
 463         if (pdata->parts != NULL)
 464                 r = add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
 465         else
 466 #endif
 467                 r = add_mtd_device(&info->mtd);
 468         if (r < 0)
 469                 goto err_release_onenand;
 470
 471         platform_set_drvdata(pdev, info);
 472
 473         return 0;
 474
 475 err_release_onenand:
 476         onenand_release(&info->mtd);
 477 err_release_dma:
 478         if (info->dma_channel != -1)
 479                 omap_free_dma(info->dma_channel);
 480         if (info->gpio_irq)
 481                 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 482 err_release_gpio:
 483         if (info->gpio_irq)
 484                 omap_free_gpio(info->gpio_irq);
 485 err_iounmap:
 486         iounmap(info->onenand.base);
 487 err_release_mem_region:
 488         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 489 err_free_cs:
 490         gpmc_cs_free(info->gpmc_cs);
 491 err_kfree:
 492         kfree(info);
 493
 494         return r;
 495 }
 496
 497 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 498 {
 499         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 500
 501         BUG_ON(info == NULL);
 502
 503 #ifdef CONFIG_MTD_PARTITIONS
 504         if (info->parts)
 505                 del_mtd_partitions(&info->mtd);
 506         else
 507                 del_mtd_device(&info->mtd);
 508 #else
 509         del_mtd_device(&info->mtd);
 510 #endif
 511
 512         onenand_release(&info->mtd);
 513         if (info->dma_channel != -1)
 514                 omap_free_dma(info->dma_channel);
 515         omap2_onenand_shutdown(pdev);
 516         platform_set_drvdata(pdev, NULL);
 517         if (info->gpio_irq) {
 518                 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 519                 omap_free_gpio(info->gpio_irq);
 520         }
 521         iounmap(info->onenand.base);
 522         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 523         kfree(info);
 524
 525         return 0;
 526 }
 527
 528 static struct platform_driver omap2_onenand_driver = {
 529         .probe          = omap2_onenand_probe,
 530         .remove         = omap2_onenand_remove,
 531         .shutdown       = omap2_onenand_shutdown,
 532         .driver         = {
 533                 .name   = "omap2-onenand",
 534                 .owner  = THIS_MODULE,
 535         },
 536 };
 537
 538 MODULE_ALIAS(DRIVER_NAME);
 539
 540 static int __init omap2_onenand_init(void)
 541 {
 542         printk(KERN_INFO "OMAP2 OneNAND driver initializing\n");
 543         return platform_driver_register(&omap2_onenand_driver);
 544 }
 545
 546 static void __exit omap2_onenand_exit(void)
 547 {
 548         platform_driver_unregister(&omap2_onenand_driver);
 549 }
 550
 551 module_init(omap2_onenand_init);
 552 module_exit(omap2_onenand_exit);
 553
 554 MODULE_LICENSE("GPL");
 555 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 556 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2");