drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2 / OMAP3
   5  *
   6  *  Copyright (C) 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/mach/flash.h>
  38 #include <mach/gpmc.h>
  39 #include <mach/onenand.h>
  40 #include <mach/gpio.h>
  41 #include <mach/gpmc.h>
  42 #include <mach/pm.h>
  43
  44 #include <linux/dma-mapping.h>
  45 #include <asm/dma-mapping.h>
  46 #include <mach/dma.h>
  47
  48 #include <mach/board.h>
  49
  50 #define DRIVER_NAME "omap2-onenand"
  51
  52 #define ONENAND_IO_SIZE         SZ_128K
  53 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  54
  55 struct omap2_onenand {
  56         struct platform_device *pdev;
  57         int gpmc_cs;
  58         unsigned long phys_base;
  59         int gpio_irq;
  60         struct mtd_info mtd;
  61         struct mtd_partition *parts;
  62         struct onenand_chip onenand;
  63         struct completion irq_done;
  64         struct completion dma_done;
  65         int dma_channel;
  66         int freq;
  67         int (*setup)(void __iomem *base, int freq);
  68 };
  69
  70 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  71 {
  72         struct omap2_onenand *c = data;
  73
  74         complete(&c->dma_done);
  75 }
  76
  77 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  78 {
  79         struct omap2_onenand *c = dev_id;
  80
  81         complete(&c->irq_done);
  82
  83         return IRQ_HANDLED;
  84 }
  85
  86 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  87 {
  88         return readw(c->onenand.base + reg);
  89 }
  90
  91 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  92                              int reg)
  93 {
  94         writew(value, c->onenand.base + reg);
  95 }
  96
  97 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
  98 {
  99         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
 100                msg, state, ctrl, intr);
 101 }
 102
 103 static void wait_warn(char *msg, int state, unsigned int ctrl,
 104                       unsigned int intr)
 105 {
 106         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
 107                "intr 0x%04x\n", msg, state, ctrl, intr);
 108 }
 109
 110 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 111 {
 112         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 113         unsigned int intr = 0;
 114         unsigned int ctrl;
 115         unsigned long timeout;
 116         u32 syscfg;
 117
 118         if (state == FL_RESETING) {
 119                 int i;
 120
 121                 for (i = 0; i < 20; i++) {
 122                         udelay(1);
 123                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 124                         if (intr & ONENAND_INT_MASTER)
 125                                 break;
 126                 }
 127                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 128                 if (ctrl & ONENAND_CTRL_ERROR) {
 129                         wait_err("controller error", state, ctrl, intr);
 130                         return -EIO;
 131                 }
 132                 if (!(intr & ONENAND_INT_RESET)) {
 133                         wait_err("timeout", state, ctrl, intr);
 134                         return -EIO;
 135                 }
 136                 return 0;
 137         }
 138
 139         if (state != FL_READING) {
 140                 int result;
 141
 142                 /* Turn interrupts on */
 143                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 144                 syscfg |= ONENAND_SYS_CFG1_IOBE;
 145                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 146
 147                 INIT_COMPLETION(c->irq_done);
 148                 if (c->gpio_irq) {
 149                         result = omap_get_gpio_datain(c->gpio_irq);
 150                         if (result == -1) {
 151                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 152                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 153                                 wait_err("gpio error", state, ctrl, intr);
 154                                 return -EIO;
 155                         }
 156                 } else
 157                         result = 0;
 158                 if (result == 0) {
 159                         int retry_cnt = 0;
 160 retry:
 161                         result = wait_for_completion_timeout(&c->irq_done,
 162                                                     msecs_to_jiffies(20));
 163                         if (result == 0) {
 164                                 /* Timeout after 20ms */
 165                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 166                                 if (ctrl & ONENAND_CTRL_ONGO) {
 167                                         /*
 168                                          * The operation seems to be still going
 169                                          * so give it some more time.
 170                                          */
 171                                         retry_cnt += 1;
 172                                         if (retry_cnt < 3)
 173                                                 goto retry;
 174                                         intr = read_reg(c,
 175                                                         ONENAND_REG_INTERRUPT);
 176                                         wait_err("timeout", state, ctrl, intr);
 177                                         return -EIO;
 178                                 }
 179                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 180                                 if ((intr & ONENAND_INT_MASTER) == 0)
 181                                         wait_warn("timeout", state, ctrl, intr);
 182                         }
 183                 }
 184         } else {
 185                 /* Turn interrupts off */
 186                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 187                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 188                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 189
 190                 timeout = jiffies + msecs_to_jiffies(20);
 191                 while (time_before(jiffies, timeout)) {
 192                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 193                         if (intr & ONENAND_INT_MASTER)
 194                                 break;
 195                 }
 196         }
 197
 198         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 199         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 200
 201         if (intr & ONENAND_INT_READ) {
 202                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 203
 204                 if (ecc) {
 205                         unsigned int addr1, addr8;
 206
 207                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 208                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 209                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 210                                 printk(KERN_ERR "onenand_wait: ECC error = "
 211                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 212                                        ecc, addr1, addr8);
 213                                 mtd->ecc_stats.failed++;
 214                                 return -EBADMSG;
 215                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 216                                 printk(KERN_NOTICE "onenand_wait: correctable "
 217                                        "ECC error = 0x%04x, addr1 %#x, "
 218                                        "addr8 %#x\n", ecc, addr1, addr8);
 219                                 mtd->ecc_stats.corrected++;
 220                         }
 221                 }
 222         } else if (state == FL_READING) {
 223                 wait_err("timeout", state, ctrl, intr);
 224                 return -EIO;
 225         }
 226
 227         if (ctrl & ONENAND_CTRL_ERROR) {
 228                 wait_err("controller error", state, ctrl, intr);
 229                 if (ctrl & ONENAND_CTRL_LOCK)
 230                         printk(KERN_ERR "onenand_wait: "
 231                                         "Device is write protected!!!\n");
 232                 return -EIO;
 233         }
 234
 235         if (ctrl & 0xFE9F)
 236                 wait_warn("unexpected controller status", state, ctrl, intr);
 237
 238         return 0;
 239 }
 240
 241 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 242 {
 243         struct onenand_chip *this = mtd->priv;
 244
 245         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 246                 if (area == ONENAND_DATARAM)
 247                         return mtd->writesize;
 248                 if (area == ONENAND_SPARERAM)
 249                         return mtd->oobsize;
 250         }
 251
 252         return 0;
 253 }
 254
 255 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
 256
 257 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 258                                         unsigned char *buffer, int offset,
 259                                         size_t count)
 260 {
 261         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 262         struct onenand_chip *this = mtd->priv;
 263         dma_addr_t dma_src, dma_dst;
 264         int bram_offset;
 265         unsigned long timeout;
 266         void *buf = (void *)buffer;
 267         size_t xtra;
 268         volatile unsigned *done;
 269
 270         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 271         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 272                 goto out_copy;
 273
 274         if (buf >= high_memory) {
 275                 struct page *p1;
 276
 277                 if (((size_t)buf & PAGE_MASK) !=
 278                     ((size_t)(buf + count - 1) & PAGE_MASK))
 279                         goto out_copy;
 280                 p1 = vmalloc_to_page(buf);
 281                 if (!p1)
 282                         goto out_copy;
 283                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 284         }
 285
 286         xtra = count & 3;
 287         if (xtra) {
 288                 count -= xtra;
 289                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 290         }
 291
 292         dma_src = c->phys_base + bram_offset;
 293         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
 294         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 295                 dev_err(&c->pdev->dev,
 296                         "Couldn't DMA map a %d byte buffer\n",
 297                         count);
 298                 goto out_copy;
 299         }
 300
 301         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 302                                      count >> 2, 1, 0, 0, 0);
 303         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 304                                 dma_src, 0, 0);
 305         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 306                                  dma_dst, 0, 0);
 307
 308         INIT_COMPLETION(c->dma_done);
 309         omap_start_dma(c->dma_channel);
 310
 311         timeout = jiffies + msecs_to_jiffies(20);
 312         done = &c->dma_done.done;
 313         while (time_before(jiffies, timeout))
 314                 if (*done)
 315                         break;
 316
 317         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 318
 319         if (!*done) {
 320                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 321                 goto out_copy;
 322         }
 323
 324         return 0;
 325
 326 out_copy:
 327         memcpy(buf, this->base + bram_offset, count);
 328         return 0;
 329 }
 330
 331 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 332                                          const unsigned char *buffer,
 333                                          int offset, size_t count)
 334 {
 335         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 336         struct onenand_chip *this = mtd->priv;
 337         dma_addr_t dma_src, dma_dst;
 338         int bram_offset;
 339         unsigned long timeout;
 340         void *buf = (void *)buffer;
 341         volatile unsigned *done;
 342
 343         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 344         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 345                 goto out_copy;
 346
 347         /* panic_write() may be in an interrupt context */
 348         if (in_interrupt())
 349                 goto out_copy;
 350
 351         if (buf >= high_memory) {
 352                 struct page *p1;
 353
 354                 if (((size_t)buf & PAGE_MASK) !=
 355                     ((size_t)(buf + count - 1) & PAGE_MASK))
 356                         goto out_copy;
 357                 p1 = vmalloc_to_page(buf);
 358                 if (!p1)
 359                         goto out_copy;
 360                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 361         }
 362
 363         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
 364         dma_dst = c->phys_base + bram_offset;
 365         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 366                 dev_err(&c->pdev->dev,
 367                         "Couldn't DMA map a %d byte buffer\n",
 368                         count);
 369                 return -1;
 370         }
 371
 372         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 373                                      count >> 2, 1, 0, 0, 0);
 374         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 375                                 dma_src, 0, 0);
 376         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 377                                  dma_dst, 0, 0);
 378
 379         INIT_COMPLETION(c->dma_done);
 380         omap_start_dma(c->dma_channel);
 381
 382         timeout = jiffies + msecs_to_jiffies(20);
 383         done = &c->dma_done.done;
 384         while (time_before(jiffies, timeout))
 385                 if (*done)
 386                         break;
 387
 388         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 389
 390         if (!*done) {
 391                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 392                 goto out_copy;
 393         }
 394
 395         return 0;
 396
 397 out_copy:
 398         memcpy(this->base + bram_offset, buf, count);
 399         return 0;
 400 }
 401
 402 #else
 403
 404 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 405                                  unsigned char *buffer, int offset,
 406                                  size_t count);
 407
 408 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 409                                   const unsigned char *buffer,
 410                                   int offset, size_t count);
 411
 412 #endif
 413
 414 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
 415
 416 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 417                                         unsigned char *buffer, int offset,
 418                                         size_t count)
 419 {
 420         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 421         struct onenand_chip *this = mtd->priv;
 422         dma_addr_t dma_src, dma_dst;
 423         int bram_offset;
 424
 425         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 426         /* DMA is not used.  Revisit PM requirements before enabling it. */
 427         if (1 || (c->dma_channel < 0) ||
 428             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 429             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 430                 memcpy(buffer, (__force void *)(this->base + bram_offset),
 431                        count);
 432                 return 0;
 433         }
 434
 435         dma_src = c->phys_base + bram_offset;
 436         dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
 437                                  DMA_FROM_DEVICE);
 438         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 439                 dev_err(&c->pdev->dev,
 440                         "Couldn't DMA map a %d byte buffer\n",
 441                         count);
 442                 return -1;
 443         }
 444
 445         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 446                                      count / 4, 1, 0, 0, 0);
 447         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 448                                 dma_src, 0, 0);
 449         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 450                                  dma_dst, 0, 0);
 451
 452         INIT_COMPLETION(c->dma_done);
 453         omap_start_dma(c->dma_channel);
 454         wait_for_completion(&c->dma_done);
 455
 456         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 457
 458         return 0;
 459 }
 460
 461 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 462                                          const unsigned char *buffer,
 463                                          int offset, size_t count)
 464 {
 465         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 466         struct onenand_chip *this = mtd->priv;
 467         dma_addr_t dma_src, dma_dst;
 468         int bram_offset;
 469
 470         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 471         /* DMA is not used.  Revisit PM requirements before enabling it. */
 472         if (1 || (c->dma_channel < 0) ||
 473             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 474             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 475                 memcpy((__force void *)(this->base + bram_offset), buffer,
 476                        count);
 477                 return 0;
 478         }
 479
 480         dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
 481                                  DMA_TO_DEVICE);
 482         dma_dst = c->phys_base + bram_offset;
 483         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 484                 dev_err(&c->pdev->dev,
 485                         "Couldn't DMA map a %d byte buffer\n",
 486                         count);
 487                 return -1;
 488         }
 489
 490         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 491                                      count / 2, 1, 0, 0, 0);
 492         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 493                                 dma_src, 0, 0);
 494         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 495                                  dma_dst, 0, 0);
 496
 497         INIT_COMPLETION(c->dma_done);
 498         omap_start_dma(c->dma_channel);
 499         wait_for_completion(&c->dma_done);
 500
 501         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 502
 503         return 0;
 504 }
 505
 506 #else
 507
 508 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 509                                  unsigned char *buffer, int offset,
 510                                  size_t count);
 511
 512 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 513                                   const unsigned char *buffer,
 514                                   int offset, size_t count);
 515
 516 #endif
 517
 518 static struct platform_driver omap2_onenand_driver;
 519
 520 static int __adjust_timing(struct device *dev, void *data)
 521 {
 522         int ret = 0;
 523         struct omap2_onenand *c;
 524
 525         c = dev_get_drvdata(dev);
 526
 527         BUG_ON(c->setup == NULL);
 528
 529         /* DMA is not in use so this is all that is needed */
 530         /* Revisit for OMAP3! */
 531         ret = c->setup(c->onenand.base, c->freq);
 532
 533         return ret;
 534 }
 535
 536 int omap2_onenand_rephase(void)
 537 {
 538         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
 539                                       NULL, __adjust_timing);
 540 }
 541
 542 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
 543 {
 544         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 545
 546         /* With certain content in the buffer RAM, the OMAP boot ROM code
 547          * can recognize the flash chip incorrectly. Zero it out before
 548          * soft reset.
 549          */
 550         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 551 }
 552
 553 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 554 {
 555         struct omap_onenand_platform_data *pdata;
 556         struct omap2_onenand *c;
 557         int r;
 558
 559         pdata = pdev->dev.platform_data;
 560         if (pdata == NULL) {
 561                 dev_err(&pdev->dev, "platform data missing\n");
 562                 return -ENODEV;
 563         }
 564
 565         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 566         if (!c)
 567                 return -ENOMEM;
 568
 569         init_completion(&c->irq_done);
 570         init_completion(&c->dma_done);
 571         c->gpmc_cs = pdata->cs;
 572         c->gpio_irq = pdata->gpio_irq;
 573         c->dma_channel = pdata->dma_channel;
 574         if (c->dma_channel < 0) {
 575                 /* if -1, don't use DMA */
 576                 c->gpio_irq = 0;
 577         }
 578
 579         r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
 580         if (r < 0) {
 581                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 582                 goto err_kfree;
 583         }
 584
 585         if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
 586                                pdev->dev.driver->name) == NULL) {
 587                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
 588                         "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
 589                 r = -EBUSY;
 590                 goto err_free_cs;
 591         }
 592         c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
 593         if (c->onenand.base == NULL) {
 594                 r = -ENOMEM;
 595                 goto err_release_mem_region;
 596         }
 597
 598         if (pdata->onenand_setup != NULL) {
 599                 r = pdata->onenand_setup(c->onenand.base, c->freq);
 600                 if (r < 0) {
 601                         dev_err(&pdev->dev, "Onenand platform setup failed: "
 602                                 "%d\n", r);
 603                         goto err_iounmap;
 604                 }
 605                 c->setup = pdata->onenand_setup;
 606         }
 607
 608         if (c->gpio_irq) {
 609                 if ((r = omap_request_gpio(c->gpio_irq)) < 0) {
 610                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 611                                 "OneNAND\n", c->gpio_irq);
 612                         goto err_iounmap;
 613         }
 614         omap_set_gpio_direction(c->gpio_irq, 1);
 615
 616         if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq),
 617                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 618                              pdev->dev.driver->name, c)) < 0)
 619                 goto err_release_gpio;
 620         }
 621
 622         if (c->dma_channel >= 0) {
 623                 r = omap_request_dma(0, pdev->dev.driver->name,
 624                                      omap2_onenand_dma_cb, (void *) c,
 625                                      &c->dma_channel);
 626                 if (r == 0) {
 627                         omap_set_dma_write_mode(c->dma_channel,
 628                                                 OMAP_DMA_WRITE_NON_POSTED);
 629                         omap_set_dma_src_data_pack(c->dma_channel, 1);
 630                         omap_set_dma_src_burst_mode(c->dma_channel,
 631                                                     OMAP_DMA_DATA_BURST_8);
 632                         omap_set_dma_dest_data_pack(c->dma_channel, 1);
 633                         omap_set_dma_dest_burst_mode(c->dma_channel,
 634                                                      OMAP_DMA_DATA_BURST_8);
 635                 } else {
 636                         dev_info(&pdev->dev,
 637                                  "failed to allocate DMA for OneNAND, "
 638                                  "using PIO instead\n");
 639                         c->dma_channel = -1;
 640                 }
 641         }
 642
 643         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
 644                  "base %p\n", c->gpmc_cs, c->phys_base,
 645                  c->onenand.base);
 646
 647         c->pdev = pdev;
 648         c->mtd.name = pdev->dev.bus_id;
 649         c->mtd.priv = &c->onenand;
 650         c->mtd.owner = THIS_MODULE;
 651
 652         if (c->dma_channel >= 0) {
 653                 struct onenand_chip *this = &c->onenand;
 654
 655                 this->wait = omap2_onenand_wait;
 656                 if (cpu_is_omap34xx()) {
 657                         this->read_bufferram = omap3_onenand_read_bufferram;
 658                         this->write_bufferram = omap3_onenand_write_bufferram;
 659                 } else {
 660                         this->read_bufferram = omap2_onenand_read_bufferram;
 661                         this->write_bufferram = omap2_onenand_write_bufferram;
 662                 }
 663         }
 664
 665         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 666                 goto err_release_dma;
 667
 668         switch ((c->onenand.version_id >> 4) & 0xf) {
 669         case 0:
 670                 c->freq = 40;
 671                 break;
 672         case 1:
 673                 c->freq = 54;
 674                 break;
 675         case 2:
 676                 c->freq = 66;
 677                 break;
 678         case 3:
 679                 c->freq = 83;
 680                 break;
 681         }
 682
 683 #ifdef CONFIG_MTD_PARTITIONS
 684         if (pdata->parts != NULL)
 685                 r = add_mtd_partitions(&c->mtd, pdata->parts,
 686                                        pdata->nr_parts);
 687         else
 688 #endif
 689                 r = add_mtd_device(&c->mtd);
 690         if (r < 0)
 691                 goto err_release_onenand;
 692
 693         platform_set_drvdata(pdev, c);
 694
 695         return 0;
 696
 697 err_release_onenand:
 698         onenand_release(&c->mtd);
 699 err_release_dma:
 700         if (c->dma_channel != -1)
 701                 omap_free_dma(c->dma_channel);
 702         if (c->gpio_irq)
 703                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
 704 err_release_gpio:
 705         if (c->gpio_irq)
 706                 omap_free_gpio(c->gpio_irq);
 707 err_iounmap:
 708         iounmap(c->onenand.base);
 709 err_release_mem_region:
 710         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 711 err_free_cs:
 712         gpmc_cs_free(c->gpmc_cs);
 713 err_kfree:
 714         kfree(c);
 715
 716         return r;
 717 }
 718
 719 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 720 {
 721         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 722
 723         BUG_ON(c == NULL);
 724
 725 #ifdef CONFIG_MTD_PARTITIONS
 726         if (c->parts)
 727                 del_mtd_partitions(&c->mtd);
 728         else
 729                 del_mtd_device(&c->mtd);
 730 #else
 731         del_mtd_device(&c->mtd);
 732 #endif
 733
 734         onenand_release(&c->mtd);
 735         if (c->dma_channel != -1)
 736                 omap_free_dma(c->dma_channel);
 737         omap2_onenand_shutdown(pdev);
 738         platform_set_drvdata(pdev, NULL);
 739         if (c->gpio_irq) {
 740                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
 741                 omap_free_gpio(c->gpio_irq);
 742         }
 743         iounmap(c->onenand.base);
 744         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 745         kfree(c);
 746
 747         return 0;
 748 }
 749
 750 static struct platform_driver omap2_onenand_driver = {
 751         .probe          = omap2_onenand_probe,
 752         .remove         = omap2_onenand_remove,
 753         .shutdown       = omap2_onenand_shutdown,
 754         .driver         = {
 755                 .name   = DRIVER_NAME,
 756                 .owner  = THIS_MODULE,
 757         },
 758 };
 759
 760 static int __init omap2_onenand_init(void)
 761 {
 762         printk(KERN_INFO "OneNAND driver initializing\n");
 763         return platform_driver_register(&omap2_onenand_driver);
 764 }
 765
 766 static void __exit omap2_onenand_exit(void)
 767 {
 768         platform_driver_unregister(&omap2_onenand_driver);
 769 }
 770
 771 module_init(omap2_onenand_init);
 772 module_exit(omap2_onenand_exit);
 773
 774 MODULE_ALIAS(DRIVER_NAME);
 775 MODULE_LICENSE("GPL");
 776 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 777 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");