drivers/mtd/nand/omap-nand-flash.c

   1 /*
   2  * drivers/mtd/nand/omap-nand-flash.c
   3  *
   4  * Copyright (c) 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   5  * Copyright (c) 2004 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/types.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/nand.h>
  20 #include <linux/mtd/partitions.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/hardware.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/mach/flash.h>
  26 #include <asm/arch/tc.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/arch/hardware.h>
  30
  31 #define DRIVER_NAME     "omapnand"
  32
  33 #ifdef CONFIG_MTD_PARTITIONS
  34 static const char *part_probes[] = { "cmdlinepart", NULL };
  35 #endif
  36
  37 struct omap_nand_info {
  38         struct nand_platform_data *pdata;
  39         struct mtd_partition    *parts;
  40         struct mtd_info         mtd;
  41         struct nand_chip        nand;
  42 };
  43
  44 /*
  45  *      hardware specific access to control-lines
  46  *      NOTE:  boards may use different bits for these!!
  47  */
  48 #define MASK_CLE        0x02
  49 #define MASK_ALE        0x04
  50 static void omap_nand_hwcontrol(struct mtd_info *mtd, int cmd)
  51 {
  52         struct nand_chip *this = mtd->priv;
  53         unsigned long IO_ADDR_W = (unsigned long) this->IO_ADDR_W;
  54
  55         switch (cmd) {
  56                 case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break;
  57                 case NAND_CTL_CLRCLE: IO_ADDR_W &= ~MASK_CLE; break;
  58                 case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break;
  59                 case NAND_CTL_CLRALE: IO_ADDR_W &= ~MASK_ALE; break;
  60         }
  61         this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
  62 }
  63
  64 static int omap_nand_dev_ready(struct mtd_info *mtd)
  65 {
  66         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd);
  67
  68         return info->pdata->dev_ready(info->pdata);
  69 }
  70
  71 static int __devinit omap_nand_probe(struct device *dev)
  72 {
  73         struct omap_nand_info           *info;
  74         struct platform_device          *pdev = to_platform_device(dev);
  75         struct nand_platform_data       *pdata = pdev->dev.platform_data;
  76         struct resource                 *res = pdev->resource;
  77         unsigned long                   size = res->end - res->start + 1;
  78         int                             err;
  79
  80         info = kmalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
  81         if (!info)
  82                 return -ENOMEM;
  83
  84         memset(info, 0, sizeof(struct omap_nand_info));
  85
  86         if (!request_mem_region(res->start, size, dev->driver->name)) {
  87                 err = -EBUSY;
  88                 goto out_free_info;
  89         }
  90
  91         info->nand.IO_ADDR_R = ioremap(res->start, size);
  92         if (!info->nand.IO_ADDR_R) {
  93                 err = -ENOMEM;
  94                 goto out_release_mem_region;
  95         }
  96         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
  97         info->nand.hwcontrol = omap_nand_hwcontrol;
  98         info->nand.eccmode = NAND_ECC_SOFT;
  99         info->nand.options = pdata->options;
 100         if (pdata->dev_ready)
 101                 info->nand.dev_ready = omap_nand_dev_ready;
 102         else
 103                 info->nand.chip_delay = 20;
 104
 105         info->mtd.name = pdev->dev.bus_id;
 106         info->mtd.priv = &info->nand;
 107
 108         info->pdata = pdata;
 109
 110         /* DIP switches on H2 and some other boards change between 8 and 16 bit
 111          * bus widths for flash.  Try the other width if the first try fails.
 112          */
 113         if (nand_scan(&info->mtd, 1)) {
 114                 info->nand.options ^= NAND_BUSWIDTH_16;
 115                 if (nand_scan(&info->mtd, 1)) {
 116                         err = -ENXIO;
 117                         goto out_iounmap;
 118                 }
 119         }
 120         info->mtd.owner = THIS_MODULE;
 121
 122 #ifdef CONFIG_MTD_PARTITIONS
 123         err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
 124         if (err > 0)
 125                 add_mtd_partitions(&info->mtd, info->parts, err);
 126         else if (err < 0 && pdata->parts)
 127                 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
 128         else
 129 #endif
 130                 add_mtd_device(&info->mtd);
 131
 132         dev_set_drvdata(&pdev->dev, info);
 133
 134         return 0;
 135
 136 out_iounmap:
 137         iounmap(info->nand.IO_ADDR_R);
 138 out_release_mem_region:
 139         release_mem_region(res->start, size);
 140 out_free_info:
 141         kfree(info);
 142
 143         return err;
 144 }
 145
 146 static int __devexit omap_nand_remove(struct device *dev)
 147 {
 148         struct platform_device *pdev = to_platform_device(dev);
 149         struct omap_nand_info *info = dev_get_drvdata(&pdev->dev);
 150
 151         dev_set_drvdata(&pdev->dev, NULL);
 152         /* Release NAND device, its internal structures and partitions */
 153         nand_release(&info->mtd);
 154         iounmap(info->nand.IO_ADDR_R);
 155         kfree(info);
 156         return 0;
 157 }
 158
 159 static struct device_driver omap_nand_driver = {
 160         .name   = DRIVER_NAME,
 161         .bus    = &platform_bus_type,
 162         .probe  = omap_nand_probe,
 163         .remove = __devexit_p(omap_nand_remove),
 164 };
 165 MODULE_ALIAS(DRIVER_NAME);
 166
 167 static int __init omap_nand_init(void)
 168 {
 169         return driver_register(&omap_nand_driver);
 170 }
 171
 172 static void __exit omap_nand_exit(void)
 173 {
 174         driver_unregister(&omap_nand_driver);
 175 }
 176
 177 module_init(omap_nand_init);
 178 module_exit(omap_nand_exit);
 179
 180 MODULE_LICENSE("GPL");
 181 MODULE_AUTHOR("Jian Zhang <jzhang@ti.com> (and others)");
 182 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
 183