drivers/mtd/nand/atmel_nand.c

   1 /*
   2  *  Copyright (C) 2003 Rick Bronson
   3  *
   4  *  Derived from drivers/mtd/nand/autcpu12.c
   5  *       Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
   6  *
   7  *  Derived from drivers/mtd/spia.c
   8  *       Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
   9  *
  10  *
  11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
  13  *
  14  *     Derived from Das U-Boot source code
  15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  16  *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  17  *
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  *
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/nand.h>
  30 #include <linux/mtd/partitions.h>
  31
  32 #include <linux/gpio.h>
  33 #include <linux/io.h>
  34
  35 #include <asm/arch/board.h>
  36
  37 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
  38 #define hard_ecc        1
  39 #else
  40 #define hard_ecc        0
  41 #endif
  42
  43 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
  44 #define no_ecc          1
  45 #else
  46 #define no_ecc          0
  47 #endif
  48
  49 /* Register access macros */
  50 #define ecc_readl(add, reg)                             \
  51         __raw_readl(add + ATMEL_ECC_##reg)
  52 #define ecc_writel(add, reg, value)                     \
  53         __raw_writel((value), add + ATMEL_ECC_##reg)
  54
  55 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  56
  57 /* oob layout for large page size
  58  * bad block info is on bytes 0 and 1
  59  * the bytes have to be consecutives to avoid
  60  * several NAND_CMD_RNDOUT during read
  61  */
  62 static struct nand_ecclayout atmel_oobinfo_large = {
  63         .eccbytes = 4,
  64         .eccpos = {60, 61, 62, 63},
  65         .oobfree = {
  66                 {2, 58}
  67         },
  68 };
  69
  70 /* oob layout for small page size
  71  * bad block info is on bytes 4 and 5
  72  * the bytes have to be consecutives to avoid
  73  * several NAND_CMD_RNDOUT during read
  74  */
  75 static struct nand_ecclayout atmel_oobinfo_small = {
  76         .eccbytes = 4,
  77         .eccpos = {0, 1, 2, 3},
  78         .oobfree = {
  79                 {6, 10}
  80         },
  81 };
  82
  83 struct atmel_nand_host {
  84         struct nand_chip        nand_chip;
  85         struct mtd_info         mtd;
  86         void __iomem            *io_base;
  87         struct atmel_nand_data  *board;
  88         struct device           *dev;
  89         void __iomem            *ecc;
  90 };
  91
  92 /*
  93  * Enable NAND.
  94  */
  95 static void atmel_nand_enable(struct atmel_nand_host *host)
  96 {
  97         if (host->board->enable_pin)
  98                 gpio_set_value(host->board->enable_pin, 0);
  99 }
 100
 101 /*
 102  * Disable NAND.
 103  */
 104 static void atmel_nand_disable(struct atmel_nand_host *host)
 105 {
 106         if (host->board->enable_pin)
 107                 gpio_set_value(host->board->enable_pin, 1);
 108 }
 109
 110 /*
 111  * Hardware specific access to control-lines
 112  */
 113 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 114 {
 115         struct nand_chip *nand_chip = mtd->priv;
 116         struct atmel_nand_host *host = nand_chip->priv;
 117
 118         if (ctrl & NAND_CTRL_CHANGE) {
 119                 if (ctrl & NAND_NCE)
 120                         atmel_nand_enable(host);
 121                 else
 122                         atmel_nand_disable(host);
 123         }
 124         if (cmd == NAND_CMD_NONE)
 125                 return;
 126
 127         if (ctrl & NAND_CLE)
 128                 writeb(cmd, host->io_base + (1 << host->board->cle));
 129         else
 130                 writeb(cmd, host->io_base + (1 << host->board->ale));
 131 }
 132
 133 /*
 134  * Read the Device Ready pin.
 135  */
 136 static int atmel_nand_device_ready(struct mtd_info *mtd)
 137 {
 138         struct nand_chip *nand_chip = mtd->priv;
 139         struct atmel_nand_host *host = nand_chip->priv;
 140
 141         return gpio_get_value(host->board->rdy_pin);
 142 }
 143
 144 /*
 145  * Minimal-overhead PIO for data access.
 146  */
 147 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 148 {
 149         struct nand_chip        *nand_chip = mtd->priv;
 150
 151         __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
 152 }
 153
 154 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
 155 {
 156         struct nand_chip        *nand_chip = mtd->priv;
 157
 158         __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
 159 }
 160
 161 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 162 {
 163         struct nand_chip        *nand_chip = mtd->priv;
 164
 165         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
 166 }
 167
 168 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
 169 {
 170         struct nand_chip        *nand_chip = mtd->priv;
 171
 172         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
 173 }
 174
 175 /*
 176  * write oob for small pages
 177  */
 178 static int atmel_nand_write_oob_512(struct mtd_info *mtd,
 179                 struct nand_chip *chip, int page)
 180 {
 181         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 182         int eccsize = chip->ecc.size, length = mtd->oobsize;
 183         int len, pos, status = 0;
 184         const uint8_t *bufpoi = chip->oob_poi;
 185
 186         pos = eccsize + chunk;
 187
 188         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
 189         len = min_t(int, length, chunk);
 190         chip->write_buf(mtd, bufpoi, len);
 191         bufpoi += len;
 192         length -= len;
 193         if (length > 0)
 194                 chip->write_buf(mtd, bufpoi, length);
 195
 196         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 197         status = chip->waitfunc(mtd, chip);
 198
 199         return status & NAND_STATUS_FAIL ? -EIO : 0;
 200
 201 }
 202
 203 /*
 204  * read oob for small pages
 205  */
 206 static int atmel_nand_read_oob_512(struct mtd_info *mtd,
 207                 struct nand_chip *chip, int page, int sndcmd)
 208 {
 209         if (sndcmd) {
 210                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 211                 sndcmd = 0;
 212         }
 213         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 214         return sndcmd;
 215 }
 216
 217 /*
 218  * Calculate HW ECC
 219  *
 220  * function called after a write
 221  *
 222  * mtd:        MTD block structure
 223  * dat:        raw data (unused)
 224  * ecc_code:   buffer for ECC
 225  */
 226 static int atmel_nand_calculate(struct mtd_info *mtd,
 227                 const u_char *dat, unsigned char *ecc_code)
 228 {
 229         struct nand_chip *nand_chip = mtd->priv;
 230         struct atmel_nand_host *host = nand_chip->priv;
 231         uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
 232         unsigned int ecc_value;
 233
 234         /* get the first 2 ECC bytes */
 235         ecc_value = ecc_readl(host->ecc, PR);
 236
 237         ecc_code[eccpos[0]] = ecc_value & 0xFF;
 238         ecc_code[eccpos[1]] = (ecc_value >> 8) & 0xFF;
 239
 240         /* get the last 2 ECC bytes */
 241         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
 242
 243         ecc_code[eccpos[2]] = ecc_value & 0xFF;
 244         ecc_code[eccpos[3]] = (ecc_value >> 8) & 0xFF;
 245
 246         return 0;
 247 }
 248
 249 /*
 250  * HW ECC read page function
 251  *
 252  * mtd:        mtd info structure
 253  * chip:       nand chip info structure
 254  * buf:        buffer to store read data
 255  */
 256 static int atmel_nand_read_page(struct mtd_info *mtd,
 257                 struct nand_chip *chip, uint8_t *buf)
 258 {
 259         int eccsize = chip->ecc.size;
 260         int eccbytes = chip->ecc.bytes;
 261         uint32_t *eccpos = chip->ecc.layout->eccpos;
 262         uint8_t *p = buf;
 263         uint8_t *oob = chip->oob_poi;
 264         uint8_t *ecc_pos;
 265         int stat;
 266
 267         /* read the page */
 268         chip->read_buf(mtd, p, eccsize);
 269
 270         /* move to ECC position if needed */
 271         if (eccpos[0] != 0) {
 272                 /* This only works on large pages
 273                  * because the ECC controller waits for
 274                  * NAND_CMD_RNDOUTSTART after the
 275                  * NAND_CMD_RNDOUT.
 276                  * anyway, for small pages, the eccpos[0] == 0
 277                  */
 278                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
 279                                 mtd->writesize + eccpos[0], -1);
 280         }
 281
 282         /* the ECC controller needs to read the ECC just after the data */
 283         ecc_pos = oob + eccpos[0];
 284         chip->read_buf(mtd, ecc_pos, eccbytes);
 285
 286         /* check if there's an error */
 287         stat = chip->ecc.correct(mtd, p, oob, NULL);
 288
 289         if (stat < 0)
 290                 mtd->ecc_stats.failed++;
 291         else
 292                 mtd->ecc_stats.corrected += stat;
 293
 294         /* get back to oob start (end of page) */
 295         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 296
 297         /* read the oob */
 298         chip->read_buf(mtd, oob, mtd->oobsize);
 299
 300         return 0;
 301 }
 302
 303 /*
 304  * HW ECC Correction
 305  *
 306  * function called after a read
 307  *
 308  * mtd:        MTD block structure
 309  * dat:        raw data read from the chip
 310  * read_ecc:   ECC from the chip (unused)
 311  * isnull:     unused
 312  *
 313  * Detect and correct a 1 bit error for a page
 314  */
 315 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 316                 u_char *read_ecc, u_char *isnull)
 317 {
 318         struct nand_chip *nand_chip = mtd->priv;
 319         struct atmel_nand_host *host = nand_chip->priv;
 320         unsigned int ecc_status;
 321         unsigned int ecc_word, ecc_bit;
 322
 323         /* get the status from the Status Register */
 324         ecc_status = ecc_readl(host->ecc, SR);
 325
 326         /* if there's no error */
 327         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
 328                 return 0;
 329
 330         /* get error bit offset (4 bits) */
 331         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
 332         /* get word address (12 bits) */
 333         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
 334         ecc_word >>= 4;
 335
 336         /* if there are multiple errors */
 337         if (ecc_status & ATMEL_ECC_MULERR) {
 338                 /* check if it is a freshly erased block
 339                  * (filled with 0xff) */
 340                 if ((ecc_bit == ATMEL_ECC_BITADDR)
 341                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
 342                         /* the block has just been erased, return OK */
 343                         return 0;
 344                 }
 345                 /* it doesn't seems to be a freshly
 346                  * erased block.
 347                  * We can't correct so many errors */
 348                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
 349                                 " Unable to correct.\n");
 350                 return -EIO;
 351         }
 352
 353         /* if there's a single bit error : we can correct it */
 354         if (ecc_status & ATMEL_ECC_ECCERR) {
 355                 /* there's nothing much to do here.
 356                  * the bit error is on the ECC itself.
 357                  */
 358                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
 359                                 " Nothing to correct\n");
 360                 return 0;
 361         }
 362
 363         dev_dbg(host->dev, "atmel_nand : one bit error on data."
 364                         " (word offset in the page :"
 365                         " 0x%x bit offset : 0x%x)\n",
 366                         ecc_word, ecc_bit);
 367         /* correct the error */
 368         if (nand_chip->options & NAND_BUSWIDTH_16) {
 369                 /* 16 bits words */
 370                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
 371         } else {
 372                 /* 8 bits words */
 373                 dat[ecc_word] ^= (1 << ecc_bit);
 374         }
 375         dev_dbg(host->dev, "atmel_nand : error corrected\n");
 376         return 1;
 377 }
 378
 379 /*
 380  * Enable HW ECC : unsused
 381  */
 382 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) { ; }
 383
 384 #ifdef CONFIG_MTD_PARTITIONS
 385 static const char *part_probes[] = { "cmdlinepart", NULL };
 386 #endif
 387
 388 /*
 389  * Probe for the NAND device.
 390  */
 391 static int __init atmel_nand_probe(struct platform_device *pdev)
 392 {
 393         struct atmel_nand_host *host;
 394         struct mtd_info *mtd;
 395         struct nand_chip *nand_chip;
 396         struct resource *regs;
 397         struct resource *mem;
 398         int res;
 399
 400 #ifdef CONFIG_MTD_PARTITIONS
 401         struct mtd_partition *partitions = NULL;
 402         int num_partitions = 0;
 403 #endif
 404
 405         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 406         if (!mem) {
 407                 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
 408                 return -ENXIO;
 409         }
 410
 411         /* Allocate memory for the device structure (and zero it) */
 412         host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
 413         if (!host) {
 414                 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
 415                 return -ENOMEM;
 416         }
 417
 418         host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
 419         if (host->io_base == NULL) {
 420                 printk(KERN_ERR "atmel_nand: ioremap failed\n");
 421                 res = -EIO;
 422                 goto err_nand_ioremap;
 423         }
 424
 425         mtd = &host->mtd;
 426         nand_chip = &host->nand_chip;
 427         host->board = pdev->dev.platform_data;
 428         host->dev = &pdev->dev;
 429
 430         nand_chip->priv = host;         /* link the private data structures */
 431         mtd->priv = nand_chip;
 432         mtd->owner = THIS_MODULE;
 433
 434         /* Set address of NAND IO lines */
 435         nand_chip->IO_ADDR_R = host->io_base;
 436         nand_chip->IO_ADDR_W = host->io_base;
 437         nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
 438
 439         if (host->board->rdy_pin)
 440                 nand_chip->dev_ready = atmel_nand_device_ready;
 441
 442         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 443         if (!regs && hard_ecc) {
 444                 printk(KERN_ERR "atmel_nand: can't get I/O resource "
 445                                 "regs\nFalling back on software ECC\n");
 446         }
 447
 448         nand_chip->ecc.mode = NAND_ECC_SOFT;    /* enable ECC */
 449         if (no_ecc)
 450                 nand_chip->ecc.mode = NAND_ECC_NONE;
 451         if (hard_ecc && regs) {
 452                 host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
 453                 if (host->ecc == NULL) {
 454                         printk(KERN_ERR "atmel_nand: ioremap failed\n");
 455                         res = -EIO;
 456                         goto err_ecc_ioremap;
 457                 }
 458                 nand_chip->ecc.mode = NAND_ECC_HW_SYNDROME;
 459                 nand_chip->ecc.calculate = atmel_nand_calculate;
 460                 nand_chip->ecc.correct = atmel_nand_correct;
 461                 nand_chip->ecc.hwctl = atmel_nand_hwctl;
 462                 nand_chip->ecc.read_page = atmel_nand_read_page;
 463                 nand_chip->ecc.bytes = 4;
 464                 nand_chip->ecc.prepad = 0;
 465                 nand_chip->ecc.postpad = 0;
 466         }
 467
 468         nand_chip->chip_delay = 20;             /* 20us command delay time */
 469
 470         if (host->board->bus_width_16) {        /* 16-bit bus width */
 471                 nand_chip->options |= NAND_BUSWIDTH_16;
 472                 nand_chip->read_buf = atmel_read_buf16;
 473                 nand_chip->write_buf = atmel_write_buf16;
 474         } else {
 475                 nand_chip->read_buf = atmel_read_buf;
 476                 nand_chip->write_buf = atmel_write_buf;
 477         }
 478
 479         platform_set_drvdata(pdev, host);
 480         atmel_nand_enable(host);
 481
 482         if (host->board->det_pin) {
 483                 if (gpio_get_value(host->board->det_pin)) {
 484                         printk("No SmartMedia card inserted.\n");
 485                         res = ENXIO;
 486                         goto err_no_card;
 487                 }
 488         }
 489
 490         /* first scan to find the device and get the page size */
 491         if (nand_scan_ident(mtd, 1)) {
 492                 res = -ENXIO;
 493                 goto err_scan_ident;
 494         }
 495
 496         if (nand_chip->ecc.mode == NAND_ECC_HW_SYNDROME) {
 497                 /* ECC is calculated for the whole page (1 step) */
 498                 nand_chip->ecc.size = mtd->writesize;
 499
 500                 /* set ECC page size and oob layout */
 501                 switch (mtd->writesize) {
 502                 case 512:
 503                         nand_chip->ecc.layout = &atmel_oobinfo_small;
 504                         nand_chip->ecc.read_oob = atmel_nand_read_oob_512;
 505                         nand_chip->ecc.write_oob = atmel_nand_write_oob_512;
 506                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
 507                         break;
 508                 case 1024:
 509                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 510                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
 511                         break;
 512                 case 2048:
 513                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 514                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
 515                         break;
 516                 case 4096:
 517                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 518                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
 519                         break;
 520                 default:
 521                         /* page size not handled by HW ECC */
 522                         /* switching back to soft ECC */
 523                         nand_chip->ecc.mode = NAND_ECC_SOFT;
 524                         nand_chip->ecc.calculate = NULL;
 525                         nand_chip->ecc.correct = NULL;
 526                         nand_chip->ecc.hwctl = NULL;
 527                         nand_chip->ecc.read_page = NULL;
 528                         nand_chip->ecc.postpad = 0;
 529                         nand_chip->ecc.prepad = 0;
 530                         nand_chip->ecc.bytes = 0;
 531                         break;
 532                 }
 533         }
 534
 535         /* second phase scan */
 536         if (nand_scan_tail(mtd)) {
 537                 res = -ENXIO;
 538                 goto err_scan_tail;
 539         }
 540
 541 #ifdef CONFIG_MTD_PARTITIONS
 542 #ifdef CONFIG_MTD_CMDLINE_PARTS
 543         mtd->name = "atmel_nand";
 544         num_partitions = parse_mtd_partitions(mtd, part_probes,
 545                                               &partitions, 0);
 546 #endif
 547         if (num_partitions <= 0 && host->board->partition_info)
 548                 partitions = host->board->partition_info(mtd->size,
 549                                                          &num_partitions);
 550
 551         if ((!partitions) || (num_partitions == 0)) {
 552                 printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
 553                 res = ENXIO;
 554                 goto err_no_partitions;
 555         }
 556
 557         res = add_mtd_partitions(mtd, partitions, num_partitions);
 558 #else
 559         res = add_mtd_device(mtd);
 560 #endif
 561
 562         if (!res)
 563                 return res;
 564
 565 #ifdef CONFIG_MTD_PARTITIONS
 566 err_no_partitions:
 567 #endif
 568         nand_release(mtd);
 569 err_scan_tail:
 570 err_scan_ident:
 571 err_no_card:
 572         atmel_nand_disable(host);
 573         platform_set_drvdata(pdev, NULL);
 574         if (host->ecc)
 575                 iounmap(host->ecc);
 576 err_ecc_ioremap:
 577         iounmap(host->io_base);
 578 err_nand_ioremap:
 579         kfree(host);
 580         return res;
 581 }
 582
 583 /*
 584  * Remove a NAND device.
 585  */
 586 static int __exit atmel_nand_remove(struct platform_device *pdev)
 587 {
 588         struct atmel_nand_host *host = platform_get_drvdata(pdev);
 589         struct mtd_info *mtd = &host->mtd;
 590
 591         nand_release(mtd);
 592
 593         atmel_nand_disable(host);
 594
 595         if (host->ecc)
 596                 iounmap(host->ecc);
 597         iounmap(host->io_base);
 598         kfree(host);
 599
 600         return 0;
 601 }
 602
 603 static struct platform_driver atmel_nand_driver = {
 604         .remove         = __exit_p(atmel_nand_remove),
 605         .driver         = {
 606                 .name   = "atmel_nand",
 607                 .owner  = THIS_MODULE,
 608         },
 609 };
 610
 611 static int __init atmel_nand_init(void)
 612 {
 613         return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
 614 }
 615
 616
 617 static void __exit atmel_nand_exit(void)
 618 {
 619         platform_driver_unregister(&atmel_nand_driver);
 620 }
 621
 622
 623 module_init(atmel_nand_init);
 624 module_exit(atmel_nand_exit);
 625
 626 MODULE_LICENSE("GPL");
 627 MODULE_AUTHOR("Rick Bronson");
 628 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
 629 MODULE_ALIAS("platform:atmel_nand");