2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
29 #include <asm/byteorder.h>
31 #include <linux/errno.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/mtd/compatmac.h>
36 #include <linux/mtd/map.h>
37 #include <linux/mtd/mtd.h>
38 #include <linux/mtd/cfi.h>
39 #include <linux/mtd/xip.h>
41 #define AMD_BOOTLOC_BUG
42 #define FORCE_WORD_WRITE 0
44 #define MAX_WORD_RETRIES 3
46 #define MANUFACTURER_AMD 0x0001
47 #define MANUFACTURER_ATMEL 0x001F
48 #define MANUFACTURER_MACRONIX 0x00C2
49 #define MANUFACTURER_SST 0x00BF
50 #define SST49LF004B 0x0060
51 #define SST49LF040B 0x0050
52 #define SST49LF008A 0x005a
53 #define AT49BV6416 0x00d6
55 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
56 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
57 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
58 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
59 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
60 static void cfi_amdstd_sync (struct mtd_info *);
61 static int cfi_amdstd_suspend (struct mtd_info *);
62 static void cfi_amdstd_resume (struct mtd_info *);
63 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
65 static void cfi_amdstd_destroy(struct mtd_info *);
67 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
68 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
70 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
71 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
74 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len);
75 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
77 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
78 .probe = NULL, /* Not usable directly */
79 .destroy = cfi_amdstd_destroy,
80 .name = "cfi_cmdset_0002",
85 /* #define DEBUG_CFI_FEATURES */
88 #ifdef DEBUG_CFI_FEATURES
89 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
91 const char* erase_suspend[3] = {
92 "Not supported", "Read only", "Read/write"
94 const char* top_bottom[6] = {
95 "No WP", "8x8KiB sectors at top & bottom, no WP",
96 "Bottom boot", "Top boot",
97 "Uniform, Bottom WP", "Uniform, Top WP"
100 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
101 printk(" Address sensitive unlock: %s\n",
102 (extp->SiliconRevision & 1) ? "Not required" : "Required");
104 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
105 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
107 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
109 if (extp->BlkProt == 0)
110 printk(" Block protection: Not supported\n");
112 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
115 printk(" Temporary block unprotect: %s\n",
116 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
117 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
118 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
119 printk(" Burst mode: %s\n",
120 extp->BurstMode ? "Supported" : "Not supported");
121 if (extp->PageMode == 0)
122 printk(" Page mode: Not supported\n");
124 printk(" Page mode: %d word page\n", extp->PageMode << 2);
126 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
127 extp->VppMin >> 4, extp->VppMin & 0xf);
128 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
129 extp->VppMax >> 4, extp->VppMax & 0xf);
131 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
132 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
134 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
138 #ifdef AMD_BOOTLOC_BUG
139 /* Wheee. Bring me the head of someone at AMD. */
140 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
142 struct map_info *map = mtd->priv;
143 struct cfi_private *cfi = map->fldrv_priv;
144 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
145 __u8 major = extp->MajorVersion;
146 __u8 minor = extp->MinorVersion;
148 if (((major << 8) | minor) < 0x3131) {
149 /* CFI version 1.0 => don't trust bootloc */
151 DEBUG(MTD_DEBUG_LEVEL1,
152 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
153 map->name, cfi->mfr, cfi->id);
155 /* AFAICS all 29LV400 with a bottom boot block have a device ID
156 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
157 * These were badly detected as they have the 0x80 bit set
158 * so treat them as a special case.
160 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
162 /* Macronix added CFI to their 2nd generation
163 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
164 * Fujitsu, Spansion, EON, ESI and older Macronix)
167 * Therefore also check the manufacturer.
168 * This reduces the risk of false detection due to
169 * the 8-bit device ID.
171 (cfi->mfr == MANUFACTURER_MACRONIX)) {
172 DEBUG(MTD_DEBUG_LEVEL1,
173 "%s: Macronix MX29LV400C with bottom boot block"
174 " detected\n", map->name);
175 extp->TopBottom = 2; /* bottom boot */
177 if (cfi->id & 0x80) {
178 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
179 extp->TopBottom = 3; /* top boot */
181 extp->TopBottom = 2; /* bottom boot */
184 DEBUG(MTD_DEBUG_LEVEL1,
185 "%s: AMD CFI PRI V%c.%c has no boot block field;"
186 " deduced %s from Device ID\n", map->name, major, minor,
187 extp->TopBottom == 2 ? "bottom" : "top");
192 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
194 struct map_info *map = mtd->priv;
195 struct cfi_private *cfi = map->fldrv_priv;
196 if (cfi->cfiq->BufWriteTimeoutTyp) {
197 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
198 mtd->write = cfi_amdstd_write_buffers;
202 /* Atmel chips don't use the same PRI format as AMD chips */
203 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
205 struct map_info *map = mtd->priv;
206 struct cfi_private *cfi = map->fldrv_priv;
207 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
208 struct cfi_pri_atmel atmel_pri;
210 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
211 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
213 if (atmel_pri.Features & 0x02)
214 extp->EraseSuspend = 2;
216 if (atmel_pri.BottomBoot)
221 /* burst write mode not supported */
222 cfi->cfiq->BufWriteTimeoutTyp = 0;
223 cfi->cfiq->BufWriteTimeoutMax = 0;
226 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
228 /* Setup for chips with a secsi area */
229 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
230 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
233 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
235 struct map_info *map = mtd->priv;
236 struct cfi_private *cfi = map->fldrv_priv;
237 if ((cfi->cfiq->NumEraseRegions == 1) &&
238 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
239 mtd->erase = cfi_amdstd_erase_chip;
245 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
248 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
250 mtd->lock = cfi_atmel_lock;
251 mtd->unlock = cfi_atmel_unlock;
252 mtd->flags |= MTD_POWERUP_LOCK;
255 static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param)
257 struct map_info *map = mtd->priv;
258 struct cfi_private *cfi = map->fldrv_priv;
260 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
261 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
262 pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name);
266 static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param)
268 struct map_info *map = mtd->priv;
269 struct cfi_private *cfi = map->fldrv_priv;
271 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
272 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
273 pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name);
277 static struct cfi_fixup cfi_fixup_table[] = {
278 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
279 #ifdef AMD_BOOTLOC_BUG
280 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
281 { MANUFACTURER_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL },
283 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
284 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
285 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
286 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
287 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
288 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
289 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors, NULL, },
290 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, },
291 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, },
292 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, },
293 #if !FORCE_WORD_WRITE
294 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
298 static struct cfi_fixup jedec_fixup_table[] = {
299 { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
300 { MANUFACTURER_SST, SST49LF040B, fixup_use_fwh_lock, NULL, },
301 { MANUFACTURER_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
305 static struct cfi_fixup fixup_table[] = {
306 /* The CFI vendor ids and the JEDEC vendor IDs appear
307 * to be common. It is like the devices id's are as
308 * well. This table is to pick all cases where
309 * we know that is the case.
311 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
312 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
317 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
319 struct cfi_private *cfi = map->fldrv_priv;
320 struct mtd_info *mtd;
323 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
325 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
329 mtd->type = MTD_NORFLASH;
331 /* Fill in the default mtd operations */
332 mtd->erase = cfi_amdstd_erase_varsize;
333 mtd->write = cfi_amdstd_write_words;
334 mtd->read = cfi_amdstd_read;
335 mtd->sync = cfi_amdstd_sync;
336 mtd->suspend = cfi_amdstd_suspend;
337 mtd->resume = cfi_amdstd_resume;
338 mtd->flags = MTD_CAP_NORFLASH;
339 mtd->name = map->name;
342 if (cfi->cfi_mode==CFI_MODE_CFI){
343 unsigned char bootloc;
345 * It's a real CFI chip, not one for which the probe
346 * routine faked a CFI structure. So we read the feature
349 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
350 struct cfi_pri_amdstd *extp;
352 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
358 if (extp->MajorVersion != '1' ||
359 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
360 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
361 "version %c.%c.\n", extp->MajorVersion,
368 /* Install our own private info structure */
369 cfi->cmdset_priv = extp;
371 /* Apply cfi device specific fixups */
372 cfi_fixup(mtd, cfi_fixup_table);
374 #ifdef DEBUG_CFI_FEATURES
375 /* Tell the user about it in lots of lovely detail */
376 cfi_tell_features(extp);
379 bootloc = extp->TopBottom;
380 if ((bootloc != 2) && (bootloc != 3)) {
381 printk(KERN_WARNING "%s: CFI does not contain boot "
382 "bank location. Assuming top.\n", map->name);
386 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
387 printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n", map->name);
389 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
390 int j = (cfi->cfiq->NumEraseRegions-1)-i;
393 swap = cfi->cfiq->EraseRegionInfo[i];
394 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
395 cfi->cfiq->EraseRegionInfo[j] = swap;
398 /* Set the default CFI lock/unlock addresses */
399 cfi->addr_unlock1 = 0x555;
400 cfi->addr_unlock2 = 0x2aa;
401 /* Modify the unlock address if we are in compatibility mode */
402 if ( /* x16 in x8 mode */
403 ((cfi->device_type == CFI_DEVICETYPE_X8) &&
404 (cfi->cfiq->InterfaceDesc ==
405 CFI_INTERFACE_X8_BY_X16_ASYNC)) ||
406 /* x32 in x16 mode */
407 ((cfi->device_type == CFI_DEVICETYPE_X16) &&
408 (cfi->cfiq->InterfaceDesc ==
409 CFI_INTERFACE_X16_BY_X32_ASYNC)))
411 cfi->addr_unlock1 = 0xaaa;
412 cfi->addr_unlock2 = 0x555;
416 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
417 /* Apply jedec specific fixups */
418 cfi_fixup(mtd, jedec_fixup_table);
420 /* Apply generic fixups */
421 cfi_fixup(mtd, fixup_table);
423 for (i=0; i< cfi->numchips; i++) {
424 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
425 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
426 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
427 cfi->chips[i].ref_point_counter = 0;
428 init_waitqueue_head(&(cfi->chips[i].wq));
431 map->fldrv = &cfi_amdstd_chipdrv;
433 return cfi_amdstd_setup(mtd);
435 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
437 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
439 struct map_info *map = mtd->priv;
440 struct cfi_private *cfi = map->fldrv_priv;
441 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
442 unsigned long offset = 0;
445 printk(KERN_NOTICE "number of %s chips: %d\n",
446 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
447 /* Select the correct geometry setup */
448 mtd->size = devsize * cfi->numchips;
450 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
451 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
452 * mtd->numeraseregions, GFP_KERNEL);
453 if (!mtd->eraseregions) {
454 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
458 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
459 unsigned long ernum, ersize;
460 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
461 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
463 if (mtd->erasesize < ersize) {
464 mtd->erasesize = ersize;
466 for (j=0; j<cfi->numchips; j++) {
467 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
468 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
469 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
471 offset += (ersize * ernum);
473 if (offset != devsize) {
475 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
480 for (i=0; i<mtd->numeraseregions;i++){
481 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
482 i,mtd->eraseregions[i].offset,
483 mtd->eraseregions[i].erasesize,
484 mtd->eraseregions[i].numblocks);
488 /* FIXME: erase-suspend-program is broken. See
489 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
490 printk(KERN_NOTICE "cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
492 __module_get(THIS_MODULE);
497 kfree(mtd->eraseregions);
500 kfree(cfi->cmdset_priv);
506 * Return true if the chip is ready.
508 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
509 * non-suspended sector) and is indicated by no toggle bits toggling.
511 * Note that anything more complicated than checking if no bits are toggling
512 * (including checking DQ5 for an error status) is tricky to get working
513 * correctly and is therefore not done (particulary with interleaved chips
514 * as each chip must be checked independantly of the others).
516 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
520 d = map_read(map, addr);
521 t = map_read(map, addr);
523 return map_word_equal(map, d, t);
527 * Return true if the chip is ready and has the correct value.
529 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
530 * non-suspended sector) and it is indicated by no bits toggling.
532 * Error are indicated by toggling bits or bits held with the wrong value,
533 * or with bits toggling.
535 * Note that anything more complicated than checking if no bits are toggling
536 * (including checking DQ5 for an error status) is tricky to get working
537 * correctly and is therefore not done (particulary with interleaved chips
538 * as each chip must be checked independantly of the others).
541 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
545 oldd = map_read(map, addr);
546 curd = map_read(map, addr);
548 return map_word_equal(map, oldd, curd) &&
549 map_word_equal(map, curd, expected);
552 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
554 DECLARE_WAITQUEUE(wait, current);
555 struct cfi_private *cfi = map->fldrv_priv;
557 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
560 timeo = jiffies + HZ;
562 switch (chip->state) {
566 if (chip_ready(map, adr))
569 if (time_after(jiffies, timeo)) {
570 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
571 spin_unlock(chip->mutex);
574 spin_unlock(chip->mutex);
576 spin_lock(chip->mutex);
577 /* Someone else might have been playing with it. */
587 if (mode == FL_WRITING) /* FIXME: Erase-suspend-program appears broken. */
590 if (!( mode == FL_READY
593 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))
594 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x1)
598 /* We could check to see if we're trying to access the sector
599 * that is currently being erased. However, no user will try
600 * anything like that so we just wait for the timeout. */
603 /* It's harmless to issue the Erase-Suspend and Erase-Resume
604 * commands when the erase algorithm isn't in progress. */
605 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
606 chip->oldstate = FL_ERASING;
607 chip->state = FL_ERASE_SUSPENDING;
608 chip->erase_suspended = 1;
610 if (chip_ready(map, adr))
613 if (time_after(jiffies, timeo)) {
614 /* Should have suspended the erase by now.
615 * Send an Erase-Resume command as either
616 * there was an error (so leave the erase
617 * routine to recover from it) or we trying to
618 * use the erase-in-progress sector. */
619 map_write(map, CMD(0x30), chip->in_progress_block_addr);
620 chip->state = FL_ERASING;
621 chip->oldstate = FL_READY;
622 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
626 spin_unlock(chip->mutex);
628 spin_lock(chip->mutex);
629 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
630 So we can just loop here. */
632 chip->state = FL_READY;
635 case FL_XIP_WHILE_ERASING:
636 if (mode != FL_READY && mode != FL_POINT &&
637 (!cfip || !(cfip->EraseSuspend&2)))
639 chip->oldstate = chip->state;
640 chip->state = FL_READY;
644 /* Only if there's no operation suspended... */
645 if (mode == FL_READY && chip->oldstate == FL_READY)
650 set_current_state(TASK_UNINTERRUPTIBLE);
651 add_wait_queue(&chip->wq, &wait);
652 spin_unlock(chip->mutex);
654 remove_wait_queue(&chip->wq, &wait);
655 spin_lock(chip->mutex);
661 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
663 struct cfi_private *cfi = map->fldrv_priv;
665 switch(chip->oldstate) {
667 chip->state = chip->oldstate;
668 map_write(map, CMD(0x30), chip->in_progress_block_addr);
669 chip->oldstate = FL_READY;
670 chip->state = FL_ERASING;
673 case FL_XIP_WHILE_ERASING:
674 chip->state = chip->oldstate;
675 chip->oldstate = FL_READY;
680 /* We should really make set_vpp() count, rather than doing this */
684 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
689 #ifdef CONFIG_MTD_XIP
692 * No interrupt what so ever can be serviced while the flash isn't in array
693 * mode. This is ensured by the xip_disable() and xip_enable() functions
694 * enclosing any code path where the flash is known not to be in array mode.
695 * And within a XIP disabled code path, only functions marked with __xipram
696 * may be called and nothing else (it's a good thing to inspect generated
697 * assembly to make sure inline functions were actually inlined and that gcc
698 * didn't emit calls to its own support functions). Also configuring MTD CFI
699 * support to a single buswidth and a single interleave is also recommended.
702 static void xip_disable(struct map_info *map, struct flchip *chip,
705 /* TODO: chips with no XIP use should ignore and return */
706 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
710 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
713 struct cfi_private *cfi = map->fldrv_priv;
715 if (chip->state != FL_POINT && chip->state != FL_READY) {
716 map_write(map, CMD(0xf0), adr);
717 chip->state = FL_READY;
719 (void) map_read(map, adr);
725 * When a delay is required for the flash operation to complete, the
726 * xip_udelay() function is polling for both the given timeout and pending
727 * (but still masked) hardware interrupts. Whenever there is an interrupt
728 * pending then the flash erase operation is suspended, array mode restored
729 * and interrupts unmasked. Task scheduling might also happen at that
730 * point. The CPU eventually returns from the interrupt or the call to
731 * schedule() and the suspended flash operation is resumed for the remaining
732 * of the delay period.
734 * Warning: this function _will_ fool interrupt latency tracing tools.
737 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
738 unsigned long adr, int usec)
740 struct cfi_private *cfi = map->fldrv_priv;
741 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
742 map_word status, OK = CMD(0x80);
743 unsigned long suspended, start = xip_currtime();
748 if (xip_irqpending() && extp &&
749 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
750 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
752 * Let's suspend the erase operation when supported.
753 * Note that we currently don't try to suspend
754 * interleaved chips if there is already another
755 * operation suspended (imagine what happens
756 * when one chip was already done with the current
757 * operation while another chip suspended it, then
758 * we resume the whole thing at once). Yes, it
761 map_write(map, CMD(0xb0), adr);
762 usec -= xip_elapsed_since(start);
763 suspended = xip_currtime();
765 if (xip_elapsed_since(suspended) > 100000) {
767 * The chip doesn't want to suspend
768 * after waiting for 100 msecs.
769 * This is a critical error but there
770 * is not much we can do here.
774 status = map_read(map, adr);
775 } while (!map_word_andequal(map, status, OK, OK));
777 /* Suspend succeeded */
778 oldstate = chip->state;
779 if (!map_word_bitsset(map, status, CMD(0x40)))
781 chip->state = FL_XIP_WHILE_ERASING;
782 chip->erase_suspended = 1;
783 map_write(map, CMD(0xf0), adr);
784 (void) map_read(map, adr);
787 spin_unlock(chip->mutex);
792 * We're back. However someone else might have
793 * decided to go write to the chip if we are in
794 * a suspended erase state. If so let's wait
797 spin_lock(chip->mutex);
798 while (chip->state != FL_XIP_WHILE_ERASING) {
799 DECLARE_WAITQUEUE(wait, current);
800 set_current_state(TASK_UNINTERRUPTIBLE);
801 add_wait_queue(&chip->wq, &wait);
802 spin_unlock(chip->mutex);
804 remove_wait_queue(&chip->wq, &wait);
805 spin_lock(chip->mutex);
807 /* Disallow XIP again */
810 /* Resume the write or erase operation */
811 map_write(map, CMD(0x30), adr);
812 chip->state = oldstate;
813 start = xip_currtime();
814 } else if (usec >= 1000000/HZ) {
816 * Try to save on CPU power when waiting delay
817 * is at least a system timer tick period.
818 * No need to be extremely accurate here.
822 status = map_read(map, adr);
823 } while (!map_word_andequal(map, status, OK, OK)
824 && xip_elapsed_since(start) < usec);
827 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
830 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
831 * the flash is actively programming or erasing since we have to poll for
832 * the operation to complete anyway. We can't do that in a generic way with
833 * a XIP setup so do it before the actual flash operation in this case
834 * and stub it out from INVALIDATE_CACHE_UDELAY.
836 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
837 INVALIDATE_CACHED_RANGE(map, from, size)
839 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
840 UDELAY(map, chip, adr, usec)
845 * Activating this XIP support changes the way the code works a bit. For
846 * example the code to suspend the current process when concurrent access
847 * happens is never executed because xip_udelay() will always return with the
848 * same chip state as it was entered with. This is why there is no care for
849 * the presence of add_wait_queue() or schedule() calls from within a couple
850 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
851 * The queueing and scheduling are always happening within xip_udelay().
853 * Similarly, get_chip() and put_chip() just happen to always be executed
854 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
855 * is in array mode, therefore never executing many cases therein and not
856 * causing any problem with XIP.
861 #define xip_disable(map, chip, adr)
862 #define xip_enable(map, chip, adr)
863 #define XIP_INVAL_CACHED_RANGE(x...)
865 #define UDELAY(map, chip, adr, usec) \
867 spin_unlock(chip->mutex); \
869 spin_lock(chip->mutex); \
872 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
874 spin_unlock(chip->mutex); \
875 INVALIDATE_CACHED_RANGE(map, adr, len); \
877 spin_lock(chip->mutex); \
882 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
884 unsigned long cmd_addr;
885 struct cfi_private *cfi = map->fldrv_priv;
890 /* Ensure cmd read/writes are aligned. */
891 cmd_addr = adr & ~(map_bankwidth(map)-1);
893 spin_lock(chip->mutex);
894 ret = get_chip(map, chip, cmd_addr, FL_READY);
896 spin_unlock(chip->mutex);
900 if (chip->state != FL_POINT && chip->state != FL_READY) {
901 map_write(map, CMD(0xf0), cmd_addr);
902 chip->state = FL_READY;
905 map_copy_from(map, buf, adr, len);
907 put_chip(map, chip, cmd_addr);
909 spin_unlock(chip->mutex);
914 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
916 struct map_info *map = mtd->priv;
917 struct cfi_private *cfi = map->fldrv_priv;
922 /* ofs: offset within the first chip that the first read should start */
924 chipnum = (from >> cfi->chipshift);
925 ofs = from - (chipnum << cfi->chipshift);
931 unsigned long thislen;
933 if (chipnum >= cfi->numchips)
936 if ((len + ofs -1) >> cfi->chipshift)
937 thislen = (1<<cfi->chipshift) - ofs;
941 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
956 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
958 DECLARE_WAITQUEUE(wait, current);
959 unsigned long timeo = jiffies + HZ;
960 struct cfi_private *cfi = map->fldrv_priv;
963 spin_lock(chip->mutex);
965 if (chip->state != FL_READY){
967 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
969 set_current_state(TASK_UNINTERRUPTIBLE);
970 add_wait_queue(&chip->wq, &wait);
972 spin_unlock(chip->mutex);
975 remove_wait_queue(&chip->wq, &wait);
977 if(signal_pending(current))
980 timeo = jiffies + HZ;
987 chip->state = FL_READY;
989 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
990 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
991 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
993 map_copy_from(map, buf, adr, len);
995 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
996 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
997 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
998 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1001 spin_unlock(chip->mutex);
1006 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1008 struct map_info *map = mtd->priv;
1009 struct cfi_private *cfi = map->fldrv_priv;
1015 /* ofs: offset within the first chip that the first read should start */
1017 /* 8 secsi bytes per chip */
1025 unsigned long thislen;
1027 if (chipnum >= cfi->numchips)
1030 if ((len + ofs -1) >> 3)
1031 thislen = (1<<3) - ofs;
1035 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1050 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
1052 struct cfi_private *cfi = map->fldrv_priv;
1053 unsigned long timeo = jiffies + HZ;
1055 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1056 * have a max write time of a few hundreds usec). However, we should
1057 * use the maximum timeout value given by the chip at probe time
1058 * instead. Unfortunately, struct flchip does have a field for
1059 * maximum timeout, only for typical which can be far too short
1060 * depending of the conditions. The ' + 1' is to avoid having a
1061 * timeout of 0 jiffies if HZ is smaller than 1000.
1063 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1070 spin_lock(chip->mutex);
1071 ret = get_chip(map, chip, adr, FL_WRITING);
1073 spin_unlock(chip->mutex);
1077 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1078 __func__, adr, datum.x[0] );
1081 * Check for a NOP for the case when the datum to write is already
1082 * present - it saves time and works around buggy chips that corrupt
1083 * data at other locations when 0xff is written to a location that
1084 * already contains 0xff.
1086 oldd = map_read(map, adr);
1087 if (map_word_equal(map, oldd, datum)) {
1088 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1093 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1095 xip_disable(map, chip, adr);
1097 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1098 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1099 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1100 map_write(map, datum, adr);
1101 chip->state = FL_WRITING;
1103 INVALIDATE_CACHE_UDELAY(map, chip,
1104 adr, map_bankwidth(map),
1105 chip->word_write_time);
1107 /* See comment above for timeout value. */
1108 timeo = jiffies + uWriteTimeout;
1110 if (chip->state != FL_WRITING) {
1111 /* Someone's suspended the write. Sleep */
1112 DECLARE_WAITQUEUE(wait, current);
1114 set_current_state(TASK_UNINTERRUPTIBLE);
1115 add_wait_queue(&chip->wq, &wait);
1116 spin_unlock(chip->mutex);
1118 remove_wait_queue(&chip->wq, &wait);
1119 timeo = jiffies + (HZ / 2); /* FIXME */
1120 spin_lock(chip->mutex);
1124 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1125 xip_enable(map, chip, adr);
1126 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1127 xip_disable(map, chip, adr);
1131 if (chip_ready(map, adr))
1134 /* Latency issues. Drop the lock, wait a while and retry */
1135 UDELAY(map, chip, adr, 1);
1137 /* Did we succeed? */
1138 if (!chip_good(map, adr, datum)) {
1139 /* reset on all failures. */
1140 map_write( map, CMD(0xF0), chip->start );
1141 /* FIXME - should have reset delay before continuing */
1143 if (++retry_cnt <= MAX_WORD_RETRIES)
1148 xip_enable(map, chip, adr);
1150 chip->state = FL_READY;
1151 put_chip(map, chip, adr);
1152 spin_unlock(chip->mutex);
1158 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1159 size_t *retlen, const u_char *buf)
1161 struct map_info *map = mtd->priv;
1162 struct cfi_private *cfi = map->fldrv_priv;
1165 unsigned long ofs, chipstart;
1166 DECLARE_WAITQUEUE(wait, current);
1172 chipnum = to >> cfi->chipshift;
1173 ofs = to - (chipnum << cfi->chipshift);
1174 chipstart = cfi->chips[chipnum].start;
1176 /* If it's not bus-aligned, do the first byte write */
1177 if (ofs & (map_bankwidth(map)-1)) {
1178 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1179 int i = ofs - bus_ofs;
1184 spin_lock(cfi->chips[chipnum].mutex);
1186 if (cfi->chips[chipnum].state != FL_READY) {
1188 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1190 set_current_state(TASK_UNINTERRUPTIBLE);
1191 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1193 spin_unlock(cfi->chips[chipnum].mutex);
1196 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1198 if(signal_pending(current))
1204 /* Load 'tmp_buf' with old contents of flash */
1205 tmp_buf = map_read(map, bus_ofs+chipstart);
1207 spin_unlock(cfi->chips[chipnum].mutex);
1209 /* Number of bytes to copy from buffer */
1210 n = min_t(int, len, map_bankwidth(map)-i);
1212 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1214 ret = do_write_oneword(map, &cfi->chips[chipnum],
1224 if (ofs >> cfi->chipshift) {
1227 if (chipnum == cfi->numchips)
1232 /* We are now aligned, write as much as possible */
1233 while(len >= map_bankwidth(map)) {
1236 datum = map_word_load(map, buf);
1238 ret = do_write_oneword(map, &cfi->chips[chipnum],
1243 ofs += map_bankwidth(map);
1244 buf += map_bankwidth(map);
1245 (*retlen) += map_bankwidth(map);
1246 len -= map_bankwidth(map);
1248 if (ofs >> cfi->chipshift) {
1251 if (chipnum == cfi->numchips)
1253 chipstart = cfi->chips[chipnum].start;
1257 /* Write the trailing bytes if any */
1258 if (len & (map_bankwidth(map)-1)) {
1262 spin_lock(cfi->chips[chipnum].mutex);
1264 if (cfi->chips[chipnum].state != FL_READY) {
1266 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1268 set_current_state(TASK_UNINTERRUPTIBLE);
1269 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1271 spin_unlock(cfi->chips[chipnum].mutex);
1274 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1276 if(signal_pending(current))
1282 tmp_buf = map_read(map, ofs + chipstart);
1284 spin_unlock(cfi->chips[chipnum].mutex);
1286 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1288 ret = do_write_oneword(map, &cfi->chips[chipnum],
1301 * FIXME: interleaved mode not tested, and probably not supported!
1303 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1304 unsigned long adr, const u_char *buf,
1307 struct cfi_private *cfi = map->fldrv_priv;
1308 unsigned long timeo = jiffies + HZ;
1309 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1310 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1312 unsigned long cmd_adr;
1319 spin_lock(chip->mutex);
1320 ret = get_chip(map, chip, adr, FL_WRITING);
1322 spin_unlock(chip->mutex);
1326 datum = map_word_load(map, buf);
1328 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1329 __func__, adr, datum.x[0] );
1331 XIP_INVAL_CACHED_RANGE(map, adr, len);
1333 xip_disable(map, chip, cmd_adr);
1335 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1336 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1337 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1339 /* Write Buffer Load */
1340 map_write(map, CMD(0x25), cmd_adr);
1342 chip->state = FL_WRITING_TO_BUFFER;
1344 /* Write length of data to come */
1345 words = len / map_bankwidth(map);
1346 map_write(map, CMD(words - 1), cmd_adr);
1349 while(z < words * map_bankwidth(map)) {
1350 datum = map_word_load(map, buf);
1351 map_write(map, datum, adr + z);
1353 z += map_bankwidth(map);
1354 buf += map_bankwidth(map);
1356 z -= map_bankwidth(map);
1360 /* Write Buffer Program Confirm: GO GO GO */
1361 map_write(map, CMD(0x29), cmd_adr);
1362 chip->state = FL_WRITING;
1364 INVALIDATE_CACHE_UDELAY(map, chip,
1365 adr, map_bankwidth(map),
1366 chip->word_write_time);
1368 timeo = jiffies + uWriteTimeout;
1371 if (chip->state != FL_WRITING) {
1372 /* Someone's suspended the write. Sleep */
1373 DECLARE_WAITQUEUE(wait, current);
1375 set_current_state(TASK_UNINTERRUPTIBLE);
1376 add_wait_queue(&chip->wq, &wait);
1377 spin_unlock(chip->mutex);
1379 remove_wait_queue(&chip->wq, &wait);
1380 timeo = jiffies + (HZ / 2); /* FIXME */
1381 spin_lock(chip->mutex);
1385 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1388 if (chip_ready(map, adr)) {
1389 xip_enable(map, chip, adr);
1393 /* Latency issues. Drop the lock, wait a while and retry */
1394 UDELAY(map, chip, adr, 1);
1397 /* reset on all failures. */
1398 map_write( map, CMD(0xF0), chip->start );
1399 xip_enable(map, chip, adr);
1400 /* FIXME - should have reset delay before continuing */
1402 printk(KERN_WARNING "MTD %s(): software timeout\n",
1407 chip->state = FL_READY;
1408 put_chip(map, chip, adr);
1409 spin_unlock(chip->mutex);
1415 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1416 size_t *retlen, const u_char *buf)
1418 struct map_info *map = mtd->priv;
1419 struct cfi_private *cfi = map->fldrv_priv;
1420 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1429 chipnum = to >> cfi->chipshift;
1430 ofs = to - (chipnum << cfi->chipshift);
1432 /* If it's not bus-aligned, do the first word write */
1433 if (ofs & (map_bankwidth(map)-1)) {
1434 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1435 if (local_len > len)
1437 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1438 local_len, retlen, buf);
1445 if (ofs >> cfi->chipshift) {
1448 if (chipnum == cfi->numchips)
1453 /* Write buffer is worth it only if more than one word to write... */
1454 while (len >= map_bankwidth(map) * 2) {
1455 /* We must not cross write block boundaries */
1456 int size = wbufsize - (ofs & (wbufsize-1));
1460 if (size % map_bankwidth(map))
1461 size -= size % map_bankwidth(map);
1463 ret = do_write_buffer(map, &cfi->chips[chipnum],
1473 if (ofs >> cfi->chipshift) {
1476 if (chipnum == cfi->numchips)
1482 size_t retlen_dregs = 0;
1484 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1485 len, &retlen_dregs, buf);
1487 *retlen += retlen_dregs;
1496 * Handle devices with one erase region, that only implement
1497 * the chip erase command.
1499 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1501 struct cfi_private *cfi = map->fldrv_priv;
1502 unsigned long timeo = jiffies + HZ;
1503 unsigned long int adr;
1504 DECLARE_WAITQUEUE(wait, current);
1507 adr = cfi->addr_unlock1;
1509 spin_lock(chip->mutex);
1510 ret = get_chip(map, chip, adr, FL_WRITING);
1512 spin_unlock(chip->mutex);
1516 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1517 __func__, chip->start );
1519 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1521 xip_disable(map, chip, adr);
1523 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1524 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1525 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1526 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1527 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1528 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1530 chip->state = FL_ERASING;
1531 chip->erase_suspended = 0;
1532 chip->in_progress_block_addr = adr;
1534 INVALIDATE_CACHE_UDELAY(map, chip,
1536 chip->erase_time*500);
1538 timeo = jiffies + (HZ*20);
1541 if (chip->state != FL_ERASING) {
1542 /* Someone's suspended the erase. Sleep */
1543 set_current_state(TASK_UNINTERRUPTIBLE);
1544 add_wait_queue(&chip->wq, &wait);
1545 spin_unlock(chip->mutex);
1547 remove_wait_queue(&chip->wq, &wait);
1548 spin_lock(chip->mutex);
1551 if (chip->erase_suspended) {
1552 /* This erase was suspended and resumed.
1553 Adjust the timeout */
1554 timeo = jiffies + (HZ*20); /* FIXME */
1555 chip->erase_suspended = 0;
1558 if (chip_ready(map, adr))
1561 if (time_after(jiffies, timeo)) {
1562 printk(KERN_WARNING "MTD %s(): software timeout\n",
1567 /* Latency issues. Drop the lock, wait a while and retry */
1568 UDELAY(map, chip, adr, 1000000/HZ);
1570 /* Did we succeed? */
1571 if (!chip_good(map, adr, map_word_ff(map))) {
1572 /* reset on all failures. */
1573 map_write( map, CMD(0xF0), chip->start );
1574 /* FIXME - should have reset delay before continuing */
1579 chip->state = FL_READY;
1580 xip_enable(map, chip, adr);
1581 put_chip(map, chip, adr);
1582 spin_unlock(chip->mutex);
1588 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1590 struct cfi_private *cfi = map->fldrv_priv;
1591 unsigned long timeo = jiffies + HZ;
1592 DECLARE_WAITQUEUE(wait, current);
1597 spin_lock(chip->mutex);
1598 ret = get_chip(map, chip, adr, FL_ERASING);
1600 spin_unlock(chip->mutex);
1604 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1607 XIP_INVAL_CACHED_RANGE(map, adr, len);
1609 xip_disable(map, chip, adr);
1611 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1612 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1613 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1614 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1615 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1616 map_write(map, CMD(0x30), adr);
1618 chip->state = FL_ERASING;
1619 chip->erase_suspended = 0;
1620 chip->in_progress_block_addr = adr;
1622 INVALIDATE_CACHE_UDELAY(map, chip,
1624 chip->erase_time*500);
1626 timeo = jiffies + (HZ*20);
1629 if (chip->state != FL_ERASING) {
1630 /* Someone's suspended the erase. Sleep */
1631 set_current_state(TASK_UNINTERRUPTIBLE);
1632 add_wait_queue(&chip->wq, &wait);
1633 spin_unlock(chip->mutex);
1635 remove_wait_queue(&chip->wq, &wait);
1636 spin_lock(chip->mutex);
1639 if (chip->erase_suspended) {
1640 /* This erase was suspended and resumed.
1641 Adjust the timeout */
1642 timeo = jiffies + (HZ*20); /* FIXME */
1643 chip->erase_suspended = 0;
1646 if (chip_ready(map, adr)) {
1647 xip_enable(map, chip, adr);
1651 if (time_after(jiffies, timeo)) {
1652 xip_enable(map, chip, adr);
1653 printk(KERN_WARNING "MTD %s(): software timeout\n",
1658 /* Latency issues. Drop the lock, wait a while and retry */
1659 UDELAY(map, chip, adr, 1000000/HZ);
1661 /* Did we succeed? */
1662 if (!chip_good(map, adr, map_word_ff(map))) {
1663 /* reset on all failures. */
1664 map_write( map, CMD(0xF0), chip->start );
1665 /* FIXME - should have reset delay before continuing */
1670 chip->state = FL_READY;
1671 put_chip(map, chip, adr);
1672 spin_unlock(chip->mutex);
1677 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1679 unsigned long ofs, len;
1685 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1689 instr->state = MTD_ERASE_DONE;
1690 mtd_erase_callback(instr);
1696 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1698 struct map_info *map = mtd->priv;
1699 struct cfi_private *cfi = map->fldrv_priv;
1702 if (instr->addr != 0)
1705 if (instr->len != mtd->size)
1708 ret = do_erase_chip(map, &cfi->chips[0]);
1712 instr->state = MTD_ERASE_DONE;
1713 mtd_erase_callback(instr);
1718 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1719 unsigned long adr, int len, void *thunk)
1721 struct cfi_private *cfi = map->fldrv_priv;
1724 spin_lock(chip->mutex);
1725 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1728 chip->state = FL_LOCKING;
1730 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1731 __func__, adr, len);
1733 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1734 cfi->device_type, NULL);
1735 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1736 cfi->device_type, NULL);
1737 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1738 cfi->device_type, NULL);
1739 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1740 cfi->device_type, NULL);
1741 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1742 cfi->device_type, NULL);
1743 map_write(map, CMD(0x40), chip->start + adr);
1745 chip->state = FL_READY;
1746 put_chip(map, chip, adr + chip->start);
1750 spin_unlock(chip->mutex);
1754 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1755 unsigned long adr, int len, void *thunk)
1757 struct cfi_private *cfi = map->fldrv_priv;
1760 spin_lock(chip->mutex);
1761 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1764 chip->state = FL_UNLOCKING;
1766 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1767 __func__, adr, len);
1769 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1770 cfi->device_type, NULL);
1771 map_write(map, CMD(0x70), adr);
1773 chip->state = FL_READY;
1774 put_chip(map, chip, adr + chip->start);
1778 spin_unlock(chip->mutex);
1782 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
1784 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1787 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
1789 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1793 static void cfi_amdstd_sync (struct mtd_info *mtd)
1795 struct map_info *map = mtd->priv;
1796 struct cfi_private *cfi = map->fldrv_priv;
1798 struct flchip *chip;
1800 DECLARE_WAITQUEUE(wait, current);
1802 for (i=0; !ret && i<cfi->numchips; i++) {
1803 chip = &cfi->chips[i];
1806 spin_lock(chip->mutex);
1808 switch(chip->state) {
1812 case FL_JEDEC_QUERY:
1813 chip->oldstate = chip->state;
1814 chip->state = FL_SYNCING;
1815 /* No need to wake_up() on this state change -
1816 * as the whole point is that nobody can do anything
1817 * with the chip now anyway.
1820 spin_unlock(chip->mutex);
1824 /* Not an idle state */
1825 set_current_state(TASK_UNINTERRUPTIBLE);
1826 add_wait_queue(&chip->wq, &wait);
1828 spin_unlock(chip->mutex);
1832 remove_wait_queue(&chip->wq, &wait);
1838 /* Unlock the chips again */
1840 for (i--; i >=0; i--) {
1841 chip = &cfi->chips[i];
1843 spin_lock(chip->mutex);
1845 if (chip->state == FL_SYNCING) {
1846 chip->state = chip->oldstate;
1849 spin_unlock(chip->mutex);
1854 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1856 struct map_info *map = mtd->priv;
1857 struct cfi_private *cfi = map->fldrv_priv;
1859 struct flchip *chip;
1862 for (i=0; !ret && i<cfi->numchips; i++) {
1863 chip = &cfi->chips[i];
1865 spin_lock(chip->mutex);
1867 switch(chip->state) {
1871 case FL_JEDEC_QUERY:
1872 chip->oldstate = chip->state;
1873 chip->state = FL_PM_SUSPENDED;
1874 /* No need to wake_up() on this state change -
1875 * as the whole point is that nobody can do anything
1876 * with the chip now anyway.
1878 case FL_PM_SUSPENDED:
1885 spin_unlock(chip->mutex);
1888 /* Unlock the chips again */
1891 for (i--; i >=0; i--) {
1892 chip = &cfi->chips[i];
1894 spin_lock(chip->mutex);
1896 if (chip->state == FL_PM_SUSPENDED) {
1897 chip->state = chip->oldstate;
1900 spin_unlock(chip->mutex);
1908 static void cfi_amdstd_resume(struct mtd_info *mtd)
1910 struct map_info *map = mtd->priv;
1911 struct cfi_private *cfi = map->fldrv_priv;
1913 struct flchip *chip;
1915 for (i=0; i<cfi->numchips; i++) {
1917 chip = &cfi->chips[i];
1919 spin_lock(chip->mutex);
1921 if (chip->state == FL_PM_SUSPENDED) {
1922 chip->state = FL_READY;
1923 map_write(map, CMD(0xF0), chip->start);
1927 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1929 spin_unlock(chip->mutex);
1933 static void cfi_amdstd_destroy(struct mtd_info *mtd)
1935 struct map_info *map = mtd->priv;
1936 struct cfi_private *cfi = map->fldrv_priv;
1938 kfree(cfi->cmdset_priv);
1941 kfree(mtd->eraseregions);
1944 MODULE_LICENSE("GPL");
1945 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1946 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");