2 * linux/drivers/media/mmc/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/config.h>
16 // #define CONFIG_MMC_DEBUG
17 #ifdef CONFIG_MMC_DEBUG
18 #define DEBUG /* for dev_dbg(), pr_debug(), etc */
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/platform_device.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/delay.h>
29 #include <linux/spinlock.h>
30 #include <linux/timer.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/protocol.h>
33 #include <linux/mmc/card.h>
37 #include <asm/scatterlist.h>
38 #include <asm/mach-types.h>
40 #include <asm/arch/board.h>
41 #include <asm/arch/gpio.h>
42 #include <asm/arch/dma.h>
43 #include <asm/arch/mux.h>
44 #include <asm/arch/fpga.h>
45 #include <asm/arch/tps65010.h>
46 #include <asm/arch/menelaus.h>
48 #include <asm/hardware/clock.h>
52 #define DRIVER_NAME "mmci-omap"
54 #ifdef CONFIG_MMC_DEBUG
55 #define DBG(x...) pr_debug(x)
56 //#define DBG(x...) printk(x)
58 #define DBG(x...) do { } while (0)
61 /* Specifies how often in millisecs to poll for card status changes
62 * when the cover switch is open */
63 #define OMAP_MMC_SWITCH_POLL_DELAY 500
65 static int mmc_omap_enable_poll = 1;
67 struct mmc_omap_host {
70 struct mmc_request * mrq;
71 struct mmc_command * cmd;
72 struct mmc_data * data;
73 struct mmc_host * mmc;
75 unsigned char id; /* 16xx chips have 2 MMC blocks */
80 unsigned char bus_mode;
81 unsigned char hw_bus_mode;
86 u32 buffer_bytes_left;
90 unsigned brs_received:1, dma_done:1;
91 unsigned dma_is_read:1;
92 unsigned dma_in_use:1;
95 struct timer_list dma_timer;
102 struct work_struct switch_work;
103 struct timer_list switch_timer;
104 int switch_last_state;
108 mmc_omap_cover_is_open(struct mmc_omap_host *host)
110 if (host->switch_pin < 0)
112 return omap_get_gpio_datain(host->switch_pin);
116 mmc_omap_show_cover_switch(struct device *dev,
117 struct device_attribute *attr, char *buf)
119 struct mmc_omap_host *host = dev_get_drvdata(dev);
121 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" : "closed");
124 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
127 mmc_omap_show_enable_poll(struct device *dev,
128 struct device_attribute *attr, char *buf)
130 return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
134 mmc_omap_store_enable_poll(struct device *dev,
135 struct device_attribute *attr, const char *buf,
140 if (sscanf(buf, "%10d", &enable_poll) != 1)
143 if (enable_poll != mmc_omap_enable_poll) {
144 struct mmc_omap_host *host = dev_get_drvdata(dev);
146 mmc_omap_enable_poll = enable_poll;
147 if (enable_poll && host->switch_pin >= 0)
148 schedule_work(&host->switch_work);
153 static DEVICE_ATTR(enable_poll, 0664,
154 mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
157 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
163 pr_debug("MMC%d: CMD%d, argument 0x%08x%s%s%s%s\n",
164 host->id, cmd->opcode, cmd->arg,
165 (cmd->flags & MMC_RSP_SHORT) ? ", 32-bit response" : "",
166 (cmd->flags & MMC_RSP_LONG) ? ", 128-bit response" : "",
167 (cmd->flags & MMC_RSP_CRC) ? ", CRC" : "",
168 (cmd->flags & MMC_RSP_BUSY) ? ", busy notification" : "");
176 * On 24xx we may have external MMC transceiver on Menelaus.
177 * In that case we need to manually toggle between open-drain
178 * and push-pull states.
180 if (omap_has_menelaus() && (host->bus_mode != host->hw_bus_mode)) {
181 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
182 menelaus_mmc_opendrain(1);
184 menelaus_mmc_opendrain(0);
185 host->hw_bus_mode = host->bus_mode;
188 /* Protocol layer does not provide response type,
189 * but our hardware needs to know exact type, not just size!
191 switch (cmd->flags & MMC_RSP_MASK) {
196 /* resp 1, resp 1b */
197 /* OR resp 3!! (assume this if bus is set opendrain) */
198 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
209 /* Protocol layer does not provide command type, but our hardware
211 * any data transfer means adtc type (but that information is not
212 * in command structure, so we flagged it into host struct.)
213 * However, telling bc, bcr and ac apart based on response is
215 * CMD0 = bc = resp0 CMD15 = ac = resp0
216 * CMD2 = bcr = resp2 CMD10 = ac = resp2
218 * Resolve to best guess with some exception testing:
219 * resp0 -> bc, except CMD15 = ac
220 * rest are ac, except if opendrain
223 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
224 } else if (resptype == 0 && cmd->opcode != 15) {
225 cmdtype = OMAP_MMC_CMDTYPE_BC;
226 } else if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) {
227 cmdtype = OMAP_MMC_CMDTYPE_BCR;
229 cmdtype = OMAP_MMC_CMDTYPE_AC;
232 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
234 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
237 if (cmd->flags & MMC_RSP_BUSY)
240 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
245 OMAP_MMC_WRITE(host->base, CTO, 200);
246 OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff);
247 OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16);
248 OMAP_MMC_WRITE(host->base, IE,
249 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
250 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
251 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
252 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
253 OMAP_MMC_STAT_END_OF_DATA);
254 OMAP_MMC_WRITE(host->base, CMD, cmdreg);
258 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
260 if (host->dma_in_use) {
261 enum dma_data_direction dma_data_dir;
263 BUG_ON(host->dma_ch < 0);
264 if (data->error != MMC_ERR_NONE)
265 omap_stop_dma(host->dma_ch);
266 /* Release DMA channel lazily */
267 mod_timer(&host->dma_timer, jiffies + HZ);
268 if (data->flags & MMC_DATA_WRITE)
269 dma_data_dir = DMA_TO_DEVICE;
271 dma_data_dir = DMA_FROM_DEVICE;
272 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
277 clk_unuse(host->fclk);
279 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
280 * dozens of requests until the card finishes writing data.
281 * It'd be cheaper to just wait till an EOFB interrupt arrives...
286 mmc_request_done(host->mmc, data->mrq);
290 mmc_omap_start_command(host, data->stop);
294 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
299 if (!host->dma_in_use) {
300 mmc_omap_xfer_done(host, data);
304 spin_lock_irqsave(&host->dma_lock, flags);
308 host->brs_received = 1;
309 spin_unlock_irqrestore(&host->dma_lock, flags);
311 mmc_omap_xfer_done(host, data);
315 mmc_omap_dma_timer(unsigned long data)
317 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
319 DBG("MMC%d: Freeing DMA channel %d\n", host->id, host->dma_ch);
320 BUG_ON(host->dma_ch < 0);
321 omap_free_dma(host->dma_ch);
326 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
332 spin_lock_irqsave(&host->dma_lock, flags);
333 if (host->brs_received)
337 spin_unlock_irqrestore(&host->dma_lock, flags);
339 mmc_omap_xfer_done(host, data);
343 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
347 switch (cmd->flags & MMC_RSP_MASK) {
352 /* response types 1, 1b, 3, 4, 5, 6 */
354 OMAP_MMC_READ(host->base, RSP6) |
355 (OMAP_MMC_READ(host->base, RSP7) << 16);
356 DBG("MMC%d: Response %08x\n", host->id, cmd->resp[0]);
359 /* response type 2 */
361 OMAP_MMC_READ(host->base, RSP0) |
362 (OMAP_MMC_READ(host->base, RSP1) << 16);
364 OMAP_MMC_READ(host->base, RSP2) |
365 (OMAP_MMC_READ(host->base, RSP3) << 16);
367 OMAP_MMC_READ(host->base, RSP4) |
368 (OMAP_MMC_READ(host->base, RSP5) << 16);
370 OMAP_MMC_READ(host->base, RSP6) |
371 (OMAP_MMC_READ(host->base, RSP7) << 16);
372 DBG("MMC%d: Response %08x %08x %08x %08x\n", host->id,
373 cmd->resp[0], cmd->resp[1],
374 cmd->resp[2], cmd->resp[3]);
378 if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
379 DBG("MMC%d: End request, err %x\n", host->id, cmd->error);
381 clk_unuse(host->fclk);
382 mmc_request_done(host->mmc, cmd->mrq);
388 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
390 struct scatterlist *sg;
392 sg = host->data->sg + host->sg_idx;
393 host->buffer_bytes_left = sg->length;
394 host->buffer = page_address(sg->page) + sg->offset;
395 if (host->buffer_bytes_left > host->total_bytes_left)
396 host->buffer_bytes_left = host->total_bytes_left;
401 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
407 if (host->buffer_bytes_left == 0) {
409 BUG_ON(host->sg_idx == host->sg_len);
410 mmc_omap_sg_to_buf(host);
413 if (n > host->buffer_bytes_left)
414 n = host->buffer_bytes_left;
415 host->buffer_bytes_left -= n;
416 host->total_bytes_left -= n;
417 host->data->bytes_xfered += n;
419 /* Optimize the loop a bit by calculating the register only
421 reg = host->base + OMAP_MMC_REG_DATA;
426 __raw_writew(*p++, reg);
429 *p++ = __raw_readw(reg);
434 static inline void mmc_omap_report_irq(u16 status)
436 static const char *mmc_omap_status_bits[] = {
437 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
438 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
442 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
443 if (status & (1 << i)) {
446 printk("%s", mmc_omap_status_bits[i]);
451 static irqreturn_t mmc_omap_irq(int irq, void *dev_id, struct pt_regs *regs)
453 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
459 if (host->cmd == NULL && host->data == NULL) {
460 status = OMAP_MMC_READ(host->base, STAT);
461 printk(KERN_INFO "MMC%d: Spurious interrupt 0x%04x\n", host->id, status);
463 OMAP_MMC_WRITE(host->base, STAT, status);
464 OMAP_MMC_WRITE(host->base, IE, 0);
473 while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) {
474 OMAP_MMC_WRITE(host->base, STAT, status); // Reset status bits
475 #ifdef CONFIG_MMC_DEBUG
476 printk(KERN_DEBUG "\tMMC IRQ %04x (CMD %d): ", status,
477 host->cmd != NULL ? host->cmd->opcode : -1);
478 mmc_omap_report_irq(status);
481 if (host->total_bytes_left) {
482 if ((status & OMAP_MMC_STAT_A_FULL) ||
483 (status & OMAP_MMC_STAT_END_OF_DATA))
484 mmc_omap_xfer_data(host, 0);
485 if (status & OMAP_MMC_STAT_A_EMPTY)
486 mmc_omap_xfer_data(host, 1);
489 if (status & OMAP_MMC_STAT_END_OF_DATA) {
490 // Block sent/received
494 if (status & OMAP_MMC_STAT_DATA_TOUT) {
496 printk(KERN_DEBUG "MMC%d: Data timeout\n", host->id);
498 host->data->error |= MMC_ERR_TIMEOUT;
503 if (status & OMAP_MMC_STAT_DATA_CRC) {
506 host->data->error |= MMC_ERR_BADCRC;
507 printk(KERN_DEBUG "MMC%d: Data CRC error, bytes left %d\n",
508 host->id, host->total_bytes_left);
511 printk(KERN_DEBUG "MMC%d: Data CRC error\n",
516 if (status & OMAP_MMC_STAT_CMD_TOUT) {
517 /* Timeouts are routine with some commands */
519 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
520 host->cmd->opcode != MMC_SEND_OP_COND &&
521 host->cmd->opcode != MMC_APP_CMD &&
522 !mmc_omap_cover_is_open(host))
523 printk(KERN_ERR "MMC%d: Command timeout, CMD%d\n",
524 host->id, host->cmd->opcode);
525 host->cmd->error |= MMC_ERR_TIMEOUT;
530 if (status & OMAP_MMC_STAT_CMD_CRC) {
533 printk(KERN_ERR "MMC%d: Command CRC error (CMD%d, arg 0x%08x)\n",
534 host->id, host->cmd->opcode,
536 host->cmd->error |= MMC_ERR_BADCRC;
539 printk(KERN_ERR "MMC%d: Command CRC error without cmd?\n", host->id);
542 if (status & OMAP_MMC_STAT_OCR_BUSY) {
543 /* OCR Busy ... happens a lot */
544 if (host->cmd && host->cmd->opcode != MMC_SEND_OP_COND
545 && host->cmd->opcode != MMC_SET_RELATIVE_ADDR) {
546 DBG("MMC%d: OCR busy error, CMD%d\n",
547 host->id, host->cmd->opcode);
551 if (status & OMAP_MMC_STAT_CARD_ERR) {
552 if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
553 u32 response = OMAP_MMC_READ(host->base, RSP6)
554 | (OMAP_MMC_READ(host->base, RSP7) << 16);
555 /* STOP sometimes sets must-ignore bits */
556 if (!(response & (R1_CC_ERROR
558 | R1_COM_CRC_ERROR))) {
565 printk(KERN_DEBUG "MMC%d: Card status error (CMD%d)\n",
566 host->id, host->cmd->opcode);
568 host->cmd->error |= MMC_ERR_FAILED;
572 host->data->error |= MMC_ERR_FAILED;
578 * NOTE: On 1610 the END_OF_CMD may come too early when
581 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
582 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
583 // End of command phase
589 mmc_omap_cmd_done(host, host->cmd);
592 mmc_omap_xfer_done(host, host->data);
593 else if (end_transfer)
594 mmc_omap_end_of_data(host, host->data);
599 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id, struct pt_regs *regs)
601 struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
603 DBG("MMC%d cover is now %s\n", host->id,
604 omap_get_gpio_datain(host->switch_pin) ? "open" : "closed");
605 schedule_work(&host->switch_work);
610 static void mmc_omap_switch_timer(unsigned long arg)
612 struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
614 schedule_work(&host->switch_work);
617 /* FIXME: Handle card insertion and removal properly. Maybe use a mask
619 static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
621 if (machine_is_omap_h4()) {
623 printk("XXX card in slot 1\n");
625 printk("XXX card in slot 2\n");
627 /* Assume card detect connected to cover switch */
629 printk("XXX cover open\n");
631 printk("XXX cover closed\n");
635 static void mmc_omap_switch_handler(void *data)
637 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
638 struct mmc_card *card;
639 static int complained = 0;
640 int cards = 0, cover_open;
642 if (host->switch_pin == -1)
644 cover_open = mmc_omap_cover_is_open(host);
645 if (cover_open != host->switch_last_state) {
646 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE, &dev_attr_cover_switch.attr);
647 host->switch_last_state = cover_open;
649 DBG("MMC cover switch handler started\n");
650 mmc_detect_change(host->mmc, 0);
651 list_for_each_entry(card, &host->mmc->cards, node) {
652 if (mmc_card_present(card))
655 DBG("MMC%d: %d card(s) present\n", host->id, cards);
656 if (mmc_omap_cover_is_open(host)) {
658 printk(KERN_INFO "MMC%d: cover is open\n", host->id);
661 if (mmc_omap_enable_poll)
662 mod_timer(&host->switch_timer, jiffies +
663 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
669 /* prepare to transfer the next segment of a scatterlist */
671 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
673 int dma_ch = host->dma_ch;
674 unsigned long data_addr;
677 struct scatterlist *sg = &data->sg[host->sg_idx];
682 data_addr = io_v2p((void __force *) host->base) + OMAP_MMC_REG_DATA;
683 frame = 1 << data->blksz_bits;
684 count = (u32)sg_dma_len(sg);
686 /* the MMC layer is confused about single block writes... */
687 if ((data->blocks == 1) && (count > (1 << data->blksz_bits))) {
688 pr_debug("patch bogus single block length! %d > %d\n",
692 host->dma_len = count;
694 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
695 * Use 16 or 32 word frames when the blocksize is at least that large.
696 * Blocksize is usually 512 bytes; but not for some SD reads.
698 if (cpu_is_omap15xx() && frame > 32)
705 if (!(data->flags & MMC_DATA_WRITE)) {
706 buf = 0x800f | ((frame - 1) << 8);
708 if (cpu_class_is_omap1()) {
709 src_port = OMAP_DMA_PORT_TIPB;
710 dst_port = OMAP_DMA_PORT_EMIFF;
712 if (cpu_is_omap24xx())
713 sync_dev = OMAP24XX_DMA_MMC1_RX;
715 omap_set_dma_src_params(dma_ch, src_port,
716 OMAP_DMA_AMODE_CONSTANT,
718 omap_set_dma_dest_params(dma_ch, dst_port,
719 OMAP_DMA_AMODE_POST_INC,
720 sg_dma_address(sg), 0, 0);
721 omap_set_dma_dest_data_pack(dma_ch, 1);
722 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
724 buf = 0x0f80 | ((frame - 1) << 0);
726 if (cpu_class_is_omap1()) {
727 src_port = OMAP_DMA_PORT_EMIFF;
728 dst_port = OMAP_DMA_PORT_TIPB;
730 if (cpu_is_omap24xx())
731 sync_dev = OMAP24XX_DMA_MMC1_TX;
733 omap_set_dma_dest_params(dma_ch, dst_port,
734 OMAP_DMA_AMODE_CONSTANT,
736 omap_set_dma_src_params(dma_ch, src_port,
737 OMAP_DMA_AMODE_POST_INC,
738 sg_dma_address(sg), 0, 0);
739 omap_set_dma_src_data_pack(dma_ch, 1);
740 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
743 /* Max limit for DMA frame count is 0xffff */
744 if (unlikely(count > 0xffff))
747 OMAP_MMC_WRITE(host->base, BUF, buf);
748 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
749 frame, count, OMAP_DMA_SYNC_FRAME,
753 /* a scatterlist segment completed */
754 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
756 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
757 struct mmc_data *mmcdat = host->data;
759 if (unlikely(host->dma_ch < 0)) {
760 printk(KERN_ERR "MMC%d: DMA callback while DMA not enabled\n",
764 /* FIXME: We really should do something to _handle_ the errors */
765 if (ch_status & OMAP_DMA_TOUT_IRQ) {
766 printk(KERN_ERR "MMC%d: DMA timeout\n", host->id);
769 if (ch_status & OMAP_DMA_DROP_IRQ) {
770 printk(KERN_ERR "MMC%d: DMA sync error\n", host->id);
773 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
774 /* REVISIT we should be able to avoid getting IRQs with
775 * just SYNC status ...
777 if ((ch_status & ~OMAP1_DMA_SYNC_IRQ))
778 pr_debug("MMC%d: DMA channel status: %04x\n",
779 host->id, ch_status);
782 mmcdat->bytes_xfered += host->dma_len;
784 pr_debug("\tMMC DMA %d bytes CB %04x (%d segments to go), %p\n",
785 host->dma_len, ch_status,
786 host->sg_len - host->sg_idx - 1, host->data);
789 if (host->sg_idx < host->sg_len) {
790 mmc_omap_prepare_dma(host, host->data);
791 omap_start_dma(host->dma_ch);
793 mmc_omap_dma_done(host, host->data);
796 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
798 const char *dev_name;
799 int sync_dev, dma_ch, is_read, r;
801 is_read = !(data->flags & MMC_DATA_WRITE);
802 del_timer_sync(&host->dma_timer);
803 if (host->dma_ch >= 0) {
804 if (is_read == host->dma_is_read)
806 omap_free_dma(host->dma_ch);
812 sync_dev = OMAP_DMA_MMC_RX;
813 dev_name = "MMC1 read";
815 sync_dev = OMAP_DMA_MMC2_RX;
816 dev_name = "MMC2 read";
820 sync_dev = OMAP_DMA_MMC_TX;
821 dev_name = "MMC1 write";
823 sync_dev = OMAP_DMA_MMC2_TX;
824 dev_name = "MMC2 write";
827 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
830 printk("MMC%d: omap_request_dma() failed with %d\n",
834 host->dma_ch = dma_ch;
835 host->dma_is_read = is_read;
840 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
844 reg = OMAP_MMC_READ(host->base, SDIO);
846 OMAP_MMC_WRITE(host->base, SDIO, reg);
847 /* Set maximum timeout */
848 OMAP_MMC_WRITE(host->base, CTO, 0xff);
851 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
856 /* Convert ns to clock cycles by assuming 20MHz frequency
857 * 1 cycle at 20MHz = 500 ns
859 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
861 /* Some cards require more time to do at least the first read operation */
862 timeout = timeout << 4;
864 /* Check if we need to use timeout multiplier register */
865 reg = OMAP_MMC_READ(host->base, SDIO);
866 if (timeout > 0xffff) {
871 OMAP_MMC_WRITE(host->base, SDIO, reg);
872 OMAP_MMC_WRITE(host->base, DTO, timeout);
876 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
878 struct mmc_data *data = req->data;
879 int i, use_dma, block_size;
884 OMAP_MMC_WRITE(host->base, BLEN, 0);
885 OMAP_MMC_WRITE(host->base, NBLK, 0);
886 OMAP_MMC_WRITE(host->base, BUF, 0);
887 host->dma_in_use = 0;
888 set_cmd_timeout(host, req);
893 block_size = 1 << data->blksz_bits;
895 OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1);
896 OMAP_MMC_WRITE(host->base, BLEN, block_size - 1);
897 set_data_timeout(host, req);
899 /* cope with calling layer confusion; it issues "single
900 * block" writes using multi-block scatterlists.
902 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
904 /* Only do DMA for entire blocks */
905 use_dma = host->use_dma;
907 for (i = 0; i < sg_len; i++) {
908 if ((data->sg[i].length % block_size) != 0) {
917 if (mmc_omap_get_dma_channel(host, data) == 0) {
918 enum dma_data_direction dma_data_dir;
920 if (data->flags & MMC_DATA_WRITE)
921 dma_data_dir = DMA_TO_DEVICE;
923 dma_data_dir = DMA_FROM_DEVICE;
925 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
926 sg_len, dma_data_dir);
927 host->total_bytes_left = 0;
928 mmc_omap_prepare_dma(host, req->data);
929 host->brs_received = 0;
931 host->dma_in_use = 1;
938 OMAP_MMC_WRITE(host->base, BUF, 0x1f1f);
939 host->total_bytes_left = data->blocks * block_size;
940 host->sg_len = sg_len;
941 mmc_omap_sg_to_buf(host);
942 host->dma_in_use = 0;
945 pr_debug("MMC%d: %s %s %s, DTO %d cycles + %d ns, "
946 "%d blocks of %d bytes, %d segments\n",
947 host->id, use_dma ? "DMA" : "PIO",
948 (data->flags & MMC_DATA_STREAM) ? "stream" : "block",
949 (data->flags & MMC_DATA_WRITE) ? "write" : "read",
950 data->timeout_clks, data->timeout_ns, data->blocks,
951 block_size, host->sg_len);
954 static inline int is_broken_card(struct mmc_card *card)
957 struct mmc_cid *c = &card->cid;
958 static const struct broken_card_cid {
964 { 0x00150000, "\x30\x30\x30\x30\x30\x30\x15\x00", 0x06, 0x03 },
967 for (i = 0; i < sizeof(broken_cards)/sizeof(broken_cards[0]); i++) {
968 const struct broken_card_cid *b = broken_cards + i;
970 if (b->manfid != c->manfid)
972 if (memcmp(b->prod_name, c->prod_name, sizeof(b->prod_name)) != 0)
974 if (b->hwrev != c->hwrev || b->fwrev != c->fwrev)
981 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
983 struct mmc_omap_host *host = mmc_priv(mmc);
985 WARN_ON(host->mrq != NULL);
989 /* Some cards (vendor left unnamed to protect the guilty) seem to
990 * require this delay after power-up. Otherwise we'll get mysterious
992 if (req->cmd->opcode == MMC_SEND_CSD) {
993 struct mmc_card *card;
994 int broken_present = 0;
996 list_for_each_entry(card, &mmc->cards, node) {
997 if (is_broken_card(card)) {
1002 if (broken_present) {
1003 static int complained = 0;
1006 printk(KERN_WARNING "MMC%d: Broken card workaround enabled\n",
1010 if (in_interrupt()) {
1012 printk(KERN_ERR "Sleeping in IRQ handler, FIXME please!\n");
1016 set_current_state(TASK_UNINTERRUPTIBLE);
1017 schedule_timeout(100 * HZ / 1000);
1022 /* only touch fifo AFTER the controller readies it */
1023 mmc_omap_prepare_data(host, req);
1024 mmc_omap_start_command(host, req->cmd);
1025 if (host->dma_in_use)
1026 omap_start_dma(host->dma_ch);
1029 static void innovator_fpga_socket_power(int on)
1031 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
1034 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
1035 OMAP1510_FPGA_POWER);
1037 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
1038 OMAP1510_FPGA_POWER);
1044 * Turn the socket power on/off. Innovator uses FPGA, most boards
1045 * probably use GPIO.
1047 static void mmc_omap_power(struct mmc_omap_host *host, int on)
1050 if (machine_is_omap_innovator())
1051 innovator_fpga_socket_power(1);
1052 else if (machine_is_omap_h2())
1053 tps65010_set_gpio_out_value(GPIO3, HIGH);
1054 else if (machine_is_omap_h3())
1055 /* GPIO 4 of TPS65010 sends SD_EN signal */
1056 tps65010_set_gpio_out_value(GPIO4, HIGH);
1057 else if (cpu_is_omap24xx()) {
1058 u16 reg = OMAP_MMC_READ(host->base, CON);
1059 OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11));
1061 if (host->power_pin >= 0)
1062 omap_set_gpio_dataout(host->power_pin, 1);
1064 if (machine_is_omap_innovator())
1065 innovator_fpga_socket_power(0);
1066 else if (machine_is_omap_h2())
1067 tps65010_set_gpio_out_value(GPIO3, LOW);
1068 else if (machine_is_omap_h3())
1069 tps65010_set_gpio_out_value(GPIO4, LOW);
1070 else if (cpu_is_omap24xx()) {
1071 u16 reg = OMAP_MMC_READ(host->base, CON);
1072 OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11));
1074 if (host->power_pin >= 0)
1075 omap_set_gpio_dataout(host->power_pin, 0);
1079 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1081 struct mmc_omap_host *host = mmc_priv(mmc);
1085 DBG("MMC%d: set_ios: clock %dHz busmode %d powermode %d Vdd %d.%02d\n",
1086 host->id, ios->clock, ios->bus_mode, ios->power_mode,
1087 ios->vdd / 100, ios->vdd % 100);
1089 if (ios->power_mode == MMC_POWER_UP && ios->clock < 400000)
1090 realclock = 400000; /* Fix for broken stack */
1092 realclock = ios->clock;
1094 if (ios->clock == 0)
1097 int func_clk_rate = clk_get_rate(host->fclk);
1099 dsor = func_clk_rate / realclock;
1103 if (func_clk_rate / dsor > realclock)
1110 if (ios->bus_width == MMC_BUS_WIDTH_4)
1114 switch (ios->power_mode) {
1116 mmc_omap_power(host, 0);
1120 mmc_omap_power(host, 1);
1125 host->bus_mode = ios->bus_mode;
1126 if (omap_has_menelaus()) {
1127 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
1128 menelaus_mmc_opendrain(1);
1130 menelaus_mmc_opendrain(0);
1132 host->hw_bus_mode = host->bus_mode;
1134 clk_use(host->fclk);
1136 /* On insanely high arm_per frequencies something sometimes
1137 * goes somehow out of sync, and the POW bit is not being set,
1138 * which results in the while loop below getting stuck.
1139 * Writing to the CON register twice seems to do the trick. */
1140 for (i = 0; i < 2; i++)
1141 OMAP_MMC_WRITE(host->base, CON, dsor);
1142 if (ios->power_mode == MMC_POWER_UP) {
1143 /* Send clock cycles, poll completion */
1144 OMAP_MMC_WRITE(host->base, IE, 0);
1145 OMAP_MMC_WRITE(host->base, STAT, 0xffff);
1146 OMAP_MMC_WRITE(host->base, CMD, 1<<7);
1147 while (0 == (OMAP_MMC_READ(host->base, STAT) & 1));
1148 OMAP_MMC_WRITE(host->base, STAT, 1);
1150 clk_unuse(host->fclk);
1153 static int mmc_omap_get_ro(struct mmc_host *mmc)
1155 struct mmc_omap_host *host = mmc_priv(mmc);
1157 return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1160 static struct mmc_host_ops mmc_omap_ops = {
1161 .request = mmc_omap_request,
1162 .set_ios = mmc_omap_set_ios,
1163 .get_ro = mmc_omap_get_ro,
1166 static int __init mmc_omap_probe(struct platform_device *pdev)
1168 struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1169 struct mmc_host *mmc;
1170 struct mmc_omap_host *host = NULL;
1173 if (pdev->resource[0].flags != IORESOURCE_MEM
1174 || pdev->resource[1].flags != IORESOURCE_IRQ) {
1175 printk(KERN_ERR "mmc_omap_probe: invalid resource type\n");
1179 if (!request_mem_region(pdev->resource[0].start,
1180 pdev->resource[0].end - pdev->resource[0].start + 1,
1182 dev_dbg(&pdev->dev, "request_mem_region failed\n");
1186 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1192 host = mmc_priv(mmc);
1195 spin_lock_init(&host->dma_lock);
1196 init_timer(&host->dma_timer);
1197 host->dma_timer.function = mmc_omap_dma_timer;
1198 host->dma_timer.data = (unsigned long) host;
1200 host->id = pdev->id;
1202 if (cpu_is_omap24xx()) {
1203 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1204 if (IS_ERR(host->iclk))
1206 clk_use(host->iclk);
1209 if (!cpu_is_omap24xx())
1210 host->fclk = clk_get(&pdev->dev,
1211 (host->id == 1) ? "mmc1_ck" : "mmc2_ck");
1213 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1215 if (IS_ERR(host->fclk)) {
1216 ret = PTR_ERR(host->fclk);
1221 * Also, use minfo->cover to decide how to manage
1222 * the card detect sensing.
1224 host->power_pin = minfo->power_pin;
1225 host->switch_pin = minfo->switch_pin;
1226 host->wp_pin = minfo->wp_pin;
1230 host->irq = pdev->resource[1].start;
1231 host->base = (void __iomem *)pdev->resource[0].start;
1234 mmc->caps |= MMC_CAP_4_BIT_DATA;
1236 mmc->ops = &mmc_omap_ops;
1237 mmc->f_min = 400000;
1238 mmc->f_max = 24000000;
1239 mmc->ocr_avail = MMC_VDD_33_34;
1241 /* Use scatterlist DMA to reduce per-transfer costs.
1242 * NOTE max_seg_size assumption that small blocks aren't
1243 * normally used (except e.g. for reading SD registers).
1245 mmc->max_phys_segs = 32;
1246 mmc->max_hw_segs = 32;
1247 mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
1248 mmc->max_seg_size = mmc->max_sectors * 512;
1250 if (host->power_pin >= 0) {
1251 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1252 printk(KERN_ERR "MMC%d: Unable to get GPIO pin for MMC power\n",
1256 omap_set_gpio_direction(host->power_pin, 0);
1259 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1263 host->dev = &pdev->dev;
1264 platform_set_drvdata(pdev, host);
1268 if (host->switch_pin >= 0) {
1269 INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
1270 init_timer(&host->switch_timer);
1271 host->switch_timer.function = mmc_omap_switch_timer;
1272 host->switch_timer.data = (unsigned long) host;
1273 if (omap_request_gpio(host->switch_pin) != 0) {
1274 printk(KERN_WARNING "MMC%d: Unable to get GPIO pin for MMC cover switch\n",
1276 host->switch_pin = -1;
1280 omap_set_gpio_direction(host->switch_pin, 1);
1281 set_irq_type(OMAP_GPIO_IRQ(host->switch_pin), IRQT_RISING);
1282 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1283 mmc_omap_switch_irq, 0, DRIVER_NAME, host);
1285 printk(KERN_WARNING "MMC%d: Unable to get IRQ for MMC cover switch\n",
1287 omap_free_gpio(host->switch_pin);
1288 host->switch_pin = -1;
1291 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1293 ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1295 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1298 printk(KERN_WARNING "MMC%d: Unable to create sysfs attributes\n",
1300 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1301 omap_free_gpio(host->switch_pin);
1302 host->switch_pin = -1;
1305 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1306 schedule_work(&host->switch_work);
1309 if (omap_has_menelaus())
1310 menelaus_mmc_register(mmc_omap_switch_callback, &host);
1316 /* FIXME: Free other resources too. */
1318 if (host->iclk && !IS_ERR(host->iclk))
1319 clk_put(host->iclk);
1320 if (host->fclk && !IS_ERR(host->fclk))
1321 clk_put(host->fclk);
1322 mmc_free_host(host->mmc);
1327 static int mmc_omap_remove(struct platform_device *pdev)
1329 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1331 platform_set_drvdata(pdev, NULL);
1334 mmc_remove_host(host->mmc);
1335 free_irq(host->irq, host);
1336 mmc_omap_power(host, 0);
1338 if (host->power_pin >= 0)
1339 omap_free_gpio(host->power_pin);
1340 if (host->switch_pin >= 0) {
1341 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1342 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1343 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1344 omap_free_gpio(host->switch_pin);
1345 host->switch_pin = -1;
1346 del_timer_sync(&host->switch_timer);
1347 flush_scheduled_work();
1349 if (host->iclk && !IS_ERR(host->iclk))
1350 clk_put(host->iclk);
1351 if (host->fclk && !IS_ERR(host->fclk))
1352 clk_put(host->fclk);
1353 mmc_free_host(host->mmc);
1356 if (omap_has_menelaus())
1357 menelaus_mmc_remove();
1359 release_mem_region(pdev->resource[0].start,
1360 pdev->resource[0].end - pdev->resource[0].start + 1);
1366 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1369 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1371 if (host && host->suspended)
1374 if (!irqs_disabled())
1378 ret = mmc_suspend_host(host->mmc, mesg);
1380 host->suspended = 1;
1385 static int mmc_omap_resume(struct platform_device *pdev)
1388 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1390 if (host && !host->suspended)
1394 ret = mmc_resume_host(host->mmc);
1396 host->suspended = 0;
1402 #define mmc_omap_suspend NULL
1403 #define mmc_omap_resume NULL
1406 static struct platform_driver mmc_omap_driver = {
1407 .probe = mmc_omap_probe,
1408 .remove = mmc_omap_remove,
1409 .suspend = mmc_omap_suspend,
1410 .resume = mmc_omap_resume,
1412 .name = DRIVER_NAME,
1416 static int __init mmc_omap_init(void)
1418 return platform_driver_register(&mmc_omap_driver);
1421 static void __exit mmc_omap_exit(void)
1423 platform_driver_unregister(&mmc_omap_driver);
1426 module_init(mmc_omap_init);
1427 module_exit(mmc_omap_exit);
1429 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1430 MODULE_LICENSE("GPL");
1431 MODULE_ALIAS(DRIVER_NAME);
1432 MODULE_AUTHOR("Juha Yrjölä");