drivers/mmc/omap.c

   1 /*
   2  *  linux/drivers/media/mmc/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/protocol.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/scatterlist.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39 #include <asm/arch/tps65010.h>
  40 #include <asm/arch/board-sx1.h>
  41
  42 #define OMAP_MMC_REG_CMD        0x00
  43 #define OMAP_MMC_REG_ARGL       0x04
  44 #define OMAP_MMC_REG_ARGH       0x08
  45 #define OMAP_MMC_REG_CON        0x0c
  46 #define OMAP_MMC_REG_STAT       0x10
  47 #define OMAP_MMC_REG_IE         0x14
  48 #define OMAP_MMC_REG_CTO        0x18
  49 #define OMAP_MMC_REG_DTO        0x1c
  50 #define OMAP_MMC_REG_DATA       0x20
  51 #define OMAP_MMC_REG_BLEN       0x24
  52 #define OMAP_MMC_REG_NBLK       0x28
  53 #define OMAP_MMC_REG_BUF        0x2c
  54 #define OMAP_MMC_REG_SDIO       0x34
  55 #define OMAP_MMC_REG_REV        0x3c
  56 #define OMAP_MMC_REG_RSP0       0x40
  57 #define OMAP_MMC_REG_RSP1       0x44
  58 #define OMAP_MMC_REG_RSP2       0x48
  59 #define OMAP_MMC_REG_RSP3       0x4c
  60 #define OMAP_MMC_REG_RSP4       0x50
  61 #define OMAP_MMC_REG_RSP5       0x54
  62 #define OMAP_MMC_REG_RSP6       0x58
  63 #define OMAP_MMC_REG_RSP7       0x5c
  64 #define OMAP_MMC_REG_IOSR       0x60
  65 #define OMAP_MMC_REG_SYSC       0x64
  66 #define OMAP_MMC_REG_SYSS       0x68
  67
  68 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  69 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  70 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  71 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  72 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  73 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  74 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  75 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  76 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  77 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  78 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  79 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  80 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  81
  82 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  83 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  84
  85 /*
  86  * Command types
  87  */
  88 #define OMAP_MMC_CMDTYPE_BC     0
  89 #define OMAP_MMC_CMDTYPE_BCR    1
  90 #define OMAP_MMC_CMDTYPE_AC     2
  91 #define OMAP_MMC_CMDTYPE_ADTC   3
  92
  93
  94 #define DRIVER_NAME "mmci-omap"
  95
  96 /* Specifies how often in millisecs to poll for card status changes
  97  * when the cover switch is open */
  98 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  99
 100 static int mmc_omap_enable_poll = 1;
 101
 102 struct mmc_omap_host {
 103         int                     initialized;
 104         int                     suspended;
 105         struct mmc_request *    mrq;
 106         struct mmc_command *    cmd;
 107         struct mmc_data *       data;
 108         struct mmc_host *       mmc;
 109         struct device *         dev;
 110         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 111         struct clk *            iclk;
 112         struct clk *            fclk;
 113         struct resource         *mem_res;
 114         void __iomem            *virt_base;
 115         unsigned int            phys_base;
 116         int                     irq;
 117         unsigned char           bus_mode;
 118         unsigned char           hw_bus_mode;
 119
 120         unsigned int            sg_len;
 121         int                     sg_idx;
 122         u16 *                   buffer;
 123         u32                     buffer_bytes_left;
 124         u32                     total_bytes_left;
 125
 126         unsigned                use_dma:1;
 127         unsigned                brs_received:1, dma_done:1;
 128         unsigned                dma_is_read:1;
 129         unsigned                dma_in_use:1;
 130         int                     dma_ch;
 131         spinlock_t              dma_lock;
 132         struct timer_list       dma_timer;
 133         unsigned                dma_len;
 134
 135         short                   power_pin;
 136         short                   wp_pin;
 137
 138         int                     switch_pin;
 139         struct work_struct      switch_work;
 140         struct timer_list       switch_timer;
 141         int                     switch_last_state;
 142 };
 143
 144 static inline int
 145 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 146 {
 147         if (host->switch_pin < 0)
 148                 return 0;
 149         return omap_get_gpio_datain(host->switch_pin);
 150 }
 151
 152 static ssize_t
 153 mmc_omap_show_cover_switch(struct device *dev,
 154         struct device_attribute *attr, char *buf)
 155 {
 156         struct mmc_omap_host *host = dev_get_drvdata(dev);
 157
 158         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
 159                         "closed");
 160 }
 161
 162 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 163
 164 static ssize_t
 165 mmc_omap_show_enable_poll(struct device *dev,
 166         struct device_attribute *attr, char *buf)
 167 {
 168         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 169 }
 170
 171 static ssize_t
 172 mmc_omap_store_enable_poll(struct device *dev,
 173         struct device_attribute *attr, const char *buf,
 174         size_t size)
 175 {
 176         int enable_poll;
 177
 178         if (sscanf(buf, "%10d", &enable_poll) != 1)
 179                 return -EINVAL;
 180
 181         if (enable_poll != mmc_omap_enable_poll) {
 182                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 183
 184                 mmc_omap_enable_poll = enable_poll;
 185                 if (enable_poll && host->switch_pin >= 0)
 186                         schedule_work(&host->switch_work);
 187         }
 188         return size;
 189 }
 190
 191 static DEVICE_ATTR(enable_poll, 0664,
 192                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 193
 194 static void
 195 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 196 {
 197         u32 cmdreg;
 198         u32 resptype;
 199         u32 cmdtype;
 200
 201         host->cmd = cmd;
 202
 203         resptype = 0;
 204         cmdtype = 0;
 205
 206         /* Our hardware needs to know exact type */
 207         switch (mmc_resp_type(cmd)) {
 208         case MMC_RSP_NONE:
 209                 break;
 210         case MMC_RSP_R1:
 211         case MMC_RSP_R1B:
 212                 /* resp 1, 1b, 6, 7 */
 213                 resptype = 1;
 214                 break;
 215         case MMC_RSP_R2:
 216                 resptype = 2;
 217                 break;
 218         case MMC_RSP_R3:
 219                 resptype = 3;
 220                 break;
 221         default:
 222                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 223                 break;
 224         }
 225
 226         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 227                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 228         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 229                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 230         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 231                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 232         } else {
 233                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 234         }
 235
 236         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 237
 238         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 239                 cmdreg |= 1 << 6;
 240
 241         if (cmd->flags & MMC_RSP_BUSY)
 242                 cmdreg |= 1 << 11;
 243
 244         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 245                 cmdreg |= 1 << 15;
 246
 247         clk_enable(host->fclk);
 248
 249         OMAP_MMC_WRITE(host, CTO, 200);
 250         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 251         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 252         OMAP_MMC_WRITE(host, IE,
 253                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 254                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 255                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 256                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 257                        OMAP_MMC_STAT_END_OF_DATA);
 258         OMAP_MMC_WRITE(host, CMD, cmdreg);
 259 }
 260
 261 static void
 262 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 263 {
 264         if (host->dma_in_use) {
 265                 enum dma_data_direction dma_data_dir;
 266
 267                 BUG_ON(host->dma_ch < 0);
 268                 if (data->error != MMC_ERR_NONE)
 269                         omap_stop_dma(host->dma_ch);
 270                 /* Release DMA channel lazily */
 271                 mod_timer(&host->dma_timer, jiffies + HZ);
 272                 if (data->flags & MMC_DATA_WRITE)
 273                         dma_data_dir = DMA_TO_DEVICE;
 274                 else
 275                         dma_data_dir = DMA_FROM_DEVICE;
 276                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 277                              dma_data_dir);
 278         }
 279         host->data = NULL;
 280         host->sg_len = 0;
 281         clk_disable(host->fclk);
 282
 283         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 284          * dozens of requests until the card finishes writing data.
 285          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 286          */
 287
 288         if (!data->stop) {
 289                 host->mrq = NULL;
 290                 mmc_request_done(host->mmc, data->mrq);
 291                 return;
 292         }
 293
 294         mmc_omap_start_command(host, data->stop);
 295 }
 296
 297 static void
 298 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 299 {
 300         unsigned long flags;
 301         int done;
 302
 303         if (!host->dma_in_use) {
 304                 mmc_omap_xfer_done(host, data);
 305                 return;
 306         }
 307         done = 0;
 308         spin_lock_irqsave(&host->dma_lock, flags);
 309         if (host->dma_done)
 310                 done = 1;
 311         else
 312                 host->brs_received = 1;
 313         spin_unlock_irqrestore(&host->dma_lock, flags);
 314         if (done)
 315                 mmc_omap_xfer_done(host, data);
 316 }
 317
 318 static void
 319 mmc_omap_dma_timer(unsigned long data)
 320 {
 321         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 322
 323         BUG_ON(host->dma_ch < 0);
 324         omap_free_dma(host->dma_ch);
 325         host->dma_ch = -1;
 326 }
 327
 328 static void
 329 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 330 {
 331         unsigned long flags;
 332         int done;
 333
 334         done = 0;
 335         spin_lock_irqsave(&host->dma_lock, flags);
 336         if (host->brs_received)
 337                 done = 1;
 338         else
 339                 host->dma_done = 1;
 340         spin_unlock_irqrestore(&host->dma_lock, flags);
 341         if (done)
 342                 mmc_omap_xfer_done(host, data);
 343 }
 344
 345 static void
 346 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 347 {
 348         host->cmd = NULL;
 349
 350         if (cmd->flags & MMC_RSP_PRESENT) {
 351                 if (cmd->flags & MMC_RSP_136) {
 352                         /* response type 2 */
 353                         cmd->resp[3] =
 354                                 OMAP_MMC_READ(host, RSP0) |
 355                                 (OMAP_MMC_READ(host, RSP1) << 16);
 356                         cmd->resp[2] =
 357                                 OMAP_MMC_READ(host, RSP2) |
 358                                 (OMAP_MMC_READ(host, RSP3) << 16);
 359                         cmd->resp[1] =
 360                                 OMAP_MMC_READ(host, RSP4) |
 361                                 (OMAP_MMC_READ(host, RSP5) << 16);
 362                         cmd->resp[0] =
 363                                 OMAP_MMC_READ(host, RSP6) |
 364                                 (OMAP_MMC_READ(host, RSP7) << 16);
 365                 } else {
 366                         /* response types 1, 1b, 3, 4, 5, 6 */
 367                         cmd->resp[0] =
 368                                 OMAP_MMC_READ(host, RSP6) |
 369                                 (OMAP_MMC_READ(host, RSP7) << 16);
 370                 }
 371         }
 372
 373         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
 374                 host->mrq = NULL;
 375                 clk_disable(host->fclk);
 376                 mmc_request_done(host->mmc, cmd->mrq);
 377         }
 378 }
 379
 380 /* PIO only */
 381 static void
 382 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 383 {
 384         struct scatterlist *sg;
 385
 386         sg = host->data->sg + host->sg_idx;
 387         host->buffer_bytes_left = sg->length;
 388         host->buffer = page_address(sg->page) + sg->offset;
 389         if (host->buffer_bytes_left > host->total_bytes_left)
 390                 host->buffer_bytes_left = host->total_bytes_left;
 391 }
 392
 393 /* PIO only */
 394 static void
 395 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 396 {
 397         int n;
 398
 399         if (host->buffer_bytes_left == 0) {
 400                 host->sg_idx++;
 401                 BUG_ON(host->sg_idx == host->sg_len);
 402                 mmc_omap_sg_to_buf(host);
 403         }
 404         n = 64;
 405         if (n > host->buffer_bytes_left)
 406                 n = host->buffer_bytes_left;
 407         host->buffer_bytes_left -= n;
 408         host->total_bytes_left -= n;
 409         host->data->bytes_xfered += n;
 410
 411         if (write) {
 412                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 413         } else {
 414                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 415         }
 416 }
 417
 418 static inline void mmc_omap_report_irq(u16 status)
 419 {
 420         static const char *mmc_omap_status_bits[] = {
 421                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 422                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 423         };
 424         int i, c = 0;
 425
 426         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 427                 if (status & (1 << i)) {
 428                         if (c)
 429                                 printk(" ");
 430                         printk("%s", mmc_omap_status_bits[i]);
 431                         c++;
 432                 }
 433 }
 434
 435 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 436 {
 437         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 438         u16 status;
 439         int end_command;
 440         int end_transfer;
 441         int transfer_error;
 442
 443         if (host->cmd == NULL && host->data == NULL) {
 444                 status = OMAP_MMC_READ(host, STAT);
 445                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 446                 if (status != 0) {
 447                         OMAP_MMC_WRITE(host, STAT, status);
 448                         OMAP_MMC_WRITE(host, IE, 0);
 449                 }
 450                 return IRQ_HANDLED;
 451         }
 452
 453         end_command = 0;
 454         end_transfer = 0;
 455         transfer_error = 0;
 456
 457         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 458                 OMAP_MMC_WRITE(host, STAT, status);
 459 #ifdef CONFIG_MMC_DEBUG
 460                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 461                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 462                 mmc_omap_report_irq(status);
 463                 printk("\n");
 464 #endif
 465                 if (host->total_bytes_left) {
 466                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 467                             (status & OMAP_MMC_STAT_END_OF_DATA))
 468                                 mmc_omap_xfer_data(host, 0);
 469                         if (status & OMAP_MMC_STAT_A_EMPTY)
 470                                 mmc_omap_xfer_data(host, 1);
 471                 }
 472
 473                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 474                         end_transfer = 1;
 475                 }
 476
 477                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 478                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 479                         if (host->data) {
 480                                 host->data->error |= MMC_ERR_TIMEOUT;
 481                                 transfer_error = 1;
 482                         }
 483                 }
 484
 485                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 486                         if (host->data) {
 487                                 host->data->error |= MMC_ERR_BADCRC;
 488                                 dev_dbg(mmc_dev(host->mmc),
 489                                          "data CRC error, bytes left %d\n",
 490                                         host->total_bytes_left);
 491                                 transfer_error = 1;
 492                         } else {
 493                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 494                         }
 495                 }
 496
 497                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 498                         /* Timeouts are routine with some commands */
 499                         if (host->cmd) {
 500                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 501                                                 host->cmd->opcode !=
 502                                                 MMC_SEND_OP_COND &&
 503                                                 host->cmd->opcode !=
 504                                                 MMC_APP_CMD &&
 505                                                 !mmc_omap_cover_is_open(host))
 506                                         dev_err(mmc_dev(host->mmc),
 507                                                 "command timeout, CMD %d\n",
 508                                                 host->cmd->opcode);
 509                                 host->cmd->error = MMC_ERR_TIMEOUT;
 510                                 end_command = 1;
 511                         }
 512                 }
 513
 514                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 515                         if (host->cmd) {
 516                                 dev_err(mmc_dev(host->mmc),
 517                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 518                                         host->cmd->opcode, host->cmd->arg);
 519                                 host->cmd->error = MMC_ERR_BADCRC;
 520                                 end_command = 1;
 521                         } else
 522                                 dev_err(mmc_dev(host->mmc),
 523                                         "command CRC error without cmd?\n");
 524                 }
 525
 526                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 527                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
 528                                 u32 response = OMAP_MMC_READ(host, RSP6)
 529                                         | (OMAP_MMC_READ(host, RSP7) << 16);
 530                                 /* STOP sometimes sets must-ignore bits */
 531                                 if (!(response & (R1_CC_ERROR
 532                                                                 | R1_ILLEGAL_COMMAND
 533                                                                 | R1_COM_CRC_ERROR))) {
 534                                         end_command = 1;
 535                                         continue;
 536                                 }
 537                         }
 538
 539                         dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
 540                                 host->cmd->opcode);
 541                         if (host->cmd) {
 542                                 host->cmd->error = MMC_ERR_FAILED;
 543                                 end_command = 1;
 544                         }
 545                         if (host->data) {
 546                                 host->data->error = MMC_ERR_FAILED;
 547                                 transfer_error = 1;
 548                         }
 549                 }
 550
 551                 /*
 552                  * NOTE: On 1610 the END_OF_CMD may come too early when
 553                  * starting a write
 554                  */
 555                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 556                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 557                         end_command = 1;
 558                 }
 559         }
 560
 561         if (end_command) {
 562                 mmc_omap_cmd_done(host, host->cmd);
 563         }
 564         if (transfer_error)
 565                 mmc_omap_xfer_done(host, host->data);
 566         else if (end_transfer)
 567                 mmc_omap_end_of_data(host, host->data);
 568
 569         return IRQ_HANDLED;
 570 }
 571
 572 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
 573 {
 574         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 575
 576         schedule_work(&host->switch_work);
 577
 578         return IRQ_HANDLED;
 579 }
 580
 581 static void mmc_omap_switch_timer(unsigned long arg)
 582 {
 583         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 584
 585         schedule_work(&host->switch_work);
 586 }
 587
 588 static void mmc_omap_switch_handler(struct work_struct *work)
 589 {
 590         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
 591         struct mmc_card *card;
 592         static int complained = 0;
 593         int cards = 0, cover_open;
 594
 595         if (host->switch_pin == -1)
 596                 return;
 597         cover_open = mmc_omap_cover_is_open(host);
 598         if (cover_open != host->switch_last_state) {
 599                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 600                 host->switch_last_state = cover_open;
 601         }
 602         mmc_detect_change(host->mmc, 0);
 603         list_for_each_entry(card, &host->mmc->cards, node) {
 604                 if (mmc_card_present(card))
 605                         cards++;
 606         }
 607         if (mmc_omap_cover_is_open(host)) {
 608                 if (!complained) {
 609                         dev_info(mmc_dev(host->mmc), "cover is open");
 610                         complained = 1;
 611                 }
 612                 if (mmc_omap_enable_poll)
 613                         mod_timer(&host->switch_timer, jiffies +
 614                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 615         } else {
 616                 complained = 0;
 617         }
 618 }
 619
 620 /* Prepare to transfer the next segment of a scatterlist */
 621 static void
 622 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 623 {
 624         int dma_ch = host->dma_ch;
 625         unsigned long data_addr;
 626         u16 buf, frame;
 627         u32 count;
 628         struct scatterlist *sg = &data->sg[host->sg_idx];
 629         int src_port = 0;
 630         int dst_port = 0;
 631         int sync_dev = 0;
 632
 633         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 634         frame = data->blksz;
 635         count = sg_dma_len(sg);
 636
 637         if ((data->blocks == 1) && (count > data->blksz))
 638                 count = frame;
 639
 640         host->dma_len = count;
 641
 642         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 643          * Use 16 or 32 word frames when the blocksize is at least that large.
 644          * Blocksize is usually 512 bytes; but not for some SD reads.
 645          */
 646         if (cpu_is_omap15xx() && frame > 32)
 647                 frame = 32;
 648         else if (frame > 64)
 649                 frame = 64;
 650         count /= frame;
 651         frame >>= 1;
 652
 653         if (!(data->flags & MMC_DATA_WRITE)) {
 654                 buf = 0x800f | ((frame - 1) << 8);
 655
 656                 if (cpu_class_is_omap1()) {
 657                         src_port = OMAP_DMA_PORT_TIPB;
 658                         dst_port = OMAP_DMA_PORT_EMIFF;
 659                 }
 660                 if (cpu_is_omap24xx())
 661                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 662
 663                 omap_set_dma_src_params(dma_ch, src_port,
 664                                         OMAP_DMA_AMODE_CONSTANT,
 665                                         data_addr, 0, 0);
 666                 omap_set_dma_dest_params(dma_ch, dst_port,
 667                                          OMAP_DMA_AMODE_POST_INC,
 668                                          sg_dma_address(sg), 0, 0);
 669                 omap_set_dma_dest_data_pack(dma_ch, 1);
 670                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 671         } else {
 672                 buf = 0x0f80 | ((frame - 1) << 0);
 673
 674                 if (cpu_class_is_omap1()) {
 675                         src_port = OMAP_DMA_PORT_EMIFF;
 676                         dst_port = OMAP_DMA_PORT_TIPB;
 677                 }
 678                 if (cpu_is_omap24xx())
 679                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 680
 681                 omap_set_dma_dest_params(dma_ch, dst_port,
 682                                          OMAP_DMA_AMODE_CONSTANT,
 683                                          data_addr, 0, 0);
 684                 omap_set_dma_src_params(dma_ch, src_port,
 685                                         OMAP_DMA_AMODE_POST_INC,
 686                                         sg_dma_address(sg), 0, 0);
 687                 omap_set_dma_src_data_pack(dma_ch, 1);
 688                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 689         }
 690
 691         /* Max limit for DMA frame count is 0xffff */
 692         BUG_ON(count > 0xffff);
 693
 694         OMAP_MMC_WRITE(host, BUF, buf);
 695         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 696                                      frame, count, OMAP_DMA_SYNC_FRAME,
 697                                      sync_dev, 0);
 698 }
 699
 700 /* A scatterlist segment completed */
 701 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 702 {
 703         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 704         struct mmc_data *mmcdat = host->data;
 705
 706         if (unlikely(host->dma_ch < 0)) {
 707                 dev_err(mmc_dev(host->mmc),
 708                         "DMA callback while DMA not enabled\n");
 709                 return;
 710         }
 711         /* FIXME: We really should do something to _handle_ the errors */
 712         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 713                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 714                 return;
 715         }
 716         if (ch_status & OMAP_DMA_DROP_IRQ) {
 717                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 718                 return;
 719         }
 720         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 721                 return;
 722         }
 723         mmcdat->bytes_xfered += host->dma_len;
 724         host->sg_idx++;
 725         if (host->sg_idx < host->sg_len) {
 726                 mmc_omap_prepare_dma(host, host->data);
 727                 omap_start_dma(host->dma_ch);
 728         } else
 729                 mmc_omap_dma_done(host, host->data);
 730 }
 731
 732 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 733 {
 734         const char *dev_name;
 735         int sync_dev, dma_ch, is_read, r;
 736
 737         is_read = !(data->flags & MMC_DATA_WRITE);
 738         del_timer_sync(&host->dma_timer);
 739         if (host->dma_ch >= 0) {
 740                 if (is_read == host->dma_is_read)
 741                         return 0;
 742                 omap_free_dma(host->dma_ch);
 743                 host->dma_ch = -1;
 744         }
 745
 746         if (is_read) {
 747                 if (host->id == 1) {
 748                         sync_dev = OMAP_DMA_MMC_RX;
 749                         dev_name = "MMC1 read";
 750                 } else {
 751                         sync_dev = OMAP_DMA_MMC2_RX;
 752                         dev_name = "MMC2 read";
 753                 }
 754         } else {
 755                 if (host->id == 1) {
 756                         sync_dev = OMAP_DMA_MMC_TX;
 757                         dev_name = "MMC1 write";
 758                 } else {
 759                         sync_dev = OMAP_DMA_MMC2_TX;
 760                         dev_name = "MMC2 write";
 761                 }
 762         }
 763         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 764                              host, &dma_ch);
 765         if (r != 0) {
 766                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 767                 return r;
 768         }
 769         host->dma_ch = dma_ch;
 770         host->dma_is_read = is_read;
 771
 772         return 0;
 773 }
 774
 775 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 776 {
 777         u16 reg;
 778
 779         reg = OMAP_MMC_READ(host, SDIO);
 780         reg &= ~(1 << 5);
 781         OMAP_MMC_WRITE(host, SDIO, reg);
 782         /* Set maximum timeout */
 783         OMAP_MMC_WRITE(host, CTO, 0xff);
 784 }
 785
 786 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 787 {
 788         int timeout;
 789         u16 reg;
 790
 791         /* Convert ns to clock cycles by assuming 20MHz frequency
 792          * 1 cycle at 20MHz = 500 ns
 793          */
 794         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 795
 796         /* Check if we need to use timeout multiplier register */
 797         reg = OMAP_MMC_READ(host, SDIO);
 798         if (timeout > 0xffff) {
 799                 reg |= (1 << 5);
 800                 timeout /= 1024;
 801         } else
 802                 reg &= ~(1 << 5);
 803         OMAP_MMC_WRITE(host, SDIO, reg);
 804         OMAP_MMC_WRITE(host, DTO, timeout);
 805 }
 806
 807 static void
 808 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 809 {
 810         struct mmc_data *data = req->data;
 811         int i, use_dma, block_size;
 812         unsigned sg_len;
 813
 814         host->data = data;
 815         if (data == NULL) {
 816                 OMAP_MMC_WRITE(host, BLEN, 0);
 817                 OMAP_MMC_WRITE(host, NBLK, 0);
 818                 OMAP_MMC_WRITE(host, BUF, 0);
 819                 host->dma_in_use = 0;
 820                 set_cmd_timeout(host, req);
 821                 return;
 822         }
 823
 824         block_size = data->blksz;
 825
 826         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 827         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 828         set_data_timeout(host, req);
 829
 830         /* cope with calling layer confusion; it issues "single
 831          * block" writes using multi-block scatterlists.
 832          */
 833         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 834
 835         /* Only do DMA for entire blocks */
 836         use_dma = host->use_dma;
 837         if (use_dma) {
 838                 for (i = 0; i < sg_len; i++) {
 839                         if ((data->sg[i].length % block_size) != 0) {
 840                                 use_dma = 0;
 841                                 break;
 842                         }
 843                 }
 844         }
 845
 846         host->sg_idx = 0;
 847         if (use_dma) {
 848                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 849                         enum dma_data_direction dma_data_dir;
 850
 851                         if (data->flags & MMC_DATA_WRITE)
 852                                 dma_data_dir = DMA_TO_DEVICE;
 853                         else
 854                                 dma_data_dir = DMA_FROM_DEVICE;
 855
 856                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 857                                                 sg_len, dma_data_dir);
 858                         host->total_bytes_left = 0;
 859                         mmc_omap_prepare_dma(host, req->data);
 860                         host->brs_received = 0;
 861                         host->dma_done = 0;
 862                         host->dma_in_use = 1;
 863                 } else
 864                         use_dma = 0;
 865         }
 866
 867         /* Revert to PIO? */
 868         if (!use_dma) {
 869                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 870                 host->total_bytes_left = data->blocks * block_size;
 871                 host->sg_len = sg_len;
 872                 mmc_omap_sg_to_buf(host);
 873                 host->dma_in_use = 0;
 874         }
 875 }
 876
 877 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 878 {
 879         struct mmc_omap_host *host = mmc_priv(mmc);
 880
 881         WARN_ON(host->mrq != NULL);
 882
 883         host->mrq = req;
 884
 885         /* only touch fifo AFTER the controller readies it */
 886         mmc_omap_prepare_data(host, req);
 887         mmc_omap_start_command(host, req->cmd);
 888         if (host->dma_in_use)
 889                 omap_start_dma(host->dma_ch);
 890 }
 891
 892 static void innovator_fpga_socket_power(int on)
 893 {
 894 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 895         if (on) {
 896                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 897                      OMAP1510_FPGA_POWER);
 898         } else {
 899                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 900                      OMAP1510_FPGA_POWER);
 901         }
 902 #endif
 903 }
 904
 905 /*
 906  * Turn the socket power on/off. Innovator uses FPGA, most boards
 907  * probably use GPIO.
 908  */
 909 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 910 {
 911         if (machine_is_sx1())
 912                 sx1_setmmcpower(on);
 913         else if (on) {
 914                 if (machine_is_omap_innovator())
 915                         innovator_fpga_socket_power(1);
 916                 else if (machine_is_omap_h2())
 917                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 918                 else if (machine_is_omap_h3())
 919                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 920                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 921                 else if (cpu_is_omap24xx()) {
 922                         u16 reg = OMAP_MMC_READ(host, CON);
 923                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 924                 } else
 925                         if (host->power_pin >= 0)
 926                                 omap_set_gpio_dataout(host->power_pin, 1);
 927         } else {
 928                 if (machine_is_omap_innovator())
 929                         innovator_fpga_socket_power(0);
 930                 else if (machine_is_omap_h2())
 931                         tps65010_set_gpio_out_value(GPIO3, LOW);
 932                 else if (machine_is_omap_h3())
 933                         tps65010_set_gpio_out_value(GPIO4, LOW);
 934                 else if (cpu_is_omap24xx()) {
 935                         u16 reg = OMAP_MMC_READ(host, CON);
 936                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 937                 } else
 938                         if (host->power_pin >= 0)
 939                                 omap_set_gpio_dataout(host->power_pin, 0);
 940         }
 941 }
 942
 943 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 944 {
 945         struct mmc_omap_host *host = mmc_priv(mmc);
 946         int dsor;
 947         int realclock, i;
 948
 949         realclock = ios->clock;
 950
 951         if (ios->clock == 0)
 952                 dsor = 0;
 953         else {
 954                 int func_clk_rate = clk_get_rate(host->fclk);
 955
 956                 dsor = func_clk_rate / realclock;
 957                 if (dsor < 1)
 958                         dsor = 1;
 959
 960                 if (func_clk_rate / dsor > realclock)
 961                         dsor++;
 962
 963                 if (dsor > 250)
 964                         dsor = 250;
 965                 dsor++;
 966
 967                 if (ios->bus_width == MMC_BUS_WIDTH_4)
 968                         dsor |= 1 << 15;
 969         }
 970
 971         switch (ios->power_mode) {
 972         case MMC_POWER_OFF:
 973                 mmc_omap_power(host, 0);
 974                 break;
 975         case MMC_POWER_UP:
 976         case MMC_POWER_ON:
 977                 mmc_omap_power(host, 1);
 978                 dsor |= 1 << 11;
 979                 break;
 980         }
 981
 982         host->bus_mode = ios->bus_mode;
 983         host->hw_bus_mode = host->bus_mode;
 984
 985         clk_enable(host->fclk);
 986
 987         /* On insanely high arm_per frequencies something sometimes
 988          * goes somehow out of sync, and the POW bit is not being set,
 989          * which results in the while loop below getting stuck.
 990          * Writing to the CON register twice seems to do the trick. */
 991         for (i = 0; i < 2; i++)
 992                 OMAP_MMC_WRITE(host, CON, dsor);
 993         if (ios->power_mode == MMC_POWER_UP) {
 994                 /* Send clock cycles, poll completion */
 995                 OMAP_MMC_WRITE(host, IE, 0);
 996                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 997                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
 998                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
 999                 OMAP_MMC_WRITE(host, STAT, 1);
1000         }
1001         clk_disable(host->fclk);
1002 }
1003
1004 static int mmc_omap_get_ro(struct mmc_host *mmc)
1005 {
1006         struct mmc_omap_host *host = mmc_priv(mmc);
1007
1008         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1009 }
1010
1011 static const struct mmc_host_ops mmc_omap_ops = {
1012         .request        = mmc_omap_request,
1013         .set_ios        = mmc_omap_set_ios,
1014         .get_ro         = mmc_omap_get_ro,
1015 };
1016
1017 static int __init mmc_omap_probe(struct platform_device *pdev)
1018 {
1019         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1020         struct mmc_host *mmc;
1021         struct mmc_omap_host *host = NULL;
1022         struct resource *res;
1023         int ret = 0;
1024         int irq;
1025
1026         if (minfo == NULL) {
1027                 dev_err(&pdev->dev, "platform data missing\n");
1028                 return -ENXIO;
1029         }
1030
1031         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1032         irq = platform_get_irq(pdev, 0);
1033         if (res == NULL || irq < 0)
1034                 return -ENXIO;
1035
1036         res = request_mem_region(res->start, res->end - res->start + 1,
1037                                  pdev->name);
1038         if (res == NULL)
1039                 return -EBUSY;
1040
1041         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1042         if (mmc == NULL) {
1043                 ret = -ENOMEM;
1044                 goto err_free_mem_region;
1045         }
1046
1047         host = mmc_priv(mmc);
1048         host->mmc = mmc;
1049
1050         spin_lock_init(&host->dma_lock);
1051         init_timer(&host->dma_timer);
1052         host->dma_timer.function = mmc_omap_dma_timer;
1053         host->dma_timer.data = (unsigned long) host;
1054
1055         host->id = pdev->id;
1056         host->mem_res = res;
1057         host->irq = irq;
1058
1059         if (cpu_is_omap24xx()) {
1060                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1061                 if (IS_ERR(host->iclk))
1062                         goto err_free_mmc_host;
1063                 clk_enable(host->iclk);
1064         }
1065
1066         if (!cpu_is_omap24xx())
1067                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1068         else
1069                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1070
1071         if (IS_ERR(host->fclk)) {
1072                 ret = PTR_ERR(host->fclk);
1073                 goto err_free_iclk;
1074         }
1075
1076         /* REVISIT:
1077          * Also, use minfo->cover to decide how to manage
1078          * the card detect sensing.
1079          */
1080         host->power_pin = minfo->power_pin;
1081         host->switch_pin = minfo->switch_pin;
1082         host->wp_pin = minfo->wp_pin;
1083         host->use_dma = 1;
1084         host->dma_ch = -1;
1085
1086         host->irq = irq;
1087         host->phys_base = host->mem_res->start;
1088         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1089
1090         mmc->ops = &mmc_omap_ops;
1091         mmc->f_min = 400000;
1092         mmc->f_max = 24000000;
1093         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1094         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1095
1096         if (minfo->wire4)
1097                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1098
1099         /* Use scatterlist DMA to reduce per-transfer costs.
1100          * NOTE max_seg_size assumption that small blocks aren't
1101          * normally used (except e.g. for reading SD registers).
1102          */
1103         mmc->max_phys_segs = 32;
1104         mmc->max_hw_segs = 32;
1105         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1106         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1107         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1108         mmc->max_seg_size = mmc->max_req_size;
1109
1110         if (host->power_pin >= 0) {
1111                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1112                         dev_err(mmc_dev(host->mmc),
1113                                 "Unable to get GPIO pin for MMC power\n");
1114                         goto err_free_fclk;
1115                 }
1116                 omap_set_gpio_direction(host->power_pin, 0);
1117         }
1118
1119         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1120         if (ret)
1121                 goto err_free_power_gpio;
1122
1123         host->dev = &pdev->dev;
1124         platform_set_drvdata(pdev, host);
1125
1126         if (host->switch_pin >= 0) {
1127                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1128                 init_timer(&host->switch_timer);
1129                 host->switch_timer.function = mmc_omap_switch_timer;
1130                 host->switch_timer.data = (unsigned long) host;
1131                 if (omap_request_gpio(host->switch_pin) != 0) {
1132                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1133                         host->switch_pin = -1;
1134                         goto no_switch;
1135                 }
1136
1137                 omap_set_gpio_direction(host->switch_pin, 1);
1138                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1139                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1140                 if (ret) {
1141                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1142                         omap_free_gpio(host->switch_pin);
1143                         host->switch_pin = -1;
1144                         goto no_switch;
1145                 }
1146                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1147                 if (ret == 0) {
1148                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1149                         if (ret != 0)
1150                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1151                 }
1152                 if (ret) {
1153                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1154                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1155                         omap_free_gpio(host->switch_pin);
1156                         host->switch_pin = -1;
1157                         goto no_switch;
1158                 }
1159                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1160                         schedule_work(&host->switch_work);
1161         }
1162
1163         mmc_add_host(mmc);
1164
1165         return 0;
1166
1167 no_switch:
1168         /* FIXME: Free other resources too. */
1169         if (host) {
1170                 if (host->iclk && !IS_ERR(host->iclk))
1171                         clk_put(host->iclk);
1172                 if (host->fclk && !IS_ERR(host->fclk))
1173                         clk_put(host->fclk);
1174                 mmc_free_host(host->mmc);
1175         }
1176 err_free_power_gpio:
1177         if (host->power_pin >= 0)
1178                 omap_free_gpio(host->power_pin);
1179 err_free_fclk:
1180         clk_put(host->fclk);
1181 err_free_iclk:
1182         if (host->iclk != NULL) {
1183                 clk_disable(host->iclk);
1184                 clk_put(host->iclk);
1185         }
1186 err_free_mmc_host:
1187         mmc_free_host(host->mmc);
1188 err_free_mem_region:
1189         release_mem_region(res->start, res->end - res->start + 1);
1190         return ret;
1191 }
1192
1193 static int mmc_omap_remove(struct platform_device *pdev)
1194 {
1195         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1196
1197         platform_set_drvdata(pdev, NULL);
1198
1199         BUG_ON(host == NULL);
1200
1201         mmc_remove_host(host->mmc);
1202         free_irq(host->irq, host);
1203
1204         if (host->power_pin >= 0)
1205                 omap_free_gpio(host->power_pin);
1206         if (host->switch_pin >= 0) {
1207                 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1208                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1209                 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1210                 omap_free_gpio(host->switch_pin);
1211                 host->switch_pin = -1;
1212                 del_timer_sync(&host->switch_timer);
1213                 flush_scheduled_work();
1214         }
1215         if (host->iclk && !IS_ERR(host->iclk))
1216                 clk_put(host->iclk);
1217         if (host->fclk && !IS_ERR(host->fclk))
1218                 clk_put(host->fclk);
1219
1220         release_mem_region(pdev->resource[0].start,
1221                            pdev->resource[0].end - pdev->resource[0].start + 1);
1222
1223         mmc_free_host(host->mmc);
1224
1225         return 0;
1226 }
1227
1228 #ifdef CONFIG_PM
1229 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1230 {
1231         int ret = 0;
1232         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1233
1234         if (host && host->suspended)
1235                 return 0;
1236
1237         if (host) {
1238                 ret = mmc_suspend_host(host->mmc, mesg);
1239                 if (ret == 0)
1240                         host->suspended = 1;
1241         }
1242         return ret;
1243 }
1244
1245 static int mmc_omap_resume(struct platform_device *pdev)
1246 {
1247         int ret = 0;
1248         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1249
1250         if (host && !host->suspended)
1251                 return 0;
1252
1253         if (host) {
1254                 ret = mmc_resume_host(host->mmc);
1255                 if (ret == 0)
1256                         host->suspended = 0;
1257         }
1258
1259         return ret;
1260 }
1261 #else
1262 #define mmc_omap_suspend        NULL
1263 #define mmc_omap_resume         NULL
1264 #endif
1265
1266 static struct platform_driver mmc_omap_driver = {
1267         .probe          = mmc_omap_probe,
1268         .remove         = mmc_omap_remove,
1269         .suspend        = mmc_omap_suspend,
1270         .resume         = mmc_omap_resume,
1271         .driver         = {
1272                 .name   = DRIVER_NAME,
1273         },
1274 };
1275
1276 static int __init mmc_omap_init(void)
1277 {
1278         return platform_driver_register(&mmc_omap_driver);
1279 }
1280
1281 static void __exit mmc_omap_exit(void)
1282 {
1283         platform_driver_unregister(&mmc_omap_driver);
1284 }
1285
1286 module_init(mmc_omap_init);
1287 module_exit(mmc_omap_exit);
1288
1289 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1290 MODULE_LICENSE("GPL");
1291 MODULE_ALIAS(DRIVER_NAME);
1292 MODULE_AUTHOR("Juha Yrjölä");