drivers/mmc/omap.c

   1 /*
   2  *  linux/drivers/media/mmc/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/protocol.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/scatterlist.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39 #include <asm/arch/tps65010.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94 #define RSP_TYPE(x)     ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
  95
  96 /* Specifies how often in millisecs to poll for card status changes
  97  * when the cover switch is open */
  98 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  99
 100 static int mmc_omap_enable_poll = 1;
 101
 102 struct mmc_omap_host {
 103         int                     initialized;
 104         int                     suspended;
 105         struct mmc_request *    mrq;
 106         struct mmc_command *    cmd;
 107         struct mmc_data *       data;
 108         struct mmc_host *       mmc;
 109         struct device *         dev;
 110         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 111         struct clk *            iclk;
 112         struct clk *            fclk;
 113         struct resource         *mem_res;
 114         void __iomem            *virt_base;
 115         unsigned int            phys_base;
 116         int                     irq;
 117         unsigned char           bus_mode;
 118         unsigned char           hw_bus_mode;
 119
 120         unsigned int            sg_len;
 121         int                     sg_idx;
 122         u16 *                   buffer;
 123         u32                     buffer_bytes_left;
 124         u32                     total_bytes_left;
 125
 126         unsigned                use_dma:1;
 127         unsigned                brs_received:1, dma_done:1;
 128         unsigned                dma_is_read:1;
 129         unsigned                dma_in_use:1;
 130         int                     dma_ch;
 131         spinlock_t              dma_lock;
 132         struct timer_list       dma_timer;
 133         unsigned                dma_len;
 134
 135         short                   power_pin;
 136         short                   wp_pin;
 137
 138         int                     switch_pin;
 139         struct work_struct      switch_work;
 140         struct timer_list       switch_timer;
 141         int                     switch_last_state;
 142 };
 143
 144 static inline int
 145 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 146 {
 147         if (host->switch_pin < 0)
 148                 return 0;
 149         return omap_get_gpio_datain(host->switch_pin);
 150 }
 151
 152 static ssize_t
 153 mmc_omap_show_cover_switch(struct device *dev,
 154         struct device_attribute *attr, char *buf)
 155 {
 156         struct mmc_omap_host *host = dev_get_drvdata(dev);
 157
 158         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
 159                         "closed");
 160 }
 161
 162 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 163
 164 static ssize_t
 165 mmc_omap_show_enable_poll(struct device *dev,
 166         struct device_attribute *attr, char *buf)
 167 {
 168         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 169 }
 170
 171 static ssize_t
 172 mmc_omap_store_enable_poll(struct device *dev,
 173         struct device_attribute *attr, const char *buf,
 174         size_t size)
 175 {
 176         int enable_poll;
 177
 178         if (sscanf(buf, "%10d", &enable_poll) != 1)
 179                 return -EINVAL;
 180
 181         if (enable_poll != mmc_omap_enable_poll) {
 182                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 183
 184                 mmc_omap_enable_poll = enable_poll;
 185                 if (enable_poll && host->switch_pin >= 0)
 186                         schedule_work(&host->switch_work);
 187         }
 188         return size;
 189 }
 190
 191 static DEVICE_ATTR(enable_poll, 0664,
 192                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 193
 194 static void
 195 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 196 {
 197         u32 cmdreg;
 198         u32 resptype;
 199         u32 cmdtype;
 200
 201         host->cmd = cmd;
 202
 203         resptype = 0;
 204         cmdtype = 0;
 205
 206         /* Our hardware needs to know exact type */
 207         switch (RSP_TYPE(mmc_resp_type(cmd))) {
 208         case RSP_TYPE(MMC_RSP_R1):
 209                 /* resp 1, resp 1b */
 210                 resptype = 1;
 211                 break;
 212         case RSP_TYPE(MMC_RSP_R2):
 213                 resptype = 2;
 214                 break;
 215         case RSP_TYPE(MMC_RSP_R3):
 216                 resptype = 3;
 217                 break;
 218         default:
 219                 break;
 220         }
 221
 222         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 223                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 224         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 225                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 226         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 227                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 228         } else {
 229                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 230         }
 231
 232         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 233
 234         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 235                 cmdreg |= 1 << 6;
 236
 237         if (cmd->flags & MMC_RSP_BUSY)
 238                 cmdreg |= 1 << 11;
 239
 240         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 241                 cmdreg |= 1 << 15;
 242
 243         clk_enable(host->fclk);
 244
 245         OMAP_MMC_WRITE(host, CTO, 200);
 246         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 247         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 248         OMAP_MMC_WRITE(host, IE,
 249                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 250                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 251                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 252                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 253                        OMAP_MMC_STAT_END_OF_DATA);
 254         OMAP_MMC_WRITE(host, CMD, cmdreg);
 255 }
 256
 257 static void
 258 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 259 {
 260         if (host->dma_in_use) {
 261                 enum dma_data_direction dma_data_dir;
 262
 263                 BUG_ON(host->dma_ch < 0);
 264                 if (data->error != MMC_ERR_NONE)
 265                         omap_stop_dma(host->dma_ch);
 266                 /* Release DMA channel lazily */
 267                 mod_timer(&host->dma_timer, jiffies + HZ);
 268                 if (data->flags & MMC_DATA_WRITE)
 269                         dma_data_dir = DMA_TO_DEVICE;
 270                 else
 271                         dma_data_dir = DMA_FROM_DEVICE;
 272                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 273                              dma_data_dir);
 274         }
 275         host->data = NULL;
 276         host->sg_len = 0;
 277         clk_disable(host->fclk);
 278
 279         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 280          * dozens of requests until the card finishes writing data.
 281          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 282          */
 283
 284         if (!data->stop) {
 285                 host->mrq = NULL;
 286                 mmc_request_done(host->mmc, data->mrq);
 287                 return;
 288         }
 289
 290         mmc_omap_start_command(host, data->stop);
 291 }
 292
 293 static void
 294 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 295 {
 296         unsigned long flags;
 297         int done;
 298
 299         if (!host->dma_in_use) {
 300                 mmc_omap_xfer_done(host, data);
 301                 return;
 302         }
 303         done = 0;
 304         spin_lock_irqsave(&host->dma_lock, flags);
 305         if (host->dma_done)
 306                 done = 1;
 307         else
 308                 host->brs_received = 1;
 309         spin_unlock_irqrestore(&host->dma_lock, flags);
 310         if (done)
 311                 mmc_omap_xfer_done(host, data);
 312 }
 313
 314 static void
 315 mmc_omap_dma_timer(unsigned long data)
 316 {
 317         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 318
 319         BUG_ON(host->dma_ch < 0);
 320         omap_free_dma(host->dma_ch);
 321         host->dma_ch = -1;
 322 }
 323
 324 static void
 325 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 326 {
 327         unsigned long flags;
 328         int done;
 329
 330         done = 0;
 331         spin_lock_irqsave(&host->dma_lock, flags);
 332         if (host->brs_received)
 333                 done = 1;
 334         else
 335                 host->dma_done = 1;
 336         spin_unlock_irqrestore(&host->dma_lock, flags);
 337         if (done)
 338                 mmc_omap_xfer_done(host, data);
 339 }
 340
 341 static void
 342 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 343 {
 344         host->cmd = NULL;
 345
 346         if (cmd->flags & MMC_RSP_PRESENT) {
 347                 if (cmd->flags & MMC_RSP_136) {
 348                         /* response type 2 */
 349                         cmd->resp[3] =
 350                                 OMAP_MMC_READ(host, RSP0) |
 351                                 (OMAP_MMC_READ(host, RSP1) << 16);
 352                         cmd->resp[2] =
 353                                 OMAP_MMC_READ(host, RSP2) |
 354                                 (OMAP_MMC_READ(host, RSP3) << 16);
 355                         cmd->resp[1] =
 356                                 OMAP_MMC_READ(host, RSP4) |
 357                                 (OMAP_MMC_READ(host, RSP5) << 16);
 358                         cmd->resp[0] =
 359                                 OMAP_MMC_READ(host, RSP6) |
 360                                 (OMAP_MMC_READ(host, RSP7) << 16);
 361                 } else {
 362                         /* response types 1, 1b, 3, 4, 5, 6 */
 363                         cmd->resp[0] =
 364                                 OMAP_MMC_READ(host, RSP6) |
 365                                 (OMAP_MMC_READ(host, RSP7) << 16);
 366                 }
 367         }
 368
 369         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
 370                 host->mrq = NULL;
 371                 clk_disable(host->fclk);
 372                 mmc_request_done(host->mmc, cmd->mrq);
 373         }
 374 }
 375
 376 /* PIO only */
 377 static void
 378 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 379 {
 380         struct scatterlist *sg;
 381
 382         sg = host->data->sg + host->sg_idx;
 383         host->buffer_bytes_left = sg->length;
 384         host->buffer = page_address(sg->page) + sg->offset;
 385         if (host->buffer_bytes_left > host->total_bytes_left)
 386                 host->buffer_bytes_left = host->total_bytes_left;
 387 }
 388
 389 /* PIO only */
 390 static void
 391 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 392 {
 393         int n;
 394
 395         if (host->buffer_bytes_left == 0) {
 396                 host->sg_idx++;
 397                 BUG_ON(host->sg_idx == host->sg_len);
 398                 mmc_omap_sg_to_buf(host);
 399         }
 400         n = 64;
 401         if (n > host->buffer_bytes_left)
 402                 n = host->buffer_bytes_left;
 403         host->buffer_bytes_left -= n;
 404         host->total_bytes_left -= n;
 405         host->data->bytes_xfered += n;
 406
 407         if (write) {
 408                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 409         } else {
 410                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 411         }
 412 }
 413
 414 static inline void mmc_omap_report_irq(u16 status)
 415 {
 416         static const char *mmc_omap_status_bits[] = {
 417                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 418                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 419         };
 420         int i, c = 0;
 421
 422         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 423                 if (status & (1 << i)) {
 424                         if (c)
 425                                 printk(" ");
 426                         printk("%s", mmc_omap_status_bits[i]);
 427                         c++;
 428                 }
 429 }
 430
 431 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 432 {
 433         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 434         u16 status;
 435         int end_command;
 436         int end_transfer;
 437         int transfer_error;
 438
 439         if (host->cmd == NULL && host->data == NULL) {
 440                 status = OMAP_MMC_READ(host, STAT);
 441                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 442                 if (status != 0) {
 443                         OMAP_MMC_WRITE(host, STAT, status);
 444                         OMAP_MMC_WRITE(host, IE, 0);
 445                 }
 446                 return IRQ_HANDLED;
 447         }
 448
 449         end_command = 0;
 450         end_transfer = 0;
 451         transfer_error = 0;
 452
 453         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 454                 OMAP_MMC_WRITE(host, STAT, status);
 455 #ifdef CONFIG_MMC_DEBUG
 456                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 457                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 458                 mmc_omap_report_irq(status);
 459                 printk("\n");
 460 #endif
 461                 if (host->total_bytes_left) {
 462                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 463                             (status & OMAP_MMC_STAT_END_OF_DATA))
 464                                 mmc_omap_xfer_data(host, 0);
 465                         if (status & OMAP_MMC_STAT_A_EMPTY)
 466                                 mmc_omap_xfer_data(host, 1);
 467                 }
 468
 469                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 470                         end_transfer = 1;
 471                 }
 472
 473                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 474                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 475                         if (host->data) {
 476                                 host->data->error |= MMC_ERR_TIMEOUT;
 477                                 transfer_error = 1;
 478                         }
 479                 }
 480
 481                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 482                         if (host->data) {
 483                                 host->data->error |= MMC_ERR_BADCRC;
 484                                 dev_dbg(mmc_dev(host->mmc),
 485                                          "data CRC error, bytes left %d\n",
 486                                         host->total_bytes_left);
 487                                 transfer_error = 1;
 488                         } else {
 489                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 490                         }
 491                 }
 492
 493                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 494                         /* Timeouts are routine with some commands */
 495                         if (host->cmd) {
 496                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 497                                                 host->cmd->opcode !=
 498                                                 MMC_SEND_OP_COND &&
 499                                                 host->cmd->opcode !=
 500                                                 MMC_APP_CMD &&
 501                                                 !mmc_omap_cover_is_open(host))
 502                                         dev_err(mmc_dev(host->mmc),
 503                                                 "command timeout, CMD %d\n",
 504                                                 host->cmd->opcode);
 505                                 host->cmd->error = MMC_ERR_TIMEOUT;
 506                                 end_command = 1;
 507                         }
 508                 }
 509
 510                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 511                         if (host->cmd) {
 512                                 dev_err(mmc_dev(host->mmc),
 513                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 514                                         host->cmd->opcode, host->cmd->arg);
 515                                 host->cmd->error = MMC_ERR_BADCRC;
 516                                 end_command = 1;
 517                         } else
 518                                 dev_err(mmc_dev(host->mmc),
 519                                         "command CRC error without cmd?\n");
 520                 }
 521
 522                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 523                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
 524                                 u32 response = OMAP_MMC_READ(host, RSP6)
 525                                         | (OMAP_MMC_READ(host, RSP7) << 16);
 526                                 /* STOP sometimes sets must-ignore bits */
 527                                 if (!(response & (R1_CC_ERROR
 528                                                                 | R1_ILLEGAL_COMMAND
 529                                                                 | R1_COM_CRC_ERROR))) {
 530                                         end_command = 1;
 531                                         continue;
 532                                 }
 533                         }
 534
 535                         dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
 536                                 host->cmd->opcode);
 537                         if (host->cmd) {
 538                                 host->cmd->error = MMC_ERR_FAILED;
 539                                 end_command = 1;
 540                         }
 541                         if (host->data) {
 542                                 host->data->error = MMC_ERR_FAILED;
 543                                 transfer_error = 1;
 544                         }
 545                 }
 546
 547                 /*
 548                  * NOTE: On 1610 the END_OF_CMD may come too early when
 549                  * starting a write
 550                  */
 551                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 552                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 553                         end_command = 1;
 554                 }
 555         }
 556
 557         if (end_command) {
 558                 mmc_omap_cmd_done(host, host->cmd);
 559         }
 560         if (transfer_error)
 561                 mmc_omap_xfer_done(host, host->data);
 562         else if (end_transfer)
 563                 mmc_omap_end_of_data(host, host->data);
 564
 565         return IRQ_HANDLED;
 566 }
 567
 568 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
 569 {
 570         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 571
 572         schedule_work(&host->switch_work);
 573
 574         return IRQ_HANDLED;
 575 }
 576
 577 static void mmc_omap_switch_timer(unsigned long arg)
 578 {
 579         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 580
 581         schedule_work(&host->switch_work);
 582 }
 583
 584 /* FIXME: Handle card insertion and removal properly. Maybe use a mask
 585  * for MMC state? */
 586 static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
 587 {
 588 }
 589
 590 static void mmc_omap_switch_handler(void *data)
 591 {
 592         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 593         struct mmc_card *card;
 594         static int complained = 0;
 595         int cards = 0, cover_open;
 596
 597         if (host->switch_pin == -1)
 598                 return;
 599         cover_open = mmc_omap_cover_is_open(host);
 600         if (cover_open != host->switch_last_state) {
 601                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 602                 host->switch_last_state = cover_open;
 603         }
 604         mmc_detect_change(host->mmc, 0);
 605         list_for_each_entry(card, &host->mmc->cards, node) {
 606                 if (mmc_card_present(card))
 607                         cards++;
 608         }
 609         if (mmc_omap_cover_is_open(host)) {
 610                 if (!complained) {
 611                         dev_info(mmc_dev(host->mmc), "cover is open");
 612                         complained = 1;
 613                 }
 614                 if (mmc_omap_enable_poll)
 615                         mod_timer(&host->switch_timer, jiffies +
 616                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 617         } else {
 618                 complained = 0;
 619         }
 620 }
 621
 622 /* Prepare to transfer the next segment of a scatterlist */
 623 static void
 624 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 625 {
 626         int dma_ch = host->dma_ch;
 627         unsigned long data_addr;
 628         u16 buf, frame;
 629         u32 count;
 630         struct scatterlist *sg = &data->sg[host->sg_idx];
 631         int src_port = 0;
 632         int dst_port = 0;
 633         int sync_dev = 0;
 634
 635         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 636         frame = data->blksz;
 637         count = sg_dma_len(sg);
 638
 639         if ((data->blocks == 1) && (count > data->blksz))
 640                 count = frame;
 641
 642         host->dma_len = count;
 643
 644         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 645          * Use 16 or 32 word frames when the blocksize is at least that large.
 646          * Blocksize is usually 512 bytes; but not for some SD reads.
 647          */
 648         if (cpu_is_omap15xx() && frame > 32)
 649                 frame = 32;
 650         else if (frame > 64)
 651                 frame = 64;
 652         count /= frame;
 653         frame >>= 1;
 654
 655         if (!(data->flags & MMC_DATA_WRITE)) {
 656                 buf = 0x800f | ((frame - 1) << 8);
 657
 658                 if (cpu_class_is_omap1()) {
 659                         src_port = OMAP_DMA_PORT_TIPB;
 660                         dst_port = OMAP_DMA_PORT_EMIFF;
 661                 }
 662                 if (cpu_is_omap24xx())
 663                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 664
 665                 omap_set_dma_src_params(dma_ch, src_port,
 666                                         OMAP_DMA_AMODE_CONSTANT,
 667                                         data_addr, 0, 0);
 668                 omap_set_dma_dest_params(dma_ch, dst_port,
 669                                          OMAP_DMA_AMODE_POST_INC,
 670                                          sg_dma_address(sg), 0, 0);
 671                 omap_set_dma_dest_data_pack(dma_ch, 1);
 672                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 673         } else {
 674                 buf = 0x0f80 | ((frame - 1) << 0);
 675
 676                 if (cpu_class_is_omap1()) {
 677                         src_port = OMAP_DMA_PORT_EMIFF;
 678                         dst_port = OMAP_DMA_PORT_TIPB;
 679                 }
 680                 if (cpu_is_omap24xx())
 681                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 682
 683                 omap_set_dma_dest_params(dma_ch, dst_port,
 684                                          OMAP_DMA_AMODE_CONSTANT,
 685                                          data_addr, 0, 0);
 686                 omap_set_dma_src_params(dma_ch, src_port,
 687                                         OMAP_DMA_AMODE_POST_INC,
 688                                         sg_dma_address(sg), 0, 0);
 689                 omap_set_dma_src_data_pack(dma_ch, 1);
 690                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 691         }
 692
 693         /* Max limit for DMA frame count is 0xffff */
 694         if (unlikely(count > 0xffff))
 695                 BUG();
 696
 697         OMAP_MMC_WRITE(host, BUF, buf);
 698         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 699                                      frame, count, OMAP_DMA_SYNC_FRAME,
 700                                      sync_dev, 0);
 701 }
 702
 703 /* A scatterlist segment completed */
 704 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 705 {
 706         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 707         struct mmc_data *mmcdat = host->data;
 708
 709         if (unlikely(host->dma_ch < 0)) {
 710                 dev_err(mmc_dev(host->mmc),
 711                         "DMA callback while DMA not enabled\n");
 712                 return;
 713         }
 714         /* FIXME: We really should do something to _handle_ the errors */
 715         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 716                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 717                 return;
 718         }
 719         if (ch_status & OMAP_DMA_DROP_IRQ) {
 720                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 721                 return;
 722         }
 723         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 724                 return;
 725         }
 726         mmcdat->bytes_xfered += host->dma_len;
 727         host->sg_idx++;
 728         if (host->sg_idx < host->sg_len) {
 729                 mmc_omap_prepare_dma(host, host->data);
 730                 omap_start_dma(host->dma_ch);
 731         } else
 732                 mmc_omap_dma_done(host, host->data);
 733 }
 734
 735 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 736 {
 737         const char *dev_name;
 738         int sync_dev, dma_ch, is_read, r;
 739
 740         is_read = !(data->flags & MMC_DATA_WRITE);
 741         del_timer_sync(&host->dma_timer);
 742         if (host->dma_ch >= 0) {
 743                 if (is_read == host->dma_is_read)
 744                         return 0;
 745                 omap_free_dma(host->dma_ch);
 746                 host->dma_ch = -1;
 747         }
 748
 749         if (is_read) {
 750                 if (host->id == 1) {
 751                         sync_dev = OMAP_DMA_MMC_RX;
 752                         dev_name = "MMC1 read";
 753                 } else {
 754                         sync_dev = OMAP_DMA_MMC2_RX;
 755                         dev_name = "MMC2 read";
 756                 }
 757         } else {
 758                 if (host->id == 1) {
 759                         sync_dev = OMAP_DMA_MMC_TX;
 760                         dev_name = "MMC1 write";
 761                 } else {
 762                         sync_dev = OMAP_DMA_MMC2_TX;
 763                         dev_name = "MMC2 write";
 764                 }
 765         }
 766         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 767                              host, &dma_ch);
 768         if (r != 0) {
 769                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 770                 return r;
 771         }
 772         host->dma_ch = dma_ch;
 773         host->dma_is_read = is_read;
 774
 775         return 0;
 776 }
 777
 778 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 779 {
 780         u16 reg;
 781
 782         reg = OMAP_MMC_READ(host, SDIO);
 783         reg &= ~(1 << 5);
 784         OMAP_MMC_WRITE(host, SDIO, reg);
 785         /* Set maximum timeout */
 786         OMAP_MMC_WRITE(host, CTO, 0xff);
 787 }
 788
 789 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 790 {
 791         int timeout;
 792         u16 reg;
 793
 794         /* Convert ns to clock cycles by assuming 20MHz frequency
 795          * 1 cycle at 20MHz = 500 ns
 796          */
 797         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 798
 799         /* Check if we need to use timeout multiplier register */
 800         reg = OMAP_MMC_READ(host, SDIO);
 801         if (timeout > 0xffff) {
 802                 reg |= (1 << 5);
 803                 timeout /= 1024;
 804         } else
 805                 reg &= ~(1 << 5);
 806         OMAP_MMC_WRITE(host, SDIO, reg);
 807         OMAP_MMC_WRITE(host, DTO, timeout);
 808 }
 809
 810 static void
 811 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 812 {
 813         struct mmc_data *data = req->data;
 814         int i, use_dma, block_size;
 815         unsigned sg_len;
 816
 817         host->data = data;
 818         if (data == NULL) {
 819                 OMAP_MMC_WRITE(host, BLEN, 0);
 820                 OMAP_MMC_WRITE(host, NBLK, 0);
 821                 OMAP_MMC_WRITE(host, BUF, 0);
 822                 host->dma_in_use = 0;
 823                 set_cmd_timeout(host, req);
 824                 return;
 825         }
 826
 827
 828         block_size = data->blksz;
 829
 830         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 831         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 832         set_data_timeout(host, req);
 833
 834         /* cope with calling layer confusion; it issues "single
 835          * block" writes using multi-block scatterlists.
 836          */
 837         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 838
 839         /* Only do DMA for entire blocks */
 840         use_dma = host->use_dma;
 841         if (use_dma) {
 842                 for (i = 0; i < sg_len; i++) {
 843                         if ((data->sg[i].length % block_size) != 0) {
 844                                 use_dma = 0;
 845                                 break;
 846                         }
 847                 }
 848         }
 849
 850         host->sg_idx = 0;
 851         if (use_dma) {
 852                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 853                         enum dma_data_direction dma_data_dir;
 854
 855                         if (data->flags & MMC_DATA_WRITE)
 856                                 dma_data_dir = DMA_TO_DEVICE;
 857                         else
 858                                 dma_data_dir = DMA_FROM_DEVICE;
 859
 860                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 861                                                 sg_len, dma_data_dir);
 862                         host->total_bytes_left = 0;
 863                         mmc_omap_prepare_dma(host, req->data);
 864                         host->brs_received = 0;
 865                         host->dma_done = 0;
 866                         host->dma_in_use = 1;
 867                 } else
 868                         use_dma = 0;
 869         }
 870
 871         /* Revert to PIO? */
 872         if (!use_dma) {
 873                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 874                 host->total_bytes_left = data->blocks * block_size;
 875                 host->sg_len = sg_len;
 876                 mmc_omap_sg_to_buf(host);
 877                 host->dma_in_use = 0;
 878         }
 879 }
 880
 881 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 882 {
 883         struct mmc_omap_host *host = mmc_priv(mmc);
 884
 885         WARN_ON(host->mrq != NULL);
 886
 887         host->mrq = req;
 888
 889         /* only touch fifo AFTER the controller readies it */
 890         mmc_omap_prepare_data(host, req);
 891         mmc_omap_start_command(host, req->cmd);
 892         if (host->dma_in_use)
 893                 omap_start_dma(host->dma_ch);
 894 }
 895
 896 static void innovator_fpga_socket_power(int on)
 897 {
 898 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 899
 900         if (on) {
 901                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 902                      OMAP1510_FPGA_POWER);
 903         } else {
 904                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 905                      OMAP1510_FPGA_POWER);
 906         }
 907 #endif
 908 }
 909
 910 /*
 911  * Turn the socket power on/off. Innovator uses FPGA, most boards
 912  * probably use GPIO.
 913  */
 914 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 915 {
 916         if (on) {
 917                 if (machine_is_omap_innovator())
 918                         innovator_fpga_socket_power(1);
 919                 else if (machine_is_omap_h2())
 920                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 921                 else if (machine_is_omap_h3())
 922                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 923                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 924                 else if (cpu_is_omap24xx()) {
 925                         u16 reg = OMAP_MMC_READ(host, CON);
 926                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 927                 } else
 928                         if (host->power_pin >= 0)
 929                                 omap_set_gpio_dataout(host->power_pin, 1);
 930         } else {
 931                 if (machine_is_omap_innovator())
 932                         innovator_fpga_socket_power(0);
 933                 else if (machine_is_omap_h2())
 934                         tps65010_set_gpio_out_value(GPIO3, LOW);
 935                 else if (machine_is_omap_h3())
 936                         tps65010_set_gpio_out_value(GPIO4, LOW);
 937                 else if (cpu_is_omap24xx()) {
 938                         u16 reg = OMAP_MMC_READ(host, CON);
 939                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 940                 } else
 941                         if (host->power_pin >= 0)
 942                                 omap_set_gpio_dataout(host->power_pin, 0);
 943         }
 944 }
 945
 946 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 947 {
 948         struct mmc_omap_host *host = mmc_priv(mmc);
 949         int dsor;
 950         int realclock, i;
 951
 952         realclock = ios->clock;
 953
 954         if (ios->clock == 0)
 955                 dsor = 0;
 956         else {
 957                 int func_clk_rate = clk_get_rate(host->fclk);
 958
 959                 dsor = func_clk_rate / realclock;
 960                 if (dsor < 1)
 961                         dsor = 1;
 962
 963                 if (func_clk_rate / dsor > realclock)
 964                         dsor++;
 965
 966                 if (dsor > 250)
 967                         dsor = 250;
 968                 dsor++;
 969
 970                 if (ios->bus_width == MMC_BUS_WIDTH_4)
 971                         dsor |= 1 << 15;
 972         }
 973
 974         switch (ios->power_mode) {
 975         case MMC_POWER_OFF:
 976                 mmc_omap_power(host, 0);
 977                 break;
 978         case MMC_POWER_UP:
 979         case MMC_POWER_ON:
 980                 mmc_omap_power(host, 1);
 981                 dsor |= 1<<11;
 982                 break;
 983         }
 984
 985         host->bus_mode = ios->bus_mode;
 986         host->hw_bus_mode = host->bus_mode;
 987
 988         clk_enable(host->fclk);
 989
 990         /* On insanely high arm_per frequencies something sometimes
 991          * goes somehow out of sync, and the POW bit is not being set,
 992          * which results in the while loop below getting stuck.
 993          * Writing to the CON register twice seems to do the trick. */
 994         for (i = 0; i < 2; i++)
 995                 OMAP_MMC_WRITE(host, CON, dsor);
 996         if (ios->power_mode == MMC_POWER_UP) {
 997                 /* Send clock cycles, poll completion */
 998                 OMAP_MMC_WRITE(host, IE, 0);
 999                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1000                 OMAP_MMC_WRITE(host, CMD, 1<<7);
1001                 while (0 == (OMAP_MMC_READ(host, STAT) & 1));
1002                 OMAP_MMC_WRITE(host, STAT, 1);
1003         }
1004         clk_disable(host->fclk);
1005 }
1006
1007 static int mmc_omap_get_ro(struct mmc_host *mmc)
1008 {
1009         struct mmc_omap_host *host = mmc_priv(mmc);
1010
1011         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1012 }
1013
1014 static const struct mmc_host_ops mmc_omap_ops = {
1015         .request        = mmc_omap_request,
1016         .set_ios        = mmc_omap_set_ios,
1017         .get_ro         = mmc_omap_get_ro,
1018 };
1019
1020 static int __init mmc_omap_probe(struct platform_device *pdev)
1021 {
1022         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1023         struct mmc_host *mmc;
1024         struct mmc_omap_host *host = NULL;
1025         struct resource *r;
1026         int ret = 0;
1027         int irq;
1028
1029         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030         irq = platform_get_irq(pdev, 0);
1031         if (!r || irq < 0)
1032                 return -ENXIO;
1033
1034         r = request_mem_region(pdev->resource[0].start,
1035                                 pdev->resource[0].end - pdev->resource[0].start + 1,
1036                                pdev->name);
1037         if (!r)
1038                 return -EBUSY;
1039
1040         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1041         if (!mmc) {
1042                 ret = -ENOMEM;
1043                 goto out;
1044         }
1045
1046         host = mmc_priv(mmc);
1047         host->mmc = mmc;
1048
1049         spin_lock_init(&host->dma_lock);
1050         init_timer(&host->dma_timer);
1051         host->dma_timer.function = mmc_omap_dma_timer;
1052         host->dma_timer.data = (unsigned long) host;
1053
1054         host->id = pdev->id;
1055         host->mem_res = r;
1056         host->irq = irq;
1057
1058         if (cpu_is_omap24xx()) {
1059                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1060                 if (IS_ERR(host->iclk))
1061                         goto out;
1062                 clk_enable(host->iclk);
1063         }
1064
1065         if (!cpu_is_omap24xx())
1066                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1067         else
1068                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1069
1070         if (IS_ERR(host->fclk)) {
1071                 ret = PTR_ERR(host->fclk);
1072                 goto out;
1073         }
1074
1075         /* REVISIT:
1076          * Also, use minfo->cover to decide how to manage
1077          * the card detect sensing.
1078          */
1079         host->power_pin = minfo->power_pin;
1080         host->switch_pin = minfo->switch_pin;
1081         host->wp_pin = minfo->wp_pin;
1082         host->use_dma = 1;
1083         host->dma_ch = -1;
1084
1085         host->irq = pdev->resource[1].start;
1086         host->phys_base = host->mem_res->start;
1087         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1088
1089         mmc->ops = &mmc_omap_ops;
1090         mmc->f_min = 400000;
1091         mmc->f_max = 24000000;
1092         mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1093         mmc->caps = MMC_CAP_BYTEBLOCK;
1094
1095         if (minfo->wire4)
1096                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1097
1098         /* Use scatterlist DMA to reduce per-transfer costs.
1099          * NOTE max_seg_size assumption that small blocks aren't
1100          * normally used (except e.g. for reading SD registers).
1101          */
1102         mmc->max_phys_segs = 32;
1103         mmc->max_hw_segs = 32;
1104         mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
1105         mmc->max_seg_size = mmc->max_sectors * 512;
1106
1107         if (host->power_pin >= 0) {
1108                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1109                         dev_err(mmc_dev(host->mmc),
1110                                 "Unable to get GPIO pin for MMC power\n");
1111                         goto out;
1112                 }
1113                 omap_set_gpio_direction(host->power_pin, 0);
1114         }
1115
1116         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1117         if (ret)
1118                 goto out;
1119
1120         host->dev = &pdev->dev;
1121         platform_set_drvdata(pdev, host);
1122
1123         mmc_add_host(mmc);
1124
1125         if (host->switch_pin >= 0) {
1126                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
1127                 init_timer(&host->switch_timer);
1128                 host->switch_timer.function = mmc_omap_switch_timer;
1129                 host->switch_timer.data = (unsigned long) host;
1130                 if (omap_request_gpio(host->switch_pin) != 0) {
1131                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1132                         host->switch_pin = -1;
1133                         goto no_switch;
1134                 }
1135
1136                 omap_set_gpio_direction(host->switch_pin, 1);
1137                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1138                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1139                 if (ret) {
1140                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1141                         omap_free_gpio(host->switch_pin);
1142                         host->switch_pin = -1;
1143                         goto no_switch;
1144                 }
1145                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1146                 if (ret == 0) {
1147                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1148                         if (ret != 0)
1149                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1150                 }
1151                 if (ret) {
1152                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1153                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1154                         omap_free_gpio(host->switch_pin);
1155                         host->switch_pin = -1;
1156                         goto no_switch;
1157                 }
1158                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1159                         schedule_work(&host->switch_work);
1160         }
1161
1162 no_switch:
1163         return 0;
1164
1165 out:
1166         /* FIXME: Free other resources too. */
1167         if (host) {
1168                 if (host->iclk && !IS_ERR(host->iclk))
1169                         clk_put(host->iclk);
1170                 if (host->fclk && !IS_ERR(host->fclk))
1171                         clk_put(host->fclk);
1172                 mmc_free_host(host->mmc);
1173         }
1174         return ret;
1175 }
1176
1177 static int mmc_omap_remove(struct platform_device *pdev)
1178 {
1179         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1180
1181         platform_set_drvdata(pdev, NULL);
1182
1183         if (host) {
1184                 mmc_remove_host(host->mmc);
1185                 free_irq(host->irq, host);
1186
1187                 if (host->power_pin >= 0)
1188                         omap_free_gpio(host->power_pin);
1189                 if (host->switch_pin >= 0) {
1190                         device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1191                         device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1192                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1193                         omap_free_gpio(host->switch_pin);
1194                         host->switch_pin = -1;
1195                         del_timer_sync(&host->switch_timer);
1196                         flush_scheduled_work();
1197                 }
1198                 if (host->iclk && !IS_ERR(host->iclk))
1199                         clk_put(host->iclk);
1200                 if (host->fclk && !IS_ERR(host->fclk))
1201                         clk_put(host->fclk);
1202                 mmc_free_host(host->mmc);
1203         }
1204
1205         release_mem_region(pdev->resource[0].start,
1206                         pdev->resource[0].end - pdev->resource[0].start + 1);
1207
1208         return 0;
1209 }
1210
1211 #ifdef CONFIG_PM
1212 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1213 {
1214         int ret = 0;
1215         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1216
1217         if (host && host->suspended)
1218                 return 0;
1219
1220         if (host) {
1221                 ret = mmc_suspend_host(host->mmc, mesg);
1222                 if (ret == 0)
1223                         host->suspended = 1;
1224         }
1225         return ret;
1226 }
1227
1228 static int mmc_omap_resume(struct platform_device *pdev)
1229 {
1230         int ret = 0;
1231         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1232
1233         if (host && !host->suspended)
1234                 return 0;
1235
1236         if (host) {
1237                 ret = mmc_resume_host(host->mmc);
1238                 if (ret == 0)
1239                         host->suspended = 0;
1240         }
1241
1242         return ret;
1243 }
1244 #else
1245 #define mmc_omap_suspend        NULL
1246 #define mmc_omap_resume         NULL
1247 #endif
1248
1249 static struct platform_driver mmc_omap_driver = {
1250         .probe          = mmc_omap_probe,
1251         .remove         = mmc_omap_remove,
1252         .suspend        = mmc_omap_suspend,
1253         .resume         = mmc_omap_resume,
1254         .driver         = {
1255                 .name   = DRIVER_NAME,
1256         },
1257 };
1258
1259 static int __init mmc_omap_init(void)
1260 {
1261         return platform_driver_register(&mmc_omap_driver);
1262 }
1263
1264 static void __exit mmc_omap_exit(void)
1265 {
1266         platform_driver_unregister(&mmc_omap_driver);
1267 }
1268
1269 module_init(mmc_omap_init);
1270 module_exit(mmc_omap_exit);
1271
1272 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1273 MODULE_LICENSE("GPL");
1274 MODULE_ALIAS(DRIVER_NAME);
1275 MODULE_AUTHOR("Juha Yrjölä");