drivers/mmc/omap.c

   1 /*
   2  *  linux/drivers/media/mmc/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/config.h>
  15
  16 // #define CONFIG_MMC_DEBUG
  17 #ifdef CONFIG_MMC_DEBUG
  18 #define DEBUG   /* for dev_dbg(), pr_debug(), etc */
  19 #endif
  20
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/init.h>
  24 #include <linux/ioport.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/delay.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/timer.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/protocol.h>
  33 #include <linux/mmc/card.h>
  34 #include <linux/clk.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/irq.h>
  38 #include <asm/scatterlist.h>
  39 #include <asm/mach-types.h>
  40
  41 #include <asm/arch/board.h>
  42 #include <asm/arch/gpio.h>
  43 #include <asm/arch/dma.h>
  44 #include <asm/arch/mux.h>
  45 #include <asm/arch/fpga.h>
  46 #include <asm/arch/tps65010.h>
  47 #include <asm/arch/menelaus.h>
  48
  49 #include "omap.h"
  50
  51 #define DRIVER_NAME "mmci-omap"
  52
  53 #ifdef CONFIG_MMC_DEBUG
  54 #define DBG(x...)       pr_debug(x)
  55 //#define DBG(x...)     printk(x)
  56 #else
  57 #define DBG(x...)       do { } while (0)
  58 #endif
  59
  60 /* Specifies how often in millisecs to poll for card status changes
  61  * when the cover switch is open */
  62 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  63
  64 static int mmc_omap_enable_poll = 1;
  65
  66 struct mmc_omap_host {
  67         int                     initialized;
  68         int                     suspended;
  69         struct mmc_request *    mrq;
  70         struct mmc_command *    cmd;
  71         struct mmc_data *       data;
  72         struct mmc_host *       mmc;
  73         struct device *         dev;
  74         unsigned char           id; /* 16xx chips have 2 MMC blocks */
  75         struct clk *            iclk;
  76         struct clk *            fclk;
  77         void __iomem            *base;
  78         int                     irq;
  79         unsigned char           bus_mode;
  80         unsigned char           hw_bus_mode;
  81
  82         unsigned int            sg_len;
  83         int                     sg_idx;
  84         u16 *                   buffer;
  85         u32                     buffer_bytes_left;
  86         u32                     total_bytes_left;
  87         struct timer_list       xfer_timer;
  88
  89         unsigned                use_dma:1;
  90         unsigned                brs_received:1, dma_done:1;
  91         unsigned                dma_is_read:1;
  92         unsigned                dma_in_use:1;
  93         int                     dma_ch;
  94         spinlock_t              dma_lock;
  95         struct timer_list       dma_timer;
  96         unsigned                dma_len;
  97
  98         short                   power_pin;
  99         short                   wp_pin;
 100
 101         int                     switch_pin;
 102         struct work_struct      switch_work;
 103         struct timer_list       switch_timer;
 104         int                     switch_last_state;
 105 };
 106
 107 static inline int
 108 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 109 {
 110         if (host->switch_pin < 0)
 111                 return 0;
 112         return omap_get_gpio_datain(host->switch_pin);
 113 }
 114
 115 static ssize_t
 116 mmc_omap_show_cover_switch(struct device *dev,
 117         struct device_attribute *attr, char *buf)
 118 {
 119         struct mmc_omap_host *host = dev_get_drvdata(dev);
 120
 121         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" : "closed");
 122 }
 123
 124 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 125
 126 static ssize_t
 127 mmc_omap_show_enable_poll(struct device *dev,
 128         struct device_attribute *attr, char *buf)
 129 {
 130         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 131 }
 132
 133 static ssize_t
 134 mmc_omap_store_enable_poll(struct device *dev,
 135         struct device_attribute *attr, const char *buf,
 136         size_t size)
 137 {
 138         int enable_poll;
 139
 140         if (sscanf(buf, "%10d", &enable_poll) != 1)
 141                 return -EINVAL;
 142
 143         if (enable_poll != mmc_omap_enable_poll) {
 144                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 145
 146                 mmc_omap_enable_poll = enable_poll;
 147                 if (enable_poll && host->switch_pin >= 0)
 148                         schedule_work(&host->switch_work);
 149         }
 150         return size;
 151 }
 152
 153 static DEVICE_ATTR(enable_poll, 0664,
 154                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 155
 156 static void
 157 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 158 {
 159         u32 cmdreg;
 160         u32 resptype;
 161         u32 cmdtype;
 162
 163         pr_debug("MMC%d: CMD%d, argument 0x%08x%s%s%s%s\n",
 164                 host->id, cmd->opcode, cmd->arg,
 165                 (cmd->flags & MMC_RSP_SHORT) ?  ", 32-bit response" : "",
 166                 (cmd->flags & MMC_RSP_LONG) ?  ", 128-bit response" : "",
 167                 (cmd->flags & MMC_RSP_CRC) ?  ", CRC" : "",
 168                 (cmd->flags & MMC_RSP_BUSY) ?  ", busy notification" : "");
 169
 170         host->cmd = cmd;
 171
 172         resptype = 0;
 173         cmdtype = 0;
 174
 175         /*
 176          * On 24xx we may have external MMC transceiver on Menelaus.
 177          * In that case we need to manually toggle between open-drain
 178          * and push-pull states.
 179          */
 180         if (omap_has_menelaus() && (host->bus_mode != host->hw_bus_mode)) {
 181                 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 182                         menelaus_mmc_opendrain(1);
 183                 else
 184                         menelaus_mmc_opendrain(0);
 185                 host->hw_bus_mode = host->bus_mode;
 186         }
 187
 188         if (!(cmd->flags & MMC_RSP_PRESENT))
 189                 resptype = 0;                   /* Resp 0 */
 190
 191         if (cmd->flags & MMC_RSP_136)
 192                 resptype = 2;                   /* Resp 2 */
 193         else {
 194                 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 195                         resptype = 3;           /* Resp 3 */
 196                 else
 197                         resptype = 1;           /* Resp 1, Resp 1b */
 198         }
 199
 200         /* Protocol layer does not provide command type, but our hardware
 201          * needs it!
 202          * any data transfer means adtc type (but that information is not
 203          * in command structure, so we flagged it into host struct.)
 204          * However, telling bc, bcr and ac apart based on response is
 205          * not foolproof:
 206          * CMD0  = bc  = resp0  CMD15 = ac  = resp0
 207          * CMD2  = bcr = resp2  CMD10 = ac  = resp2
 208          *
 209          * Resolve to best guess with some exception testing:
 210          * resp0 -> bc, except CMD15 = ac
 211          * rest are ac, except if opendrain
 212          */
 213         if (host->data) {
 214                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 215         } else if (resptype == 0 && cmd->opcode != 15) {
 216                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 217         } else if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) {
 218                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 219         } else {
 220                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 221         }
 222
 223         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 224
 225         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 226                 cmdreg |= 1 << 6;
 227
 228         if (cmd->flags & MMC_RSP_BUSY)
 229                 cmdreg |= 1 << 11;
 230
 231         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 232                 cmdreg |= 1 << 15;
 233
 234         clk_enable(host->fclk);
 235
 236         OMAP_MMC_WRITE(host->base, CTO, 200);
 237         OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff);
 238         OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16);
 239         OMAP_MMC_WRITE(host->base, IE,
 240                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 241                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 242                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 243                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 244                        OMAP_MMC_STAT_END_OF_DATA);
 245         OMAP_MMC_WRITE(host->base, CMD, cmdreg);
 246 }
 247
 248 static void
 249 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 250 {
 251         del_timer_sync(&host->xfer_timer);
 252
 253         if (host->dma_in_use) {
 254                 enum dma_data_direction dma_data_dir;
 255
 256                 BUG_ON(host->dma_ch < 0);
 257                 if (data->error != MMC_ERR_NONE)
 258                         omap_stop_dma(host->dma_ch);
 259                 /* Release DMA channel lazily */
 260                 mod_timer(&host->dma_timer, jiffies + HZ);
 261                 if (data->flags & MMC_DATA_WRITE)
 262                         dma_data_dir = DMA_TO_DEVICE;
 263                 else
 264                         dma_data_dir = DMA_FROM_DEVICE;
 265                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 266                              dma_data_dir);
 267         }
 268         host->data = NULL;
 269         host->sg_len = 0;
 270         clk_disable(host->fclk);
 271
 272         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 273          * dozens of requests until the card finishes writing data.
 274          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 275          */
 276
 277         if (!data->stop) {
 278                 host->mrq = NULL;
 279                 mmc_request_done(host->mmc, data->mrq);
 280                 return;
 281         }
 282
 283         mmc_omap_start_command(host, data->stop);
 284 }
 285
 286 static void
 287 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 288 {
 289         unsigned long flags;
 290         int done;
 291
 292         if (!host->dma_in_use) {
 293                 mmc_omap_xfer_done(host, data);
 294                 return;
 295         }
 296         done = 0;
 297         spin_lock_irqsave(&host->dma_lock, flags);
 298         if (host->dma_done)
 299                 done = 1;
 300         else
 301                 host->brs_received = 1;
 302         spin_unlock_irqrestore(&host->dma_lock, flags);
 303         if (done)
 304                 mmc_omap_xfer_done(host, data);
 305 }
 306
 307 static void
 308 mmc_omap_dma_timer(unsigned long data)
 309 {
 310         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 311
 312         DBG("MMC%d: Freeing DMA channel %d\n", host->id, host->dma_ch);
 313         BUG_ON(host->dma_ch < 0);
 314         omap_free_dma(host->dma_ch);
 315         host->dma_ch = -1;
 316 }
 317
 318 static void
 319 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 320 {
 321         unsigned long flags;
 322         int done;
 323
 324         done = 0;
 325         spin_lock_irqsave(&host->dma_lock, flags);
 326         if (host->brs_received)
 327                 done = 1;
 328         else
 329                 host->dma_done = 1;
 330         spin_unlock_irqrestore(&host->dma_lock, flags);
 331         if (done)
 332                 mmc_omap_xfer_done(host, data);
 333 }
 334
 335 static void
 336 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd, int card_ready)
 337 {
 338         host->cmd = NULL;
 339
 340         if (cmd->flags & MMC_RSP_136) {
 341                 /* Response type 2 */
 342                 cmd->resp[3] =
 343                         OMAP_MMC_READ(host->base, RSP0) |
 344                         (OMAP_MMC_READ(host->base, RSP1) << 16);
 345                 cmd->resp[2] =
 346                         OMAP_MMC_READ(host->base, RSP2) |
 347                         (OMAP_MMC_READ(host->base, RSP3) << 16);
 348                 cmd->resp[1] =
 349                         OMAP_MMC_READ(host->base, RSP4) |
 350                         (OMAP_MMC_READ(host->base, RSP5) << 16);
 351                 cmd->resp[0] =
 352                         OMAP_MMC_READ(host->base, RSP6) |
 353                         (OMAP_MMC_READ(host->base, RSP7) << 16);
 354                 DBG("MMC%d: Response %08x %08x %08x %08x\n", host->id,
 355                     cmd->resp[0], cmd->resp[1],
 356                     cmd->resp[2], cmd->resp[3]);
 357         } else {
 358                 /* Response types 1, 1b, 3, 4, 5, 6 */
 359                 cmd->resp[0] =
 360                         OMAP_MMC_READ(host->base, RSP6) |
 361                         (OMAP_MMC_READ(host->base, RSP7) << 16);
 362                 DBG("MMC%d: Response %08x\n", host->id, cmd->resp[0]);
 363                 if (card_ready) {
 364                         pr_debug("MMC%d: Faking card ready based on EOFB\n", host->id);
 365                         cmd->resp[0] |= R1_READY_FOR_DATA;
 366                 }
 367         }
 368
 369         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
 370                 DBG("MMC%d: End request, err %x\n", host->id, cmd->error);
 371                 if (host->data != NULL)
 372                         del_timer_sync(&host->xfer_timer);
 373                 host->mrq = NULL;
 374                 clk_disable(host->fclk);
 375                 mmc_request_done(host->mmc, cmd->mrq);
 376         }
 377 }
 378
 379 static void
 380 mmc_omap_xfer_timeout(unsigned long data)
 381 {
 382         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 383
 384         printk(KERN_ERR "MMC%d: Data xfer timeout\n", host->id);
 385         if (host->data != NULL) {
 386                 host->data->error |= MMC_ERR_TIMEOUT;
 387                 /* Perform a pseudo-reset of the MMC core logic, since
 388                  * the controller seems to get really stuck */
 389                 OMAP_MMC_WRITE(host->base, CON, OMAP_MMC_READ(host->base, CON) & ~(1 << 11));
 390                 OMAP_MMC_WRITE(host->base, CON, OMAP_MMC_READ(host->base, CON) | (1 << 11));
 391                 mmc_omap_xfer_done(host, host->data);
 392         }
 393 }
 394
 395 /* PIO only */
 396 static void
 397 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 398 {
 399         struct scatterlist *sg;
 400
 401         sg = host->data->sg + host->sg_idx;
 402         host->buffer_bytes_left = sg->length;
 403         host->buffer = page_address(sg->page) + sg->offset;
 404         if (host->buffer_bytes_left > host->total_bytes_left)
 405                 host->buffer_bytes_left = host->total_bytes_left;
 406 }
 407
 408 /* PIO only */
 409 static void
 410 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 411 {
 412         int n;
 413         void __iomem *reg;
 414         u16 *p;
 415
 416         if (host->buffer_bytes_left == 0) {
 417                 host->sg_idx++;
 418                 BUG_ON(host->sg_idx == host->sg_len);
 419                 mmc_omap_sg_to_buf(host);
 420         }
 421         n = 64;
 422         if (n > host->buffer_bytes_left)
 423                 n = host->buffer_bytes_left;
 424         host->buffer_bytes_left -= n;
 425         host->total_bytes_left -= n;
 426         host->data->bytes_xfered += n;
 427
 428         /* Optimize the loop a bit by calculating the register only
 429          * once */
 430         reg = host->base + OMAP_MMC_REG_DATA;
 431         p = host->buffer;
 432         n /= 2;
 433         if (write) {
 434                 while (n--)
 435                         __raw_writew(*p++, reg);
 436         } else {
 437                 while (n-- > 0)
 438                         *p++ = __raw_readw(reg);
 439         }
 440         host->buffer = p;
 441 }
 442
 443 static inline void mmc_omap_report_irq(u16 status)
 444 {
 445         static const char *mmc_omap_status_bits[] = {
 446                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 447                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 448         };
 449         int i, c = 0;
 450
 451         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 452                 if (status & (1 << i)) {
 453                         if (c)
 454                                 printk(" ");
 455                         printk("%s", mmc_omap_status_bits[i]);
 456                         c++;
 457                 }
 458 }
 459
 460 static irqreturn_t mmc_omap_irq(int irq, void *dev_id, struct pt_regs *regs)
 461 {
 462         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 463         u16 status;
 464         int end_command;
 465         int end_transfer;
 466         int card_ready;
 467         int transfer_error;
 468
 469         if (host->cmd == NULL && host->data == NULL) {
 470                 status = OMAP_MMC_READ(host->base, STAT);
 471                 printk(KERN_INFO "MMC%d: Spurious interrupt 0x%04x\n", host->id, status);
 472                 if (status != 0) {
 473                         OMAP_MMC_WRITE(host->base, STAT, status);
 474                         OMAP_MMC_WRITE(host->base, IE, 0);
 475                 }
 476                 return IRQ_HANDLED;
 477         }
 478
 479         end_command = 0;
 480         end_transfer = 0;
 481         card_ready = 0;
 482         transfer_error = 0;
 483
 484         while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) {
 485                 OMAP_MMC_WRITE(host->base, STAT, status); // Reset status bits
 486 #ifdef CONFIG_MMC_DEBUG
 487                 printk(KERN_DEBUG "\tMMC IRQ %04x (CMD %d): ", status,
 488                        host->cmd != NULL ? host->cmd->opcode : -1);
 489                 mmc_omap_report_irq(status);
 490                 printk("\n");
 491 #endif
 492                 if (host->total_bytes_left) {
 493                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 494                             (status & OMAP_MMC_STAT_END_OF_DATA))
 495                                 mmc_omap_xfer_data(host, 0);
 496                         if (status & OMAP_MMC_STAT_A_EMPTY)
 497                                 mmc_omap_xfer_data(host, 1);
 498                 }
 499
 500                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 501                         // Block sent/received
 502                         end_transfer = 1;
 503                 }
 504
 505                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 506                         // Data timeout
 507                         printk(KERN_DEBUG "MMC%d: Data timeout\n", host->id);
 508                         if (host->data) {
 509                                 host->data->error |= MMC_ERR_TIMEOUT;
 510                                 transfer_error = 1;
 511                         }
 512                 }
 513
 514                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 515                         // Data CRC error
 516                         if (host->data) {
 517                                 host->data->error |= MMC_ERR_BADCRC;
 518                                 printk(KERN_DEBUG "MMC%d: Data CRC error, bytes left %d\n",
 519                                        host->id, host->total_bytes_left);
 520                                 transfer_error = 1;
 521                         } else {
 522                                 printk(KERN_DEBUG "MMC%d: Data CRC error\n",
 523                                        host->id);
 524                         }
 525                 }
 526
 527                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 528                         /* Timeouts are routine with some commands */
 529                         if (host->cmd) {
 530                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 531                                     host->cmd->opcode != MMC_SEND_OP_COND &&
 532                                     host->cmd->opcode != MMC_APP_CMD &&
 533                                     !mmc_omap_cover_is_open(host))
 534                                         printk(KERN_ERR "MMC%d: Command timeout, CMD%d\n",
 535                                                host->id, host->cmd->opcode);
 536                                 host->cmd->error |= MMC_ERR_TIMEOUT;
 537                                 end_command = 1;
 538                         }
 539                 }
 540
 541                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 542                         // Command CRC error
 543                         if (host->cmd) {
 544                                 printk(KERN_ERR "MMC%d: Command CRC error (CMD%d, arg 0x%08x)\n",
 545                                        host->id, host->cmd->opcode,
 546                                        host->cmd->arg);
 547                                 host->cmd->error |= MMC_ERR_BADCRC;
 548                                 end_command = 1;
 549                         } else
 550                                 printk(KERN_ERR "MMC%d: Command CRC error without cmd?\n", host->id);
 551                 }
 552
 553                 if (status & OMAP_MMC_STAT_OCR_BUSY) {
 554                         /* OCR Busy ... happens a lot */
 555                         if (host->cmd && host->cmd->opcode != MMC_SEND_OP_COND
 556                                 && host->cmd->opcode != MMC_SET_RELATIVE_ADDR) {
 557                                 DBG("MMC%d: OCR busy error, CMD%d\n",
 558                                        host->id, host->cmd->opcode);
 559                         }
 560                 }
 561
 562                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 563                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
 564                                 u32 response = OMAP_MMC_READ(host->base, RSP6)
 565                                         | (OMAP_MMC_READ(host->base, RSP7) << 16);
 566                                 /* STOP sometimes sets must-ignore bits */
 567                                 if (!(response & (R1_CC_ERROR
 568                                                   | R1_ILLEGAL_COMMAND
 569                                                   | R1_COM_CRC_ERROR))) {
 570                                         end_command = 1;
 571                                         continue;
 572                                 }
 573                         }
 574
 575                         // Card status error
 576                         printk(KERN_DEBUG "MMC%d: Card status error (CMD%d)\n",
 577                                host->id, host->cmd->opcode);
 578                         if (host->cmd) {
 579                                 host->cmd->error |= MMC_ERR_FAILED;
 580                                 end_command = 1;
 581                         }
 582                         if (host->data) {
 583                                 host->data->error |= MMC_ERR_FAILED;
 584                                 transfer_error = 1;
 585                         }
 586                 }
 587
 588                 /*
 589                  * NOTE: On 1610 the END_OF_CMD may come too early when
 590                  *       starting a write
 591                  */
 592                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 593                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 594                         // End of command phase
 595                         end_command = 1;
 596                 }
 597                 /*
 598                  * Some cards produce EOFB interrupt and never
 599                  * raise R1_READY_FOR_DATA bit after that.
 600                  * To avoid infinite card status polling loop,
 601                  * we must fake that bit to MMC layer.
 602                  */
 603                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 604                     (status & OMAP_MMC_STAT_END_BUSY)) {
 605                         card_ready = 1;
 606                 }
 607         }
 608
 609         if (end_command) {
 610                 mmc_omap_cmd_done(host, host->cmd, card_ready);
 611         }
 612         if (transfer_error)
 613                 mmc_omap_xfer_done(host, host->data);
 614         else if (end_transfer)
 615                 mmc_omap_end_of_data(host, host->data);
 616
 617         return IRQ_HANDLED;
 618 }
 619
 620 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id, struct pt_regs *regs)
 621 {
 622         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 623         int cover_open, detect_now;
 624
 625         cover_open = mmc_omap_cover_is_open(host);
 626         DBG("MMC%d cover is now %s\n", host->id,
 627             cover_open ? "open" : "closed");
 628         set_irq_type(OMAP_GPIO_IRQ(host->switch_pin), 0);
 629         detect_now = 0;
 630         if (host->switch_last_state != cover_open) {
 631                 /* If the cover was just opened and a card is inserted,
 632                  * we want to inform user-space about the event as soon as
 633                  * possible */
 634                 if (cover_open) {
 635                         struct mmc_card *card;
 636
 637                         list_for_each_entry(card, &host->mmc->cards, node)
 638                                 if (mmc_card_present(card))
 639                                         detect_now = 1;
 640                 }
 641         }
 642         if (detect_now)
 643                 schedule_work(&host->switch_work);
 644         else {
 645                 /* Delay the switch work a little bit to get rid of the GPIO
 646                  * line bounces */
 647                 mod_timer(&host->switch_timer,
 648                           jiffies + msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY) / 2);
 649         }
 650
 651         return IRQ_HANDLED;
 652 }
 653
 654 static void mmc_omap_switch_timer(unsigned long arg)
 655 {
 656         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 657
 658         schedule_work(&host->switch_work);
 659 }
 660
 661 /* FIXME: Handle card insertion and removal properly. Maybe use a mask
 662  * for MMC state? */
 663 static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
 664 {
 665         if (machine_is_omap_h4()) {
 666                 if (mmc_mask & 0x1)
 667                         printk("XXX card in slot 1\n");
 668                 if (mmc_mask & 0x2)
 669                         printk("XXX card in slot 2\n");
 670         } else {
 671                 /* Assume card detect connected to cover switch */
 672                 if (mmc_mask & 0x2)
 673                         printk("XXX cover open\n");
 674                 else
 675                         printk("XXX cover closed\n");
 676         }
 677 }
 678
 679 static void mmc_omap_switch_handler(void *data)
 680 {
 681         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 682         struct mmc_card *card;
 683         static int complained = 0;
 684         int cards = 0, cover_open;
 685
 686         if (host->switch_pin == -1)
 687                 return;
 688         set_irq_type(OMAP_GPIO_IRQ(host->switch_pin), IRQT_RISING | IRQT_FALLING);
 689         cover_open = mmc_omap_cover_is_open(host);
 690         if (cover_open != host->switch_last_state) {
 691                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 692                 host->switch_last_state = cover_open;
 693         }
 694         DBG("MMC cover switch handler started\n");
 695         mmc_detect_change(host->mmc, 0);
 696         list_for_each_entry(card, &host->mmc->cards, node) {
 697                 if (mmc_card_present(card))
 698                         cards++;
 699         }
 700         DBG("MMC%d: %d card(s) present\n", host->id, cards);
 701         if (cover_open) {
 702                 if (!complained) {
 703                         printk(KERN_INFO "MMC%d: cover is open\n", host->id);
 704                         complained = 1;
 705                 }
 706                 if (cover_open && (cards || mmc_omap_enable_poll))
 707                         mod_timer(&host->switch_timer, jiffies +
 708                                   msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 709         } else {
 710                 complained = 0;
 711         }
 712 }
 713
 714 /* prepare to transfer the next segment of a scatterlist */
 715 static void
 716 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 717 {
 718         int dma_ch = host->dma_ch;
 719         unsigned long data_addr;
 720         u16 buf, frame;
 721         u32 count;
 722         struct scatterlist *sg = &data->sg[host->sg_idx];
 723         int src_port = 0;
 724         int dst_port = 0;
 725         int sync_dev = 0;
 726
 727         data_addr = (unsigned long)io_v2p((void __force *) host->base) + OMAP_MMC_REG_DATA;
 728         frame = 1 << data->blksz_bits;
 729         count = (u32)sg_dma_len(sg);
 730
 731         /* the MMC layer is confused about single block writes... */
 732         if ((data->blocks == 1) && (count > (1 << data->blksz_bits))) {
 733                 pr_debug("patch bogus single block length! %d > %d\n",
 734                                 count, frame);
 735                 count = frame;
 736         }
 737         host->dma_len = count;
 738
 739         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 740          * Use 16 or 32 word frames when the blocksize is at least that large.
 741          * Blocksize is usually 512 bytes; but not for some SD reads.
 742          */
 743         if (cpu_is_omap15xx() && frame > 32)
 744                 frame = 32;
 745         else if (frame > 64)
 746                 frame = 64;
 747         count /= frame;
 748         frame >>= 1;
 749
 750         if (!(data->flags & MMC_DATA_WRITE)) {
 751                 buf = 0x800f | ((frame - 1) << 8);
 752
 753                 if (cpu_class_is_omap1()) {
 754                         src_port = OMAP_DMA_PORT_TIPB;
 755                         dst_port = OMAP_DMA_PORT_EMIFF;
 756                 }
 757                 if (cpu_is_omap24xx())
 758                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 759
 760                 omap_set_dma_src_params(dma_ch, src_port,
 761                                         OMAP_DMA_AMODE_CONSTANT,
 762                                         data_addr, 0, 0);
 763                 omap_set_dma_dest_params(dma_ch, dst_port,
 764                                          OMAP_DMA_AMODE_POST_INC,
 765                                          sg_dma_address(sg), 0, 0);
 766                 omap_set_dma_dest_data_pack(dma_ch, 1);
 767                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 768         } else {
 769                 buf = 0x0f80 | ((frame - 1) << 0);
 770
 771                 if (cpu_class_is_omap1()) {
 772                         src_port = OMAP_DMA_PORT_EMIFF;
 773                         dst_port = OMAP_DMA_PORT_TIPB;
 774                 }
 775                 if (cpu_is_omap24xx())
 776                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 777
 778                 omap_set_dma_dest_params(dma_ch, dst_port,
 779                                          OMAP_DMA_AMODE_CONSTANT,
 780                                          data_addr, 0, 0);
 781                 omap_set_dma_src_params(dma_ch, src_port,
 782                                         OMAP_DMA_AMODE_POST_INC,
 783                                         sg_dma_address(sg), 0, 0);
 784                 omap_set_dma_src_data_pack(dma_ch, 1);
 785                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 786         }
 787
 788         /* Max limit for DMA frame count is 0xffff */
 789         if (unlikely(count > 0xffff))
 790                 BUG();
 791
 792         OMAP_MMC_WRITE(host->base, BUF, buf);
 793         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 794                                      frame, count, OMAP_DMA_SYNC_FRAME,
 795                                      sync_dev, 0);
 796 }
 797
 798 /* a scatterlist segment completed */
 799 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 800 {
 801         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 802         struct mmc_data *mmcdat = host->data;
 803
 804         if (unlikely(host->dma_ch < 0)) {
 805                 printk(KERN_ERR "MMC%d: DMA callback while DMA not enabled\n",
 806                        host->id);
 807                 return;
 808         }
 809         /* FIXME: We really should do something to _handle_ the errors */
 810         if (ch_status & OMAP_DMA_TOUT_IRQ) {
 811                 printk(KERN_ERR "MMC%d: DMA timeout\n", host->id);
 812                 return;
 813         }
 814         if (ch_status & OMAP_DMA_DROP_IRQ) {
 815                 printk(KERN_ERR "MMC%d: DMA sync error\n", host->id);
 816                 return;
 817         }
 818         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 819                 /* REVISIT we should be able to avoid getting IRQs with
 820                  * just SYNC status ...
 821                  */
 822                 if ((ch_status & ~OMAP1_DMA_SYNC_IRQ))
 823                         pr_debug("MMC%d: DMA channel status: %04x\n",
 824                                host->id, ch_status);
 825                 return;
 826         }
 827         mmcdat->bytes_xfered += host->dma_len;
 828
 829         pr_debug("\tMMC DMA %d bytes CB %04x (%d segments to go), %p\n",
 830                 host->dma_len, ch_status,
 831                 host->sg_len - host->sg_idx - 1, host->data);
 832
 833         host->sg_idx++;
 834         if (host->sg_idx < host->sg_len) {
 835                 mmc_omap_prepare_dma(host, host->data);
 836                 omap_start_dma(host->dma_ch);
 837         } else
 838                 mmc_omap_dma_done(host, host->data);
 839 }
 840
 841 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 842 {
 843         const char *dev_name;
 844         int sync_dev, dma_ch, is_read, r;
 845
 846         is_read = !(data->flags & MMC_DATA_WRITE);
 847         del_timer_sync(&host->dma_timer);
 848         if (host->dma_ch >= 0) {
 849                 if (is_read == host->dma_is_read)
 850                         return 0;
 851                 omap_free_dma(host->dma_ch);
 852                 host->dma_ch = -1;
 853         }
 854
 855         if (is_read) {
 856                 if (host->id == 1) {
 857                         sync_dev = OMAP_DMA_MMC_RX;
 858                         dev_name = "MMC1 read";
 859                 } else {
 860                         sync_dev = OMAP_DMA_MMC2_RX;
 861                         dev_name = "MMC2 read";
 862                 }
 863         } else {
 864                 if (host->id == 1) {
 865                         sync_dev = OMAP_DMA_MMC_TX;
 866                         dev_name = "MMC1 write";
 867                 } else {
 868                         sync_dev = OMAP_DMA_MMC2_TX;
 869                         dev_name = "MMC2 write";
 870                 }
 871         }
 872         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 873                              host, &dma_ch);
 874         if (r != 0) {
 875                 printk("MMC%d: omap_request_dma() failed with %d\n",
 876                        host->id, r);
 877                 return r;
 878         }
 879         host->dma_ch = dma_ch;
 880         host->dma_is_read = is_read;
 881
 882         return 0;
 883 }
 884
 885 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 886 {
 887         u16 reg;
 888
 889         reg = OMAP_MMC_READ(host->base, SDIO);
 890         reg &= ~(1 << 5);
 891         OMAP_MMC_WRITE(host->base, SDIO, reg);
 892         /* Set maximum timeout */
 893         OMAP_MMC_WRITE(host->base, CTO, 0xff);
 894 }
 895
 896 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 897 {
 898         int timeout;
 899         u16 reg;
 900
 901         /* Convert ns to clock cycles by assuming 20MHz frequency
 902          * 1 cycle at 20MHz = 500 ns
 903          */
 904         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 905
 906         /* Some cards require more time to do at least the first read operation */
 907         timeout = timeout << 4;
 908
 909         /* Check if we need to use timeout multiplier register */
 910         reg = OMAP_MMC_READ(host->base, SDIO);
 911         if (timeout > 0xffff) {
 912                 reg |= (1 << 5);
 913                 timeout /= 1024;
 914         } else
 915                 reg &= ~(1 << 5);
 916         OMAP_MMC_WRITE(host->base, SDIO, reg);
 917         OMAP_MMC_WRITE(host->base, DTO, timeout);
 918 }
 919
 920 static void
 921 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 922 {
 923         struct mmc_data *data = req->data;
 924         int i, use_dma, block_size;
 925         unsigned sg_len;
 926
 927         host->data = data;
 928         if (data == NULL) {
 929                 OMAP_MMC_WRITE(host->base, BLEN, 0);
 930                 OMAP_MMC_WRITE(host->base, NBLK, 0);
 931                 OMAP_MMC_WRITE(host->base, BUF, 0);
 932                 host->dma_in_use = 0;
 933                 set_cmd_timeout(host, req);
 934                 return;
 935         }
 936
 937
 938         block_size = 1 << data->blksz_bits;
 939
 940         OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1);
 941         OMAP_MMC_WRITE(host->base, BLEN, block_size - 1);
 942         set_data_timeout(host, req);
 943
 944         /* cope with calling layer confusion; it issues "single
 945          * block" writes using multi-block scatterlists.
 946          */
 947         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 948
 949         /* Only do DMA for entire blocks */
 950         use_dma = host->use_dma;
 951         if (use_dma) {
 952                 for (i = 0; i < sg_len; i++) {
 953                         if ((data->sg[i].length % block_size) != 0) {
 954                                 use_dma = 0;
 955                                 break;
 956                         }
 957                 }
 958         }
 959
 960         host->sg_idx = 0;
 961         if (use_dma) {
 962                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 963                         enum dma_data_direction dma_data_dir;
 964
 965                         if (data->flags & MMC_DATA_WRITE)
 966                                 dma_data_dir = DMA_TO_DEVICE;
 967                         else
 968                                 dma_data_dir = DMA_FROM_DEVICE;
 969
 970                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 971                                                 sg_len, dma_data_dir);
 972                         host->total_bytes_left = 0;
 973                         mmc_omap_prepare_dma(host, req->data);
 974                         host->brs_received = 0;
 975                         host->dma_done = 0;
 976                         host->dma_in_use = 1;
 977                 } else
 978                         use_dma = 0;
 979         }
 980
 981         /* Revert to PIO? */
 982         if (!use_dma) {
 983                 OMAP_MMC_WRITE(host->base, BUF, 0x1f1f);
 984                 host->total_bytes_left = data->blocks * block_size;
 985                 host->sg_len = sg_len;
 986                 mmc_omap_sg_to_buf(host);
 987                 host->dma_in_use = 0;
 988         }
 989         mod_timer(&host->xfer_timer, jiffies + msecs_to_jiffies(500));
 990
 991         pr_debug("MMC%d: %s %s %s, DTO %d cycles + %d ns, "
 992                         "%d blocks of %d bytes, %d segments\n",
 993                 host->id, use_dma ? "DMA" : "PIO",
 994                 (data->flags & MMC_DATA_STREAM) ? "stream" : "block",
 995                 (data->flags & MMC_DATA_WRITE) ? "write" : "read",
 996                 data->timeout_clks, data->timeout_ns, data->blocks,
 997                 block_size, host->sg_len);
 998 }
 999
1000 static inline int is_broken_card(struct mmc_card *card)
1001 {
1002         int i;
1003         struct mmc_cid *c = &card->cid;
1004         static const struct broken_card_cid {
1005                 unsigned int manfid;
1006                 char prod_name[8];
1007                 unsigned char hwrev;
1008                 unsigned char fwrev;
1009         } broken_cards[] = {
1010                 { 0x00150000, "\x30\x30\x30\x30\x30\x30\x15\x00", 0x06, 0x03 },
1011         };
1012
1013         for (i = 0; i < sizeof(broken_cards)/sizeof(broken_cards[0]); i++) {
1014                 const struct broken_card_cid *b = broken_cards + i;
1015
1016                 if (b->manfid != c->manfid)
1017                         continue;
1018                 if (memcmp(b->prod_name, c->prod_name, sizeof(b->prod_name)) != 0)
1019                         continue;
1020                 if (b->hwrev != c->hwrev || b->fwrev != c->fwrev)
1021                         continue;
1022                 return 1;
1023         }
1024         return 0;
1025 }
1026
1027 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1028 {
1029         struct mmc_omap_host *host = mmc_priv(mmc);
1030
1031         WARN_ON(host->mrq != NULL);
1032
1033         host->mrq = req;
1034
1035         /* Some cards (vendor left unnamed to protect the guilty) seem to
1036          * require this delay after power-up. Otherwise we'll get mysterious
1037          * data timeouts. */
1038         if (req->cmd->opcode == MMC_SEND_CSD) {
1039                 struct mmc_card *card;
1040                 int broken_present = 0;
1041
1042                 list_for_each_entry(card, &mmc->cards, node) {
1043                         if (is_broken_card(card)) {
1044                                 broken_present = 1;
1045                                 break;
1046                         }
1047                 }
1048                 if (broken_present) {
1049                         static int complained = 0;
1050
1051                         if (!complained) {
1052                                 printk(KERN_WARNING "MMC%d: Broken card workaround enabled\n",
1053                                        host->id);
1054                                 complained = 1;
1055                         }
1056                         if (in_interrupt()) {
1057                                 /* This is nasty */
1058                                  printk(KERN_ERR "Sleeping in IRQ handler, FIXME please!\n");
1059                                  dump_stack();
1060                                  mdelay(100);
1061                         } else {
1062                                 set_current_state(TASK_UNINTERRUPTIBLE);
1063                                 schedule_timeout(100 * HZ / 1000);
1064                         }
1065                 }
1066         }
1067
1068         /* only touch fifo AFTER the controller readies it */
1069         mmc_omap_prepare_data(host, req);
1070         mmc_omap_start_command(host, req->cmd);
1071         if (host->dma_in_use)
1072                 omap_start_dma(host->dma_ch);
1073 }
1074
1075 static void innovator_fpga_socket_power(int on)
1076 {
1077 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
1078
1079         if (on) {
1080                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
1081                      OMAP1510_FPGA_POWER);
1082         } else {
1083                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
1084                      OMAP1510_FPGA_POWER);
1085         }
1086 #endif
1087 }
1088
1089 /*
1090  * Turn the socket power on/off. Innovator uses FPGA, most boards
1091  * probably use GPIO.
1092  */
1093 static void mmc_omap_power(struct mmc_omap_host *host, int on)
1094 {
1095         if (on) {
1096                 if (machine_is_omap_innovator())
1097                         innovator_fpga_socket_power(1);
1098                 else if (machine_is_omap_h2())
1099                         tps65010_set_gpio_out_value(GPIO3, HIGH);
1100                 else if (machine_is_omap_h3())
1101                         /* GPIO 4 of TPS65010 sends SD_EN signal */
1102                         tps65010_set_gpio_out_value(GPIO4, HIGH);
1103                 else if (cpu_is_omap24xx()) {
1104                         u16 reg = OMAP_MMC_READ(host->base, CON);
1105                         OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11));
1106                 } else
1107                         if (host->power_pin >= 0)
1108                                 omap_set_gpio_dataout(host->power_pin, 1);
1109         } else {
1110                 if (machine_is_omap_innovator())
1111                         innovator_fpga_socket_power(0);
1112                 else if (machine_is_omap_h2())
1113                         tps65010_set_gpio_out_value(GPIO3, LOW);
1114                 else if (machine_is_omap_h3())
1115                         tps65010_set_gpio_out_value(GPIO4, LOW);
1116                 else if (cpu_is_omap24xx()) {
1117                         u16 reg = OMAP_MMC_READ(host->base, CON);
1118                         OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11));
1119                 } else
1120                         if (host->power_pin >= 0)
1121                                 omap_set_gpio_dataout(host->power_pin, 0);
1122         }
1123 }
1124
1125 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1126 {
1127         struct mmc_omap_host *host = mmc_priv(mmc);
1128         int dsor;
1129         int realclock, i;
1130
1131         DBG("MMC%d: set_ios: clock %dHz busmode %d powermode %d Vdd %d.%02d\n",
1132             host->id, ios->clock, ios->bus_mode, ios->power_mode,
1133             ios->vdd / 100, ios->vdd % 100);
1134
1135         if (ios->power_mode == MMC_POWER_UP && ios->clock < 400000)
1136                 realclock = 400000;             /* Fix for broken stack */
1137         else
1138                 realclock = ios->clock;
1139
1140         if (ios->clock == 0)
1141                 dsor = 0;
1142         else {
1143                 int func_clk_rate = clk_get_rate(host->fclk);
1144
1145                 dsor = func_clk_rate / realclock;
1146                 if (dsor < 1)
1147                         dsor = 1;
1148
1149                 if (func_clk_rate / dsor > realclock)
1150                         dsor++;
1151
1152                 if (dsor > 250)
1153                         dsor = 250;
1154                 dsor++;
1155
1156                 if (ios->bus_width == MMC_BUS_WIDTH_4)
1157                         dsor |= 1 << 15;
1158         }
1159
1160         switch (ios->power_mode) {
1161         case MMC_POWER_OFF:
1162                 mmc_omap_power(host, 0);
1163                 break;
1164         case MMC_POWER_UP:
1165         case MMC_POWER_ON:
1166                 mmc_omap_power(host, 1);
1167                 dsor |= 1<<11;
1168                 break;
1169         }
1170
1171         host->bus_mode = ios->bus_mode;
1172         if (omap_has_menelaus()) {
1173                 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
1174                         menelaus_mmc_opendrain(1);
1175                 else
1176                         menelaus_mmc_opendrain(0);
1177         }
1178         host->hw_bus_mode = host->bus_mode;
1179
1180         clk_enable(host->fclk);
1181
1182         /* On insanely high arm_per frequencies something sometimes
1183          * goes somehow out of sync, and the POW bit is not being set,
1184          * which results in the while loop below getting stuck.
1185          * Writing to the CON register twice seems to do the trick. */
1186         for (i = 0; i < 2; i++)
1187                 OMAP_MMC_WRITE(host->base, CON, dsor);
1188         if (ios->power_mode == MMC_POWER_UP) {
1189                 /* Wait a little while for the power regulator to
1190                  * settle */
1191                 msleep(1);
1192                 /* Send clock cycles, poll completion */
1193                 OMAP_MMC_WRITE(host->base, IE, 0);
1194                 OMAP_MMC_WRITE(host->base, STAT, 0xffff);
1195                 OMAP_MMC_WRITE(host->base, CMD, 1<<7);
1196                 while (0 == (OMAP_MMC_READ(host->base, STAT) & 1));
1197                 OMAP_MMC_WRITE(host->base, STAT, 1);
1198         }
1199         clk_disable(host->fclk);
1200 }
1201
1202 static int mmc_omap_get_ro(struct mmc_host *mmc)
1203 {
1204         struct mmc_omap_host *host = mmc_priv(mmc);
1205
1206         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1207 }
1208
1209 static struct mmc_host_ops mmc_omap_ops = {
1210         .request        = mmc_omap_request,
1211         .set_ios        = mmc_omap_set_ios,
1212         .get_ro         = mmc_omap_get_ro,
1213 };
1214
1215 static int __init mmc_omap_probe(struct platform_device *pdev)
1216 {
1217         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1218         struct mmc_host *mmc;
1219         struct mmc_omap_host *host = NULL;
1220         int ret = 0;
1221
1222         if (pdev->resource[0].flags != IORESOURCE_MEM
1223             || pdev->resource[1].flags != IORESOURCE_IRQ) {
1224                 printk(KERN_ERR "mmc_omap_probe: invalid resource type\n");
1225                 return -ENODEV;
1226         }
1227
1228         if (!request_mem_region(pdev->resource[0].start,
1229                                 pdev->resource[0].end - pdev->resource[0].start + 1,
1230                                 pdev->name)) {
1231                 dev_dbg(&pdev->dev, "request_mem_region failed\n");
1232                 return -EBUSY;
1233         }
1234
1235         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1236         if (!mmc) {
1237                 ret = -ENOMEM;
1238                 goto out;
1239         }
1240
1241         host = mmc_priv(mmc);
1242         host->mmc = mmc;
1243
1244         spin_lock_init(&host->dma_lock);
1245         init_timer(&host->dma_timer);
1246         host->dma_timer.function = mmc_omap_dma_timer;
1247         host->dma_timer.data = (unsigned long) host;
1248
1249         init_timer(&host->xfer_timer);
1250         host->xfer_timer.function = mmc_omap_xfer_timeout;
1251         host->xfer_timer.data = (unsigned long) host;
1252
1253         host->id = pdev->id;
1254
1255         if (cpu_is_omap24xx()) {
1256                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1257                 if (IS_ERR(host->iclk))
1258                         goto out;
1259                 clk_enable(host->iclk);
1260         }
1261
1262         if (!cpu_is_omap24xx())
1263                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1264         else
1265                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1266
1267         if (IS_ERR(host->fclk)) {
1268                 ret = PTR_ERR(host->fclk);
1269                 goto out;
1270         }
1271
1272         /* REVISIT:
1273          * Also, use minfo->cover to decide how to manage
1274          * the card detect sensing.
1275          */
1276         host->power_pin = minfo->power_pin;
1277         host->switch_pin = minfo->switch_pin;
1278         host->wp_pin = minfo->wp_pin;
1279         host->use_dma = 1;
1280         host->dma_ch = -1;
1281
1282         host->irq = pdev->resource[1].start;
1283         host->base = (void __iomem *)pdev->resource[0].start;
1284
1285          if (minfo->wire4)
1286                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1287
1288         mmc->ops = &mmc_omap_ops;
1289         mmc->f_min = 400000;
1290         mmc->f_max = 24000000;
1291         mmc->ocr_avail = MMC_VDD_33_34;
1292
1293         /* Use scatterlist DMA to reduce per-transfer costs.
1294          * NOTE max_seg_size assumption that small blocks aren't
1295          * normally used (except e.g. for reading SD registers).
1296          */
1297         mmc->max_phys_segs = 32;
1298         mmc->max_hw_segs = 32;
1299         mmc->max_sectors = 120; /* NBLK max 11-bits, OMAP also limited by DMA */
1300         mmc->max_seg_size = mmc->max_sectors * 512;
1301
1302         if (host->power_pin >= 0) {
1303                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1304                         printk(KERN_ERR "MMC%d: Unable to get GPIO pin for MMC power\n",
1305                                host->id);
1306                         goto out;
1307                 }
1308                 omap_set_gpio_direction(host->power_pin, 0);
1309         }
1310
1311         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1312         if (ret)
1313                 goto out;
1314
1315         host->dev = &pdev->dev;
1316         platform_set_drvdata(pdev, host);
1317
1318         mmc_add_host(mmc);
1319
1320         if (host->switch_pin >= 0) {
1321                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
1322                 init_timer(&host->switch_timer);
1323                 host->switch_timer.function = mmc_omap_switch_timer;
1324                 host->switch_timer.data = (unsigned long) host;
1325                 if (omap_request_gpio(host->switch_pin) != 0) {
1326                         printk(KERN_WARNING "MMC%d: Unable to get GPIO pin for MMC cover switch\n",
1327                                host->id);
1328                         host->switch_pin = -1;
1329                         goto no_switch;
1330                 }
1331
1332                 omap_set_gpio_direction(host->switch_pin, 1);
1333                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1334                                   mmc_omap_switch_irq,
1335                                   SA_TRIGGER_RISING | SA_TRIGGER_FALLING,
1336                                   DRIVER_NAME, host);
1337                 if (ret) {
1338                         printk(KERN_WARNING "MMC%d: Unable to get IRQ for MMC cover switch\n",
1339                                host->id);
1340                         omap_free_gpio(host->switch_pin);
1341                         host->switch_pin = -1;
1342                         goto no_switch;
1343                 }
1344                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1345                 if (ret == 0) {
1346                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1347                         if (ret != 0)
1348                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1349                 }
1350                 if (ret) {
1351                         printk(KERN_WARNING "MMC%d: Unable to create sysfs attributes\n",
1352                                host->id);
1353                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1354                         omap_free_gpio(host->switch_pin);
1355                         host->switch_pin = -1;
1356                         goto no_switch;
1357                 }
1358                 host->switch_last_state = mmc_omap_cover_is_open(host);
1359                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1360                         schedule_work(&host->switch_work);
1361         }
1362
1363         if (omap_has_menelaus())
1364                 menelaus_mmc_register(mmc_omap_switch_callback,
1365           (unsigned long)&host);
1366
1367 no_switch:
1368         return 0;
1369
1370 out:
1371         /* FIXME: Free other resources too. */
1372         if (host) {
1373                 if (host->iclk && !IS_ERR(host->iclk))
1374                         clk_put(host->iclk);
1375                 if (host->fclk && !IS_ERR(host->fclk))
1376                         clk_put(host->fclk);
1377                 mmc_free_host(host->mmc);
1378         }
1379         return ret;
1380 }
1381
1382 static int mmc_omap_remove(struct platform_device *pdev)
1383 {
1384         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1385
1386         platform_set_drvdata(pdev, NULL);
1387
1388         if (host) {
1389                 mmc_remove_host(host->mmc);
1390                 free_irq(host->irq, host);
1391                 mmc_omap_power(host, 0);
1392
1393                 if (host->power_pin >= 0)
1394                         omap_free_gpio(host->power_pin);
1395                 if (host->switch_pin >= 0) {
1396                         device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1397                         device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1398                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1399                         omap_free_gpio(host->switch_pin);
1400                         host->switch_pin = -1;
1401                         del_timer_sync(&host->switch_timer);
1402                         flush_scheduled_work();
1403                 }
1404                 if (host->iclk && !IS_ERR(host->iclk))
1405                         clk_put(host->iclk);
1406                 if (host->fclk && !IS_ERR(host->fclk))
1407                         clk_put(host->fclk);
1408                 mmc_free_host(host->mmc);
1409         }
1410
1411         if (omap_has_menelaus())
1412                 menelaus_mmc_remove();
1413
1414         release_mem_region(pdev->resource[0].start,
1415                            pdev->resource[0].end - pdev->resource[0].start + 1);
1416
1417         return 0;
1418 }
1419
1420 #ifdef CONFIG_PM
1421 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1422 {
1423         int ret = 0;
1424         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1425
1426         if (host && host->suspended)
1427                 return 0;
1428
1429         if (!irqs_disabled())
1430                 return -EAGAIN;
1431
1432         if (host) {
1433                 ret = mmc_suspend_host(host->mmc, mesg);
1434                 if (ret == 0)
1435                         host->suspended = 1;
1436         }
1437         return ret;
1438 }
1439
1440 static int mmc_omap_resume(struct platform_device *pdev)
1441 {
1442         int ret = 0;
1443         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1444
1445         if (host && !host->suspended)
1446                 return 0;
1447
1448         if (host) {
1449                 ret = mmc_resume_host(host->mmc);
1450                 if (ret == 0)
1451                         host->suspended = 0;
1452         }
1453
1454         return ret;
1455 }
1456 #else
1457 #define mmc_omap_suspend        NULL
1458 #define mmc_omap_resume         NULL
1459 #endif
1460
1461 static struct platform_driver mmc_omap_driver = {
1462         .probe          = mmc_omap_probe,
1463         .remove         = mmc_omap_remove,
1464         .suspend        = mmc_omap_suspend,
1465         .resume         = mmc_omap_resume,
1466         .driver         = {
1467                 .name   = DRIVER_NAME,
1468         },
1469 };
1470
1471 static int __init mmc_omap_init(void)
1472 {
1473         return platform_driver_register(&mmc_omap_driver);
1474 }
1475
1476 static void __exit mmc_omap_exit(void)
1477 {
1478         platform_driver_unregister(&mmc_omap_driver);
1479 }
1480
1481 module_init(mmc_omap_init);
1482 module_exit(mmc_omap_exit);
1483
1484 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1485 MODULE_LICENSE("GPL");
1486 MODULE_ALIAS(DRIVER_NAME);
1487 MODULE_AUTHOR("Juha Yrjölä");