drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/highmem.h>
  14 #include <linux/pci.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/scatterlist.h>
  17
  18 #include <linux/mmc/host.h>
  19
  20 #include "sdhci.h"
  21
  22 #define DRIVER_NAME "sdhci"
  23
  24 #define DBG(f, x...) \
  25         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  26
  27 static unsigned int debug_quirks = 0;
  28
  29 /*
  30  * Different quirks to handle when the hardware deviates from a strict
  31  * interpretation of the SDHCI specification.
  32  */
  33
  34 /* Controller doesn't honor resets unless we touch the clock register */
  35 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  36 /* Controller has bad caps bits, but really supports DMA */
  37 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
  38 /* Controller doesn't like some resets when there is no card inserted. */
  39 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
  40 /* Controller doesn't like clearing the power reg before a change */
  41 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
  42 /* Controller has flaky internal state so reset it on each ios change */
  43 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
  44 /* Controller has an unusable DMA engine */
  45 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
  46 /* Controller can only DMA from 32-bit aligned addresses */
  47 #define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<6)
  48 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
  49 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<7)
  50
  51 static const struct pci_device_id pci_ids[] __devinitdata = {
  52         {
  53                 .vendor         = PCI_VENDOR_ID_RICOH,
  54                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  55                 .subvendor      = PCI_VENDOR_ID_IBM,
  56                 .subdevice      = PCI_ANY_ID,
  57                 .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  58                                   SDHCI_QUIRK_FORCE_DMA,
  59         },
  60
  61         {
  62                 .vendor         = PCI_VENDOR_ID_RICOH,
  63                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  64                 .subvendor      = PCI_ANY_ID,
  65                 .subdevice      = PCI_ANY_ID,
  66                 .driver_data    = SDHCI_QUIRK_FORCE_DMA |
  67                                   SDHCI_QUIRK_NO_CARD_NO_RESET,
  68         },
  69
  70         {
  71                 .vendor         = PCI_VENDOR_ID_TI,
  72                 .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  73                 .subvendor      = PCI_ANY_ID,
  74                 .subdevice      = PCI_ANY_ID,
  75                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  76         },
  77
  78         {
  79                 .vendor         = PCI_VENDOR_ID_ENE,
  80                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
  81                 .subvendor      = PCI_ANY_ID,
  82                 .subdevice      = PCI_ANY_ID,
  83                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  84                                   SDHCI_QUIRK_BROKEN_DMA,
  85         },
  86
  87         {
  88                 .vendor         = PCI_VENDOR_ID_ENE,
  89                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
  90                 .subvendor      = PCI_ANY_ID,
  91                 .subdevice      = PCI_ANY_ID,
  92                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  93                                   SDHCI_QUIRK_BROKEN_DMA,
  94         },
  95
  96         {
  97                 .vendor         = PCI_VENDOR_ID_ENE,
  98                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
  99                 .subvendor      = PCI_ANY_ID,
 100                 .subdevice      = PCI_ANY_ID,
 101                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 102                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
 103         },
 104
 105         {
 106                 .vendor         = PCI_VENDOR_ID_ENE,
 107                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
 108                 .subvendor      = PCI_ANY_ID,
 109                 .subdevice      = PCI_ANY_ID,
 110                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 111                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
 112         },
 113
 114         {       /* Generic SD host controller */
 115                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
 116         },
 117
 118         { /* end: all zeroes */ },
 119 };
 120
 121 MODULE_DEVICE_TABLE(pci, pci_ids);
 122
 123 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
 124 static void sdhci_finish_data(struct sdhci_host *);
 125
 126 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 127 static void sdhci_finish_command(struct sdhci_host *);
 128
 129 static void sdhci_dumpregs(struct sdhci_host *host)
 130 {
 131         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
 132
 133         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 134                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 135                 readw(host->ioaddr + SDHCI_HOST_VERSION));
 136         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 137                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
 138                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
 139         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 140                 readl(host->ioaddr + SDHCI_ARGUMENT),
 141                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
 142         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 143                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
 144                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
 145         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 146                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
 147                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
 148         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 149                 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
 150                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
 151         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 152                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
 153                 readl(host->ioaddr + SDHCI_INT_STATUS));
 154         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 155                 readl(host->ioaddr + SDHCI_INT_ENABLE),
 156                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
 157         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 158                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
 159                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
 160         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
 161                 readl(host->ioaddr + SDHCI_CAPABILITIES),
 162                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
 163
 164         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 165 }
 166
 167 /*****************************************************************************\
 168  *                                                                           *
 169  * Low level functions                                                       *
 170  *                                                                           *
 171 \*****************************************************************************/
 172
 173 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 174 {
 175         unsigned long timeout;
 176
 177         if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 178                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 179                         SDHCI_CARD_PRESENT))
 180                         return;
 181         }
 182
 183         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
 184
 185         if (mask & SDHCI_RESET_ALL)
 186                 host->clock = 0;
 187
 188         /* Wait max 100 ms */
 189         timeout = 100;
 190
 191         /* hw clears the bit when it's done */
 192         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 193                 if (timeout == 0) {
 194                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 195                                 mmc_hostname(host->mmc), (int)mask);
 196                         sdhci_dumpregs(host);
 197                         return;
 198                 }
 199                 timeout--;
 200                 mdelay(1);
 201         }
 202 }
 203
 204 static void sdhci_init(struct sdhci_host *host)
 205 {
 206         u32 intmask;
 207
 208         sdhci_reset(host, SDHCI_RESET_ALL);
 209
 210         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 211                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 212                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 213                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 214                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 215                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
 216
 217         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 218         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 219 }
 220
 221 static void sdhci_activate_led(struct sdhci_host *host)
 222 {
 223         u8 ctrl;
 224
 225         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 226         ctrl |= SDHCI_CTRL_LED;
 227         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 228 }
 229
 230 static void sdhci_deactivate_led(struct sdhci_host *host)
 231 {
 232         u8 ctrl;
 233
 234         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 235         ctrl &= ~SDHCI_CTRL_LED;
 236         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 237 }
 238
 239 /*****************************************************************************\
 240  *                                                                           *
 241  * Core functions                                                            *
 242  *                                                                           *
 243 \*****************************************************************************/
 244
 245 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 246 {
 247         return sg_virt(host->cur_sg);
 248 }
 249
 250 static inline int sdhci_next_sg(struct sdhci_host* host)
 251 {
 252         /*
 253          * Skip to next SG entry.
 254          */
 255         host->cur_sg++;
 256         host->num_sg--;
 257
 258         /*
 259          * Any entries left?
 260          */
 261         if (host->num_sg > 0) {
 262                 host->offset = 0;
 263                 host->remain = host->cur_sg->length;
 264         }
 265
 266         return host->num_sg;
 267 }
 268
 269 static void sdhci_read_block_pio(struct sdhci_host *host)
 270 {
 271         int blksize, chunk_remain;
 272         u32 data;
 273         char *buffer;
 274         int size;
 275
 276         DBG("PIO reading\n");
 277
 278         blksize = host->data->blksz;
 279         chunk_remain = 0;
 280         data = 0;
 281
 282         buffer = sdhci_sg_to_buffer(host) + host->offset;
 283
 284         while (blksize) {
 285                 if (chunk_remain == 0) {
 286                         data = readl(host->ioaddr + SDHCI_BUFFER);
 287                         chunk_remain = min(blksize, 4);
 288                 }
 289
 290                 size = min(host->remain, chunk_remain);
 291
 292                 chunk_remain -= size;
 293                 blksize -= size;
 294                 host->offset += size;
 295                 host->remain -= size;
 296
 297                 while (size) {
 298                         *buffer = data & 0xFF;
 299                         buffer++;
 300                         data >>= 8;
 301                         size--;
 302                 }
 303
 304                 if (host->remain == 0) {
 305                         if (sdhci_next_sg(host) == 0) {
 306                                 BUG_ON(blksize != 0);
 307                                 return;
 308                         }
 309                         buffer = sdhci_sg_to_buffer(host);
 310                 }
 311         }
 312 }
 313
 314 static void sdhci_write_block_pio(struct sdhci_host *host)
 315 {
 316         int blksize, chunk_remain;
 317         u32 data;
 318         char *buffer;
 319         int bytes, size;
 320
 321         DBG("PIO writing\n");
 322
 323         blksize = host->data->blksz;
 324         chunk_remain = 4;
 325         data = 0;
 326
 327         bytes = 0;
 328         buffer = sdhci_sg_to_buffer(host) + host->offset;
 329
 330         while (blksize) {
 331                 size = min(host->remain, chunk_remain);
 332
 333                 chunk_remain -= size;
 334                 blksize -= size;
 335                 host->offset += size;
 336                 host->remain -= size;
 337
 338                 while (size) {
 339                         data >>= 8;
 340                         data |= (u32)*buffer << 24;
 341                         buffer++;
 342                         size--;
 343                 }
 344
 345                 if (chunk_remain == 0) {
 346                         writel(data, host->ioaddr + SDHCI_BUFFER);
 347                         chunk_remain = min(blksize, 4);
 348                 }
 349
 350                 if (host->remain == 0) {
 351                         if (sdhci_next_sg(host) == 0) {
 352                                 BUG_ON(blksize != 0);
 353                                 return;
 354                         }
 355                         buffer = sdhci_sg_to_buffer(host);
 356                 }
 357         }
 358 }
 359
 360 static void sdhci_transfer_pio(struct sdhci_host *host)
 361 {
 362         u32 mask;
 363
 364         BUG_ON(!host->data);
 365
 366         if (host->num_sg == 0)
 367                 return;
 368
 369         if (host->data->flags & MMC_DATA_READ)
 370                 mask = SDHCI_DATA_AVAILABLE;
 371         else
 372                 mask = SDHCI_SPACE_AVAILABLE;
 373
 374         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 375                 if (host->data->flags & MMC_DATA_READ)
 376                         sdhci_read_block_pio(host);
 377                 else
 378                         sdhci_write_block_pio(host);
 379
 380                 if (host->num_sg == 0)
 381                         break;
 382         }
 383
 384         DBG("PIO transfer complete.\n");
 385 }
 386
 387 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 388 {
 389         u8 count;
 390         unsigned target_timeout, current_timeout;
 391
 392         WARN_ON(host->data);
 393
 394         if (data == NULL)
 395                 return;
 396
 397         /* Sanity checks */
 398         BUG_ON(data->blksz * data->blocks > 524288);
 399         BUG_ON(data->blksz > host->mmc->max_blk_size);
 400         BUG_ON(data->blocks > 65535);
 401
 402         host->data = data;
 403         host->data_early = 0;
 404
 405         /* timeout in us */
 406         target_timeout = data->timeout_ns / 1000 +
 407                 data->timeout_clks / host->clock;
 408
 409         /*
 410          * Figure out needed cycles.
 411          * We do this in steps in order to fit inside a 32 bit int.
 412          * The first step is the minimum timeout, which will have a
 413          * minimum resolution of 6 bits:
 414          * (1) 2^13*1000 > 2^22,
 415          * (2) host->timeout_clk < 2^16
 416          *     =>
 417          *     (1) / (2) > 2^6
 418          */
 419         count = 0;
 420         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 421         while (current_timeout < target_timeout) {
 422                 count++;
 423                 current_timeout <<= 1;
 424                 if (count >= 0xF)
 425                         break;
 426         }
 427
 428         if (count >= 0xF) {
 429                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 430                         mmc_hostname(host->mmc));
 431                 count = 0xE;
 432         }
 433
 434         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 435
 436         if (host->flags & SDHCI_USE_DMA)
 437                 host->flags |= SDHCI_REQ_USE_DMA;
 438
 439         if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
 440                 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
 441                 ((data->blksz * data->blocks) & 0x3))) {
 442                 DBG("Reverting to PIO because of transfer size (%d)\n",
 443                         data->blksz * data->blocks);
 444                 host->flags &= ~SDHCI_REQ_USE_DMA;
 445         }
 446
 447         /*
 448          * The assumption here being that alignment is the same after
 449          * translation to device address space.
 450          */
 451         if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
 452                 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 453                 (data->sg->offset & 0x3))) {
 454                 DBG("Reverting to PIO because of bad alignment\n");
 455                 host->flags &= ~SDHCI_REQ_USE_DMA;
 456         }
 457
 458         if (host->flags & SDHCI_REQ_USE_DMA) {
 459                 int count;
 460
 461                 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
 462                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 463                 BUG_ON(count != 1);
 464
 465                 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
 466         } else {
 467                 host->cur_sg = data->sg;
 468                 host->num_sg = data->sg_len;
 469
 470                 host->offset = 0;
 471                 host->remain = host->cur_sg->length;
 472         }
 473
 474         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 475         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 476                 host->ioaddr + SDHCI_BLOCK_SIZE);
 477         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 478 }
 479
 480 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 481         struct mmc_data *data)
 482 {
 483         u16 mode;
 484
 485         if (data == NULL)
 486                 return;
 487
 488         WARN_ON(!host->data);
 489
 490         mode = SDHCI_TRNS_BLK_CNT_EN;
 491         if (data->blocks > 1)
 492                 mode |= SDHCI_TRNS_MULTI;
 493         if (data->flags & MMC_DATA_READ)
 494                 mode |= SDHCI_TRNS_READ;
 495         if (host->flags & SDHCI_REQ_USE_DMA)
 496                 mode |= SDHCI_TRNS_DMA;
 497
 498         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 499 }
 500
 501 static void sdhci_finish_data(struct sdhci_host *host)
 502 {
 503         struct mmc_data *data;
 504         u16 blocks;
 505
 506         BUG_ON(!host->data);
 507
 508         data = host->data;
 509         host->data = NULL;
 510
 511         if (host->flags & SDHCI_REQ_USE_DMA) {
 512                 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
 513                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 514         }
 515
 516         /*
 517          * Controller doesn't count down when in single block mode.
 518          */
 519         if (data->blocks == 1)
 520                 blocks = (data->error == 0) ? 0 : 1;
 521         else
 522                 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
 523         data->bytes_xfered = data->blksz * (data->blocks - blocks);
 524
 525         if (!data->error && blocks) {
 526                 printk(KERN_ERR "%s: Controller signalled completion even "
 527                         "though there were blocks left.\n",
 528                         mmc_hostname(host->mmc));
 529                 data->error = -EIO;
 530         }
 531
 532         if (data->stop) {
 533                 /*
 534                  * The controller needs a reset of internal state machines
 535                  * upon error conditions.
 536                  */
 537                 if (data->error) {
 538                         sdhci_reset(host, SDHCI_RESET_CMD);
 539                         sdhci_reset(host, SDHCI_RESET_DATA);
 540                 }
 541
 542                 sdhci_send_command(host, data->stop);
 543         } else
 544                 tasklet_schedule(&host->finish_tasklet);
 545 }
 546
 547 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 548 {
 549         int flags;
 550         u32 mask;
 551         unsigned long timeout;
 552
 553         WARN_ON(host->cmd);
 554
 555         /* Wait max 10 ms */
 556         timeout = 10;
 557
 558         mask = SDHCI_CMD_INHIBIT;
 559         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 560                 mask |= SDHCI_DATA_INHIBIT;
 561
 562         /* We shouldn't wait for data inihibit for stop commands, even
 563            though they might use busy signaling */
 564         if (host->mrq->data && (cmd == host->mrq->data->stop))
 565                 mask &= ~SDHCI_DATA_INHIBIT;
 566
 567         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 568                 if (timeout == 0) {
 569                         printk(KERN_ERR "%s: Controller never released "
 570                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 571                         sdhci_dumpregs(host);
 572                         cmd->error = -EIO;
 573                         tasklet_schedule(&host->finish_tasklet);
 574                         return;
 575                 }
 576                 timeout--;
 577                 mdelay(1);
 578         }
 579
 580         mod_timer(&host->timer, jiffies + 10 * HZ);
 581
 582         host->cmd = cmd;
 583
 584         sdhci_prepare_data(host, cmd->data);
 585
 586         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 587
 588         sdhci_set_transfer_mode(host, cmd->data);
 589
 590         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 591                 printk(KERN_ERR "%s: Unsupported response type!\n",
 592                         mmc_hostname(host->mmc));
 593                 cmd->error = -EINVAL;
 594                 tasklet_schedule(&host->finish_tasklet);
 595                 return;
 596         }
 597
 598         if (!(cmd->flags & MMC_RSP_PRESENT))
 599                 flags = SDHCI_CMD_RESP_NONE;
 600         else if (cmd->flags & MMC_RSP_136)
 601                 flags = SDHCI_CMD_RESP_LONG;
 602         else if (cmd->flags & MMC_RSP_BUSY)
 603                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 604         else
 605                 flags = SDHCI_CMD_RESP_SHORT;
 606
 607         if (cmd->flags & MMC_RSP_CRC)
 608                 flags |= SDHCI_CMD_CRC;
 609         if (cmd->flags & MMC_RSP_OPCODE)
 610                 flags |= SDHCI_CMD_INDEX;
 611         if (cmd->data)
 612                 flags |= SDHCI_CMD_DATA;
 613
 614         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 615                 host->ioaddr + SDHCI_COMMAND);
 616 }
 617
 618 static void sdhci_finish_command(struct sdhci_host *host)
 619 {
 620         int i;
 621
 622         BUG_ON(host->cmd == NULL);
 623
 624         if (host->cmd->flags & MMC_RSP_PRESENT) {
 625                 if (host->cmd->flags & MMC_RSP_136) {
 626                         /* CRC is stripped so we need to do some shifting. */
 627                         for (i = 0;i < 4;i++) {
 628                                 host->cmd->resp[i] = readl(host->ioaddr +
 629                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 630                                 if (i != 3)
 631                                         host->cmd->resp[i] |=
 632                                                 readb(host->ioaddr +
 633                                                 SDHCI_RESPONSE + (3-i)*4-1);
 634                         }
 635                 } else {
 636                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 637                 }
 638         }
 639
 640         host->cmd->error = 0;
 641
 642         if (host->data && host->data_early)
 643                 sdhci_finish_data(host);
 644
 645         if (!host->cmd->data)
 646                 tasklet_schedule(&host->finish_tasklet);
 647
 648         host->cmd = NULL;
 649 }
 650
 651 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 652 {
 653         int div;
 654         u16 clk;
 655         unsigned long timeout;
 656
 657         if (clock == host->clock)
 658                 return;
 659
 660         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 661
 662         if (clock == 0)
 663                 goto out;
 664
 665         for (div = 1;div < 256;div *= 2) {
 666                 if ((host->max_clk / div) <= clock)
 667                         break;
 668         }
 669         div >>= 1;
 670
 671         clk = div << SDHCI_DIVIDER_SHIFT;
 672         clk |= SDHCI_CLOCK_INT_EN;
 673         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 674
 675         /* Wait max 10 ms */
 676         timeout = 10;
 677         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 678                 & SDHCI_CLOCK_INT_STABLE)) {
 679                 if (timeout == 0) {
 680                         printk(KERN_ERR "%s: Internal clock never "
 681                                 "stabilised.\n", mmc_hostname(host->mmc));
 682                         sdhci_dumpregs(host);
 683                         return;
 684                 }
 685                 timeout--;
 686                 mdelay(1);
 687         }
 688
 689         clk |= SDHCI_CLOCK_CARD_EN;
 690         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 691
 692 out:
 693         host->clock = clock;
 694 }
 695
 696 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 697 {
 698         u8 pwr;
 699
 700         if (host->power == power)
 701                 return;
 702
 703         if (power == (unsigned short)-1) {
 704                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 705                 goto out;
 706         }
 707
 708         /*
 709          * Spec says that we should clear the power reg before setting
 710          * a new value. Some controllers don't seem to like this though.
 711          */
 712         if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 713                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 714
 715         pwr = SDHCI_POWER_ON;
 716
 717         switch (1 << power) {
 718         case MMC_VDD_165_195:
 719                 pwr |= SDHCI_POWER_180;
 720                 break;
 721         case MMC_VDD_29_30:
 722         case MMC_VDD_30_31:
 723                 pwr |= SDHCI_POWER_300;
 724                 break;
 725         case MMC_VDD_32_33:
 726         case MMC_VDD_33_34:
 727                 pwr |= SDHCI_POWER_330;
 728                 break;
 729         default:
 730                 BUG();
 731         }
 732
 733         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 734
 735 out:
 736         host->power = power;
 737 }
 738
 739 /*****************************************************************************\
 740  *                                                                           *
 741  * MMC callbacks                                                             *
 742  *                                                                           *
 743 \*****************************************************************************/
 744
 745 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 746 {
 747         struct sdhci_host *host;
 748         unsigned long flags;
 749
 750         host = mmc_priv(mmc);
 751
 752         spin_lock_irqsave(&host->lock, flags);
 753
 754         WARN_ON(host->mrq != NULL);
 755
 756         sdhci_activate_led(host);
 757
 758         host->mrq = mrq;
 759
 760         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 761                 host->mrq->cmd->error = -ENOMEDIUM;
 762                 tasklet_schedule(&host->finish_tasklet);
 763         } else
 764                 sdhci_send_command(host, mrq->cmd);
 765
 766         mmiowb();
 767         spin_unlock_irqrestore(&host->lock, flags);
 768 }
 769
 770 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 771 {
 772         struct sdhci_host *host;
 773         unsigned long flags;
 774         u8 ctrl;
 775
 776         host = mmc_priv(mmc);
 777
 778         spin_lock_irqsave(&host->lock, flags);
 779
 780         /*
 781          * Reset the chip on each power off.
 782          * Should clear out any weird states.
 783          */
 784         if (ios->power_mode == MMC_POWER_OFF) {
 785                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 786                 sdhci_init(host);
 787         }
 788
 789         sdhci_set_clock(host, ios->clock);
 790
 791         if (ios->power_mode == MMC_POWER_OFF)
 792                 sdhci_set_power(host, -1);
 793         else
 794                 sdhci_set_power(host, ios->vdd);
 795
 796         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 797
 798         if (ios->bus_width == MMC_BUS_WIDTH_4)
 799                 ctrl |= SDHCI_CTRL_4BITBUS;
 800         else
 801                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 802
 803         if (ios->timing == MMC_TIMING_SD_HS)
 804                 ctrl |= SDHCI_CTRL_HISPD;
 805         else
 806                 ctrl &= ~SDHCI_CTRL_HISPD;
 807
 808         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 809
 810         /*
 811          * Some (ENE) controllers go apeshit on some ios operation,
 812          * signalling timeout and CRC errors even on CMD0. Resetting
 813          * it on each ios seems to solve the problem.
 814          */
 815         if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
 816                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 817
 818         mmiowb();
 819         spin_unlock_irqrestore(&host->lock, flags);
 820 }
 821
 822 static int sdhci_get_ro(struct mmc_host *mmc)
 823 {
 824         struct sdhci_host *host;
 825         unsigned long flags;
 826         int present;
 827
 828         host = mmc_priv(mmc);
 829
 830         spin_lock_irqsave(&host->lock, flags);
 831
 832         present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 833
 834         spin_unlock_irqrestore(&host->lock, flags);
 835
 836         return !(present & SDHCI_WRITE_PROTECT);
 837 }
 838
 839 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 840 {
 841         struct sdhci_host *host;
 842         unsigned long flags;
 843         u32 ier;
 844
 845         host = mmc_priv(mmc);
 846
 847         spin_lock_irqsave(&host->lock, flags);
 848
 849         ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
 850
 851         ier &= ~SDHCI_INT_CARD_INT;
 852         if (enable)
 853                 ier |= SDHCI_INT_CARD_INT;
 854
 855         writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
 856         writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 857
 858         mmiowb();
 859
 860         spin_unlock_irqrestore(&host->lock, flags);
 861 }
 862
 863 static const struct mmc_host_ops sdhci_ops = {
 864         .request        = sdhci_request,
 865         .set_ios        = sdhci_set_ios,
 866         .get_ro         = sdhci_get_ro,
 867         .enable_sdio_irq = sdhci_enable_sdio_irq,
 868 };
 869
 870 /*****************************************************************************\
 871  *                                                                           *
 872  * Tasklets                                                                  *
 873  *                                                                           *
 874 \*****************************************************************************/
 875
 876 static void sdhci_tasklet_card(unsigned long param)
 877 {
 878         struct sdhci_host *host;
 879         unsigned long flags;
 880
 881         host = (struct sdhci_host*)param;
 882
 883         spin_lock_irqsave(&host->lock, flags);
 884
 885         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 886                 if (host->mrq) {
 887                         printk(KERN_ERR "%s: Card removed during transfer!\n",
 888                                 mmc_hostname(host->mmc));
 889                         printk(KERN_ERR "%s: Resetting controller.\n",
 890                                 mmc_hostname(host->mmc));
 891
 892                         sdhci_reset(host, SDHCI_RESET_CMD);
 893                         sdhci_reset(host, SDHCI_RESET_DATA);
 894
 895                         host->mrq->cmd->error = -ENOMEDIUM;
 896                         tasklet_schedule(&host->finish_tasklet);
 897                 }
 898         }
 899
 900         spin_unlock_irqrestore(&host->lock, flags);
 901
 902         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 903 }
 904
 905 static void sdhci_tasklet_finish(unsigned long param)
 906 {
 907         struct sdhci_host *host;
 908         unsigned long flags;
 909         struct mmc_request *mrq;
 910
 911         host = (struct sdhci_host*)param;
 912
 913         spin_lock_irqsave(&host->lock, flags);
 914
 915         del_timer(&host->timer);
 916
 917         mrq = host->mrq;
 918
 919         /*
 920          * The controller needs a reset of internal state machines
 921          * upon error conditions.
 922          */
 923         if (mrq->cmd->error ||
 924                 (mrq->data && (mrq->data->error ||
 925                 (mrq->data->stop && mrq->data->stop->error)))) {
 926
 927                 /* Some controllers need this kick or reset won't work here */
 928                 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
 929                         unsigned int clock;
 930
 931                         /* This is to force an update */
 932                         clock = host->clock;
 933                         host->clock = 0;
 934                         sdhci_set_clock(host, clock);
 935                 }
 936
 937                 /* Spec says we should do both at the same time, but Ricoh
 938                    controllers do not like that. */
 939                 sdhci_reset(host, SDHCI_RESET_CMD);
 940                 sdhci_reset(host, SDHCI_RESET_DATA);
 941         }
 942
 943         host->mrq = NULL;
 944         host->cmd = NULL;
 945         host->data = NULL;
 946
 947         sdhci_deactivate_led(host);
 948
 949         mmiowb();
 950         spin_unlock_irqrestore(&host->lock, flags);
 951
 952         mmc_request_done(host->mmc, mrq);
 953 }
 954
 955 static void sdhci_timeout_timer(unsigned long data)
 956 {
 957         struct sdhci_host *host;
 958         unsigned long flags;
 959
 960         host = (struct sdhci_host*)data;
 961
 962         spin_lock_irqsave(&host->lock, flags);
 963
 964         if (host->mrq) {
 965                 printk(KERN_ERR "%s: Timeout waiting for hardware "
 966                         "interrupt.\n", mmc_hostname(host->mmc));
 967                 sdhci_dumpregs(host);
 968
 969                 if (host->data) {
 970                         host->data->error = -ETIMEDOUT;
 971                         sdhci_finish_data(host);
 972                 } else {
 973                         if (host->cmd)
 974                                 host->cmd->error = -ETIMEDOUT;
 975                         else
 976                                 host->mrq->cmd->error = -ETIMEDOUT;
 977
 978                         tasklet_schedule(&host->finish_tasklet);
 979                 }
 980         }
 981
 982         mmiowb();
 983         spin_unlock_irqrestore(&host->lock, flags);
 984 }
 985
 986 /*****************************************************************************\
 987  *                                                                           *
 988  * Interrupt handling                                                        *
 989  *                                                                           *
 990 \*****************************************************************************/
 991
 992 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
 993 {
 994         BUG_ON(intmask == 0);
 995
 996         if (!host->cmd) {
 997                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
 998                         "though no command operation was in progress.\n",
 999                         mmc_hostname(host->mmc), (unsigned)intmask);
1000                 sdhci_dumpregs(host);
1001                 return;
1002         }
1003
1004         if (intmask & SDHCI_INT_TIMEOUT)
1005                 host->cmd->error = -ETIMEDOUT;
1006         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1007                         SDHCI_INT_INDEX))
1008                 host->cmd->error = -EILSEQ;
1009
1010         if (host->cmd->error)
1011                 tasklet_schedule(&host->finish_tasklet);
1012         else if (intmask & SDHCI_INT_RESPONSE)
1013                 sdhci_finish_command(host);
1014 }
1015
1016 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1017 {
1018         BUG_ON(intmask == 0);
1019
1020         if (!host->data) {
1021                 /*
1022                  * A data end interrupt is sent together with the response
1023                  * for the stop command.
1024                  */
1025                 if (intmask & SDHCI_INT_DATA_END)
1026                         return;
1027
1028                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1029                         "though no data operation was in progress.\n",
1030                         mmc_hostname(host->mmc), (unsigned)intmask);
1031                 sdhci_dumpregs(host);
1032
1033                 return;
1034         }
1035
1036         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1037                 host->data->error = -ETIMEDOUT;
1038         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1039                 host->data->error = -EILSEQ;
1040
1041         if (host->data->error)
1042                 sdhci_finish_data(host);
1043         else {
1044                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1045                         sdhci_transfer_pio(host);
1046
1047                 /*
1048                  * We currently don't do anything fancy with DMA
1049                  * boundaries, but as we can't disable the feature
1050                  * we need to at least restart the transfer.
1051                  */
1052                 if (intmask & SDHCI_INT_DMA_END)
1053                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1054                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1055
1056                 if (intmask & SDHCI_INT_DATA_END) {
1057                         if (host->cmd) {
1058                                 /*
1059                                  * Data managed to finish before the
1060                                  * command completed. Make sure we do
1061                                  * things in the proper order.
1062                                  */
1063                                 host->data_early = 1;
1064                         } else {
1065                                 sdhci_finish_data(host);
1066                         }
1067                 }
1068         }
1069 }
1070
1071 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1072 {
1073         irqreturn_t result;
1074         struct sdhci_host* host = dev_id;
1075         u32 intmask;
1076         int cardint = 0;
1077
1078         spin_lock(&host->lock);
1079
1080         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1081
1082         if (!intmask || intmask == 0xffffffff) {
1083                 result = IRQ_NONE;
1084                 goto out;
1085         }
1086
1087         DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1088
1089         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1090                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1091                         host->ioaddr + SDHCI_INT_STATUS);
1092                 tasklet_schedule(&host->card_tasklet);
1093         }
1094
1095         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1096
1097         if (intmask & SDHCI_INT_CMD_MASK) {
1098                 writel(intmask & SDHCI_INT_CMD_MASK,
1099                         host->ioaddr + SDHCI_INT_STATUS);
1100                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1101         }
1102
1103         if (intmask & SDHCI_INT_DATA_MASK) {
1104                 writel(intmask & SDHCI_INT_DATA_MASK,
1105                         host->ioaddr + SDHCI_INT_STATUS);
1106                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1107         }
1108
1109         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1110
1111         intmask &= ~SDHCI_INT_ERROR;
1112
1113         if (intmask & SDHCI_INT_BUS_POWER) {
1114                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1115                         mmc_hostname(host->mmc));
1116                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1117         }
1118
1119         intmask &= ~SDHCI_INT_BUS_POWER;
1120
1121         if (intmask & SDHCI_INT_CARD_INT)
1122                 cardint = 1;
1123
1124         intmask &= ~SDHCI_INT_CARD_INT;
1125
1126         if (intmask) {
1127                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1128                         mmc_hostname(host->mmc), intmask);
1129                 sdhci_dumpregs(host);
1130
1131                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1132         }
1133
1134         result = IRQ_HANDLED;
1135
1136         mmiowb();
1137 out:
1138         spin_unlock(&host->lock);
1139
1140         /*
1141          * We have to delay this as it calls back into the driver.
1142          */
1143         if (cardint)
1144                 mmc_signal_sdio_irq(host->mmc);
1145
1146         return result;
1147 }
1148
1149 /*****************************************************************************\
1150  *                                                                           *
1151  * Suspend/resume                                                            *
1152  *                                                                           *
1153 \*****************************************************************************/
1154
1155 #ifdef CONFIG_PM
1156
1157 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1158 {
1159         struct sdhci_chip *chip;
1160         int i, ret;
1161
1162         chip = pci_get_drvdata(pdev);
1163         if (!chip)
1164                 return 0;
1165
1166         DBG("Suspending...\n");
1167
1168         for (i = 0;i < chip->num_slots;i++) {
1169                 if (!chip->hosts[i])
1170                         continue;
1171                 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1172                 if (ret) {
1173                         for (i--;i >= 0;i--)
1174                                 mmc_resume_host(chip->hosts[i]->mmc);
1175                         return ret;
1176                 }
1177         }
1178
1179         pci_save_state(pdev);
1180         pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1181
1182         for (i = 0;i < chip->num_slots;i++) {
1183                 if (!chip->hosts[i])
1184                         continue;
1185                 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1186         }
1187
1188         pci_disable_device(pdev);
1189         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1190
1191         return 0;
1192 }
1193
1194 static int sdhci_resume (struct pci_dev *pdev)
1195 {
1196         struct sdhci_chip *chip;
1197         int i, ret;
1198
1199         chip = pci_get_drvdata(pdev);
1200         if (!chip)
1201                 return 0;
1202
1203         DBG("Resuming...\n");
1204
1205         pci_set_power_state(pdev, PCI_D0);
1206         pci_restore_state(pdev);
1207         ret = pci_enable_device(pdev);
1208         if (ret)
1209                 return ret;
1210
1211         for (i = 0;i < chip->num_slots;i++) {
1212                 if (!chip->hosts[i])
1213                         continue;
1214                 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1215                         pci_set_master(pdev);
1216                 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1217                         IRQF_SHARED, chip->hosts[i]->slot_descr,
1218                         chip->hosts[i]);
1219                 if (ret)
1220                         return ret;
1221                 sdhci_init(chip->hosts[i]);
1222                 mmiowb();
1223                 ret = mmc_resume_host(chip->hosts[i]->mmc);
1224                 if (ret)
1225                         return ret;
1226         }
1227
1228         return 0;
1229 }
1230
1231 #else /* CONFIG_PM */
1232
1233 #define sdhci_suspend NULL
1234 #define sdhci_resume NULL
1235
1236 #endif /* CONFIG_PM */
1237
1238 /*****************************************************************************\
1239  *                                                                           *
1240  * Device probing/removal                                                    *
1241  *                                                                           *
1242 \*****************************************************************************/
1243
1244 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1245 {
1246         int ret;
1247         unsigned int version;
1248         struct sdhci_chip *chip;
1249         struct mmc_host *mmc;
1250         struct sdhci_host *host;
1251
1252         u8 first_bar;
1253         unsigned int caps;
1254
1255         chip = pci_get_drvdata(pdev);
1256         BUG_ON(!chip);
1257
1258         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1259         if (ret)
1260                 return ret;
1261
1262         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1263
1264         if (first_bar > 5) {
1265                 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1266                 return -ENODEV;
1267         }
1268
1269         if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1270                 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1271                 return -ENODEV;
1272         }
1273
1274         if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1275                 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1276                         "You may experience problems.\n");
1277         }
1278
1279         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1280                 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1281                 return -ENODEV;
1282         }
1283
1284         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1285                 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1286                 return -ENODEV;
1287         }
1288
1289         mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1290         if (!mmc)
1291                 return -ENOMEM;
1292
1293         host = mmc_priv(mmc);
1294         host->mmc = mmc;
1295
1296         host->chip = chip;
1297         chip->hosts[slot] = host;
1298
1299         host->bar = first_bar + slot;
1300
1301         host->addr = pci_resource_start(pdev, host->bar);
1302         host->irq = pdev->irq;
1303
1304         DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1305
1306         snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1307
1308         ret = pci_request_region(pdev, host->bar, host->slot_descr);
1309         if (ret)
1310                 goto free;
1311
1312         host->ioaddr = ioremap_nocache(host->addr,
1313                 pci_resource_len(pdev, host->bar));
1314         if (!host->ioaddr) {
1315                 ret = -ENOMEM;
1316                 goto release;
1317         }
1318
1319         sdhci_reset(host, SDHCI_RESET_ALL);
1320
1321         version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1322         version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1323         if (version > 1) {
1324                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1325                         "You may experience problems.\n", host->slot_descr,
1326                         version);
1327         }
1328
1329         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1330
1331         if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1332                 host->flags |= SDHCI_USE_DMA;
1333         else if (!(caps & SDHCI_CAN_DO_DMA))
1334                 DBG("Controller doesn't have DMA capability\n");
1335         else
1336                 host->flags |= SDHCI_USE_DMA;
1337
1338         if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1339                 (host->flags & SDHCI_USE_DMA)) {
1340                 DBG("Disabling DMA as it is marked broken\n");
1341                 host->flags &= ~SDHCI_USE_DMA;
1342         }
1343
1344         if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1345                 (host->flags & SDHCI_USE_DMA)) {
1346                 printk(KERN_WARNING "%s: Will use DMA "
1347                         "mode even though HW doesn't fully "
1348                         "claim to support it.\n", host->slot_descr);
1349         }
1350
1351         if (host->flags & SDHCI_USE_DMA) {
1352                 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1353                         printk(KERN_WARNING "%s: No suitable DMA available. "
1354                                 "Falling back to PIO.\n", host->slot_descr);
1355                         host->flags &= ~SDHCI_USE_DMA;
1356                 }
1357         }
1358
1359         if (host->flags & SDHCI_USE_DMA)
1360                 pci_set_master(pdev);
1361         else /* XXX: Hack to get MMC layer to avoid highmem */
1362                 pdev->dma_mask = 0;
1363
1364         host->max_clk =
1365                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1366         if (host->max_clk == 0) {
1367                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1368                         "frequency.\n", host->slot_descr);
1369                 ret = -ENODEV;
1370                 goto unmap;
1371         }
1372         host->max_clk *= 1000000;
1373
1374         host->timeout_clk =
1375                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1376         if (host->timeout_clk == 0) {
1377                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1378                         "frequency.\n", host->slot_descr);
1379                 ret = -ENODEV;
1380                 goto unmap;
1381         }
1382         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1383                 host->timeout_clk *= 1000;
1384
1385         /*
1386          * Set host parameters.
1387          */
1388         mmc->ops = &sdhci_ops;
1389         mmc->f_min = host->max_clk / 256;
1390         mmc->f_max = host->max_clk;
1391         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1392
1393         if (caps & SDHCI_CAN_DO_HISPD)
1394                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1395
1396         mmc->ocr_avail = 0;
1397         if (caps & SDHCI_CAN_VDD_330)
1398                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1399         if (caps & SDHCI_CAN_VDD_300)
1400                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1401         if (caps & SDHCI_CAN_VDD_180)
1402                 mmc->ocr_avail |= MMC_VDD_165_195;
1403
1404         if (mmc->ocr_avail == 0) {
1405                 printk(KERN_ERR "%s: Hardware doesn't report any "
1406                         "support voltages.\n", host->slot_descr);
1407                 ret = -ENODEV;
1408                 goto unmap;
1409         }
1410
1411         spin_lock_init(&host->lock);
1412
1413         /*
1414          * Maximum number of segments. Hardware cannot do scatter lists.
1415          */
1416         if (host->flags & SDHCI_USE_DMA)
1417                 mmc->max_hw_segs = 1;
1418         else
1419                 mmc->max_hw_segs = 16;
1420         mmc->max_phys_segs = 16;
1421
1422         /*
1423          * Maximum number of sectors in one transfer. Limited by DMA boundary
1424          * size (512KiB).
1425          */
1426         mmc->max_req_size = 524288;
1427
1428         /*
1429          * Maximum segment size. Could be one segment with the maximum number
1430          * of bytes.
1431          */
1432         mmc->max_seg_size = mmc->max_req_size;
1433
1434         /*
1435          * Maximum block size. This varies from controller to controller and
1436          * is specified in the capabilities register.
1437          */
1438         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1439         if (mmc->max_blk_size >= 3) {
1440                 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1441                         host->slot_descr);
1442                 mmc->max_blk_size = 512;
1443         } else
1444                 mmc->max_blk_size = 512 << mmc->max_blk_size;
1445
1446         /*
1447          * Maximum block count.
1448          */
1449         mmc->max_blk_count = 65535;
1450
1451         /*
1452          * Init tasklets.
1453          */
1454         tasklet_init(&host->card_tasklet,
1455                 sdhci_tasklet_card, (unsigned long)host);
1456         tasklet_init(&host->finish_tasklet,
1457                 sdhci_tasklet_finish, (unsigned long)host);
1458
1459         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1460
1461         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1462                 host->slot_descr, host);
1463         if (ret)
1464                 goto untasklet;
1465
1466         sdhci_init(host);
1467
1468 #ifdef CONFIG_MMC_DEBUG
1469         sdhci_dumpregs(host);
1470 #endif
1471
1472         mmiowb();
1473
1474         mmc_add_host(mmc);
1475
1476         printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1477                 host->addr, host->irq,
1478                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1479
1480         return 0;
1481
1482 untasklet:
1483         tasklet_kill(&host->card_tasklet);
1484         tasklet_kill(&host->finish_tasklet);
1485 unmap:
1486         iounmap(host->ioaddr);
1487 release:
1488         pci_release_region(pdev, host->bar);
1489 free:
1490         mmc_free_host(mmc);
1491
1492         return ret;
1493 }
1494
1495 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1496 {
1497         struct sdhci_chip *chip;
1498         struct mmc_host *mmc;
1499         struct sdhci_host *host;
1500
1501         chip = pci_get_drvdata(pdev);
1502         host = chip->hosts[slot];
1503         mmc = host->mmc;
1504
1505         chip->hosts[slot] = NULL;
1506
1507         mmc_remove_host(mmc);
1508
1509         sdhci_reset(host, SDHCI_RESET_ALL);
1510
1511         free_irq(host->irq, host);
1512
1513         del_timer_sync(&host->timer);
1514
1515         tasklet_kill(&host->card_tasklet);
1516         tasklet_kill(&host->finish_tasklet);
1517
1518         iounmap(host->ioaddr);
1519
1520         pci_release_region(pdev, host->bar);
1521
1522         mmc_free_host(mmc);
1523 }
1524
1525 static int __devinit sdhci_probe(struct pci_dev *pdev,
1526         const struct pci_device_id *ent)
1527 {
1528         int ret, i;
1529         u8 slots, rev;
1530         struct sdhci_chip *chip;
1531
1532         BUG_ON(pdev == NULL);
1533         BUG_ON(ent == NULL);
1534
1535         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1536
1537         printk(KERN_INFO DRIVER_NAME
1538                 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1539                 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1540                 (int)rev);
1541
1542         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1543         if (ret)
1544                 return ret;
1545
1546         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1547         DBG("found %d slot(s)\n", slots);
1548         if (slots == 0)
1549                 return -ENODEV;
1550
1551         ret = pci_enable_device(pdev);
1552         if (ret)
1553                 return ret;
1554
1555         chip = kzalloc(sizeof(struct sdhci_chip) +
1556                 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1557         if (!chip) {
1558                 ret = -ENOMEM;
1559                 goto err;
1560         }
1561
1562         chip->pdev = pdev;
1563         chip->quirks = ent->driver_data;
1564
1565         if (debug_quirks)
1566                 chip->quirks = debug_quirks;
1567
1568         chip->num_slots = slots;
1569         pci_set_drvdata(pdev, chip);
1570
1571         for (i = 0;i < slots;i++) {
1572                 ret = sdhci_probe_slot(pdev, i);
1573                 if (ret) {
1574                         for (i--;i >= 0;i--)
1575                                 sdhci_remove_slot(pdev, i);
1576                         goto free;
1577                 }
1578         }
1579
1580         return 0;
1581
1582 free:
1583         pci_set_drvdata(pdev, NULL);
1584         kfree(chip);
1585
1586 err:
1587         pci_disable_device(pdev);
1588         return ret;
1589 }
1590
1591 static void __devexit sdhci_remove(struct pci_dev *pdev)
1592 {
1593         int i;
1594         struct sdhci_chip *chip;
1595
1596         chip = pci_get_drvdata(pdev);
1597
1598         if (chip) {
1599                 for (i = 0;i < chip->num_slots;i++)
1600                         sdhci_remove_slot(pdev, i);
1601
1602                 pci_set_drvdata(pdev, NULL);
1603
1604                 kfree(chip);
1605         }
1606
1607         pci_disable_device(pdev);
1608 }
1609
1610 static struct pci_driver sdhci_driver = {
1611         .name =         DRIVER_NAME,
1612         .id_table =     pci_ids,
1613         .probe =        sdhci_probe,
1614         .remove =       __devexit_p(sdhci_remove),
1615         .suspend =      sdhci_suspend,
1616         .resume =       sdhci_resume,
1617 };
1618
1619 /*****************************************************************************\
1620  *                                                                           *
1621  * Driver init/exit                                                          *
1622  *                                                                           *
1623 \*****************************************************************************/
1624
1625 static int __init sdhci_drv_init(void)
1626 {
1627         printk(KERN_INFO DRIVER_NAME
1628                 ": Secure Digital Host Controller Interface driver\n");
1629         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1630
1631         return pci_register_driver(&sdhci_driver);
1632 }
1633
1634 static void __exit sdhci_drv_exit(void)
1635 {
1636         DBG("Exiting\n");
1637
1638         pci_unregister_driver(&sdhci_driver);
1639 }
1640
1641 module_init(sdhci_drv_init);
1642 module_exit(sdhci_drv_exit);
1643
1644 module_param(debug_quirks, uint, 0444);
1645
1646 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1647 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1648 MODULE_LICENSE("GPL");
1649
1650 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");