2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
17 #include <linux/mmc/host.h>
19 #include <asm/scatterlist.h>
23 #define DRIVER_NAME "sdhci"
25 #define DBG(f, x...) \
26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
28 static unsigned int debug_nodma = 0;
29 static unsigned int debug_forcedma = 0;
30 static unsigned int debug_quirks = 0;
32 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
33 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
34 /* Controller doesn't like some resets when there is no card inserted. */
35 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
36 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
37 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
38 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
40 static const struct pci_device_id pci_ids[] __devinitdata = {
42 .vendor = PCI_VENDOR_ID_RICOH,
43 .device = PCI_DEVICE_ID_RICOH_R5C822,
44 .subvendor = PCI_VENDOR_ID_IBM,
45 .subdevice = PCI_ANY_ID,
46 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
47 SDHCI_QUIRK_FORCE_DMA,
51 .vendor = PCI_VENDOR_ID_RICOH,
52 .device = PCI_DEVICE_ID_RICOH_R5C822,
53 .subvendor = PCI_ANY_ID,
54 .subdevice = PCI_ANY_ID,
55 .driver_data = SDHCI_QUIRK_FORCE_DMA |
56 SDHCI_QUIRK_NO_CARD_NO_RESET,
60 .vendor = PCI_VENDOR_ID_TI,
61 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
62 .subvendor = PCI_ANY_ID,
63 .subdevice = PCI_ANY_ID,
64 .driver_data = SDHCI_QUIRK_FORCE_DMA,
68 .vendor = PCI_VENDOR_ID_ENE,
69 .device = PCI_DEVICE_ID_ENE_CB712_SD,
70 .subvendor = PCI_ANY_ID,
71 .subdevice = PCI_ANY_ID,
72 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
73 SDHCI_QUIRK_BROKEN_DMA,
77 .vendor = PCI_VENDOR_ID_ENE,
78 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
79 .subvendor = PCI_ANY_ID,
80 .subdevice = PCI_ANY_ID,
81 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
82 SDHCI_QUIRK_BROKEN_DMA,
86 .vendor = PCI_VENDOR_ID_ENE,
87 .device = PCI_DEVICE_ID_ENE_CB714_SD,
88 .subvendor = PCI_ANY_ID,
89 .subdevice = PCI_ANY_ID,
90 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
91 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
95 .vendor = PCI_VENDOR_ID_ENE,
96 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
97 .subvendor = PCI_ANY_ID,
98 .subdevice = PCI_ANY_ID,
99 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
100 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
103 { /* Generic SD host controller */
104 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
107 { /* end: all zeroes */ },
110 MODULE_DEVICE_TABLE(pci, pci_ids);
112 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
113 static void sdhci_finish_data(struct sdhci_host *);
115 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
116 static void sdhci_finish_command(struct sdhci_host *);
118 static void sdhci_dumpregs(struct sdhci_host *host)
120 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
122 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
123 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
124 readw(host->ioaddr + SDHCI_HOST_VERSION));
125 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
126 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
127 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
128 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ARGUMENT),
130 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
131 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_PRESENT_STATE),
133 readb(host->ioaddr + SDHCI_HOST_CONTROL));
134 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
135 readb(host->ioaddr + SDHCI_POWER_CONTROL),
136 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
137 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
138 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
139 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
140 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
141 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
142 readl(host->ioaddr + SDHCI_INT_STATUS));
143 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
144 readl(host->ioaddr + SDHCI_INT_ENABLE),
145 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
146 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
147 readw(host->ioaddr + SDHCI_ACMD12_ERR),
148 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
149 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
150 readl(host->ioaddr + SDHCI_CAPABILITIES),
151 readl(host->ioaddr + SDHCI_MAX_CURRENT));
153 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
156 /*****************************************************************************\
158 * Low level functions *
160 \*****************************************************************************/
162 static void sdhci_reset(struct sdhci_host *host, u8 mask)
164 unsigned long timeout;
166 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
167 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
172 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
174 if (mask & SDHCI_RESET_ALL)
177 /* Wait max 100 ms */
180 /* hw clears the bit when it's done */
181 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
183 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
184 mmc_hostname(host->mmc), (int)mask);
185 sdhci_dumpregs(host);
193 static void sdhci_init(struct sdhci_host *host)
197 sdhci_reset(host, SDHCI_RESET_ALL);
199 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
200 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
201 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
202 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
203 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
204 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
206 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
207 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
210 static void sdhci_activate_led(struct sdhci_host *host)
214 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
215 ctrl |= SDHCI_CTRL_LED;
216 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
219 static void sdhci_deactivate_led(struct sdhci_host *host)
223 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
224 ctrl &= ~SDHCI_CTRL_LED;
225 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
228 /*****************************************************************************\
232 \*****************************************************************************/
234 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
236 return page_address(host->cur_sg->page) + host->cur_sg->offset;
239 static inline int sdhci_next_sg(struct sdhci_host* host)
242 * Skip to next SG entry.
250 if (host->num_sg > 0) {
252 host->remain = host->cur_sg->length;
258 static void sdhci_read_block_pio(struct sdhci_host *host)
260 int blksize, chunk_remain;
265 DBG("PIO reading\n");
267 blksize = host->data->blksz;
271 buffer = sdhci_sg_to_buffer(host) + host->offset;
274 if (chunk_remain == 0) {
275 data = readl(host->ioaddr + SDHCI_BUFFER);
276 chunk_remain = min(blksize, 4);
279 size = min(host->remain, chunk_remain);
281 chunk_remain -= size;
283 host->offset += size;
284 host->remain -= size;
287 *buffer = data & 0xFF;
293 if (host->remain == 0) {
294 if (sdhci_next_sg(host) == 0) {
295 BUG_ON(blksize != 0);
298 buffer = sdhci_sg_to_buffer(host);
303 static void sdhci_write_block_pio(struct sdhci_host *host)
305 int blksize, chunk_remain;
310 DBG("PIO writing\n");
312 blksize = host->data->blksz;
317 buffer = sdhci_sg_to_buffer(host) + host->offset;
320 size = min(host->remain, chunk_remain);
322 chunk_remain -= size;
324 host->offset += size;
325 host->remain -= size;
329 data |= (u32)*buffer << 24;
334 if (chunk_remain == 0) {
335 writel(data, host->ioaddr + SDHCI_BUFFER);
336 chunk_remain = min(blksize, 4);
339 if (host->remain == 0) {
340 if (sdhci_next_sg(host) == 0) {
341 BUG_ON(blksize != 0);
344 buffer = sdhci_sg_to_buffer(host);
349 static void sdhci_transfer_pio(struct sdhci_host *host)
355 if (host->num_sg == 0)
358 if (host->data->flags & MMC_DATA_READ)
359 mask = SDHCI_DATA_AVAILABLE;
361 mask = SDHCI_SPACE_AVAILABLE;
363 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
364 if (host->data->flags & MMC_DATA_READ)
365 sdhci_read_block_pio(host);
367 sdhci_write_block_pio(host);
369 if (host->num_sg == 0)
373 DBG("PIO transfer complete.\n");
376 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
379 unsigned target_timeout, current_timeout;
387 BUG_ON(data->blksz * data->blocks > 524288);
388 BUG_ON(data->blksz > host->mmc->max_blk_size);
389 BUG_ON(data->blocks > 65535);
392 host->data_early = 0;
395 target_timeout = data->timeout_ns / 1000 +
396 data->timeout_clks / host->clock;
399 * Figure out needed cycles.
400 * We do this in steps in order to fit inside a 32 bit int.
401 * The first step is the minimum timeout, which will have a
402 * minimum resolution of 6 bits:
403 * (1) 2^13*1000 > 2^22,
404 * (2) host->timeout_clk < 2^16
409 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
410 while (current_timeout < target_timeout) {
412 current_timeout <<= 1;
418 printk(KERN_WARNING "%s: Too large timeout requested!\n",
419 mmc_hostname(host->mmc));
423 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
425 if (host->flags & SDHCI_USE_DMA) {
428 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
429 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
432 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
434 host->cur_sg = data->sg;
435 host->num_sg = data->sg_len;
438 host->remain = host->cur_sg->length;
441 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
442 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
443 host->ioaddr + SDHCI_BLOCK_SIZE);
444 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
447 static void sdhci_set_transfer_mode(struct sdhci_host *host,
448 struct mmc_data *data)
455 WARN_ON(!host->data);
457 mode = SDHCI_TRNS_BLK_CNT_EN;
458 if (data->blocks > 1)
459 mode |= SDHCI_TRNS_MULTI;
460 if (data->flags & MMC_DATA_READ)
461 mode |= SDHCI_TRNS_READ;
462 if (host->flags & SDHCI_USE_DMA)
463 mode |= SDHCI_TRNS_DMA;
465 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
468 static void sdhci_finish_data(struct sdhci_host *host)
470 struct mmc_data *data;
478 if (host->flags & SDHCI_USE_DMA) {
479 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
480 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
484 * Controller doesn't count down when in single block mode.
486 if (data->blocks == 1)
487 blocks = (data->error == 0) ? 0 : 1;
489 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
490 data->bytes_xfered = data->blksz * (data->blocks - blocks);
492 if (!data->error && blocks) {
493 printk(KERN_ERR "%s: Controller signalled completion even "
494 "though there were blocks left.\n",
495 mmc_hostname(host->mmc));
501 * The controller needs a reset of internal state machines
502 * upon error conditions.
505 sdhci_reset(host, SDHCI_RESET_CMD);
506 sdhci_reset(host, SDHCI_RESET_DATA);
509 sdhci_send_command(host, data->stop);
511 tasklet_schedule(&host->finish_tasklet);
514 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
518 unsigned long timeout;
525 mask = SDHCI_CMD_INHIBIT;
526 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
527 mask |= SDHCI_DATA_INHIBIT;
529 /* We shouldn't wait for data inihibit for stop commands, even
530 though they might use busy signaling */
531 if (host->mrq->data && (cmd == host->mrq->data->stop))
532 mask &= ~SDHCI_DATA_INHIBIT;
534 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
536 printk(KERN_ERR "%s: Controller never released "
537 "inhibit bit(s).\n", mmc_hostname(host->mmc));
538 sdhci_dumpregs(host);
540 tasklet_schedule(&host->finish_tasklet);
547 mod_timer(&host->timer, jiffies + 10 * HZ);
551 sdhci_prepare_data(host, cmd->data);
553 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
555 sdhci_set_transfer_mode(host, cmd->data);
557 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
558 printk(KERN_ERR "%s: Unsupported response type!\n",
559 mmc_hostname(host->mmc));
560 cmd->error = -EINVAL;
561 tasklet_schedule(&host->finish_tasklet);
565 if (!(cmd->flags & MMC_RSP_PRESENT))
566 flags = SDHCI_CMD_RESP_NONE;
567 else if (cmd->flags & MMC_RSP_136)
568 flags = SDHCI_CMD_RESP_LONG;
569 else if (cmd->flags & MMC_RSP_BUSY)
570 flags = SDHCI_CMD_RESP_SHORT_BUSY;
572 flags = SDHCI_CMD_RESP_SHORT;
574 if (cmd->flags & MMC_RSP_CRC)
575 flags |= SDHCI_CMD_CRC;
576 if (cmd->flags & MMC_RSP_OPCODE)
577 flags |= SDHCI_CMD_INDEX;
579 flags |= SDHCI_CMD_DATA;
581 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
582 host->ioaddr + SDHCI_COMMAND);
585 static void sdhci_finish_command(struct sdhci_host *host)
589 BUG_ON(host->cmd == NULL);
591 if (host->cmd->flags & MMC_RSP_PRESENT) {
592 if (host->cmd->flags & MMC_RSP_136) {
593 /* CRC is stripped so we need to do some shifting. */
594 for (i = 0;i < 4;i++) {
595 host->cmd->resp[i] = readl(host->ioaddr +
596 SDHCI_RESPONSE + (3-i)*4) << 8;
598 host->cmd->resp[i] |=
600 SDHCI_RESPONSE + (3-i)*4-1);
603 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
607 host->cmd->error = 0;
609 if (host->data && host->data_early)
610 sdhci_finish_data(host);
612 if (!host->cmd->data)
613 tasklet_schedule(&host->finish_tasklet);
618 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
622 unsigned long timeout;
624 if (clock == host->clock)
627 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
632 for (div = 1;div < 256;div *= 2) {
633 if ((host->max_clk / div) <= clock)
638 clk = div << SDHCI_DIVIDER_SHIFT;
639 clk |= SDHCI_CLOCK_INT_EN;
640 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
644 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
645 & SDHCI_CLOCK_INT_STABLE)) {
647 printk(KERN_ERR "%s: Internal clock never "
648 "stabilised.\n", mmc_hostname(host->mmc));
649 sdhci_dumpregs(host);
656 clk |= SDHCI_CLOCK_CARD_EN;
657 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
663 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
667 if (host->power == power)
670 if (power == (unsigned short)-1) {
671 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
676 * Spec says that we should clear the power reg before setting
677 * a new value. Some controllers don't seem to like this though.
679 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
680 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
682 pwr = SDHCI_POWER_ON;
684 switch (1 << power) {
685 case MMC_VDD_165_195:
686 pwr |= SDHCI_POWER_180;
690 pwr |= SDHCI_POWER_300;
694 pwr |= SDHCI_POWER_330;
700 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
706 /*****************************************************************************\
710 \*****************************************************************************/
712 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
714 struct sdhci_host *host;
717 host = mmc_priv(mmc);
719 spin_lock_irqsave(&host->lock, flags);
721 WARN_ON(host->mrq != NULL);
723 sdhci_activate_led(host);
727 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
728 host->mrq->cmd->error = -ENOMEDIUM;
729 tasklet_schedule(&host->finish_tasklet);
731 sdhci_send_command(host, mrq->cmd);
734 spin_unlock_irqrestore(&host->lock, flags);
737 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
739 struct sdhci_host *host;
743 host = mmc_priv(mmc);
745 spin_lock_irqsave(&host->lock, flags);
748 * Reset the chip on each power off.
749 * Should clear out any weird states.
751 if (ios->power_mode == MMC_POWER_OFF) {
752 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
756 sdhci_set_clock(host, ios->clock);
758 if (ios->power_mode == MMC_POWER_OFF)
759 sdhci_set_power(host, -1);
761 sdhci_set_power(host, ios->vdd);
763 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
765 if (ios->bus_width == MMC_BUS_WIDTH_4)
766 ctrl |= SDHCI_CTRL_4BITBUS;
768 ctrl &= ~SDHCI_CTRL_4BITBUS;
770 if (ios->timing == MMC_TIMING_SD_HS)
771 ctrl |= SDHCI_CTRL_HISPD;
773 ctrl &= ~SDHCI_CTRL_HISPD;
775 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
778 * Some (ENE) controllers go apeshit on some ios operation,
779 * signalling timeout and CRC errors even on CMD0. Resetting
780 * it on each ios seems to solve the problem.
782 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
783 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
786 spin_unlock_irqrestore(&host->lock, flags);
789 static int sdhci_get_ro(struct mmc_host *mmc)
791 struct sdhci_host *host;
795 host = mmc_priv(mmc);
797 spin_lock_irqsave(&host->lock, flags);
799 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
801 spin_unlock_irqrestore(&host->lock, flags);
803 return !(present & SDHCI_WRITE_PROTECT);
806 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
808 struct sdhci_host *host;
812 host = mmc_priv(mmc);
814 spin_lock_irqsave(&host->lock, flags);
816 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
818 ier &= ~SDHCI_INT_CARD_INT;
820 ier |= SDHCI_INT_CARD_INT;
822 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
823 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
827 spin_unlock_irqrestore(&host->lock, flags);
830 static const struct mmc_host_ops sdhci_ops = {
831 .request = sdhci_request,
832 .set_ios = sdhci_set_ios,
833 .get_ro = sdhci_get_ro,
834 .enable_sdio_irq = sdhci_enable_sdio_irq,
837 /*****************************************************************************\
841 \*****************************************************************************/
843 static void sdhci_tasklet_card(unsigned long param)
845 struct sdhci_host *host;
848 host = (struct sdhci_host*)param;
850 spin_lock_irqsave(&host->lock, flags);
852 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
854 printk(KERN_ERR "%s: Card removed during transfer!\n",
855 mmc_hostname(host->mmc));
856 printk(KERN_ERR "%s: Resetting controller.\n",
857 mmc_hostname(host->mmc));
859 sdhci_reset(host, SDHCI_RESET_CMD);
860 sdhci_reset(host, SDHCI_RESET_DATA);
862 host->mrq->cmd->error = -ENOMEDIUM;
863 tasklet_schedule(&host->finish_tasklet);
867 spin_unlock_irqrestore(&host->lock, flags);
869 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
872 static void sdhci_tasklet_finish(unsigned long param)
874 struct sdhci_host *host;
876 struct mmc_request *mrq;
878 host = (struct sdhci_host*)param;
880 spin_lock_irqsave(&host->lock, flags);
882 del_timer(&host->timer);
887 * The controller needs a reset of internal state machines
888 * upon error conditions.
890 if (mrq->cmd->error ||
891 (mrq->data && (mrq->data->error ||
892 (mrq->data->stop && mrq->data->stop->error)))) {
894 /* Some controllers need this kick or reset won't work here */
895 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
898 /* This is to force an update */
901 sdhci_set_clock(host, clock);
904 /* Spec says we should do both at the same time, but Ricoh
905 controllers do not like that. */
906 sdhci_reset(host, SDHCI_RESET_CMD);
907 sdhci_reset(host, SDHCI_RESET_DATA);
914 sdhci_deactivate_led(host);
917 spin_unlock_irqrestore(&host->lock, flags);
919 mmc_request_done(host->mmc, mrq);
922 static void sdhci_timeout_timer(unsigned long data)
924 struct sdhci_host *host;
927 host = (struct sdhci_host*)data;
929 spin_lock_irqsave(&host->lock, flags);
932 printk(KERN_ERR "%s: Timeout waiting for hardware "
933 "interrupt.\n", mmc_hostname(host->mmc));
934 sdhci_dumpregs(host);
937 host->data->error = -ETIMEDOUT;
938 sdhci_finish_data(host);
941 host->cmd->error = -ETIMEDOUT;
943 host->mrq->cmd->error = -ETIMEDOUT;
945 tasklet_schedule(&host->finish_tasklet);
950 spin_unlock_irqrestore(&host->lock, flags);
953 /*****************************************************************************\
955 * Interrupt handling *
957 \*****************************************************************************/
959 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
961 BUG_ON(intmask == 0);
964 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
965 "though no command operation was in progress.\n",
966 mmc_hostname(host->mmc), (unsigned)intmask);
967 sdhci_dumpregs(host);
971 if (intmask & SDHCI_INT_TIMEOUT)
972 host->cmd->error = -ETIMEDOUT;
973 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
975 host->cmd->error = -EILSEQ;
977 if (host->cmd->error)
978 tasklet_schedule(&host->finish_tasklet);
979 else if (intmask & SDHCI_INT_RESPONSE)
980 sdhci_finish_command(host);
983 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
985 BUG_ON(intmask == 0);
989 * A data end interrupt is sent together with the response
990 * for the stop command.
992 if (intmask & SDHCI_INT_DATA_END)
995 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
996 "though no data operation was in progress.\n",
997 mmc_hostname(host->mmc), (unsigned)intmask);
998 sdhci_dumpregs(host);
1003 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1004 host->data->error = -ETIMEDOUT;
1005 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1006 host->data->error = -EILSEQ;
1008 if (host->data->error)
1009 sdhci_finish_data(host);
1011 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1012 sdhci_transfer_pio(host);
1015 * We currently don't do anything fancy with DMA
1016 * boundaries, but as we can't disable the feature
1017 * we need to at least restart the transfer.
1019 if (intmask & SDHCI_INT_DMA_END)
1020 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1021 host->ioaddr + SDHCI_DMA_ADDRESS);
1023 if (intmask & SDHCI_INT_DATA_END) {
1026 * Data managed to finish before the
1027 * command completed. Make sure we do
1028 * things in the proper order.
1030 host->data_early = 1;
1032 sdhci_finish_data(host);
1038 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1041 struct sdhci_host* host = dev_id;
1045 spin_lock(&host->lock);
1047 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1049 if (!intmask || intmask == 0xffffffff) {
1054 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1056 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1057 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1058 host->ioaddr + SDHCI_INT_STATUS);
1059 tasklet_schedule(&host->card_tasklet);
1062 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1064 if (intmask & SDHCI_INT_CMD_MASK) {
1065 writel(intmask & SDHCI_INT_CMD_MASK,
1066 host->ioaddr + SDHCI_INT_STATUS);
1067 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1070 if (intmask & SDHCI_INT_DATA_MASK) {
1071 writel(intmask & SDHCI_INT_DATA_MASK,
1072 host->ioaddr + SDHCI_INT_STATUS);
1073 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1076 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1078 intmask &= ~SDHCI_INT_ERROR;
1080 if (intmask & SDHCI_INT_BUS_POWER) {
1081 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1082 mmc_hostname(host->mmc));
1083 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1086 intmask &= ~SDHCI_INT_BUS_POWER;
1088 if (intmask & SDHCI_INT_CARD_INT)
1091 intmask &= ~SDHCI_INT_CARD_INT;
1094 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1095 mmc_hostname(host->mmc), intmask);
1096 sdhci_dumpregs(host);
1098 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1101 result = IRQ_HANDLED;
1105 spin_unlock(&host->lock);
1108 * We have to delay this as it calls back into the driver.
1111 mmc_signal_sdio_irq(host->mmc);
1116 /*****************************************************************************\
1120 \*****************************************************************************/
1124 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1126 struct sdhci_chip *chip;
1129 chip = pci_get_drvdata(pdev);
1133 DBG("Suspending...\n");
1135 for (i = 0;i < chip->num_slots;i++) {
1136 if (!chip->hosts[i])
1138 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1140 for (i--;i >= 0;i--)
1141 mmc_resume_host(chip->hosts[i]->mmc);
1146 pci_save_state(pdev);
1147 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1149 for (i = 0;i < chip->num_slots;i++) {
1150 if (!chip->hosts[i])
1152 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1155 pci_disable_device(pdev);
1156 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1161 static int sdhci_resume (struct pci_dev *pdev)
1163 struct sdhci_chip *chip;
1166 chip = pci_get_drvdata(pdev);
1170 DBG("Resuming...\n");
1172 pci_set_power_state(pdev, PCI_D0);
1173 pci_restore_state(pdev);
1174 ret = pci_enable_device(pdev);
1178 for (i = 0;i < chip->num_slots;i++) {
1179 if (!chip->hosts[i])
1181 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1182 pci_set_master(pdev);
1183 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1184 IRQF_SHARED, chip->hosts[i]->slot_descr,
1188 sdhci_init(chip->hosts[i]);
1190 ret = mmc_resume_host(chip->hosts[i]->mmc);
1198 #else /* CONFIG_PM */
1200 #define sdhci_suspend NULL
1201 #define sdhci_resume NULL
1203 #endif /* CONFIG_PM */
1205 /*****************************************************************************\
1207 * Device probing/removal *
1209 \*****************************************************************************/
1211 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1214 unsigned int version;
1215 struct sdhci_chip *chip;
1216 struct mmc_host *mmc;
1217 struct sdhci_host *host;
1222 chip = pci_get_drvdata(pdev);
1225 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1229 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1231 if (first_bar > 5) {
1232 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1236 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1237 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1241 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1242 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1243 "You may experience problems.\n");
1246 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1247 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1251 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1252 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1256 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1260 host = mmc_priv(mmc);
1264 chip->hosts[slot] = host;
1266 host->bar = first_bar + slot;
1268 host->addr = pci_resource_start(pdev, host->bar);
1269 host->irq = pdev->irq;
1271 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1273 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1275 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1279 host->ioaddr = ioremap_nocache(host->addr,
1280 pci_resource_len(pdev, host->bar));
1281 if (!host->ioaddr) {
1286 sdhci_reset(host, SDHCI_RESET_ALL);
1288 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1289 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1291 printk(KERN_ERR "%s: Unknown controller version (%d). "
1292 "You may experience problems.\n", host->slot_descr,
1296 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1299 DBG("DMA forced off\n");
1300 else if (debug_forcedma) {
1301 DBG("DMA forced on\n");
1302 host->flags |= SDHCI_USE_DMA;
1303 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1304 host->flags |= SDHCI_USE_DMA;
1305 else if (!(caps & SDHCI_CAN_DO_DMA))
1306 DBG("Controller doesn't have DMA capability\n");
1308 host->flags |= SDHCI_USE_DMA;
1310 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1311 (host->flags & SDHCI_USE_DMA)) {
1312 DBG("Disabling DMA as it is marked broken");
1313 host->flags &= ~SDHCI_USE_DMA;
1316 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1317 (host->flags & SDHCI_USE_DMA)) {
1318 printk(KERN_WARNING "%s: Will use DMA "
1319 "mode even though HW doesn't fully "
1320 "claim to support it.\n", host->slot_descr);
1323 if (host->flags & SDHCI_USE_DMA) {
1324 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1325 printk(KERN_WARNING "%s: No suitable DMA available. "
1326 "Falling back to PIO.\n", host->slot_descr);
1327 host->flags &= ~SDHCI_USE_DMA;
1331 if (host->flags & SDHCI_USE_DMA)
1332 pci_set_master(pdev);
1333 else /* XXX: Hack to get MMC layer to avoid highmem */
1337 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1338 if (host->max_clk == 0) {
1339 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1340 "frequency.\n", host->slot_descr);
1344 host->max_clk *= 1000000;
1347 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1348 if (host->timeout_clk == 0) {
1349 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1350 "frequency.\n", host->slot_descr);
1354 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1355 host->timeout_clk *= 1000;
1358 * Set host parameters.
1360 mmc->ops = &sdhci_ops;
1361 mmc->f_min = host->max_clk / 256;
1362 mmc->f_max = host->max_clk;
1363 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1365 if (caps & SDHCI_CAN_DO_HISPD)
1366 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1369 if (caps & SDHCI_CAN_VDD_330)
1370 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1371 if (caps & SDHCI_CAN_VDD_300)
1372 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1373 if (caps & SDHCI_CAN_VDD_180)
1374 mmc->ocr_avail |= MMC_VDD_165_195;
1376 if (mmc->ocr_avail == 0) {
1377 printk(KERN_ERR "%s: Hardware doesn't report any "
1378 "support voltages.\n", host->slot_descr);
1383 spin_lock_init(&host->lock);
1386 * Maximum number of segments. Hardware cannot do scatter lists.
1388 if (host->flags & SDHCI_USE_DMA)
1389 mmc->max_hw_segs = 1;
1391 mmc->max_hw_segs = 16;
1392 mmc->max_phys_segs = 16;
1395 * Maximum number of sectors in one transfer. Limited by DMA boundary
1398 mmc->max_req_size = 524288;
1401 * Maximum segment size. Could be one segment with the maximum number
1404 mmc->max_seg_size = mmc->max_req_size;
1407 * Maximum block size. This varies from controller to controller and
1408 * is specified in the capabilities register.
1410 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1411 if (mmc->max_blk_size >= 3) {
1412 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1414 mmc->max_blk_size = 512;
1416 mmc->max_blk_size = 512 << mmc->max_blk_size;
1419 * Maximum block count.
1421 mmc->max_blk_count = 65535;
1426 tasklet_init(&host->card_tasklet,
1427 sdhci_tasklet_card, (unsigned long)host);
1428 tasklet_init(&host->finish_tasklet,
1429 sdhci_tasklet_finish, (unsigned long)host);
1431 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1433 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1434 host->slot_descr, host);
1440 #ifdef CONFIG_MMC_DEBUG
1441 sdhci_dumpregs(host);
1448 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1449 host->addr, host->irq,
1450 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1455 tasklet_kill(&host->card_tasklet);
1456 tasklet_kill(&host->finish_tasklet);
1458 iounmap(host->ioaddr);
1460 pci_release_region(pdev, host->bar);
1467 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1469 struct sdhci_chip *chip;
1470 struct mmc_host *mmc;
1471 struct sdhci_host *host;
1473 chip = pci_get_drvdata(pdev);
1474 host = chip->hosts[slot];
1477 chip->hosts[slot] = NULL;
1479 mmc_remove_host(mmc);
1481 sdhci_reset(host, SDHCI_RESET_ALL);
1483 free_irq(host->irq, host);
1485 del_timer_sync(&host->timer);
1487 tasklet_kill(&host->card_tasklet);
1488 tasklet_kill(&host->finish_tasklet);
1490 iounmap(host->ioaddr);
1492 pci_release_region(pdev, host->bar);
1497 static int __devinit sdhci_probe(struct pci_dev *pdev,
1498 const struct pci_device_id *ent)
1502 struct sdhci_chip *chip;
1504 BUG_ON(pdev == NULL);
1505 BUG_ON(ent == NULL);
1507 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1509 printk(KERN_INFO DRIVER_NAME
1510 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1511 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1514 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1518 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1519 DBG("found %d slot(s)\n", slots);
1523 ret = pci_enable_device(pdev);
1527 chip = kzalloc(sizeof(struct sdhci_chip) +
1528 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1535 chip->quirks = ent->driver_data;
1538 chip->quirks = debug_quirks;
1540 chip->num_slots = slots;
1541 pci_set_drvdata(pdev, chip);
1543 for (i = 0;i < slots;i++) {
1544 ret = sdhci_probe_slot(pdev, i);
1546 for (i--;i >= 0;i--)
1547 sdhci_remove_slot(pdev, i);
1555 pci_set_drvdata(pdev, NULL);
1559 pci_disable_device(pdev);
1563 static void __devexit sdhci_remove(struct pci_dev *pdev)
1566 struct sdhci_chip *chip;
1568 chip = pci_get_drvdata(pdev);
1571 for (i = 0;i < chip->num_slots;i++)
1572 sdhci_remove_slot(pdev, i);
1574 pci_set_drvdata(pdev, NULL);
1579 pci_disable_device(pdev);
1582 static struct pci_driver sdhci_driver = {
1583 .name = DRIVER_NAME,
1584 .id_table = pci_ids,
1585 .probe = sdhci_probe,
1586 .remove = __devexit_p(sdhci_remove),
1587 .suspend = sdhci_suspend,
1588 .resume = sdhci_resume,
1591 /*****************************************************************************\
1593 * Driver init/exit *
1595 \*****************************************************************************/
1597 static int __init sdhci_drv_init(void)
1599 printk(KERN_INFO DRIVER_NAME
1600 ": Secure Digital Host Controller Interface driver\n");
1601 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1603 return pci_register_driver(&sdhci_driver);
1606 static void __exit sdhci_drv_exit(void)
1610 pci_unregister_driver(&sdhci_driver);
1613 module_init(sdhci_drv_init);
1614 module_exit(sdhci_drv_exit);
1616 module_param(debug_nodma, uint, 0444);
1617 module_param(debug_forcedma, uint, 0444);
1618 module_param(debug_quirks, uint, 0444);
1620 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1621 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1622 MODULE_LICENSE("GPL");
1624 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1625 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1626 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");