2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
22 #include <linux/leds.h>
24 #include <linux/mmc/host.h>
28 #define DRIVER_NAME "sdhci"
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35 #define SDHCI_USE_LEDS_CLASS
38 static unsigned int debug_quirks = 0;
40 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
41 static void sdhci_finish_data(struct sdhci_host *);
43 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
44 static void sdhci_finish_command(struct sdhci_host *);
46 static void sdhci_dumpregs(struct sdhci_host *host)
48 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
50 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
51 sdhci_readl(host, SDHCI_DMA_ADDRESS),
52 sdhci_readw(host, SDHCI_HOST_VERSION));
53 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
54 sdhci_readw(host, SDHCI_BLOCK_SIZE),
55 sdhci_readw(host, SDHCI_BLOCK_COUNT));
56 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
57 sdhci_readl(host, SDHCI_ARGUMENT),
58 sdhci_readw(host, SDHCI_TRANSFER_MODE));
59 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
60 sdhci_readl(host, SDHCI_PRESENT_STATE),
61 sdhci_readb(host, SDHCI_HOST_CONTROL));
62 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
63 sdhci_readb(host, SDHCI_POWER_CONTROL),
64 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
65 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
66 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
67 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
68 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
69 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
70 sdhci_readl(host, SDHCI_INT_STATUS));
71 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
72 sdhci_readl(host, SDHCI_INT_ENABLE),
73 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
74 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
75 sdhci_readw(host, SDHCI_ACMD12_ERR),
76 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
77 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT));
81 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
84 /*****************************************************************************\
86 * Low level functions *
88 \*****************************************************************************/
90 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
94 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
97 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
98 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
101 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
103 sdhci_clear_set_irqs(host, 0, irqs);
106 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
108 sdhci_clear_set_irqs(host, irqs, 0);
111 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
113 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
116 sdhci_unmask_irqs(host, irqs);
118 sdhci_mask_irqs(host, irqs);
121 static void sdhci_enable_card_detection(struct sdhci_host *host)
123 sdhci_set_card_detection(host, true);
126 static void sdhci_disable_card_detection(struct sdhci_host *host)
128 sdhci_set_card_detection(host, false);
131 static void sdhci_reset(struct sdhci_host *host, u8 mask)
133 unsigned long timeout;
135 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
136 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
143 if (mask & SDHCI_RESET_ALL)
146 /* Wait max 100 ms */
149 /* hw clears the bit when it's done */
150 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
152 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
153 mmc_hostname(host->mmc), (int)mask);
154 sdhci_dumpregs(host);
162 static void sdhci_init(struct sdhci_host *host)
164 sdhci_reset(host, SDHCI_RESET_ALL);
166 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
167 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
168 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
169 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
170 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
171 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
172 SDHCI_INT_ADMA_ERROR);
175 static void sdhci_reinit(struct sdhci_host *host)
178 sdhci_enable_card_detection(host);
181 static void sdhci_activate_led(struct sdhci_host *host)
185 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
186 ctrl |= SDHCI_CTRL_LED;
187 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
190 static void sdhci_deactivate_led(struct sdhci_host *host)
194 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
195 ctrl &= ~SDHCI_CTRL_LED;
196 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
199 #ifdef SDHCI_USE_LEDS_CLASS
200 static void sdhci_led_control(struct led_classdev *led,
201 enum led_brightness brightness)
203 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
206 spin_lock_irqsave(&host->lock, flags);
208 if (brightness == LED_OFF)
209 sdhci_deactivate_led(host);
211 sdhci_activate_led(host);
213 spin_unlock_irqrestore(&host->lock, flags);
217 /*****************************************************************************\
221 \*****************************************************************************/
223 static void sdhci_read_block_pio(struct sdhci_host *host)
226 size_t blksize, len, chunk;
227 u32 uninitialized_var(scratch);
230 DBG("PIO reading\n");
232 blksize = host->data->blksz;
235 local_irq_save(flags);
238 if (!sg_miter_next(&host->sg_miter))
241 len = min(host->sg_miter.length, blksize);
244 host->sg_miter.consumed = len;
246 buf = host->sg_miter.addr;
250 scratch = sdhci_readl(host, SDHCI_BUFFER);
254 *buf = scratch & 0xFF;
263 sg_miter_stop(&host->sg_miter);
265 local_irq_restore(flags);
268 static void sdhci_write_block_pio(struct sdhci_host *host)
271 size_t blksize, len, chunk;
275 DBG("PIO writing\n");
277 blksize = host->data->blksz;
281 local_irq_save(flags);
284 if (!sg_miter_next(&host->sg_miter))
287 len = min(host->sg_miter.length, blksize);
290 host->sg_miter.consumed = len;
292 buf = host->sg_miter.addr;
295 scratch |= (u32)*buf << (chunk * 8);
301 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
302 sdhci_writel(host, scratch, SDHCI_BUFFER);
309 sg_miter_stop(&host->sg_miter);
311 local_irq_restore(flags);
314 static void sdhci_transfer_pio(struct sdhci_host *host)
320 if (host->blocks == 0)
323 if (host->data->flags & MMC_DATA_READ)
324 mask = SDHCI_DATA_AVAILABLE;
326 mask = SDHCI_SPACE_AVAILABLE;
329 * Some controllers (JMicron JMB38x) mess up the buffer bits
330 * for transfers < 4 bytes. As long as it is just one block,
331 * we can ignore the bits.
333 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
334 (host->data->blocks == 1))
337 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
338 if (host->data->flags & MMC_DATA_READ)
339 sdhci_read_block_pio(host);
341 sdhci_write_block_pio(host);
344 if (host->blocks == 0)
348 DBG("PIO transfer complete.\n");
351 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
353 local_irq_save(*flags);
354 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
357 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
359 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
360 local_irq_restore(*flags);
363 static int sdhci_adma_table_pre(struct sdhci_host *host,
364 struct mmc_data *data)
371 dma_addr_t align_addr;
374 struct scatterlist *sg;
380 * The spec does not specify endianness of descriptor table.
381 * We currently guess that it is LE.
384 if (data->flags & MMC_DATA_READ)
385 direction = DMA_FROM_DEVICE;
387 direction = DMA_TO_DEVICE;
390 * The ADMA descriptor table is mapped further down as we
391 * need to fill it with data first.
394 host->align_addr = dma_map_single(mmc_dev(host->mmc),
395 host->align_buffer, 128 * 4, direction);
396 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
398 BUG_ON(host->align_addr & 0x3);
400 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
401 data->sg, data->sg_len, direction);
402 if (host->sg_count == 0)
405 desc = host->adma_desc;
406 align = host->align_buffer;
408 align_addr = host->align_addr;
410 for_each_sg(data->sg, sg, host->sg_count, i) {
411 addr = sg_dma_address(sg);
412 len = sg_dma_len(sg);
415 * The SDHCI specification states that ADMA
416 * addresses must be 32-bit aligned. If they
417 * aren't, then we use a bounce buffer for
418 * the (up to three) bytes that screw up the
421 offset = (4 - (addr & 0x3)) & 0x3;
423 if (data->flags & MMC_DATA_WRITE) {
424 buffer = sdhci_kmap_atomic(sg, &flags);
425 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
426 memcpy(align, buffer, offset);
427 sdhci_kunmap_atomic(buffer, &flags);
430 desc[7] = (align_addr >> 24) & 0xff;
431 desc[6] = (align_addr >> 16) & 0xff;
432 desc[5] = (align_addr >> 8) & 0xff;
433 desc[4] = (align_addr >> 0) & 0xff;
435 BUG_ON(offset > 65536);
437 desc[3] = (offset >> 8) & 0xff;
438 desc[2] = (offset >> 0) & 0xff;
441 desc[0] = 0x21; /* tran, valid */
452 desc[7] = (addr >> 24) & 0xff;
453 desc[6] = (addr >> 16) & 0xff;
454 desc[5] = (addr >> 8) & 0xff;
455 desc[4] = (addr >> 0) & 0xff;
459 desc[3] = (len >> 8) & 0xff;
460 desc[2] = (len >> 0) & 0xff;
463 desc[0] = 0x21; /* tran, valid */
468 * If this triggers then we have a calculation bug
471 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
475 * Add a terminating entry.
486 desc[0] = 0x03; /* nop, end, valid */
489 * Resync align buffer as we might have changed it.
491 if (data->flags & MMC_DATA_WRITE) {
492 dma_sync_single_for_device(mmc_dev(host->mmc),
493 host->align_addr, 128 * 4, direction);
496 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
497 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
498 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
500 BUG_ON(host->adma_addr & 0x3);
505 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
506 data->sg_len, direction);
508 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
514 static void sdhci_adma_table_post(struct sdhci_host *host,
515 struct mmc_data *data)
519 struct scatterlist *sg;
525 if (data->flags & MMC_DATA_READ)
526 direction = DMA_FROM_DEVICE;
528 direction = DMA_TO_DEVICE;
530 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
531 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
533 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
536 if (data->flags & MMC_DATA_READ) {
537 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
538 data->sg_len, direction);
540 align = host->align_buffer;
542 for_each_sg(data->sg, sg, host->sg_count, i) {
543 if (sg_dma_address(sg) & 0x3) {
544 size = 4 - (sg_dma_address(sg) & 0x3);
546 buffer = sdhci_kmap_atomic(sg, &flags);
547 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
548 memcpy(buffer, align, size);
549 sdhci_kunmap_atomic(buffer, &flags);
556 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
557 data->sg_len, direction);
560 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
563 unsigned target_timeout, current_timeout;
566 * If the host controller provides us with an incorrect timeout
567 * value, just skip the check and use 0xE. The hardware may take
568 * longer to time out, but that's much better than having a too-short
571 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
575 target_timeout = data->timeout_ns / 1000 +
576 data->timeout_clks / host->clock;
579 * Figure out needed cycles.
580 * We do this in steps in order to fit inside a 32 bit int.
581 * The first step is the minimum timeout, which will have a
582 * minimum resolution of 6 bits:
583 * (1) 2^13*1000 > 2^22,
584 * (2) host->timeout_clk < 2^16
589 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
590 while (current_timeout < target_timeout) {
592 current_timeout <<= 1;
598 printk(KERN_WARNING "%s: Too large timeout requested!\n",
599 mmc_hostname(host->mmc));
606 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
618 BUG_ON(data->blksz * data->blocks > 524288);
619 BUG_ON(data->blksz > host->mmc->max_blk_size);
620 BUG_ON(data->blocks > 65535);
623 host->data_early = 0;
625 count = sdhci_calc_timeout(host, data);
626 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
628 if (host->flags & SDHCI_USE_DMA)
629 host->flags |= SDHCI_REQ_USE_DMA;
632 * FIXME: This doesn't account for merging when mapping the
635 if (host->flags & SDHCI_REQ_USE_DMA) {
637 struct scatterlist *sg;
640 if (host->flags & SDHCI_USE_ADMA) {
641 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
644 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
648 if (unlikely(broken)) {
649 for_each_sg(data->sg, sg, data->sg_len, i) {
650 if (sg->length & 0x3) {
651 DBG("Reverting to PIO because of "
652 "transfer size (%d)\n",
654 host->flags &= ~SDHCI_REQ_USE_DMA;
662 * The assumption here being that alignment is the same after
663 * translation to device address space.
665 if (host->flags & SDHCI_REQ_USE_DMA) {
667 struct scatterlist *sg;
670 if (host->flags & SDHCI_USE_ADMA) {
672 * As we use 3 byte chunks to work around
673 * alignment problems, we need to check this
676 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
679 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
683 if (unlikely(broken)) {
684 for_each_sg(data->sg, sg, data->sg_len, i) {
685 if (sg->offset & 0x3) {
686 DBG("Reverting to PIO because of "
688 host->flags &= ~SDHCI_REQ_USE_DMA;
695 if (host->flags & SDHCI_REQ_USE_DMA) {
696 if (host->flags & SDHCI_USE_ADMA) {
697 ret = sdhci_adma_table_pre(host, data);
700 * This only happens when someone fed
701 * us an invalid request.
704 host->flags &= ~SDHCI_REQ_USE_DMA;
706 sdhci_writel(host, host->adma_addr,
712 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
713 data->sg, data->sg_len,
714 (data->flags & MMC_DATA_READ) ?
719 * This only happens when someone fed
720 * us an invalid request.
723 host->flags &= ~SDHCI_REQ_USE_DMA;
725 WARN_ON(sg_cnt != 1);
726 sdhci_writel(host, sg_dma_address(data->sg),
733 * Always adjust the DMA selection as some controllers
734 * (e.g. JMicron) can't do PIO properly when the selection
737 if (host->version >= SDHCI_SPEC_200) {
738 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
739 ctrl &= ~SDHCI_CTRL_DMA_MASK;
740 if ((host->flags & SDHCI_REQ_USE_DMA) &&
741 (host->flags & SDHCI_USE_ADMA))
742 ctrl |= SDHCI_CTRL_ADMA32;
744 ctrl |= SDHCI_CTRL_SDMA;
745 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
748 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
749 sg_miter_start(&host->sg_miter,
750 data->sg, data->sg_len, SG_MITER_ATOMIC);
751 host->blocks = data->blocks;
754 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
755 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
756 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
759 static void sdhci_set_transfer_mode(struct sdhci_host *host,
760 struct mmc_data *data)
767 WARN_ON(!host->data);
769 mode = SDHCI_TRNS_BLK_CNT_EN;
770 if (data->blocks > 1)
771 mode |= SDHCI_TRNS_MULTI;
772 if (data->flags & MMC_DATA_READ)
773 mode |= SDHCI_TRNS_READ;
774 if (host->flags & SDHCI_REQ_USE_DMA)
775 mode |= SDHCI_TRNS_DMA;
777 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
780 static void sdhci_finish_data(struct sdhci_host *host)
782 struct mmc_data *data;
789 if (host->flags & SDHCI_REQ_USE_DMA) {
790 if (host->flags & SDHCI_USE_ADMA)
791 sdhci_adma_table_post(host, data);
793 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
794 data->sg_len, (data->flags & MMC_DATA_READ) ?
795 DMA_FROM_DEVICE : DMA_TO_DEVICE);
800 * The specification states that the block count register must
801 * be updated, but it does not specify at what point in the
802 * data flow. That makes the register entirely useless to read
803 * back so we have to assume that nothing made it to the card
804 * in the event of an error.
807 data->bytes_xfered = 0;
809 data->bytes_xfered = data->blksz * data->blocks;
813 * The controller needs a reset of internal state machines
814 * upon error conditions.
817 sdhci_reset(host, SDHCI_RESET_CMD);
818 sdhci_reset(host, SDHCI_RESET_DATA);
821 sdhci_send_command(host, data->stop);
823 tasklet_schedule(&host->finish_tasklet);
826 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
830 unsigned long timeout;
837 mask = SDHCI_CMD_INHIBIT;
838 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
839 mask |= SDHCI_DATA_INHIBIT;
841 /* We shouldn't wait for data inihibit for stop commands, even
842 though they might use busy signaling */
843 if (host->mrq->data && (cmd == host->mrq->data->stop))
844 mask &= ~SDHCI_DATA_INHIBIT;
846 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
848 printk(KERN_ERR "%s: Controller never released "
849 "inhibit bit(s).\n", mmc_hostname(host->mmc));
850 sdhci_dumpregs(host);
852 tasklet_schedule(&host->finish_tasklet);
859 mod_timer(&host->timer, jiffies + 10 * HZ);
863 sdhci_prepare_data(host, cmd->data);
865 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
867 sdhci_set_transfer_mode(host, cmd->data);
869 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
870 printk(KERN_ERR "%s: Unsupported response type!\n",
871 mmc_hostname(host->mmc));
872 cmd->error = -EINVAL;
873 tasklet_schedule(&host->finish_tasklet);
877 if (!(cmd->flags & MMC_RSP_PRESENT))
878 flags = SDHCI_CMD_RESP_NONE;
879 else if (cmd->flags & MMC_RSP_136)
880 flags = SDHCI_CMD_RESP_LONG;
881 else if (cmd->flags & MMC_RSP_BUSY)
882 flags = SDHCI_CMD_RESP_SHORT_BUSY;
884 flags = SDHCI_CMD_RESP_SHORT;
886 if (cmd->flags & MMC_RSP_CRC)
887 flags |= SDHCI_CMD_CRC;
888 if (cmd->flags & MMC_RSP_OPCODE)
889 flags |= SDHCI_CMD_INDEX;
891 flags |= SDHCI_CMD_DATA;
893 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
896 static void sdhci_finish_command(struct sdhci_host *host)
900 BUG_ON(host->cmd == NULL);
902 if (host->cmd->flags & MMC_RSP_PRESENT) {
903 if (host->cmd->flags & MMC_RSP_136) {
904 /* CRC is stripped so we need to do some shifting. */
905 for (i = 0;i < 4;i++) {
906 host->cmd->resp[i] = sdhci_readl(host,
907 SDHCI_RESPONSE + (3-i)*4) << 8;
909 host->cmd->resp[i] |=
911 SDHCI_RESPONSE + (3-i)*4-1);
914 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
918 host->cmd->error = 0;
920 if (host->data && host->data_early)
921 sdhci_finish_data(host);
923 if (!host->cmd->data)
924 tasklet_schedule(&host->finish_tasklet);
929 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
933 unsigned long timeout;
935 if (clock == host->clock)
938 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
943 for (div = 1;div < 256;div *= 2) {
944 if ((host->max_clk / div) <= clock)
949 clk = div << SDHCI_DIVIDER_SHIFT;
950 clk |= SDHCI_CLOCK_INT_EN;
951 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
955 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
956 & SDHCI_CLOCK_INT_STABLE)) {
958 printk(KERN_ERR "%s: Internal clock never "
959 "stabilised.\n", mmc_hostname(host->mmc));
960 sdhci_dumpregs(host);
967 clk |= SDHCI_CLOCK_CARD_EN;
968 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
974 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
978 if (host->power == power)
981 if (power == (unsigned short)-1) {
982 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
987 * Spec says that we should clear the power reg before setting
988 * a new value. Some controllers don't seem to like this though.
990 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
991 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
993 pwr = SDHCI_POWER_ON;
995 switch (1 << power) {
996 case MMC_VDD_165_195:
997 pwr |= SDHCI_POWER_180;
1001 pwr |= SDHCI_POWER_300;
1005 pwr |= SDHCI_POWER_330;
1012 * At least the Marvell CaFe chip gets confused if we set the voltage
1013 * and set turn on power at the same time, so set the voltage first.
1015 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
1016 sdhci_writeb(host, pwr & ~SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1018 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1021 host->power = power;
1024 /*****************************************************************************\
1028 \*****************************************************************************/
1030 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1032 struct sdhci_host *host;
1033 unsigned long flags;
1035 host = mmc_priv(mmc);
1037 spin_lock_irqsave(&host->lock, flags);
1039 WARN_ON(host->mrq != NULL);
1041 #ifndef SDHCI_USE_LEDS_CLASS
1042 sdhci_activate_led(host);
1047 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1048 || (host->flags & SDHCI_DEVICE_DEAD)) {
1049 host->mrq->cmd->error = -ENOMEDIUM;
1050 tasklet_schedule(&host->finish_tasklet);
1052 sdhci_send_command(host, mrq->cmd);
1055 spin_unlock_irqrestore(&host->lock, flags);
1058 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1060 struct sdhci_host *host;
1061 unsigned long flags;
1064 host = mmc_priv(mmc);
1066 spin_lock_irqsave(&host->lock, flags);
1068 if (host->flags & SDHCI_DEVICE_DEAD)
1072 * Reset the chip on each power off.
1073 * Should clear out any weird states.
1075 if (ios->power_mode == MMC_POWER_OFF) {
1076 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1080 sdhci_set_clock(host, ios->clock);
1082 if (ios->power_mode == MMC_POWER_OFF)
1083 sdhci_set_power(host, -1);
1085 sdhci_set_power(host, ios->vdd);
1087 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1089 if (ios->bus_width == MMC_BUS_WIDTH_4)
1090 ctrl |= SDHCI_CTRL_4BITBUS;
1092 ctrl &= ~SDHCI_CTRL_4BITBUS;
1094 if (ios->timing == MMC_TIMING_SD_HS)
1095 ctrl |= SDHCI_CTRL_HISPD;
1097 ctrl &= ~SDHCI_CTRL_HISPD;
1099 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1102 * Some (ENE) controllers go apeshit on some ios operation,
1103 * signalling timeout and CRC errors even on CMD0. Resetting
1104 * it on each ios seems to solve the problem.
1106 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1107 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1111 spin_unlock_irqrestore(&host->lock, flags);
1114 static int sdhci_get_ro(struct mmc_host *mmc)
1116 struct sdhci_host *host;
1117 unsigned long flags;
1120 host = mmc_priv(mmc);
1122 spin_lock_irqsave(&host->lock, flags);
1124 if (host->flags & SDHCI_DEVICE_DEAD)
1127 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1129 spin_unlock_irqrestore(&host->lock, flags);
1131 return !(present & SDHCI_WRITE_PROTECT);
1134 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1136 struct sdhci_host *host;
1137 unsigned long flags;
1139 host = mmc_priv(mmc);
1141 spin_lock_irqsave(&host->lock, flags);
1143 if (host->flags & SDHCI_DEVICE_DEAD)
1147 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1149 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1153 spin_unlock_irqrestore(&host->lock, flags);
1156 static const struct mmc_host_ops sdhci_ops = {
1157 .request = sdhci_request,
1158 .set_ios = sdhci_set_ios,
1159 .get_ro = sdhci_get_ro,
1160 .enable_sdio_irq = sdhci_enable_sdio_irq,
1163 /*****************************************************************************\
1167 \*****************************************************************************/
1169 static void sdhci_tasklet_card(unsigned long param)
1171 struct sdhci_host *host;
1172 unsigned long flags;
1174 host = (struct sdhci_host*)param;
1176 spin_lock_irqsave(&host->lock, flags);
1178 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1180 printk(KERN_ERR "%s: Card removed during transfer!\n",
1181 mmc_hostname(host->mmc));
1182 printk(KERN_ERR "%s: Resetting controller.\n",
1183 mmc_hostname(host->mmc));
1185 sdhci_reset(host, SDHCI_RESET_CMD);
1186 sdhci_reset(host, SDHCI_RESET_DATA);
1188 host->mrq->cmd->error = -ENOMEDIUM;
1189 tasklet_schedule(&host->finish_tasklet);
1193 spin_unlock_irqrestore(&host->lock, flags);
1195 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1198 static void sdhci_tasklet_finish(unsigned long param)
1200 struct sdhci_host *host;
1201 unsigned long flags;
1202 struct mmc_request *mrq;
1204 host = (struct sdhci_host*)param;
1206 spin_lock_irqsave(&host->lock, flags);
1208 del_timer(&host->timer);
1213 * The controller needs a reset of internal state machines
1214 * upon error conditions.
1216 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1218 (mrq->data && (mrq->data->error ||
1219 (mrq->data->stop && mrq->data->stop->error))) ||
1220 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1222 /* Some controllers need this kick or reset won't work here */
1223 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1226 /* This is to force an update */
1227 clock = host->clock;
1229 sdhci_set_clock(host, clock);
1232 /* Spec says we should do both at the same time, but Ricoh
1233 controllers do not like that. */
1234 sdhci_reset(host, SDHCI_RESET_CMD);
1235 sdhci_reset(host, SDHCI_RESET_DATA);
1242 #ifndef SDHCI_USE_LEDS_CLASS
1243 sdhci_deactivate_led(host);
1247 spin_unlock_irqrestore(&host->lock, flags);
1249 mmc_request_done(host->mmc, mrq);
1252 static void sdhci_timeout_timer(unsigned long data)
1254 struct sdhci_host *host;
1255 unsigned long flags;
1257 host = (struct sdhci_host*)data;
1259 spin_lock_irqsave(&host->lock, flags);
1262 printk(KERN_ERR "%s: Timeout waiting for hardware "
1263 "interrupt.\n", mmc_hostname(host->mmc));
1264 sdhci_dumpregs(host);
1267 host->data->error = -ETIMEDOUT;
1268 sdhci_finish_data(host);
1271 host->cmd->error = -ETIMEDOUT;
1273 host->mrq->cmd->error = -ETIMEDOUT;
1275 tasklet_schedule(&host->finish_tasklet);
1280 spin_unlock_irqrestore(&host->lock, flags);
1283 /*****************************************************************************\
1285 * Interrupt handling *
1287 \*****************************************************************************/
1289 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1291 BUG_ON(intmask == 0);
1294 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1295 "though no command operation was in progress.\n",
1296 mmc_hostname(host->mmc), (unsigned)intmask);
1297 sdhci_dumpregs(host);
1301 if (intmask & SDHCI_INT_TIMEOUT)
1302 host->cmd->error = -ETIMEDOUT;
1303 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1305 host->cmd->error = -EILSEQ;
1307 if (host->cmd->error) {
1308 tasklet_schedule(&host->finish_tasklet);
1313 * The host can send and interrupt when the busy state has
1314 * ended, allowing us to wait without wasting CPU cycles.
1315 * Unfortunately this is overloaded on the "data complete"
1316 * interrupt, so we need to take some care when handling
1319 * Note: The 1.0 specification is a bit ambiguous about this
1320 * feature so there might be some problems with older
1323 if (host->cmd->flags & MMC_RSP_BUSY) {
1324 if (host->cmd->data)
1325 DBG("Cannot wait for busy signal when also "
1326 "doing a data transfer");
1327 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1330 /* The controller does not support the end-of-busy IRQ,
1331 * fall through and take the SDHCI_INT_RESPONSE */
1334 if (intmask & SDHCI_INT_RESPONSE)
1335 sdhci_finish_command(host);
1338 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1340 BUG_ON(intmask == 0);
1344 * The "data complete" interrupt is also used to
1345 * indicate that a busy state has ended. See comment
1346 * above in sdhci_cmd_irq().
1348 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1349 if (intmask & SDHCI_INT_DATA_END) {
1350 sdhci_finish_command(host);
1355 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1356 "though no data operation was in progress.\n",
1357 mmc_hostname(host->mmc), (unsigned)intmask);
1358 sdhci_dumpregs(host);
1363 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1364 host->data->error = -ETIMEDOUT;
1365 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1366 host->data->error = -EILSEQ;
1367 else if (intmask & SDHCI_INT_ADMA_ERROR)
1368 host->data->error = -EIO;
1370 if (host->data->error)
1371 sdhci_finish_data(host);
1373 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1374 sdhci_transfer_pio(host);
1377 * We currently don't do anything fancy with DMA
1378 * boundaries, but as we can't disable the feature
1379 * we need to at least restart the transfer.
1381 if (intmask & SDHCI_INT_DMA_END)
1382 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1385 if (intmask & SDHCI_INT_DATA_END) {
1388 * Data managed to finish before the
1389 * command completed. Make sure we do
1390 * things in the proper order.
1392 host->data_early = 1;
1394 sdhci_finish_data(host);
1400 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1403 struct sdhci_host* host = dev_id;
1407 spin_lock(&host->lock);
1409 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1411 if (!intmask || intmask == 0xffffffff) {
1416 DBG("*** %s got interrupt: 0x%08x\n",
1417 mmc_hostname(host->mmc), intmask);
1419 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1420 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1421 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1422 tasklet_schedule(&host->card_tasklet);
1425 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1427 if (intmask & SDHCI_INT_CMD_MASK) {
1428 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1430 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1433 if (intmask & SDHCI_INT_DATA_MASK) {
1434 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1436 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1439 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1441 intmask &= ~SDHCI_INT_ERROR;
1443 if (intmask & SDHCI_INT_BUS_POWER) {
1444 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1445 mmc_hostname(host->mmc));
1446 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1449 intmask &= ~SDHCI_INT_BUS_POWER;
1451 if (intmask & SDHCI_INT_CARD_INT)
1454 intmask &= ~SDHCI_INT_CARD_INT;
1457 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1458 mmc_hostname(host->mmc), intmask);
1459 sdhci_dumpregs(host);
1461 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1464 result = IRQ_HANDLED;
1468 spin_unlock(&host->lock);
1471 * We have to delay this as it calls back into the driver.
1474 mmc_signal_sdio_irq(host->mmc);
1479 /*****************************************************************************\
1483 \*****************************************************************************/
1487 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1491 sdhci_disable_card_detection(host);
1493 ret = mmc_suspend_host(host->mmc, state);
1497 free_irq(host->irq, host);
1502 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1504 int sdhci_resume_host(struct sdhci_host *host)
1508 if (host->flags & SDHCI_USE_DMA) {
1509 if (host->ops->enable_dma)
1510 host->ops->enable_dma(host);
1513 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1514 mmc_hostname(host->mmc), host);
1521 ret = mmc_resume_host(host->mmc);
1525 sdhci_enable_card_detection(host);
1530 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1532 #endif /* CONFIG_PM */
1534 /*****************************************************************************\
1536 * Device allocation/registration *
1538 \*****************************************************************************/
1540 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1543 struct mmc_host *mmc;
1544 struct sdhci_host *host;
1546 WARN_ON(dev == NULL);
1548 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1550 return ERR_PTR(-ENOMEM);
1552 host = mmc_priv(mmc);
1558 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1560 int sdhci_add_host(struct sdhci_host *host)
1562 struct mmc_host *mmc;
1566 WARN_ON(host == NULL);
1573 host->quirks = debug_quirks;
1575 sdhci_reset(host, SDHCI_RESET_ALL);
1577 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1578 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1579 >> SDHCI_SPEC_VER_SHIFT;
1580 if (host->version > SDHCI_SPEC_200) {
1581 printk(KERN_ERR "%s: Unknown controller version (%d). "
1582 "You may experience problems.\n", mmc_hostname(mmc),
1586 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1588 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1589 host->flags |= SDHCI_USE_DMA;
1590 else if (!(caps & SDHCI_CAN_DO_DMA))
1591 DBG("Controller doesn't have DMA capability\n");
1593 host->flags |= SDHCI_USE_DMA;
1595 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1596 (host->flags & SDHCI_USE_DMA)) {
1597 DBG("Disabling DMA as it is marked broken\n");
1598 host->flags &= ~SDHCI_USE_DMA;
1601 if (host->flags & SDHCI_USE_DMA) {
1602 if ((host->version >= SDHCI_SPEC_200) &&
1603 (caps & SDHCI_CAN_DO_ADMA2))
1604 host->flags |= SDHCI_USE_ADMA;
1607 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1608 (host->flags & SDHCI_USE_ADMA)) {
1609 DBG("Disabling ADMA as it is marked broken\n");
1610 host->flags &= ~SDHCI_USE_ADMA;
1613 if (host->flags & SDHCI_USE_DMA) {
1614 if (host->ops->enable_dma) {
1615 if (host->ops->enable_dma(host)) {
1616 printk(KERN_WARNING "%s: No suitable DMA "
1617 "available. Falling back to PIO.\n",
1619 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
1624 if (host->flags & SDHCI_USE_ADMA) {
1626 * We need to allocate descriptors for all sg entries
1627 * (128) and potentially one alignment transfer for
1628 * each of those entries.
1630 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1631 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1632 if (!host->adma_desc || !host->align_buffer) {
1633 kfree(host->adma_desc);
1634 kfree(host->align_buffer);
1635 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1636 "buffers. Falling back to standard DMA.\n",
1638 host->flags &= ~SDHCI_USE_ADMA;
1643 * If we use DMA, then it's up to the caller to set the DMA
1644 * mask, but PIO does not need the hw shim so we set a new
1645 * mask here in that case.
1647 if (!(host->flags & SDHCI_USE_DMA)) {
1648 host->dma_mask = DMA_BIT_MASK(64);
1649 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1653 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1654 if (host->max_clk == 0) {
1655 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1656 "frequency.\n", mmc_hostname(mmc));
1659 host->max_clk *= 1000000;
1662 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1663 if (host->timeout_clk == 0) {
1664 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1665 "frequency.\n", mmc_hostname(mmc));
1668 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1669 host->timeout_clk *= 1000;
1672 * Set host parameters.
1674 mmc->ops = &sdhci_ops;
1675 mmc->f_min = host->max_clk / 256;
1676 mmc->f_max = host->max_clk;
1677 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1679 if (caps & SDHCI_CAN_DO_HISPD)
1680 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1683 if (caps & SDHCI_CAN_VDD_330)
1684 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1685 if (caps & SDHCI_CAN_VDD_300)
1686 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1687 if (caps & SDHCI_CAN_VDD_180)
1688 mmc->ocr_avail |= MMC_VDD_165_195;
1690 if (mmc->ocr_avail == 0) {
1691 printk(KERN_ERR "%s: Hardware doesn't report any "
1692 "support voltages.\n", mmc_hostname(mmc));
1696 spin_lock_init(&host->lock);
1699 * Maximum number of segments. Depends on if the hardware
1700 * can do scatter/gather or not.
1702 if (host->flags & SDHCI_USE_ADMA)
1703 mmc->max_hw_segs = 128;
1704 else if (host->flags & SDHCI_USE_DMA)
1705 mmc->max_hw_segs = 1;
1707 mmc->max_hw_segs = 128;
1708 mmc->max_phys_segs = 128;
1711 * Maximum number of sectors in one transfer. Limited by DMA boundary
1714 mmc->max_req_size = 524288;
1717 * Maximum segment size. Could be one segment with the maximum number
1718 * of bytes. When doing hardware scatter/gather, each entry cannot
1719 * be larger than 64 KiB though.
1721 if (host->flags & SDHCI_USE_ADMA)
1722 mmc->max_seg_size = 65536;
1724 mmc->max_seg_size = mmc->max_req_size;
1727 * Maximum block size. This varies from controller to controller and
1728 * is specified in the capabilities register.
1730 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1731 if (mmc->max_blk_size >= 3) {
1732 printk(KERN_WARNING "%s: Invalid maximum block size, "
1733 "assuming 512 bytes\n", mmc_hostname(mmc));
1734 mmc->max_blk_size = 512;
1736 mmc->max_blk_size = 512 << mmc->max_blk_size;
1739 * Maximum block count.
1741 mmc->max_blk_count = 65535;
1746 tasklet_init(&host->card_tasklet,
1747 sdhci_tasklet_card, (unsigned long)host);
1748 tasklet_init(&host->finish_tasklet,
1749 sdhci_tasklet_finish, (unsigned long)host);
1751 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1753 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1754 mmc_hostname(mmc), host);
1760 #ifdef CONFIG_MMC_DEBUG
1761 sdhci_dumpregs(host);
1764 #ifdef SDHCI_USE_LEDS_CLASS
1765 snprintf(host->led_name, sizeof(host->led_name),
1766 "%s::", mmc_hostname(mmc));
1767 host->led.name = host->led_name;
1768 host->led.brightness = LED_OFF;
1769 host->led.default_trigger = mmc_hostname(mmc);
1770 host->led.brightness_set = sdhci_led_control;
1772 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1781 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
1782 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1783 (host->flags & SDHCI_USE_ADMA)?"A":"",
1784 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1786 sdhci_enable_card_detection(host);
1790 #ifdef SDHCI_USE_LEDS_CLASS
1792 sdhci_reset(host, SDHCI_RESET_ALL);
1793 free_irq(host->irq, host);
1796 tasklet_kill(&host->card_tasklet);
1797 tasklet_kill(&host->finish_tasklet);
1802 EXPORT_SYMBOL_GPL(sdhci_add_host);
1804 void sdhci_remove_host(struct sdhci_host *host, int dead)
1806 unsigned long flags;
1809 spin_lock_irqsave(&host->lock, flags);
1811 host->flags |= SDHCI_DEVICE_DEAD;
1814 printk(KERN_ERR "%s: Controller removed during "
1815 " transfer!\n", mmc_hostname(host->mmc));
1817 host->mrq->cmd->error = -ENOMEDIUM;
1818 tasklet_schedule(&host->finish_tasklet);
1821 spin_unlock_irqrestore(&host->lock, flags);
1824 sdhci_disable_card_detection(host);
1826 mmc_remove_host(host->mmc);
1828 #ifdef SDHCI_USE_LEDS_CLASS
1829 led_classdev_unregister(&host->led);
1833 sdhci_reset(host, SDHCI_RESET_ALL);
1835 free_irq(host->irq, host);
1837 del_timer_sync(&host->timer);
1839 tasklet_kill(&host->card_tasklet);
1840 tasklet_kill(&host->finish_tasklet);
1842 kfree(host->adma_desc);
1843 kfree(host->align_buffer);
1845 host->adma_desc = NULL;
1846 host->align_buffer = NULL;
1849 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1851 void sdhci_free_host(struct sdhci_host *host)
1853 mmc_free_host(host->mmc);
1856 EXPORT_SYMBOL_GPL(sdhci_free_host);
1858 /*****************************************************************************\
1860 * Driver init/exit *
1862 \*****************************************************************************/
1864 static int __init sdhci_drv_init(void)
1866 printk(KERN_INFO DRIVER_NAME
1867 ": Secure Digital Host Controller Interface driver\n");
1868 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1873 static void __exit sdhci_drv_exit(void)
1877 module_init(sdhci_drv_init);
1878 module_exit(sdhci_drv_exit);
1880 module_param(debug_quirks, uint, 0444);
1882 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1883 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1884 MODULE_LICENSE("GPL");
1886 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");