drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/scatterlist.h>
  21
  22 #include <linux/leds.h>
  23
  24 #include <linux/mmc/host.h>
  25
  26 #include "sdhci.h"
  27
  28 #define DRIVER_NAME "sdhci"
  29
  30 #define DBG(f, x...) \
  31         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  32
  33 static unsigned int debug_quirks = 0;
  34
  35 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  36 static void sdhci_finish_data(struct sdhci_host *);
  37
  38 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  39 static void sdhci_finish_command(struct sdhci_host *);
  40
  41 static void sdhci_dumpregs(struct sdhci_host *host)
  42 {
  43         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  44
  45         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  46                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  47                 readw(host->ioaddr + SDHCI_HOST_VERSION));
  48         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  49                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  50                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  51         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  52                 readl(host->ioaddr + SDHCI_ARGUMENT),
  53                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  54         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  55                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
  56                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
  57         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  58                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
  59                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  60         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  61                 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
  62                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  63         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  64                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  65                 readl(host->ioaddr + SDHCI_INT_STATUS));
  66         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  67                 readl(host->ioaddr + SDHCI_INT_ENABLE),
  68                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  69         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  70                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
  71                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  72         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
  73                 readl(host->ioaddr + SDHCI_CAPABILITIES),
  74                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
  75
  76         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  77 }
  78
  79 /*****************************************************************************\
  80  *                                                                           *
  81  * Low level functions                                                       *
  82  *                                                                           *
  83 \*****************************************************************************/
  84
  85 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  86 {
  87         unsigned long timeout;
  88
  89         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
  90                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  91                         SDHCI_CARD_PRESENT))
  92                         return;
  93         }
  94
  95         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  96
  97         if (mask & SDHCI_RESET_ALL)
  98                 host->clock = 0;
  99
 100         /* Wait max 100 ms */
 101         timeout = 100;
 102
 103         /* hw clears the bit when it's done */
 104         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 105                 if (timeout == 0) {
 106                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 107                                 mmc_hostname(host->mmc), (int)mask);
 108                         sdhci_dumpregs(host);
 109                         return;
 110                 }
 111                 timeout--;
 112                 mdelay(1);
 113         }
 114 }
 115
 116 static void sdhci_init(struct sdhci_host *host)
 117 {
 118         u32 intmask;
 119
 120         sdhci_reset(host, SDHCI_RESET_ALL);
 121
 122         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 123                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 124                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 125                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 126                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 127                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
 128                 SDHCI_INT_ADMA_ERROR;
 129
 130         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 131         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 132 }
 133
 134 static void sdhci_activate_led(struct sdhci_host *host)
 135 {
 136         u8 ctrl;
 137
 138         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 139         ctrl |= SDHCI_CTRL_LED;
 140         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 141 }
 142
 143 static void sdhci_deactivate_led(struct sdhci_host *host)
 144 {
 145         u8 ctrl;
 146
 147         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 148         ctrl &= ~SDHCI_CTRL_LED;
 149         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 150 }
 151
 152 #ifdef CONFIG_LEDS_CLASS
 153 static void sdhci_led_control(struct led_classdev *led,
 154         enum led_brightness brightness)
 155 {
 156         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 157         unsigned long flags;
 158
 159         spin_lock_irqsave(&host->lock, flags);
 160
 161         if (brightness == LED_OFF)
 162                 sdhci_deactivate_led(host);
 163         else
 164                 sdhci_activate_led(host);
 165
 166         spin_unlock_irqrestore(&host->lock, flags);
 167 }
 168 #endif
 169
 170 /*****************************************************************************\
 171  *                                                                           *
 172  * Core functions                                                            *
 173  *                                                                           *
 174 \*****************************************************************************/
 175
 176 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 177 {
 178         return sg_virt(host->cur_sg);
 179 }
 180
 181 static inline int sdhci_next_sg(struct sdhci_host* host)
 182 {
 183         /*
 184          * Skip to next SG entry.
 185          */
 186         host->cur_sg++;
 187         host->num_sg--;
 188
 189         /*
 190          * Any entries left?
 191          */
 192         if (host->num_sg > 0) {
 193                 host->offset = 0;
 194                 host->remain = host->cur_sg->length;
 195         }
 196
 197         return host->num_sg;
 198 }
 199
 200 static void sdhci_read_block_pio(struct sdhci_host *host)
 201 {
 202         int blksize, chunk_remain;
 203         u32 data;
 204         char *buffer;
 205         int size;
 206
 207         DBG("PIO reading\n");
 208
 209         blksize = host->data->blksz;
 210         chunk_remain = 0;
 211         data = 0;
 212
 213         buffer = sdhci_sg_to_buffer(host) + host->offset;
 214
 215         while (blksize) {
 216                 if (chunk_remain == 0) {
 217                         data = readl(host->ioaddr + SDHCI_BUFFER);
 218                         chunk_remain = min(blksize, 4);
 219                 }
 220
 221                 size = min(host->remain, chunk_remain);
 222
 223                 chunk_remain -= size;
 224                 blksize -= size;
 225                 host->offset += size;
 226                 host->remain -= size;
 227
 228                 while (size) {
 229                         *buffer = data & 0xFF;
 230                         buffer++;
 231                         data >>= 8;
 232                         size--;
 233                 }
 234
 235                 if (host->remain == 0) {
 236                         if (sdhci_next_sg(host) == 0) {
 237                                 BUG_ON(blksize != 0);
 238                                 return;
 239                         }
 240                         buffer = sdhci_sg_to_buffer(host);
 241                 }
 242         }
 243 }
 244
 245 static void sdhci_write_block_pio(struct sdhci_host *host)
 246 {
 247         int blksize, chunk_remain;
 248         u32 data;
 249         char *buffer;
 250         int bytes, size;
 251
 252         DBG("PIO writing\n");
 253
 254         blksize = host->data->blksz;
 255         chunk_remain = 4;
 256         data = 0;
 257
 258         bytes = 0;
 259         buffer = sdhci_sg_to_buffer(host) + host->offset;
 260
 261         while (blksize) {
 262                 size = min(host->remain, chunk_remain);
 263
 264                 chunk_remain -= size;
 265                 blksize -= size;
 266                 host->offset += size;
 267                 host->remain -= size;
 268
 269                 while (size) {
 270                         data >>= 8;
 271                         data |= (u32)*buffer << 24;
 272                         buffer++;
 273                         size--;
 274                 }
 275
 276                 if (chunk_remain == 0) {
 277                         writel(data, host->ioaddr + SDHCI_BUFFER);
 278                         chunk_remain = min(blksize, 4);
 279                 }
 280
 281                 if (host->remain == 0) {
 282                         if (sdhci_next_sg(host) == 0) {
 283                                 BUG_ON(blksize != 0);
 284                                 return;
 285                         }
 286                         buffer = sdhci_sg_to_buffer(host);
 287                 }
 288         }
 289 }
 290
 291 static void sdhci_transfer_pio(struct sdhci_host *host)
 292 {
 293         u32 mask;
 294
 295         BUG_ON(!host->data);
 296
 297         if (host->num_sg == 0)
 298                 return;
 299
 300         if (host->data->flags & MMC_DATA_READ)
 301                 mask = SDHCI_DATA_AVAILABLE;
 302         else
 303                 mask = SDHCI_SPACE_AVAILABLE;
 304
 305         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 306                 if (host->data->flags & MMC_DATA_READ)
 307                         sdhci_read_block_pio(host);
 308                 else
 309                         sdhci_write_block_pio(host);
 310
 311                 if (host->num_sg == 0)
 312                         break;
 313         }
 314
 315         DBG("PIO transfer complete.\n");
 316 }
 317
 318 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 319 {
 320         local_irq_save(*flags);
 321         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 322 }
 323
 324 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 325 {
 326         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 327         local_irq_restore(*flags);
 328 }
 329
 330 static void sdhci_adma_table_pre(struct sdhci_host *host,
 331         struct mmc_data *data)
 332 {
 333         int direction;
 334
 335         u8 *desc;
 336         u8 *align;
 337         dma_addr_t addr;
 338         dma_addr_t align_addr;
 339         int len, offset;
 340
 341         struct scatterlist *sg;
 342         int i;
 343         char *buffer;
 344         unsigned long flags;
 345
 346         /*
 347          * The spec does not specify endianness of descriptor table.
 348          * We currently guess that it is LE.
 349          */
 350
 351         if (data->flags & MMC_DATA_READ)
 352                 direction = DMA_FROM_DEVICE;
 353         else
 354                 direction = DMA_TO_DEVICE;
 355
 356         /*
 357          * The ADMA descriptor table is mapped further down as we
 358          * need to fill it with data first.
 359          */
 360
 361         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 362                 host->align_buffer, 128 * 4, direction);
 363         BUG_ON(host->align_addr & 0x3);
 364
 365         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 366                 data->sg, data->sg_len, direction);
 367
 368         desc = host->adma_desc;
 369         align = host->align_buffer;
 370
 371         align_addr = host->align_addr;
 372
 373         for_each_sg(data->sg, sg, host->sg_count, i) {
 374                 addr = sg_dma_address(sg);
 375                 len = sg_dma_len(sg);
 376
 377                 /*
 378                  * The SDHCI specification states that ADMA
 379                  * addresses must be 32-bit aligned. If they
 380                  * aren't, then we use a bounce buffer for
 381                  * the (up to three) bytes that screw up the
 382                  * alignment.
 383                  */
 384                 offset = (4 - (addr & 0x3)) & 0x3;
 385                 if (offset) {
 386                         if (data->flags & MMC_DATA_WRITE) {
 387                                 buffer = sdhci_kmap_atomic(sg, &flags);
 388                                 memcpy(align, buffer, offset);
 389                                 sdhci_kunmap_atomic(buffer, &flags);
 390                         }
 391
 392                         desc[7] = (align_addr >> 24) & 0xff;
 393                         desc[6] = (align_addr >> 16) & 0xff;
 394                         desc[5] = (align_addr >> 8) & 0xff;
 395                         desc[4] = (align_addr >> 0) & 0xff;
 396
 397                         BUG_ON(offset > 65536);
 398
 399                         desc[3] = (offset >> 8) & 0xff;
 400                         desc[2] = (offset >> 0) & 0xff;
 401
 402                         desc[1] = 0x00;
 403                         desc[0] = 0x21; /* tran, valid */
 404
 405                         align += 4;
 406                         align_addr += 4;
 407
 408                         desc += 8;
 409
 410                         addr += offset;
 411                         len -= offset;
 412                 }
 413
 414                 desc[7] = (addr >> 24) & 0xff;
 415                 desc[6] = (addr >> 16) & 0xff;
 416                 desc[5] = (addr >> 8) & 0xff;
 417                 desc[4] = (addr >> 0) & 0xff;
 418
 419                 BUG_ON(len > 65536);
 420
 421                 desc[3] = (len >> 8) & 0xff;
 422                 desc[2] = (len >> 0) & 0xff;
 423
 424                 desc[1] = 0x00;
 425                 desc[0] = 0x21; /* tran, valid */
 426
 427                 desc += 8;
 428
 429                 /*
 430                  * If this triggers then we have a calculation bug
 431                  * somewhere. :/
 432                  */
 433                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 434         }
 435
 436         /*
 437          * Add a terminating entry.
 438          */
 439         desc[7] = 0;
 440         desc[6] = 0;
 441         desc[5] = 0;
 442         desc[4] = 0;
 443
 444         desc[3] = 0;
 445         desc[2] = 0;
 446
 447         desc[1] = 0x00;
 448         desc[0] = 0x03; /* nop, end, valid */
 449
 450         /*
 451          * Resync align buffer as we might have changed it.
 452          */
 453         if (data->flags & MMC_DATA_WRITE) {
 454                 dma_sync_single_for_device(mmc_dev(host->mmc),
 455                         host->align_addr, 128 * 4, direction);
 456         }
 457
 458         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 459                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 460         BUG_ON(host->adma_addr & 0x3);
 461 }
 462
 463 static void sdhci_adma_table_post(struct sdhci_host *host,
 464         struct mmc_data *data)
 465 {
 466         int direction;
 467
 468         struct scatterlist *sg;
 469         int i, size;
 470         u8 *align;
 471         char *buffer;
 472         unsigned long flags;
 473
 474         if (data->flags & MMC_DATA_READ)
 475                 direction = DMA_FROM_DEVICE;
 476         else
 477                 direction = DMA_TO_DEVICE;
 478
 479         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 480                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 481
 482         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 483                 128 * 4, direction);
 484
 485         if (data->flags & MMC_DATA_READ) {
 486                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 487                         data->sg_len, direction);
 488
 489                 align = host->align_buffer;
 490
 491                 for_each_sg(data->sg, sg, host->sg_count, i) {
 492                         if (sg_dma_address(sg) & 0x3) {
 493                                 size = 4 - (sg_dma_address(sg) & 0x3);
 494
 495                                 buffer = sdhci_kmap_atomic(sg, &flags);
 496                                 memcpy(buffer, align, size);
 497                                 sdhci_kunmap_atomic(buffer, &flags);
 498
 499                                 align += 4;
 500                         }
 501                 }
 502         }
 503
 504         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 505                 data->sg_len, direction);
 506 }
 507
 508 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
 509 {
 510         u8 count;
 511         unsigned target_timeout, current_timeout;
 512
 513         /*
 514          * If the host controller provides us with an incorrect timeout
 515          * value, just skip the check and use 0xE.  The hardware may take
 516          * longer to time out, but that's much better than having a too-short
 517          * timeout value.
 518          */
 519         if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
 520                 return 0xE;
 521
 522         /* timeout in us */
 523         target_timeout = data->timeout_ns / 1000 +
 524                 data->timeout_clks / host->clock;
 525
 526         /*
 527          * Figure out needed cycles.
 528          * We do this in steps in order to fit inside a 32 bit int.
 529          * The first step is the minimum timeout, which will have a
 530          * minimum resolution of 6 bits:
 531          * (1) 2^13*1000 > 2^22,
 532          * (2) host->timeout_clk < 2^16
 533          *     =>
 534          *     (1) / (2) > 2^6
 535          */
 536         count = 0;
 537         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 538         while (current_timeout < target_timeout) {
 539                 count++;
 540                 current_timeout <<= 1;
 541                 if (count >= 0xF)
 542                         break;
 543         }
 544
 545         if (count >= 0xF) {
 546                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 547                         mmc_hostname(host->mmc));
 548                 count = 0xE;
 549         }
 550
 551         return count;
 552 }
 553
 554 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 555 {
 556         u8 count;
 557         u8 ctrl;
 558
 559         WARN_ON(host->data);
 560
 561         if (data == NULL)
 562                 return;
 563
 564         /* Sanity checks */
 565         BUG_ON(data->blksz * data->blocks > 524288);
 566         BUG_ON(data->blksz > host->mmc->max_blk_size);
 567         BUG_ON(data->blocks > 65535);
 568
 569         host->data = data;
 570         host->data_early = 0;
 571
 572         count = sdhci_calc_timeout(host, data);
 573         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 574
 575         if (host->flags & SDHCI_USE_DMA)
 576                 host->flags |= SDHCI_REQ_USE_DMA;
 577
 578         /*
 579          * FIXME: This doesn't account for merging when mapping the
 580          * scatterlist.
 581          */
 582         if (host->flags & SDHCI_REQ_USE_DMA) {
 583                 int broken, i;
 584                 struct scatterlist *sg;
 585
 586                 broken = 0;
 587                 if (host->flags & SDHCI_USE_ADMA) {
 588                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 589                                 broken = 1;
 590                 } else {
 591                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 592                                 broken = 1;
 593                 }
 594
 595                 if (unlikely(broken)) {
 596                         for_each_sg(data->sg, sg, data->sg_len, i) {
 597                                 if (sg->length & 0x3) {
 598                                         DBG("Reverting to PIO because of "
 599                                                 "transfer size (%d)\n",
 600                                                 sg->length);
 601                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 602                                         break;
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         /*
 609          * The assumption here being that alignment is the same after
 610          * translation to device address space.
 611          */
 612         if (host->flags & SDHCI_REQ_USE_DMA) {
 613                 int broken, i;
 614                 struct scatterlist *sg;
 615
 616                 broken = 0;
 617                 if (host->flags & SDHCI_USE_ADMA) {
 618                         /*
 619                          * As we use 3 byte chunks to work around
 620                          * alignment problems, we need to check this
 621                          * quirk.
 622                          */
 623                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 624                                 broken = 1;
 625                 } else {
 626                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 627                                 broken = 1;
 628                 }
 629
 630                 if (unlikely(broken)) {
 631                         for_each_sg(data->sg, sg, data->sg_len, i) {
 632                                 if (sg->offset & 0x3) {
 633                                         DBG("Reverting to PIO because of "
 634                                                 "bad alignment\n");
 635                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 636                                         break;
 637                                 }
 638                         }
 639                 }
 640         }
 641
 642         /*
 643          * Always adjust the DMA selection as some controllers
 644          * (e.g. JMicron) can't do PIO properly when the selection
 645          * is ADMA.
 646          */
 647         if (host->version >= SDHCI_SPEC_200) {
 648                 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 649                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 650                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 651                         (host->flags & SDHCI_USE_ADMA))
 652                         ctrl |= SDHCI_CTRL_ADMA32;
 653                 else
 654                         ctrl |= SDHCI_CTRL_SDMA;
 655                 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 656         }
 657
 658         if (host->flags & SDHCI_REQ_USE_DMA) {
 659                 if (host->flags & SDHCI_USE_ADMA) {
 660                         sdhci_adma_table_pre(host, data);
 661                         writel(host->adma_addr,
 662                                 host->ioaddr + SDHCI_ADMA_ADDRESS);
 663                 } else {
 664                         int count;
 665
 666                         count = dma_map_sg(mmc_dev(host->mmc),
 667                                         data->sg, data->sg_len,
 668                                         (data->flags & MMC_DATA_READ) ?
 669                                                 DMA_FROM_DEVICE :
 670                                                 DMA_TO_DEVICE);
 671                         WARN_ON(count != 1);
 672
 673                         writel(sg_dma_address(data->sg),
 674                                 host->ioaddr + SDHCI_DMA_ADDRESS);
 675                 }
 676         } else {
 677                 host->cur_sg = data->sg;
 678                 host->num_sg = data->sg_len;
 679
 680                 host->offset = 0;
 681                 host->remain = host->cur_sg->length;
 682         }
 683
 684         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 685         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 686                 host->ioaddr + SDHCI_BLOCK_SIZE);
 687         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 688 }
 689
 690 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 691         struct mmc_data *data)
 692 {
 693         u16 mode;
 694
 695         if (data == NULL)
 696                 return;
 697
 698         WARN_ON(!host->data);
 699
 700         mode = SDHCI_TRNS_BLK_CNT_EN;
 701         if (data->blocks > 1)
 702                 mode |= SDHCI_TRNS_MULTI;
 703         if (data->flags & MMC_DATA_READ)
 704                 mode |= SDHCI_TRNS_READ;
 705         if (host->flags & SDHCI_REQ_USE_DMA)
 706                 mode |= SDHCI_TRNS_DMA;
 707
 708         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 709 }
 710
 711 static void sdhci_finish_data(struct sdhci_host *host)
 712 {
 713         struct mmc_data *data;
 714
 715         BUG_ON(!host->data);
 716
 717         data = host->data;
 718         host->data = NULL;
 719
 720         if (host->flags & SDHCI_REQ_USE_DMA) {
 721                 if (host->flags & SDHCI_USE_ADMA)
 722                         sdhci_adma_table_post(host, data);
 723                 else {
 724                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 725                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 726                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 727                 }
 728         }
 729
 730         /*
 731          * The specification states that the block count register must
 732          * be updated, but it does not specify at what point in the
 733          * data flow. That makes the register entirely useless to read
 734          * back so we have to assume that nothing made it to the card
 735          * in the event of an error.
 736          */
 737         if (data->error)
 738                 data->bytes_xfered = 0;
 739         else
 740                 data->bytes_xfered = data->blksz * data->blocks;
 741
 742         if (data->stop) {
 743                 /*
 744                  * The controller needs a reset of internal state machines
 745                  * upon error conditions.
 746                  */
 747                 if (data->error) {
 748                         sdhci_reset(host, SDHCI_RESET_CMD);
 749                         sdhci_reset(host, SDHCI_RESET_DATA);
 750                 }
 751
 752                 sdhci_send_command(host, data->stop);
 753         } else
 754                 tasklet_schedule(&host->finish_tasklet);
 755 }
 756
 757 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 758 {
 759         int flags;
 760         u32 mask;
 761         unsigned long timeout;
 762
 763         WARN_ON(host->cmd);
 764
 765         /* Wait max 10 ms */
 766         timeout = 10;
 767
 768         mask = SDHCI_CMD_INHIBIT;
 769         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 770                 mask |= SDHCI_DATA_INHIBIT;
 771
 772         /* We shouldn't wait for data inihibit for stop commands, even
 773            though they might use busy signaling */
 774         if (host->mrq->data && (cmd == host->mrq->data->stop))
 775                 mask &= ~SDHCI_DATA_INHIBIT;
 776
 777         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 778                 if (timeout == 0) {
 779                         printk(KERN_ERR "%s: Controller never released "
 780                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 781                         sdhci_dumpregs(host);
 782                         cmd->error = -EIO;
 783                         tasklet_schedule(&host->finish_tasklet);
 784                         return;
 785                 }
 786                 timeout--;
 787                 mdelay(1);
 788         }
 789
 790         mod_timer(&host->timer, jiffies + 10 * HZ);
 791
 792         host->cmd = cmd;
 793
 794         sdhci_prepare_data(host, cmd->data);
 795
 796         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 797
 798         sdhci_set_transfer_mode(host, cmd->data);
 799
 800         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 801                 printk(KERN_ERR "%s: Unsupported response type!\n",
 802                         mmc_hostname(host->mmc));
 803                 cmd->error = -EINVAL;
 804                 tasklet_schedule(&host->finish_tasklet);
 805                 return;
 806         }
 807
 808         if (!(cmd->flags & MMC_RSP_PRESENT))
 809                 flags = SDHCI_CMD_RESP_NONE;
 810         else if (cmd->flags & MMC_RSP_136)
 811                 flags = SDHCI_CMD_RESP_LONG;
 812         else if (cmd->flags & MMC_RSP_BUSY)
 813                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 814         else
 815                 flags = SDHCI_CMD_RESP_SHORT;
 816
 817         if (cmd->flags & MMC_RSP_CRC)
 818                 flags |= SDHCI_CMD_CRC;
 819         if (cmd->flags & MMC_RSP_OPCODE)
 820                 flags |= SDHCI_CMD_INDEX;
 821         if (cmd->data)
 822                 flags |= SDHCI_CMD_DATA;
 823
 824         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 825                 host->ioaddr + SDHCI_COMMAND);
 826 }
 827
 828 static void sdhci_finish_command(struct sdhci_host *host)
 829 {
 830         int i;
 831
 832         BUG_ON(host->cmd == NULL);
 833
 834         if (host->cmd->flags & MMC_RSP_PRESENT) {
 835                 if (host->cmd->flags & MMC_RSP_136) {
 836                         /* CRC is stripped so we need to do some shifting. */
 837                         for (i = 0;i < 4;i++) {
 838                                 host->cmd->resp[i] = readl(host->ioaddr +
 839                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 840                                 if (i != 3)
 841                                         host->cmd->resp[i] |=
 842                                                 readb(host->ioaddr +
 843                                                 SDHCI_RESPONSE + (3-i)*4-1);
 844                         }
 845                 } else {
 846                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 847                 }
 848         }
 849
 850         host->cmd->error = 0;
 851
 852         if (host->data && host->data_early)
 853                 sdhci_finish_data(host);
 854
 855         if (!host->cmd->data)
 856                 tasklet_schedule(&host->finish_tasklet);
 857
 858         host->cmd = NULL;
 859 }
 860
 861 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 862 {
 863         int div;
 864         u16 clk;
 865         unsigned long timeout;
 866
 867         if (clock == host->clock)
 868                 return;
 869
 870         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 871
 872         if (clock == 0)
 873                 goto out;
 874
 875         for (div = 1;div < 256;div *= 2) {
 876                 if ((host->max_clk / div) <= clock)
 877                         break;
 878         }
 879         div >>= 1;
 880
 881         clk = div << SDHCI_DIVIDER_SHIFT;
 882         clk |= SDHCI_CLOCK_INT_EN;
 883         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 884
 885         /* Wait max 10 ms */
 886         timeout = 10;
 887         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 888                 & SDHCI_CLOCK_INT_STABLE)) {
 889                 if (timeout == 0) {
 890                         printk(KERN_ERR "%s: Internal clock never "
 891                                 "stabilised.\n", mmc_hostname(host->mmc));
 892                         sdhci_dumpregs(host);
 893                         return;
 894                 }
 895                 timeout--;
 896                 mdelay(1);
 897         }
 898
 899         clk |= SDHCI_CLOCK_CARD_EN;
 900         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 901
 902 out:
 903         host->clock = clock;
 904 }
 905
 906 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 907 {
 908         u8 pwr;
 909
 910         if (host->power == power)
 911                 return;
 912
 913         if (power == (unsigned short)-1) {
 914                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 915                 goto out;
 916         }
 917
 918         /*
 919          * Spec says that we should clear the power reg before setting
 920          * a new value. Some controllers don't seem to like this though.
 921          */
 922         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 923                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 924
 925         pwr = SDHCI_POWER_ON;
 926
 927         switch (1 << power) {
 928         case MMC_VDD_165_195:
 929                 pwr |= SDHCI_POWER_180;
 930                 break;
 931         case MMC_VDD_29_30:
 932         case MMC_VDD_30_31:
 933                 pwr |= SDHCI_POWER_300;
 934                 break;
 935         case MMC_VDD_32_33:
 936         case MMC_VDD_33_34:
 937                 pwr |= SDHCI_POWER_330;
 938                 break;
 939         default:
 940                 BUG();
 941         }
 942
 943         /*
 944          * At least the CaFe chip gets confused if we set the voltage
 945          * and set turn on power at the same time, so set the voltage first.
 946          */
 947         if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
 948                 writeb(pwr & ~SDHCI_POWER_ON,
 949                                 host->ioaddr + SDHCI_POWER_CONTROL);
 950
 951         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 952
 953 out:
 954         host->power = power;
 955 }
 956
 957 /*****************************************************************************\
 958  *                                                                           *
 959  * MMC callbacks                                                             *
 960  *                                                                           *
 961 \*****************************************************************************/
 962
 963 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 964 {
 965         struct sdhci_host *host;
 966         unsigned long flags;
 967
 968         host = mmc_priv(mmc);
 969
 970         spin_lock_irqsave(&host->lock, flags);
 971
 972         WARN_ON(host->mrq != NULL);
 973
 974 #ifndef CONFIG_LEDS_CLASS
 975         sdhci_activate_led(host);
 976 #endif
 977
 978         host->mrq = mrq;
 979
 980         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
 981                 || (host->flags & SDHCI_DEVICE_DEAD)) {
 982                 host->mrq->cmd->error = -ENOMEDIUM;
 983                 tasklet_schedule(&host->finish_tasklet);
 984         } else
 985                 sdhci_send_command(host, mrq->cmd);
 986
 987         mmiowb();
 988         spin_unlock_irqrestore(&host->lock, flags);
 989 }
 990
 991 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 992 {
 993         struct sdhci_host *host;
 994         unsigned long flags;
 995         u8 ctrl;
 996
 997         host = mmc_priv(mmc);
 998
 999         spin_lock_irqsave(&host->lock, flags);
1000
1001         if (host->flags & SDHCI_DEVICE_DEAD)
1002                 goto out;
1003
1004         /*
1005          * Reset the chip on each power off.
1006          * Should clear out any weird states.
1007          */
1008         if (ios->power_mode == MMC_POWER_OFF) {
1009                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1010                 sdhci_init(host);
1011         }
1012
1013         sdhci_set_clock(host, ios->clock);
1014
1015         if (ios->power_mode == MMC_POWER_OFF)
1016                 sdhci_set_power(host, -1);
1017         else
1018                 sdhci_set_power(host, ios->vdd);
1019
1020         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
1021
1022         if (ios->bus_width == MMC_BUS_WIDTH_4)
1023                 ctrl |= SDHCI_CTRL_4BITBUS;
1024         else
1025                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1026
1027         if (ios->timing == MMC_TIMING_SD_HS)
1028                 ctrl |= SDHCI_CTRL_HISPD;
1029         else
1030                 ctrl &= ~SDHCI_CTRL_HISPD;
1031
1032         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
1033
1034         /*
1035          * Some (ENE) controllers go apeshit on some ios operation,
1036          * signalling timeout and CRC errors even on CMD0. Resetting
1037          * it on each ios seems to solve the problem.
1038          */
1039         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1040                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1041
1042 out:
1043         mmiowb();
1044         spin_unlock_irqrestore(&host->lock, flags);
1045 }
1046
1047 static int sdhci_get_ro(struct mmc_host *mmc)
1048 {
1049         struct sdhci_host *host;
1050         unsigned long flags;
1051         int present;
1052
1053         host = mmc_priv(mmc);
1054
1055         spin_lock_irqsave(&host->lock, flags);
1056
1057         if (host->flags & SDHCI_DEVICE_DEAD)
1058                 present = 0;
1059         else
1060                 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
1061
1062         spin_unlock_irqrestore(&host->lock, flags);
1063
1064         return !(present & SDHCI_WRITE_PROTECT);
1065 }
1066
1067 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1068 {
1069         struct sdhci_host *host;
1070         unsigned long flags;
1071         u32 ier;
1072
1073         host = mmc_priv(mmc);
1074
1075         spin_lock_irqsave(&host->lock, flags);
1076
1077         if (host->flags & SDHCI_DEVICE_DEAD)
1078                 goto out;
1079
1080         ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
1081
1082         ier &= ~SDHCI_INT_CARD_INT;
1083         if (enable)
1084                 ier |= SDHCI_INT_CARD_INT;
1085
1086         writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
1087         writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1088
1089 out:
1090         mmiowb();
1091
1092         spin_unlock_irqrestore(&host->lock, flags);
1093 }
1094
1095 static const struct mmc_host_ops sdhci_ops = {
1096         .request        = sdhci_request,
1097         .set_ios        = sdhci_set_ios,
1098         .get_ro         = sdhci_get_ro,
1099         .enable_sdio_irq = sdhci_enable_sdio_irq,
1100 };
1101
1102 /*****************************************************************************\
1103  *                                                                           *
1104  * Tasklets                                                                  *
1105  *                                                                           *
1106 \*****************************************************************************/
1107
1108 static void sdhci_tasklet_card(unsigned long param)
1109 {
1110         struct sdhci_host *host;
1111         unsigned long flags;
1112
1113         host = (struct sdhci_host*)param;
1114
1115         spin_lock_irqsave(&host->lock, flags);
1116
1117         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1118                 if (host->mrq) {
1119                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1120                                 mmc_hostname(host->mmc));
1121                         printk(KERN_ERR "%s: Resetting controller.\n",
1122                                 mmc_hostname(host->mmc));
1123
1124                         sdhci_reset(host, SDHCI_RESET_CMD);
1125                         sdhci_reset(host, SDHCI_RESET_DATA);
1126
1127                         host->mrq->cmd->error = -ENOMEDIUM;
1128                         tasklet_schedule(&host->finish_tasklet);
1129                 }
1130         }
1131
1132         spin_unlock_irqrestore(&host->lock, flags);
1133
1134         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1135 }
1136
1137 static void sdhci_tasklet_finish(unsigned long param)
1138 {
1139         struct sdhci_host *host;
1140         unsigned long flags;
1141         struct mmc_request *mrq;
1142
1143         host = (struct sdhci_host*)param;
1144
1145         spin_lock_irqsave(&host->lock, flags);
1146
1147         del_timer(&host->timer);
1148
1149         mrq = host->mrq;
1150
1151         /*
1152          * The controller needs a reset of internal state machines
1153          * upon error conditions.
1154          */
1155         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1156                 (mrq->cmd->error ||
1157                  (mrq->data && (mrq->data->error ||
1158                   (mrq->data->stop && mrq->data->stop->error))) ||
1159                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1160
1161                 /* Some controllers need this kick or reset won't work here */
1162                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1163                         unsigned int clock;
1164
1165                         /* This is to force an update */
1166                         clock = host->clock;
1167                         host->clock = 0;
1168                         sdhci_set_clock(host, clock);
1169                 }
1170
1171                 /* Spec says we should do both at the same time, but Ricoh
1172                    controllers do not like that. */
1173                 sdhci_reset(host, SDHCI_RESET_CMD);
1174                 sdhci_reset(host, SDHCI_RESET_DATA);
1175         }
1176
1177         host->mrq = NULL;
1178         host->cmd = NULL;
1179         host->data = NULL;
1180
1181 #ifndef CONFIG_LEDS_CLASS
1182         sdhci_deactivate_led(host);
1183 #endif
1184
1185         mmiowb();
1186         spin_unlock_irqrestore(&host->lock, flags);
1187
1188         mmc_request_done(host->mmc, mrq);
1189 }
1190
1191 static void sdhci_timeout_timer(unsigned long data)
1192 {
1193         struct sdhci_host *host;
1194         unsigned long flags;
1195
1196         host = (struct sdhci_host*)data;
1197
1198         spin_lock_irqsave(&host->lock, flags);
1199
1200         if (host->mrq) {
1201                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1202                         "interrupt.\n", mmc_hostname(host->mmc));
1203                 sdhci_dumpregs(host);
1204
1205                 if (host->data) {
1206                         host->data->error = -ETIMEDOUT;
1207                         sdhci_finish_data(host);
1208                 } else {
1209                         if (host->cmd)
1210                                 host->cmd->error = -ETIMEDOUT;
1211                         else
1212                                 host->mrq->cmd->error = -ETIMEDOUT;
1213
1214                         tasklet_schedule(&host->finish_tasklet);
1215                 }
1216         }
1217
1218         mmiowb();
1219         spin_unlock_irqrestore(&host->lock, flags);
1220 }
1221
1222 /*****************************************************************************\
1223  *                                                                           *
1224  * Interrupt handling                                                        *
1225  *                                                                           *
1226 \*****************************************************************************/
1227
1228 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1229 {
1230         BUG_ON(intmask == 0);
1231
1232         if (!host->cmd) {
1233                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1234                         "though no command operation was in progress.\n",
1235                         mmc_hostname(host->mmc), (unsigned)intmask);
1236                 sdhci_dumpregs(host);
1237                 return;
1238         }
1239
1240         if (intmask & SDHCI_INT_TIMEOUT)
1241                 host->cmd->error = -ETIMEDOUT;
1242         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1243                         SDHCI_INT_INDEX))
1244                 host->cmd->error = -EILSEQ;
1245
1246         if (host->cmd->error)
1247                 tasklet_schedule(&host->finish_tasklet);
1248         else if (intmask & SDHCI_INT_RESPONSE)
1249                 sdhci_finish_command(host);
1250 }
1251
1252 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1253 {
1254         BUG_ON(intmask == 0);
1255
1256         if (!host->data) {
1257                 /*
1258                  * A data end interrupt is sent together with the response
1259                  * for the stop command.
1260                  */
1261                 if (intmask & SDHCI_INT_DATA_END)
1262                         return;
1263
1264                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1265                         "though no data operation was in progress.\n",
1266                         mmc_hostname(host->mmc), (unsigned)intmask);
1267                 sdhci_dumpregs(host);
1268
1269                 return;
1270         }
1271
1272         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1273                 host->data->error = -ETIMEDOUT;
1274         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1275                 host->data->error = -EILSEQ;
1276         else if (intmask & SDHCI_INT_ADMA_ERROR)
1277                 host->data->error = -EIO;
1278
1279         if (host->data->error)
1280                 sdhci_finish_data(host);
1281         else {
1282                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1283                         sdhci_transfer_pio(host);
1284
1285                 /*
1286                  * We currently don't do anything fancy with DMA
1287                  * boundaries, but as we can't disable the feature
1288                  * we need to at least restart the transfer.
1289                  */
1290                 if (intmask & SDHCI_INT_DMA_END)
1291                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1292                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1293
1294                 if (intmask & SDHCI_INT_DATA_END) {
1295                         if (host->cmd) {
1296                                 /*
1297                                  * Data managed to finish before the
1298                                  * command completed. Make sure we do
1299                                  * things in the proper order.
1300                                  */
1301                                 host->data_early = 1;
1302                         } else {
1303                                 sdhci_finish_data(host);
1304                         }
1305                 }
1306         }
1307 }
1308
1309 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1310 {
1311         irqreturn_t result;
1312         struct sdhci_host* host = dev_id;
1313         u32 intmask;
1314         int cardint = 0;
1315
1316         spin_lock(&host->lock);
1317
1318         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1319
1320         if (!intmask || intmask == 0xffffffff) {
1321                 result = IRQ_NONE;
1322                 goto out;
1323         }
1324
1325         DBG("*** %s got interrupt: 0x%08x\n",
1326                 mmc_hostname(host->mmc), intmask);
1327
1328         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1329                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1330                         host->ioaddr + SDHCI_INT_STATUS);
1331                 tasklet_schedule(&host->card_tasklet);
1332         }
1333
1334         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1335
1336         if (intmask & SDHCI_INT_CMD_MASK) {
1337                 writel(intmask & SDHCI_INT_CMD_MASK,
1338                         host->ioaddr + SDHCI_INT_STATUS);
1339                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1340         }
1341
1342         if (intmask & SDHCI_INT_DATA_MASK) {
1343                 writel(intmask & SDHCI_INT_DATA_MASK,
1344                         host->ioaddr + SDHCI_INT_STATUS);
1345                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1346         }
1347
1348         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1349
1350         intmask &= ~SDHCI_INT_ERROR;
1351
1352         if (intmask & SDHCI_INT_BUS_POWER) {
1353                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1354                         mmc_hostname(host->mmc));
1355                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1356         }
1357
1358         intmask &= ~SDHCI_INT_BUS_POWER;
1359
1360         if (intmask & SDHCI_INT_CARD_INT)
1361                 cardint = 1;
1362
1363         intmask &= ~SDHCI_INT_CARD_INT;
1364
1365         if (intmask) {
1366                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1367                         mmc_hostname(host->mmc), intmask);
1368                 sdhci_dumpregs(host);
1369
1370                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1371         }
1372
1373         result = IRQ_HANDLED;
1374
1375         mmiowb();
1376 out:
1377         spin_unlock(&host->lock);
1378
1379         /*
1380          * We have to delay this as it calls back into the driver.
1381          */
1382         if (cardint)
1383                 mmc_signal_sdio_irq(host->mmc);
1384
1385         return result;
1386 }
1387
1388 /*****************************************************************************\
1389  *                                                                           *
1390  * Suspend/resume                                                            *
1391  *                                                                           *
1392 \*****************************************************************************/
1393
1394 #ifdef CONFIG_PM
1395
1396 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1397 {
1398         int ret;
1399
1400         ret = mmc_suspend_host(host->mmc, state);
1401         if (ret)
1402                 return ret;
1403
1404         free_irq(host->irq, host);
1405
1406         return 0;
1407 }
1408
1409 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1410
1411 int sdhci_resume_host(struct sdhci_host *host)
1412 {
1413         int ret;
1414
1415         if (host->flags & SDHCI_USE_DMA) {
1416                 if (host->ops->enable_dma)
1417                         host->ops->enable_dma(host);
1418         }
1419
1420         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1421                           mmc_hostname(host->mmc), host);
1422         if (ret)
1423                 return ret;
1424
1425         sdhci_init(host);
1426         mmiowb();
1427
1428         ret = mmc_resume_host(host->mmc);
1429         if (ret)
1430                 return ret;
1431
1432         return 0;
1433 }
1434
1435 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1436
1437 #endif /* CONFIG_PM */
1438
1439 /*****************************************************************************\
1440  *                                                                           *
1441  * Device allocation/registration                                            *
1442  *                                                                           *
1443 \*****************************************************************************/
1444
1445 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1446         size_t priv_size)
1447 {
1448         struct mmc_host *mmc;
1449         struct sdhci_host *host;
1450
1451         WARN_ON(dev == NULL);
1452
1453         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1454         if (!mmc)
1455                 return ERR_PTR(-ENOMEM);
1456
1457         host = mmc_priv(mmc);
1458         host->mmc = mmc;
1459
1460         return host;
1461 }
1462
1463 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1464
1465 int sdhci_add_host(struct sdhci_host *host)
1466 {
1467         struct mmc_host *mmc;
1468         unsigned int caps;
1469         int ret;
1470
1471         WARN_ON(host == NULL);
1472         if (host == NULL)
1473                 return -EINVAL;
1474
1475         mmc = host->mmc;
1476
1477         if (debug_quirks)
1478                 host->quirks = debug_quirks;
1479
1480         sdhci_reset(host, SDHCI_RESET_ALL);
1481
1482         host->version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1483         host->version = (host->version & SDHCI_SPEC_VER_MASK)
1484                                 >> SDHCI_SPEC_VER_SHIFT;
1485         if (host->version > SDHCI_SPEC_200) {
1486                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1487                         "You may experience problems.\n", mmc_hostname(mmc),
1488                         host->version);
1489         }
1490
1491         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1492
1493         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1494                 host->flags |= SDHCI_USE_DMA;
1495         else if (!(caps & SDHCI_CAN_DO_DMA))
1496                 DBG("Controller doesn't have DMA capability\n");
1497         else
1498                 host->flags |= SDHCI_USE_DMA;
1499
1500         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1501                 (host->flags & SDHCI_USE_DMA)) {
1502                 DBG("Disabling DMA as it is marked broken\n");
1503                 host->flags &= ~SDHCI_USE_DMA;
1504         }
1505
1506         if (host->flags & SDHCI_USE_DMA) {
1507                 if ((host->version >= SDHCI_SPEC_200) &&
1508                                 (caps & SDHCI_CAN_DO_ADMA2))
1509                         host->flags |= SDHCI_USE_ADMA;
1510         }
1511
1512         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1513                 (host->flags & SDHCI_USE_ADMA)) {
1514                 DBG("Disabling ADMA as it is marked broken\n");
1515                 host->flags &= ~SDHCI_USE_ADMA;
1516         }
1517
1518         if (host->flags & SDHCI_USE_DMA) {
1519                 if (host->ops->enable_dma) {
1520                         if (host->ops->enable_dma(host)) {
1521                                 printk(KERN_WARNING "%s: No suitable DMA "
1522                                         "available. Falling back to PIO.\n",
1523                                         mmc_hostname(mmc));
1524                                 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
1525                         }
1526                 }
1527         }
1528
1529         if (host->flags & SDHCI_USE_ADMA) {
1530                 /*
1531                  * We need to allocate descriptors for all sg entries
1532                  * (128) and potentially one alignment transfer for
1533                  * each of those entries.
1534                  */
1535                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1536                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1537                 if (!host->adma_desc || !host->align_buffer) {
1538                         kfree(host->adma_desc);
1539                         kfree(host->align_buffer);
1540                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
1541                                 "buffers. Falling back to standard DMA.\n",
1542                                 mmc_hostname(mmc));
1543                         host->flags &= ~SDHCI_USE_ADMA;
1544                 }
1545         }
1546
1547         /* XXX: Hack to get MMC layer to avoid highmem */
1548         if (!(host->flags & SDHCI_USE_DMA))
1549                 mmc_dev(host->mmc)->dma_mask = 0;
1550
1551         host->max_clk =
1552                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1553         if (host->max_clk == 0) {
1554                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1555                         "frequency.\n", mmc_hostname(mmc));
1556                 return -ENODEV;
1557         }
1558         host->max_clk *= 1000000;
1559
1560         host->timeout_clk =
1561                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1562         if (host->timeout_clk == 0) {
1563                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1564                         "frequency.\n", mmc_hostname(mmc));
1565                 return -ENODEV;
1566         }
1567         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1568                 host->timeout_clk *= 1000;
1569
1570         /*
1571          * Set host parameters.
1572          */
1573         mmc->ops = &sdhci_ops;
1574         mmc->f_min = host->max_clk / 256;
1575         mmc->f_max = host->max_clk;
1576         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1577
1578         if (caps & SDHCI_CAN_DO_HISPD)
1579                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1580
1581         mmc->ocr_avail = 0;
1582         if (caps & SDHCI_CAN_VDD_330)
1583                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1584         if (caps & SDHCI_CAN_VDD_300)
1585                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1586         if (caps & SDHCI_CAN_VDD_180)
1587                 mmc->ocr_avail |= MMC_VDD_165_195;
1588
1589         if (mmc->ocr_avail == 0) {
1590                 printk(KERN_ERR "%s: Hardware doesn't report any "
1591                         "support voltages.\n", mmc_hostname(mmc));
1592                 return -ENODEV;
1593         }
1594
1595         spin_lock_init(&host->lock);
1596
1597         /*
1598          * Maximum number of segments. Depends on if the hardware
1599          * can do scatter/gather or not.
1600          */
1601         if (host->flags & SDHCI_USE_ADMA)
1602                 mmc->max_hw_segs = 128;
1603         else if (host->flags & SDHCI_USE_DMA)
1604                 mmc->max_hw_segs = 1;
1605         else /* PIO */
1606                 mmc->max_hw_segs = 128;
1607         mmc->max_phys_segs = 128;
1608
1609         /*
1610          * Maximum number of sectors in one transfer. Limited by DMA boundary
1611          * size (512KiB).
1612          */
1613         mmc->max_req_size = 524288;
1614
1615         /*
1616          * Maximum segment size. Could be one segment with the maximum number
1617          * of bytes. When doing hardware scatter/gather, each entry cannot
1618          * be larger than 64 KiB though.
1619          */
1620         if (host->flags & SDHCI_USE_ADMA)
1621                 mmc->max_seg_size = 65536;
1622         else
1623                 mmc->max_seg_size = mmc->max_req_size;
1624
1625         /*
1626          * Maximum block size. This varies from controller to controller and
1627          * is specified in the capabilities register.
1628          */
1629         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1630         if (mmc->max_blk_size >= 3) {
1631                 printk(KERN_WARNING "%s: Invalid maximum block size, "
1632                         "assuming 512 bytes\n", mmc_hostname(mmc));
1633                 mmc->max_blk_size = 512;
1634         } else
1635                 mmc->max_blk_size = 512 << mmc->max_blk_size;
1636
1637         /*
1638          * Maximum block count.
1639          */
1640         mmc->max_blk_count = 65535;
1641
1642         /*
1643          * Init tasklets.
1644          */
1645         tasklet_init(&host->card_tasklet,
1646                 sdhci_tasklet_card, (unsigned long)host);
1647         tasklet_init(&host->finish_tasklet,
1648                 sdhci_tasklet_finish, (unsigned long)host);
1649
1650         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1651
1652         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1653                 mmc_hostname(mmc), host);
1654         if (ret)
1655                 goto untasklet;
1656
1657         sdhci_init(host);
1658
1659 #ifdef CONFIG_MMC_DEBUG
1660         sdhci_dumpregs(host);
1661 #endif
1662
1663 #ifdef CONFIG_LEDS_CLASS
1664         host->led.name = mmc_hostname(mmc);
1665         host->led.brightness = LED_OFF;
1666         host->led.default_trigger = mmc_hostname(mmc);
1667         host->led.brightness_set = sdhci_led_control;
1668
1669         ret = led_classdev_register(mmc_dev(mmc), &host->led);
1670         if (ret)
1671                 goto reset;
1672 #endif
1673
1674         mmiowb();
1675
1676         mmc_add_host(mmc);
1677
1678         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
1679                 mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
1680                 (host->flags & SDHCI_USE_ADMA)?"A":"",
1681                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1682
1683         return 0;
1684
1685 #ifdef CONFIG_LEDS_CLASS
1686 reset:
1687         sdhci_reset(host, SDHCI_RESET_ALL);
1688         free_irq(host->irq, host);
1689 #endif
1690 untasklet:
1691         tasklet_kill(&host->card_tasklet);
1692         tasklet_kill(&host->finish_tasklet);
1693
1694         return ret;
1695 }
1696
1697 EXPORT_SYMBOL_GPL(sdhci_add_host);
1698
1699 void sdhci_remove_host(struct sdhci_host *host, int dead)
1700 {
1701         unsigned long flags;
1702
1703         if (dead) {
1704                 spin_lock_irqsave(&host->lock, flags);
1705
1706                 host->flags |= SDHCI_DEVICE_DEAD;
1707
1708                 if (host->mrq) {
1709                         printk(KERN_ERR "%s: Controller removed during "
1710                                 " transfer!\n", mmc_hostname(host->mmc));
1711
1712                         host->mrq->cmd->error = -ENOMEDIUM;
1713                         tasklet_schedule(&host->finish_tasklet);
1714                 }
1715
1716                 spin_unlock_irqrestore(&host->lock, flags);
1717         }
1718
1719         mmc_remove_host(host->mmc);
1720
1721 #ifdef CONFIG_LEDS_CLASS
1722         led_classdev_unregister(&host->led);
1723 #endif
1724
1725         if (!dead)
1726                 sdhci_reset(host, SDHCI_RESET_ALL);
1727
1728         free_irq(host->irq, host);
1729
1730         del_timer_sync(&host->timer);
1731
1732         tasklet_kill(&host->card_tasklet);
1733         tasklet_kill(&host->finish_tasklet);
1734
1735         kfree(host->adma_desc);
1736         kfree(host->align_buffer);
1737
1738         host->adma_desc = NULL;
1739         host->align_buffer = NULL;
1740 }
1741
1742 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1743
1744 void sdhci_free_host(struct sdhci_host *host)
1745 {
1746         mmc_free_host(host->mmc);
1747 }
1748
1749 EXPORT_SYMBOL_GPL(sdhci_free_host);
1750
1751 /*****************************************************************************\
1752  *                                                                           *
1753  * Driver init/exit                                                          *
1754  *                                                                           *
1755 \*****************************************************************************/
1756
1757 static int __init sdhci_drv_init(void)
1758 {
1759         printk(KERN_INFO DRIVER_NAME
1760                 ": Secure Digital Host Controller Interface driver\n");
1761         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1762
1763         return 0;
1764 }
1765
1766 static void __exit sdhci_drv_exit(void)
1767 {
1768 }
1769
1770 module_init(sdhci_drv_init);
1771 module_exit(sdhci_drv_exit);
1772
1773 module_param(debug_quirks, uint, 0444);
1774
1775 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1776 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1777 MODULE_LICENSE("GPL");
1778
1779 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");