drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/scatterlist.h>
  21
  22 #include <linux/leds.h>
  23
  24 #include <linux/mmc/host.h>
  25
  26 #include "sdhci.h"
  27
  28 #define DRIVER_NAME "sdhci"
  29
  30 #define DBG(f, x...) \
  31         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  32
  33 static unsigned int debug_quirks = 0;
  34
  35 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  36 static void sdhci_finish_data(struct sdhci_host *);
  37
  38 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  39 static void sdhci_finish_command(struct sdhci_host *);
  40
  41 static void sdhci_dumpregs(struct sdhci_host *host)
  42 {
  43         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  44
  45         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  46                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  47                 readw(host->ioaddr + SDHCI_HOST_VERSION));
  48         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  49                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  50                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  51         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  52                 readl(host->ioaddr + SDHCI_ARGUMENT),
  53                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  54         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  55                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
  56                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
  57         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  58                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
  59                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  60         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  61                 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
  62                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  63         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  64                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  65                 readl(host->ioaddr + SDHCI_INT_STATUS));
  66         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  67                 readl(host->ioaddr + SDHCI_INT_ENABLE),
  68                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  69         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  70                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
  71                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  72         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
  73                 readl(host->ioaddr + SDHCI_CAPABILITIES),
  74                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
  75
  76         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  77 }
  78
  79 /*****************************************************************************\
  80  *                                                                           *
  81  * Low level functions                                                       *
  82  *                                                                           *
  83 \*****************************************************************************/
  84
  85 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  86 {
  87         unsigned long timeout;
  88
  89         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
  90                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  91                         SDHCI_CARD_PRESENT))
  92                         return;
  93         }
  94
  95         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  96
  97         if (mask & SDHCI_RESET_ALL)
  98                 host->clock = 0;
  99
 100         /* Wait max 100 ms */
 101         timeout = 100;
 102
 103         /* hw clears the bit when it's done */
 104         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 105                 if (timeout == 0) {
 106                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 107                                 mmc_hostname(host->mmc), (int)mask);
 108                         sdhci_dumpregs(host);
 109                         return;
 110                 }
 111                 timeout--;
 112                 mdelay(1);
 113         }
 114 }
 115
 116 static void sdhci_init(struct sdhci_host *host)
 117 {
 118         u32 intmask;
 119
 120         sdhci_reset(host, SDHCI_RESET_ALL);
 121
 122         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 123                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 124                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 125                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 126                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 127                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
 128                 SDHCI_INT_ADMA_ERROR;
 129
 130         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 131         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 132 }
 133
 134 static void sdhci_activate_led(struct sdhci_host *host)
 135 {
 136         u8 ctrl;
 137
 138         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 139         ctrl |= SDHCI_CTRL_LED;
 140         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 141 }
 142
 143 static void sdhci_deactivate_led(struct sdhci_host *host)
 144 {
 145         u8 ctrl;
 146
 147         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 148         ctrl &= ~SDHCI_CTRL_LED;
 149         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 150 }
 151
 152 #ifdef CONFIG_LEDS_CLASS
 153 static void sdhci_led_control(struct led_classdev *led,
 154         enum led_brightness brightness)
 155 {
 156         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 157         unsigned long flags;
 158
 159         spin_lock_irqsave(&host->lock, flags);
 160
 161         if (brightness == LED_OFF)
 162                 sdhci_deactivate_led(host);
 163         else
 164                 sdhci_activate_led(host);
 165
 166         spin_unlock_irqrestore(&host->lock, flags);
 167 }
 168 #endif
 169
 170 /*****************************************************************************\
 171  *                                                                           *
 172  * Core functions                                                            *
 173  *                                                                           *
 174 \*****************************************************************************/
 175
 176 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 177 {
 178         return sg_virt(host->cur_sg);
 179 }
 180
 181 static inline int sdhci_next_sg(struct sdhci_host* host)
 182 {
 183         /*
 184          * Skip to next SG entry.
 185          */
 186         host->cur_sg++;
 187         host->num_sg--;
 188
 189         /*
 190          * Any entries left?
 191          */
 192         if (host->num_sg > 0) {
 193                 host->offset = 0;
 194                 host->remain = host->cur_sg->length;
 195         }
 196
 197         return host->num_sg;
 198 }
 199
 200 static void sdhci_read_block_pio(struct sdhci_host *host)
 201 {
 202         int blksize, chunk_remain;
 203         u32 data;
 204         char *buffer;
 205         int size;
 206
 207         DBG("PIO reading\n");
 208
 209         blksize = host->data->blksz;
 210         chunk_remain = 0;
 211         data = 0;
 212
 213         buffer = sdhci_sg_to_buffer(host) + host->offset;
 214
 215         while (blksize) {
 216                 if (chunk_remain == 0) {
 217                         data = readl(host->ioaddr + SDHCI_BUFFER);
 218                         chunk_remain = min(blksize, 4);
 219                 }
 220
 221                 size = min(host->remain, chunk_remain);
 222
 223                 chunk_remain -= size;
 224                 blksize -= size;
 225                 host->offset += size;
 226                 host->remain -= size;
 227
 228                 while (size) {
 229                         *buffer = data & 0xFF;
 230                         buffer++;
 231                         data >>= 8;
 232                         size--;
 233                 }
 234
 235                 if (host->remain == 0) {
 236                         if (sdhci_next_sg(host) == 0) {
 237                                 BUG_ON(blksize != 0);
 238                                 return;
 239                         }
 240                         buffer = sdhci_sg_to_buffer(host);
 241                 }
 242         }
 243 }
 244
 245 static void sdhci_write_block_pio(struct sdhci_host *host)
 246 {
 247         int blksize, chunk_remain;
 248         u32 data;
 249         char *buffer;
 250         int bytes, size;
 251
 252         DBG("PIO writing\n");
 253
 254         blksize = host->data->blksz;
 255         chunk_remain = 4;
 256         data = 0;
 257
 258         bytes = 0;
 259         buffer = sdhci_sg_to_buffer(host) + host->offset;
 260
 261         while (blksize) {
 262                 size = min(host->remain, chunk_remain);
 263
 264                 chunk_remain -= size;
 265                 blksize -= size;
 266                 host->offset += size;
 267                 host->remain -= size;
 268
 269                 while (size) {
 270                         data >>= 8;
 271                         data |= (u32)*buffer << 24;
 272                         buffer++;
 273                         size--;
 274                 }
 275
 276                 if (chunk_remain == 0) {
 277                         writel(data, host->ioaddr + SDHCI_BUFFER);
 278                         chunk_remain = min(blksize, 4);
 279                 }
 280
 281                 if (host->remain == 0) {
 282                         if (sdhci_next_sg(host) == 0) {
 283                                 BUG_ON(blksize != 0);
 284                                 return;
 285                         }
 286                         buffer = sdhci_sg_to_buffer(host);
 287                 }
 288         }
 289 }
 290
 291 static void sdhci_transfer_pio(struct sdhci_host *host)
 292 {
 293         u32 mask;
 294
 295         BUG_ON(!host->data);
 296
 297         if (host->num_sg == 0)
 298                 return;
 299
 300         if (host->data->flags & MMC_DATA_READ)
 301                 mask = SDHCI_DATA_AVAILABLE;
 302         else
 303                 mask = SDHCI_SPACE_AVAILABLE;
 304
 305         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 306                 if (host->data->flags & MMC_DATA_READ)
 307                         sdhci_read_block_pio(host);
 308                 else
 309                         sdhci_write_block_pio(host);
 310
 311                 if (host->num_sg == 0)
 312                         break;
 313         }
 314
 315         DBG("PIO transfer complete.\n");
 316 }
 317
 318 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 319 {
 320         local_irq_save(*flags);
 321         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 322 }
 323
 324 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 325 {
 326         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 327         local_irq_restore(*flags);
 328 }
 329
 330 static int sdhci_adma_table_pre(struct sdhci_host *host,
 331         struct mmc_data *data)
 332 {
 333         int direction;
 334
 335         u8 *desc;
 336         u8 *align;
 337         dma_addr_t addr;
 338         dma_addr_t align_addr;
 339         int len, offset;
 340
 341         struct scatterlist *sg;
 342         int i;
 343         char *buffer;
 344         unsigned long flags;
 345
 346         /*
 347          * The spec does not specify endianness of descriptor table.
 348          * We currently guess that it is LE.
 349          */
 350
 351         if (data->flags & MMC_DATA_READ)
 352                 direction = DMA_FROM_DEVICE;
 353         else
 354                 direction = DMA_TO_DEVICE;
 355
 356         /*
 357          * The ADMA descriptor table is mapped further down as we
 358          * need to fill it with data first.
 359          */
 360
 361         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 362                 host->align_buffer, 128 * 4, direction);
 363         if (dma_mapping_error(host->align_addr))
 364                 goto fail;
 365         BUG_ON(host->align_addr & 0x3);
 366
 367         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 368                 data->sg, data->sg_len, direction);
 369         if (host->sg_count == 0)
 370                 goto unmap_align;
 371
 372         desc = host->adma_desc;
 373         align = host->align_buffer;
 374
 375         align_addr = host->align_addr;
 376
 377         for_each_sg(data->sg, sg, host->sg_count, i) {
 378                 addr = sg_dma_address(sg);
 379                 len = sg_dma_len(sg);
 380
 381                 /*
 382                  * The SDHCI specification states that ADMA
 383                  * addresses must be 32-bit aligned. If they
 384                  * aren't, then we use a bounce buffer for
 385                  * the (up to three) bytes that screw up the
 386                  * alignment.
 387                  */
 388                 offset = (4 - (addr & 0x3)) & 0x3;
 389                 if (offset) {
 390                         if (data->flags & MMC_DATA_WRITE) {
 391                                 buffer = sdhci_kmap_atomic(sg, &flags);
 392                                 memcpy(align, buffer, offset);
 393                                 sdhci_kunmap_atomic(buffer, &flags);
 394                         }
 395
 396                         desc[7] = (align_addr >> 24) & 0xff;
 397                         desc[6] = (align_addr >> 16) & 0xff;
 398                         desc[5] = (align_addr >> 8) & 0xff;
 399                         desc[4] = (align_addr >> 0) & 0xff;
 400
 401                         BUG_ON(offset > 65536);
 402
 403                         desc[3] = (offset >> 8) & 0xff;
 404                         desc[2] = (offset >> 0) & 0xff;
 405
 406                         desc[1] = 0x00;
 407                         desc[0] = 0x21; /* tran, valid */
 408
 409                         align += 4;
 410                         align_addr += 4;
 411
 412                         desc += 8;
 413
 414                         addr += offset;
 415                         len -= offset;
 416                 }
 417
 418                 desc[7] = (addr >> 24) & 0xff;
 419                 desc[6] = (addr >> 16) & 0xff;
 420                 desc[5] = (addr >> 8) & 0xff;
 421                 desc[4] = (addr >> 0) & 0xff;
 422
 423                 BUG_ON(len > 65536);
 424
 425                 desc[3] = (len >> 8) & 0xff;
 426                 desc[2] = (len >> 0) & 0xff;
 427
 428                 desc[1] = 0x00;
 429                 desc[0] = 0x21; /* tran, valid */
 430
 431                 desc += 8;
 432
 433                 /*
 434                  * If this triggers then we have a calculation bug
 435                  * somewhere. :/
 436                  */
 437                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 438         }
 439
 440         /*
 441          * Add a terminating entry.
 442          */
 443         desc[7] = 0;
 444         desc[6] = 0;
 445         desc[5] = 0;
 446         desc[4] = 0;
 447
 448         desc[3] = 0;
 449         desc[2] = 0;
 450
 451         desc[1] = 0x00;
 452         desc[0] = 0x03; /* nop, end, valid */
 453
 454         /*
 455          * Resync align buffer as we might have changed it.
 456          */
 457         if (data->flags & MMC_DATA_WRITE) {
 458                 dma_sync_single_for_device(mmc_dev(host->mmc),
 459                         host->align_addr, 128 * 4, direction);
 460         }
 461
 462         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 463                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 464         if (dma_mapping_error(host->align_addr))
 465                 goto unmap_entries;
 466         BUG_ON(host->adma_addr & 0x3);
 467
 468         return 0;
 469
 470 unmap_entries:
 471         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 472                 data->sg_len, direction);
 473 unmap_align:
 474         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 475                 128 * 4, direction);
 476 fail:
 477         return -EINVAL;
 478 }
 479
 480 static void sdhci_adma_table_post(struct sdhci_host *host,
 481         struct mmc_data *data)
 482 {
 483         int direction;
 484
 485         struct scatterlist *sg;
 486         int i, size;
 487         u8 *align;
 488         char *buffer;
 489         unsigned long flags;
 490
 491         if (data->flags & MMC_DATA_READ)
 492                 direction = DMA_FROM_DEVICE;
 493         else
 494                 direction = DMA_TO_DEVICE;
 495
 496         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 497                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 498
 499         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 500                 128 * 4, direction);
 501
 502         if (data->flags & MMC_DATA_READ) {
 503                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 504                         data->sg_len, direction);
 505
 506                 align = host->align_buffer;
 507
 508                 for_each_sg(data->sg, sg, host->sg_count, i) {
 509                         if (sg_dma_address(sg) & 0x3) {
 510                                 size = 4 - (sg_dma_address(sg) & 0x3);
 511
 512                                 buffer = sdhci_kmap_atomic(sg, &flags);
 513                                 memcpy(buffer, align, size);
 514                                 sdhci_kunmap_atomic(buffer, &flags);
 515
 516                                 align += 4;
 517                         }
 518                 }
 519         }
 520
 521         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 522                 data->sg_len, direction);
 523 }
 524
 525 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
 526 {
 527         u8 count;
 528         unsigned target_timeout, current_timeout;
 529
 530         /*
 531          * If the host controller provides us with an incorrect timeout
 532          * value, just skip the check and use 0xE.  The hardware may take
 533          * longer to time out, but that's much better than having a too-short
 534          * timeout value.
 535          */
 536         if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
 537                 return 0xE;
 538
 539         /* timeout in us */
 540         target_timeout = data->timeout_ns / 1000 +
 541                 data->timeout_clks / host->clock;
 542
 543         /*
 544          * Figure out needed cycles.
 545          * We do this in steps in order to fit inside a 32 bit int.
 546          * The first step is the minimum timeout, which will have a
 547          * minimum resolution of 6 bits:
 548          * (1) 2^13*1000 > 2^22,
 549          * (2) host->timeout_clk < 2^16
 550          *     =>
 551          *     (1) / (2) > 2^6
 552          */
 553         count = 0;
 554         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 555         while (current_timeout < target_timeout) {
 556                 count++;
 557                 current_timeout <<= 1;
 558                 if (count >= 0xF)
 559                         break;
 560         }
 561
 562         if (count >= 0xF) {
 563                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 564                         mmc_hostname(host->mmc));
 565                 count = 0xE;
 566         }
 567
 568         return count;
 569 }
 570
 571 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 572 {
 573         u8 count;
 574         u8 ctrl;
 575         int ret;
 576
 577         WARN_ON(host->data);
 578
 579         if (data == NULL)
 580                 return;
 581
 582         /* Sanity checks */
 583         BUG_ON(data->blksz * data->blocks > 524288);
 584         BUG_ON(data->blksz > host->mmc->max_blk_size);
 585         BUG_ON(data->blocks > 65535);
 586
 587         host->data = data;
 588         host->data_early = 0;
 589
 590         count = sdhci_calc_timeout(host, data);
 591         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 592
 593         if (host->flags & SDHCI_USE_DMA)
 594                 host->flags |= SDHCI_REQ_USE_DMA;
 595
 596         /*
 597          * FIXME: This doesn't account for merging when mapping the
 598          * scatterlist.
 599          */
 600         if (host->flags & SDHCI_REQ_USE_DMA) {
 601                 int broken, i;
 602                 struct scatterlist *sg;
 603
 604                 broken = 0;
 605                 if (host->flags & SDHCI_USE_ADMA) {
 606                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 607                                 broken = 1;
 608                 } else {
 609                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 610                                 broken = 1;
 611                 }
 612
 613                 if (unlikely(broken)) {
 614                         for_each_sg(data->sg, sg, data->sg_len, i) {
 615                                 if (sg->length & 0x3) {
 616                                         DBG("Reverting to PIO because of "
 617                                                 "transfer size (%d)\n",
 618                                                 sg->length);
 619                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 620                                         break;
 621                                 }
 622                         }
 623                 }
 624         }
 625
 626         /*
 627          * The assumption here being that alignment is the same after
 628          * translation to device address space.
 629          */
 630         if (host->flags & SDHCI_REQ_USE_DMA) {
 631                 int broken, i;
 632                 struct scatterlist *sg;
 633
 634                 broken = 0;
 635                 if (host->flags & SDHCI_USE_ADMA) {
 636                         /*
 637                          * As we use 3 byte chunks to work around
 638                          * alignment problems, we need to check this
 639                          * quirk.
 640                          */
 641                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 642                                 broken = 1;
 643                 } else {
 644                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 645                                 broken = 1;
 646                 }
 647
 648                 if (unlikely(broken)) {
 649                         for_each_sg(data->sg, sg, data->sg_len, i) {
 650                                 if (sg->offset & 0x3) {
 651                                         DBG("Reverting to PIO because of "
 652                                                 "bad alignment\n");
 653                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 654                                         break;
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         if (host->flags & SDHCI_REQ_USE_DMA) {
 661                 if (host->flags & SDHCI_USE_ADMA) {
 662                         ret = sdhci_adma_table_pre(host, data);
 663                         if (ret) {
 664                                 /*
 665                                  * This only happens when someone fed
 666                                  * us an invalid request.
 667                                  */
 668                                 WARN_ON(1);
 669                                 host->flags &= ~SDHCI_USE_DMA;
 670                         } else {
 671                                 writel(host->adma_addr,
 672                                         host->ioaddr + SDHCI_ADMA_ADDRESS);
 673                         }
 674                 } else {
 675                         int count;
 676
 677                         count = dma_map_sg(mmc_dev(host->mmc),
 678                                         data->sg, data->sg_len,
 679                                         (data->flags & MMC_DATA_READ) ?
 680                                                 DMA_FROM_DEVICE :
 681                                                 DMA_TO_DEVICE);
 682                         if (count == 0) {
 683                                 /*
 684                                  * This only happens when someone fed
 685                                  * us an invalid request.
 686                                  */
 687                                 WARN_ON(1);
 688                                 host->flags &= ~SDHCI_USE_DMA;
 689                         } else {
 690                                 WARN_ON(count != 1);
 691                                 writel(sg_dma_address(data->sg),
 692                                         host->ioaddr + SDHCI_DMA_ADDRESS);
 693                         }
 694                 }
 695         }
 696
 697         /*
 698          * Always adjust the DMA selection as some controllers
 699          * (e.g. JMicron) can't do PIO properly when the selection
 700          * is ADMA.
 701          */
 702         if (host->version >= SDHCI_SPEC_200) {
 703                 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 704                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 705                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 706                         (host->flags & SDHCI_USE_ADMA))
 707                         ctrl |= SDHCI_CTRL_ADMA32;
 708                 else
 709                         ctrl |= SDHCI_CTRL_SDMA;
 710                 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 711         }
 712
 713         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 714                 host->cur_sg = data->sg;
 715                 host->num_sg = data->sg_len;
 716
 717                 host->offset = 0;
 718                 host->remain = host->cur_sg->length;
 719         }
 720
 721         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 722         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 723                 host->ioaddr + SDHCI_BLOCK_SIZE);
 724         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 725 }
 726
 727 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 728         struct mmc_data *data)
 729 {
 730         u16 mode;
 731
 732         if (data == NULL)
 733                 return;
 734
 735         WARN_ON(!host->data);
 736
 737         mode = SDHCI_TRNS_BLK_CNT_EN;
 738         if (data->blocks > 1)
 739                 mode |= SDHCI_TRNS_MULTI;
 740         if (data->flags & MMC_DATA_READ)
 741                 mode |= SDHCI_TRNS_READ;
 742         if (host->flags & SDHCI_REQ_USE_DMA)
 743                 mode |= SDHCI_TRNS_DMA;
 744
 745         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 746 }
 747
 748 static void sdhci_finish_data(struct sdhci_host *host)
 749 {
 750         struct mmc_data *data;
 751
 752         BUG_ON(!host->data);
 753
 754         data = host->data;
 755         host->data = NULL;
 756
 757         if (host->flags & SDHCI_REQ_USE_DMA) {
 758                 if (host->flags & SDHCI_USE_ADMA)
 759                         sdhci_adma_table_post(host, data);
 760                 else {
 761                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 762                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 763                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 764                 }
 765         }
 766
 767         /*
 768          * The specification states that the block count register must
 769          * be updated, but it does not specify at what point in the
 770          * data flow. That makes the register entirely useless to read
 771          * back so we have to assume that nothing made it to the card
 772          * in the event of an error.
 773          */
 774         if (data->error)
 775                 data->bytes_xfered = 0;
 776         else
 777                 data->bytes_xfered = data->blksz * data->blocks;
 778
 779         if (data->stop) {
 780                 /*
 781                  * The controller needs a reset of internal state machines
 782                  * upon error conditions.
 783                  */
 784                 if (data->error) {
 785                         sdhci_reset(host, SDHCI_RESET_CMD);
 786                         sdhci_reset(host, SDHCI_RESET_DATA);
 787                 }
 788
 789                 sdhci_send_command(host, data->stop);
 790         } else
 791                 tasklet_schedule(&host->finish_tasklet);
 792 }
 793
 794 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 795 {
 796         int flags;
 797         u32 mask;
 798         unsigned long timeout;
 799
 800         WARN_ON(host->cmd);
 801
 802         /* Wait max 10 ms */
 803         timeout = 10;
 804
 805         mask = SDHCI_CMD_INHIBIT;
 806         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 807                 mask |= SDHCI_DATA_INHIBIT;
 808
 809         /* We shouldn't wait for data inihibit for stop commands, even
 810            though they might use busy signaling */
 811         if (host->mrq->data && (cmd == host->mrq->data->stop))
 812                 mask &= ~SDHCI_DATA_INHIBIT;
 813
 814         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 815                 if (timeout == 0) {
 816                         printk(KERN_ERR "%s: Controller never released "
 817                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 818                         sdhci_dumpregs(host);
 819                         cmd->error = -EIO;
 820                         tasklet_schedule(&host->finish_tasklet);
 821                         return;
 822                 }
 823                 timeout--;
 824                 mdelay(1);
 825         }
 826
 827         mod_timer(&host->timer, jiffies + 10 * HZ);
 828
 829         host->cmd = cmd;
 830
 831         sdhci_prepare_data(host, cmd->data);
 832
 833         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 834
 835         sdhci_set_transfer_mode(host, cmd->data);
 836
 837         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 838                 printk(KERN_ERR "%s: Unsupported response type!\n",
 839                         mmc_hostname(host->mmc));
 840                 cmd->error = -EINVAL;
 841                 tasklet_schedule(&host->finish_tasklet);
 842                 return;
 843         }
 844
 845         if (!(cmd->flags & MMC_RSP_PRESENT))
 846                 flags = SDHCI_CMD_RESP_NONE;
 847         else if (cmd->flags & MMC_RSP_136)
 848                 flags = SDHCI_CMD_RESP_LONG;
 849         else if (cmd->flags & MMC_RSP_BUSY)
 850                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 851         else
 852                 flags = SDHCI_CMD_RESP_SHORT;
 853
 854         if (cmd->flags & MMC_RSP_CRC)
 855                 flags |= SDHCI_CMD_CRC;
 856         if (cmd->flags & MMC_RSP_OPCODE)
 857                 flags |= SDHCI_CMD_INDEX;
 858         if (cmd->data)
 859                 flags |= SDHCI_CMD_DATA;
 860
 861         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 862                 host->ioaddr + SDHCI_COMMAND);
 863 }
 864
 865 static void sdhci_finish_command(struct sdhci_host *host)
 866 {
 867         int i;
 868
 869         BUG_ON(host->cmd == NULL);
 870
 871         if (host->cmd->flags & MMC_RSP_PRESENT) {
 872                 if (host->cmd->flags & MMC_RSP_136) {
 873                         /* CRC is stripped so we need to do some shifting. */
 874                         for (i = 0;i < 4;i++) {
 875                                 host->cmd->resp[i] = readl(host->ioaddr +
 876                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 877                                 if (i != 3)
 878                                         host->cmd->resp[i] |=
 879                                                 readb(host->ioaddr +
 880                                                 SDHCI_RESPONSE + (3-i)*4-1);
 881                         }
 882                 } else {
 883                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 884                 }
 885         }
 886
 887         host->cmd->error = 0;
 888
 889         if (host->data && host->data_early)
 890                 sdhci_finish_data(host);
 891
 892         if (!host->cmd->data)
 893                 tasklet_schedule(&host->finish_tasklet);
 894
 895         host->cmd = NULL;
 896 }
 897
 898 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 899 {
 900         int div;
 901         u16 clk;
 902         unsigned long timeout;
 903
 904         if (clock == host->clock)
 905                 return;
 906
 907         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 908
 909         if (clock == 0)
 910                 goto out;
 911
 912         for (div = 1;div < 256;div *= 2) {
 913                 if ((host->max_clk / div) <= clock)
 914                         break;
 915         }
 916         div >>= 1;
 917
 918         clk = div << SDHCI_DIVIDER_SHIFT;
 919         clk |= SDHCI_CLOCK_INT_EN;
 920         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 921
 922         /* Wait max 10 ms */
 923         timeout = 10;
 924         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 925                 & SDHCI_CLOCK_INT_STABLE)) {
 926                 if (timeout == 0) {
 927                         printk(KERN_ERR "%s: Internal clock never "
 928                                 "stabilised.\n", mmc_hostname(host->mmc));
 929                         sdhci_dumpregs(host);
 930                         return;
 931                 }
 932                 timeout--;
 933                 mdelay(1);
 934         }
 935
 936         clk |= SDHCI_CLOCK_CARD_EN;
 937         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 938
 939 out:
 940         host->clock = clock;
 941 }
 942
 943 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 944 {
 945         u8 pwr;
 946
 947         if (host->power == power)
 948                 return;
 949
 950         if (power == (unsigned short)-1) {
 951                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 952                 goto out;
 953         }
 954
 955         /*
 956          * Spec says that we should clear the power reg before setting
 957          * a new value. Some controllers don't seem to like this though.
 958          */
 959         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 960                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 961
 962         pwr = SDHCI_POWER_ON;
 963
 964         switch (1 << power) {
 965         case MMC_VDD_165_195:
 966                 pwr |= SDHCI_POWER_180;
 967                 break;
 968         case MMC_VDD_29_30:
 969         case MMC_VDD_30_31:
 970                 pwr |= SDHCI_POWER_300;
 971                 break;
 972         case MMC_VDD_32_33:
 973         case MMC_VDD_33_34:
 974                 pwr |= SDHCI_POWER_330;
 975                 break;
 976         default:
 977                 BUG();
 978         }
 979
 980         /*
 981          * At least the CaFe chip gets confused if we set the voltage
 982          * and set turn on power at the same time, so set the voltage first.
 983          */
 984         if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
 985                 writeb(pwr & ~SDHCI_POWER_ON,
 986                                 host->ioaddr + SDHCI_POWER_CONTROL);
 987
 988         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 989
 990 out:
 991         host->power = power;
 992 }
 993
 994 /*****************************************************************************\
 995  *                                                                           *
 996  * MMC callbacks                                                             *
 997  *                                                                           *
 998 \*****************************************************************************/
 999
1000 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1001 {
1002         struct sdhci_host *host;
1003         unsigned long flags;
1004
1005         host = mmc_priv(mmc);
1006
1007         spin_lock_irqsave(&host->lock, flags);
1008
1009         WARN_ON(host->mrq != NULL);
1010
1011 #ifndef CONFIG_LEDS_CLASS
1012         sdhci_activate_led(host);
1013 #endif
1014
1015         host->mrq = mrq;
1016
1017         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1018                 || (host->flags & SDHCI_DEVICE_DEAD)) {
1019                 host->mrq->cmd->error = -ENOMEDIUM;
1020                 tasklet_schedule(&host->finish_tasklet);
1021         } else
1022                 sdhci_send_command(host, mrq->cmd);
1023
1024         mmiowb();
1025         spin_unlock_irqrestore(&host->lock, flags);
1026 }
1027
1028 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1029 {
1030         struct sdhci_host *host;
1031         unsigned long flags;
1032         u8 ctrl;
1033
1034         host = mmc_priv(mmc);
1035
1036         spin_lock_irqsave(&host->lock, flags);
1037
1038         if (host->flags & SDHCI_DEVICE_DEAD)
1039                 goto out;
1040
1041         /*
1042          * Reset the chip on each power off.
1043          * Should clear out any weird states.
1044          */
1045         if (ios->power_mode == MMC_POWER_OFF) {
1046                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1047                 sdhci_init(host);
1048         }
1049
1050         sdhci_set_clock(host, ios->clock);
1051
1052         if (ios->power_mode == MMC_POWER_OFF)
1053                 sdhci_set_power(host, -1);
1054         else
1055                 sdhci_set_power(host, ios->vdd);
1056
1057         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
1058
1059         if (ios->bus_width == MMC_BUS_WIDTH_4)
1060                 ctrl |= SDHCI_CTRL_4BITBUS;
1061         else
1062                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1063
1064         if (ios->timing == MMC_TIMING_SD_HS)
1065                 ctrl |= SDHCI_CTRL_HISPD;
1066         else
1067                 ctrl &= ~SDHCI_CTRL_HISPD;
1068
1069         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
1070
1071         /*
1072          * Some (ENE) controllers go apeshit on some ios operation,
1073          * signalling timeout and CRC errors even on CMD0. Resetting
1074          * it on each ios seems to solve the problem.
1075          */
1076         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1077                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1078
1079 out:
1080         mmiowb();
1081         spin_unlock_irqrestore(&host->lock, flags);
1082 }
1083
1084 static int sdhci_get_ro(struct mmc_host *mmc)
1085 {
1086         struct sdhci_host *host;
1087         unsigned long flags;
1088         int present;
1089
1090         host = mmc_priv(mmc);
1091
1092         spin_lock_irqsave(&host->lock, flags);
1093
1094         if (host->flags & SDHCI_DEVICE_DEAD)
1095                 present = 0;
1096         else
1097                 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
1098
1099         spin_unlock_irqrestore(&host->lock, flags);
1100
1101         return !(present & SDHCI_WRITE_PROTECT);
1102 }
1103
1104 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1105 {
1106         struct sdhci_host *host;
1107         unsigned long flags;
1108         u32 ier;
1109
1110         host = mmc_priv(mmc);
1111
1112         spin_lock_irqsave(&host->lock, flags);
1113
1114         if (host->flags & SDHCI_DEVICE_DEAD)
1115                 goto out;
1116
1117         ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
1118
1119         ier &= ~SDHCI_INT_CARD_INT;
1120         if (enable)
1121                 ier |= SDHCI_INT_CARD_INT;
1122
1123         writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
1124         writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1125
1126 out:
1127         mmiowb();
1128
1129         spin_unlock_irqrestore(&host->lock, flags);
1130 }
1131
1132 static const struct mmc_host_ops sdhci_ops = {
1133         .request        = sdhci_request,
1134         .set_ios        = sdhci_set_ios,
1135         .get_ro         = sdhci_get_ro,
1136         .enable_sdio_irq = sdhci_enable_sdio_irq,
1137 };
1138
1139 /*****************************************************************************\
1140  *                                                                           *
1141  * Tasklets                                                                  *
1142  *                                                                           *
1143 \*****************************************************************************/
1144
1145 static void sdhci_tasklet_card(unsigned long param)
1146 {
1147         struct sdhci_host *host;
1148         unsigned long flags;
1149
1150         host = (struct sdhci_host*)param;
1151
1152         spin_lock_irqsave(&host->lock, flags);
1153
1154         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1155                 if (host->mrq) {
1156                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1157                                 mmc_hostname(host->mmc));
1158                         printk(KERN_ERR "%s: Resetting controller.\n",
1159                                 mmc_hostname(host->mmc));
1160
1161                         sdhci_reset(host, SDHCI_RESET_CMD);
1162                         sdhci_reset(host, SDHCI_RESET_DATA);
1163
1164                         host->mrq->cmd->error = -ENOMEDIUM;
1165                         tasklet_schedule(&host->finish_tasklet);
1166                 }
1167         }
1168
1169         spin_unlock_irqrestore(&host->lock, flags);
1170
1171         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1172 }
1173
1174 static void sdhci_tasklet_finish(unsigned long param)
1175 {
1176         struct sdhci_host *host;
1177         unsigned long flags;
1178         struct mmc_request *mrq;
1179
1180         host = (struct sdhci_host*)param;
1181
1182         spin_lock_irqsave(&host->lock, flags);
1183
1184         del_timer(&host->timer);
1185
1186         mrq = host->mrq;
1187
1188         /*
1189          * The controller needs a reset of internal state machines
1190          * upon error conditions.
1191          */
1192         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1193                 (mrq->cmd->error ||
1194                  (mrq->data && (mrq->data->error ||
1195                   (mrq->data->stop && mrq->data->stop->error))) ||
1196                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1197
1198                 /* Some controllers need this kick or reset won't work here */
1199                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1200                         unsigned int clock;
1201
1202                         /* This is to force an update */
1203                         clock = host->clock;
1204                         host->clock = 0;
1205                         sdhci_set_clock(host, clock);
1206                 }
1207
1208                 /* Spec says we should do both at the same time, but Ricoh
1209                    controllers do not like that. */
1210                 sdhci_reset(host, SDHCI_RESET_CMD);
1211                 sdhci_reset(host, SDHCI_RESET_DATA);
1212         }
1213
1214         host->mrq = NULL;
1215         host->cmd = NULL;
1216         host->data = NULL;
1217
1218 #ifndef CONFIG_LEDS_CLASS
1219         sdhci_deactivate_led(host);
1220 #endif
1221
1222         mmiowb();
1223         spin_unlock_irqrestore(&host->lock, flags);
1224
1225         mmc_request_done(host->mmc, mrq);
1226 }
1227
1228 static void sdhci_timeout_timer(unsigned long data)
1229 {
1230         struct sdhci_host *host;
1231         unsigned long flags;
1232
1233         host = (struct sdhci_host*)data;
1234
1235         spin_lock_irqsave(&host->lock, flags);
1236
1237         if (host->mrq) {
1238                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1239                         "interrupt.\n", mmc_hostname(host->mmc));
1240                 sdhci_dumpregs(host);
1241
1242                 if (host->data) {
1243                         host->data->error = -ETIMEDOUT;
1244                         sdhci_finish_data(host);
1245                 } else {
1246                         if (host->cmd)
1247                                 host->cmd->error = -ETIMEDOUT;
1248                         else
1249                                 host->mrq->cmd->error = -ETIMEDOUT;
1250
1251                         tasklet_schedule(&host->finish_tasklet);
1252                 }
1253         }
1254
1255         mmiowb();
1256         spin_unlock_irqrestore(&host->lock, flags);
1257 }
1258
1259 /*****************************************************************************\
1260  *                                                                           *
1261  * Interrupt handling                                                        *
1262  *                                                                           *
1263 \*****************************************************************************/
1264
1265 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1266 {
1267         BUG_ON(intmask == 0);
1268
1269         if (!host->cmd) {
1270                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1271                         "though no command operation was in progress.\n",
1272                         mmc_hostname(host->mmc), (unsigned)intmask);
1273                 sdhci_dumpregs(host);
1274                 return;
1275         }
1276
1277         if (intmask & SDHCI_INT_TIMEOUT)
1278                 host->cmd->error = -ETIMEDOUT;
1279         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1280                         SDHCI_INT_INDEX))
1281                 host->cmd->error = -EILSEQ;
1282
1283         if (host->cmd->error)
1284                 tasklet_schedule(&host->finish_tasklet);
1285         else if (intmask & SDHCI_INT_RESPONSE)
1286                 sdhci_finish_command(host);
1287 }
1288
1289 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1290 {
1291         BUG_ON(intmask == 0);
1292
1293         if (!host->data) {
1294                 /*
1295                  * A data end interrupt is sent together with the response
1296                  * for the stop command.
1297                  */
1298                 if (intmask & SDHCI_INT_DATA_END)
1299                         return;
1300
1301                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1302                         "though no data operation was in progress.\n",
1303                         mmc_hostname(host->mmc), (unsigned)intmask);
1304                 sdhci_dumpregs(host);
1305
1306                 return;
1307         }
1308
1309         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1310                 host->data->error = -ETIMEDOUT;
1311         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1312                 host->data->error = -EILSEQ;
1313         else if (intmask & SDHCI_INT_ADMA_ERROR)
1314                 host->data->error = -EIO;
1315
1316         if (host->data->error)
1317                 sdhci_finish_data(host);
1318         else {
1319                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1320                         sdhci_transfer_pio(host);
1321
1322                 /*
1323                  * We currently don't do anything fancy with DMA
1324                  * boundaries, but as we can't disable the feature
1325                  * we need to at least restart the transfer.
1326                  */
1327                 if (intmask & SDHCI_INT_DMA_END)
1328                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1329                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1330
1331                 if (intmask & SDHCI_INT_DATA_END) {
1332                         if (host->cmd) {
1333                                 /*
1334                                  * Data managed to finish before the
1335                                  * command completed. Make sure we do
1336                                  * things in the proper order.
1337                                  */
1338                                 host->data_early = 1;
1339                         } else {
1340                                 sdhci_finish_data(host);
1341                         }
1342                 }
1343         }
1344 }
1345
1346 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1347 {
1348         irqreturn_t result;
1349         struct sdhci_host* host = dev_id;
1350         u32 intmask;
1351         int cardint = 0;
1352
1353         spin_lock(&host->lock);
1354
1355         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1356
1357         if (!intmask || intmask == 0xffffffff) {
1358                 result = IRQ_NONE;
1359                 goto out;
1360         }
1361
1362         DBG("*** %s got interrupt: 0x%08x\n",
1363                 mmc_hostname(host->mmc), intmask);
1364
1365         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1366                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1367                         host->ioaddr + SDHCI_INT_STATUS);
1368                 tasklet_schedule(&host->card_tasklet);
1369         }
1370
1371         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1372
1373         if (intmask & SDHCI_INT_CMD_MASK) {
1374                 writel(intmask & SDHCI_INT_CMD_MASK,
1375                         host->ioaddr + SDHCI_INT_STATUS);
1376                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1377         }
1378
1379         if (intmask & SDHCI_INT_DATA_MASK) {
1380                 writel(intmask & SDHCI_INT_DATA_MASK,
1381                         host->ioaddr + SDHCI_INT_STATUS);
1382                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1383         }
1384
1385         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1386
1387         intmask &= ~SDHCI_INT_ERROR;
1388
1389         if (intmask & SDHCI_INT_BUS_POWER) {
1390                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1391                         mmc_hostname(host->mmc));
1392                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1393         }
1394
1395         intmask &= ~SDHCI_INT_BUS_POWER;
1396
1397         if (intmask & SDHCI_INT_CARD_INT)
1398                 cardint = 1;
1399
1400         intmask &= ~SDHCI_INT_CARD_INT;
1401
1402         if (intmask) {
1403                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1404                         mmc_hostname(host->mmc), intmask);
1405                 sdhci_dumpregs(host);
1406
1407                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1408         }
1409
1410         result = IRQ_HANDLED;
1411
1412         mmiowb();
1413 out:
1414         spin_unlock(&host->lock);
1415
1416         /*
1417          * We have to delay this as it calls back into the driver.
1418          */
1419         if (cardint)
1420                 mmc_signal_sdio_irq(host->mmc);
1421
1422         return result;
1423 }
1424
1425 /*****************************************************************************\
1426  *                                                                           *
1427  * Suspend/resume                                                            *
1428  *                                                                           *
1429 \*****************************************************************************/
1430
1431 #ifdef CONFIG_PM
1432
1433 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1434 {
1435         int ret;
1436
1437         ret = mmc_suspend_host(host->mmc, state);
1438         if (ret)
1439                 return ret;
1440
1441         free_irq(host->irq, host);
1442
1443         return 0;
1444 }
1445
1446 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1447
1448 int sdhci_resume_host(struct sdhci_host *host)
1449 {
1450         int ret;
1451
1452         if (host->flags & SDHCI_USE_DMA) {
1453                 if (host->ops->enable_dma)
1454                         host->ops->enable_dma(host);
1455         }
1456
1457         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1458                           mmc_hostname(host->mmc), host);
1459         if (ret)
1460                 return ret;
1461
1462         sdhci_init(host);
1463         mmiowb();
1464
1465         ret = mmc_resume_host(host->mmc);
1466         if (ret)
1467                 return ret;
1468
1469         return 0;
1470 }
1471
1472 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1473
1474 #endif /* CONFIG_PM */
1475
1476 /*****************************************************************************\
1477  *                                                                           *
1478  * Device allocation/registration                                            *
1479  *                                                                           *
1480 \*****************************************************************************/
1481
1482 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1483         size_t priv_size)
1484 {
1485         struct mmc_host *mmc;
1486         struct sdhci_host *host;
1487
1488         WARN_ON(dev == NULL);
1489
1490         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1491         if (!mmc)
1492                 return ERR_PTR(-ENOMEM);
1493
1494         host = mmc_priv(mmc);
1495         host->mmc = mmc;
1496
1497         return host;
1498 }
1499
1500 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1501
1502 int sdhci_add_host(struct sdhci_host *host)
1503 {
1504         struct mmc_host *mmc;
1505         unsigned int caps;
1506         int ret;
1507
1508         WARN_ON(host == NULL);
1509         if (host == NULL)
1510                 return -EINVAL;
1511
1512         mmc = host->mmc;
1513
1514         if (debug_quirks)
1515                 host->quirks = debug_quirks;
1516
1517         sdhci_reset(host, SDHCI_RESET_ALL);
1518
1519         host->version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1520         host->version = (host->version & SDHCI_SPEC_VER_MASK)
1521                                 >> SDHCI_SPEC_VER_SHIFT;
1522         if (host->version > SDHCI_SPEC_200) {
1523                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1524                         "You may experience problems.\n", mmc_hostname(mmc),
1525                         host->version);
1526         }
1527
1528         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1529
1530         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1531                 host->flags |= SDHCI_USE_DMA;
1532         else if (!(caps & SDHCI_CAN_DO_DMA))
1533                 DBG("Controller doesn't have DMA capability\n");
1534         else
1535                 host->flags |= SDHCI_USE_DMA;
1536
1537         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1538                 (host->flags & SDHCI_USE_DMA)) {
1539                 DBG("Disabling DMA as it is marked broken\n");
1540                 host->flags &= ~SDHCI_USE_DMA;
1541         }
1542
1543         if (host->flags & SDHCI_USE_DMA) {
1544                 if ((host->version >= SDHCI_SPEC_200) &&
1545                                 (caps & SDHCI_CAN_DO_ADMA2))
1546                         host->flags |= SDHCI_USE_ADMA;
1547         }
1548
1549         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1550                 (host->flags & SDHCI_USE_ADMA)) {
1551                 DBG("Disabling ADMA as it is marked broken\n");
1552                 host->flags &= ~SDHCI_USE_ADMA;
1553         }
1554
1555         if (host->flags & SDHCI_USE_DMA) {
1556                 if (host->ops->enable_dma) {
1557                         if (host->ops->enable_dma(host)) {
1558                                 printk(KERN_WARNING "%s: No suitable DMA "
1559                                         "available. Falling back to PIO.\n",
1560                                         mmc_hostname(mmc));
1561                                 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
1562                         }
1563                 }
1564         }
1565
1566         if (host->flags & SDHCI_USE_ADMA) {
1567                 /*
1568                  * We need to allocate descriptors for all sg entries
1569                  * (128) and potentially one alignment transfer for
1570                  * each of those entries.
1571                  */
1572                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1573                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1574                 if (!host->adma_desc || !host->align_buffer) {
1575                         kfree(host->adma_desc);
1576                         kfree(host->align_buffer);
1577                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
1578                                 "buffers. Falling back to standard DMA.\n",
1579                                 mmc_hostname(mmc));
1580                         host->flags &= ~SDHCI_USE_ADMA;
1581                 }
1582         }
1583
1584         /* XXX: Hack to get MMC layer to avoid highmem */
1585         if (!(host->flags & SDHCI_USE_DMA))
1586                 mmc_dev(host->mmc)->dma_mask = 0;
1587
1588         host->max_clk =
1589                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1590         if (host->max_clk == 0) {
1591                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1592                         "frequency.\n", mmc_hostname(mmc));
1593                 return -ENODEV;
1594         }
1595         host->max_clk *= 1000000;
1596
1597         host->timeout_clk =
1598                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1599         if (host->timeout_clk == 0) {
1600                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1601                         "frequency.\n", mmc_hostname(mmc));
1602                 return -ENODEV;
1603         }
1604         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1605                 host->timeout_clk *= 1000;
1606
1607         /*
1608          * Set host parameters.
1609          */
1610         mmc->ops = &sdhci_ops;
1611         mmc->f_min = host->max_clk / 256;
1612         mmc->f_max = host->max_clk;
1613         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1614
1615         if (caps & SDHCI_CAN_DO_HISPD)
1616                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1617
1618         mmc->ocr_avail = 0;
1619         if (caps & SDHCI_CAN_VDD_330)
1620                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1621         if (caps & SDHCI_CAN_VDD_300)
1622                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1623         if (caps & SDHCI_CAN_VDD_180)
1624                 mmc->ocr_avail |= MMC_VDD_165_195;
1625
1626         if (mmc->ocr_avail == 0) {
1627                 printk(KERN_ERR "%s: Hardware doesn't report any "
1628                         "support voltages.\n", mmc_hostname(mmc));
1629                 return -ENODEV;
1630         }
1631
1632         spin_lock_init(&host->lock);
1633
1634         /*
1635          * Maximum number of segments. Depends on if the hardware
1636          * can do scatter/gather or not.
1637          */
1638         if (host->flags & SDHCI_USE_ADMA)
1639                 mmc->max_hw_segs = 128;
1640         else if (host->flags & SDHCI_USE_DMA)
1641                 mmc->max_hw_segs = 1;
1642         else /* PIO */
1643                 mmc->max_hw_segs = 128;
1644         mmc->max_phys_segs = 128;
1645
1646         /*
1647          * Maximum number of sectors in one transfer. Limited by DMA boundary
1648          * size (512KiB).
1649          */
1650         mmc->max_req_size = 524288;
1651
1652         /*
1653          * Maximum segment size. Could be one segment with the maximum number
1654          * of bytes. When doing hardware scatter/gather, each entry cannot
1655          * be larger than 64 KiB though.
1656          */
1657         if (host->flags & SDHCI_USE_ADMA)
1658                 mmc->max_seg_size = 65536;
1659         else
1660                 mmc->max_seg_size = mmc->max_req_size;
1661
1662         /*
1663          * Maximum block size. This varies from controller to controller and
1664          * is specified in the capabilities register.
1665          */
1666         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1667         if (mmc->max_blk_size >= 3) {
1668                 printk(KERN_WARNING "%s: Invalid maximum block size, "
1669                         "assuming 512 bytes\n", mmc_hostname(mmc));
1670                 mmc->max_blk_size = 512;
1671         } else
1672                 mmc->max_blk_size = 512 << mmc->max_blk_size;
1673
1674         /*
1675          * Maximum block count.
1676          */
1677         mmc->max_blk_count = 65535;
1678
1679         /*
1680          * Init tasklets.
1681          */
1682         tasklet_init(&host->card_tasklet,
1683                 sdhci_tasklet_card, (unsigned long)host);
1684         tasklet_init(&host->finish_tasklet,
1685                 sdhci_tasklet_finish, (unsigned long)host);
1686
1687         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1688
1689         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1690                 mmc_hostname(mmc), host);
1691         if (ret)
1692                 goto untasklet;
1693
1694         sdhci_init(host);
1695
1696 #ifdef CONFIG_MMC_DEBUG
1697         sdhci_dumpregs(host);
1698 #endif
1699
1700 #ifdef CONFIG_LEDS_CLASS
1701         host->led.name = mmc_hostname(mmc);
1702         host->led.brightness = LED_OFF;
1703         host->led.default_trigger = mmc_hostname(mmc);
1704         host->led.brightness_set = sdhci_led_control;
1705
1706         ret = led_classdev_register(mmc_dev(mmc), &host->led);
1707         if (ret)
1708                 goto reset;
1709 #endif
1710
1711         mmiowb();
1712
1713         mmc_add_host(mmc);
1714
1715         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
1716                 mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
1717                 (host->flags & SDHCI_USE_ADMA)?"A":"",
1718                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1719
1720         return 0;
1721
1722 #ifdef CONFIG_LEDS_CLASS
1723 reset:
1724         sdhci_reset(host, SDHCI_RESET_ALL);
1725         free_irq(host->irq, host);
1726 #endif
1727 untasklet:
1728         tasklet_kill(&host->card_tasklet);
1729         tasklet_kill(&host->finish_tasklet);
1730
1731         return ret;
1732 }
1733
1734 EXPORT_SYMBOL_GPL(sdhci_add_host);
1735
1736 void sdhci_remove_host(struct sdhci_host *host, int dead)
1737 {
1738         unsigned long flags;
1739
1740         if (dead) {
1741                 spin_lock_irqsave(&host->lock, flags);
1742
1743                 host->flags |= SDHCI_DEVICE_DEAD;
1744
1745                 if (host->mrq) {
1746                         printk(KERN_ERR "%s: Controller removed during "
1747                                 " transfer!\n", mmc_hostname(host->mmc));
1748
1749                         host->mrq->cmd->error = -ENOMEDIUM;
1750                         tasklet_schedule(&host->finish_tasklet);
1751                 }
1752
1753                 spin_unlock_irqrestore(&host->lock, flags);
1754         }
1755
1756         mmc_remove_host(host->mmc);
1757
1758 #ifdef CONFIG_LEDS_CLASS
1759         led_classdev_unregister(&host->led);
1760 #endif
1761
1762         if (!dead)
1763                 sdhci_reset(host, SDHCI_RESET_ALL);
1764
1765         free_irq(host->irq, host);
1766
1767         del_timer_sync(&host->timer);
1768
1769         tasklet_kill(&host->card_tasklet);
1770         tasklet_kill(&host->finish_tasklet);
1771
1772         kfree(host->adma_desc);
1773         kfree(host->align_buffer);
1774
1775         host->adma_desc = NULL;
1776         host->align_buffer = NULL;
1777 }
1778
1779 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1780
1781 void sdhci_free_host(struct sdhci_host *host)
1782 {
1783         mmc_free_host(host->mmc);
1784 }
1785
1786 EXPORT_SYMBOL_GPL(sdhci_free_host);
1787
1788 /*****************************************************************************\
1789  *                                                                           *
1790  * Driver init/exit                                                          *
1791  *                                                                           *
1792 \*****************************************************************************/
1793
1794 static int __init sdhci_drv_init(void)
1795 {
1796         printk(KERN_INFO DRIVER_NAME
1797                 ": Secure Digital Host Controller Interface driver\n");
1798         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1799
1800         return 0;
1801 }
1802
1803 static void __exit sdhci_drv_exit(void)
1804 {
1805 }
1806
1807 module_init(sdhci_drv_init);
1808 module_exit(sdhci_drv_exit);
1809
1810 module_param(debug_quirks, uint, 0444);
1811
1812 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1813 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1814 MODULE_LICENSE("GPL");
1815
1816 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");