2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/scatterlist.h>
18 #include <linux/mmc/host.h>
22 #define DRIVER_NAME "sdhci"
24 #define DBG(f, x...) \
25 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
27 static unsigned int debug_quirks = 0;
30 * Different quirks to handle when the hardware deviates from a strict
31 * interpretation of the SDHCI specification.
34 /* Controller doesn't honor resets unless we touch the clock register */
35 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
36 /* Controller has bad caps bits, but really supports DMA */
37 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
38 /* Controller doesn't like some resets when there is no card inserted. */
39 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
40 /* Controller doesn't like clearing the power reg before a change */
41 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
42 /* Controller has flaky internal state so reset it on each ios change */
43 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
44 /* Controller has an unusable DMA engine */
45 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
46 /* Controller can only DMA from 32-bit aligned addresses */
47 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
48 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
49 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
51 static const struct pci_device_id pci_ids[] __devinitdata = {
53 .vendor = PCI_VENDOR_ID_RICOH,
54 .device = PCI_DEVICE_ID_RICOH_R5C822,
55 .subvendor = PCI_VENDOR_ID_IBM,
56 .subdevice = PCI_ANY_ID,
57 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
58 SDHCI_QUIRK_FORCE_DMA,
62 .vendor = PCI_VENDOR_ID_RICOH,
63 .device = PCI_DEVICE_ID_RICOH_R5C822,
64 .subvendor = PCI_ANY_ID,
65 .subdevice = PCI_ANY_ID,
66 .driver_data = SDHCI_QUIRK_FORCE_DMA |
67 SDHCI_QUIRK_NO_CARD_NO_RESET,
71 .vendor = PCI_VENDOR_ID_TI,
72 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
73 .subvendor = PCI_ANY_ID,
74 .subdevice = PCI_ANY_ID,
75 .driver_data = SDHCI_QUIRK_FORCE_DMA,
79 .vendor = PCI_VENDOR_ID_ENE,
80 .device = PCI_DEVICE_ID_ENE_CB712_SD,
81 .subvendor = PCI_ANY_ID,
82 .subdevice = PCI_ANY_ID,
83 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
84 SDHCI_QUIRK_BROKEN_DMA,
88 .vendor = PCI_VENDOR_ID_ENE,
89 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
90 .subvendor = PCI_ANY_ID,
91 .subdevice = PCI_ANY_ID,
92 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
93 SDHCI_QUIRK_BROKEN_DMA,
97 .vendor = PCI_VENDOR_ID_ENE,
98 .device = PCI_DEVICE_ID_ENE_CB714_SD,
99 .subvendor = PCI_ANY_ID,
100 .subdevice = PCI_ANY_ID,
101 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
102 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
106 .vendor = PCI_VENDOR_ID_ENE,
107 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
108 .subvendor = PCI_ANY_ID,
109 .subdevice = PCI_ANY_ID,
110 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
111 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
114 { /* Generic SD host controller */
115 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
118 { /* end: all zeroes */ },
121 MODULE_DEVICE_TABLE(pci, pci_ids);
123 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
124 static void sdhci_finish_data(struct sdhci_host *);
126 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
127 static void sdhci_finish_command(struct sdhci_host *);
129 static void sdhci_dumpregs(struct sdhci_host *host)
131 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
133 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
134 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
135 readw(host->ioaddr + SDHCI_HOST_VERSION));
136 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
137 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
138 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
139 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
140 readl(host->ioaddr + SDHCI_ARGUMENT),
141 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
142 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
143 readl(host->ioaddr + SDHCI_PRESENT_STATE),
144 readb(host->ioaddr + SDHCI_HOST_CONTROL));
145 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
146 readb(host->ioaddr + SDHCI_POWER_CONTROL),
147 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
148 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
149 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
150 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
151 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
152 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
153 readl(host->ioaddr + SDHCI_INT_STATUS));
154 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
155 readl(host->ioaddr + SDHCI_INT_ENABLE),
156 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
157 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
158 readw(host->ioaddr + SDHCI_ACMD12_ERR),
159 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
160 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
161 readl(host->ioaddr + SDHCI_CAPABILITIES),
162 readl(host->ioaddr + SDHCI_MAX_CURRENT));
164 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
167 /*****************************************************************************\
169 * Low level functions *
171 \*****************************************************************************/
173 static void sdhci_reset(struct sdhci_host *host, u8 mask)
175 unsigned long timeout;
177 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
178 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
183 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
185 if (mask & SDHCI_RESET_ALL)
188 /* Wait max 100 ms */
191 /* hw clears the bit when it's done */
192 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
194 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
195 mmc_hostname(host->mmc), (int)mask);
196 sdhci_dumpregs(host);
204 static void sdhci_init(struct sdhci_host *host)
208 sdhci_reset(host, SDHCI_RESET_ALL);
210 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
211 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
212 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
213 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
214 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
215 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
217 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
218 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
221 static void sdhci_activate_led(struct sdhci_host *host)
225 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
226 ctrl |= SDHCI_CTRL_LED;
227 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
230 static void sdhci_deactivate_led(struct sdhci_host *host)
234 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
235 ctrl &= ~SDHCI_CTRL_LED;
236 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
239 /*****************************************************************************\
243 \*****************************************************************************/
245 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
247 return sg_virt(host->cur_sg);
250 static inline int sdhci_next_sg(struct sdhci_host* host)
253 * Skip to next SG entry.
261 if (host->num_sg > 0) {
263 host->remain = host->cur_sg->length;
269 static void sdhci_read_block_pio(struct sdhci_host *host)
271 int blksize, chunk_remain;
276 DBG("PIO reading\n");
278 blksize = host->data->blksz;
282 buffer = sdhci_sg_to_buffer(host) + host->offset;
285 if (chunk_remain == 0) {
286 data = readl(host->ioaddr + SDHCI_BUFFER);
287 chunk_remain = min(blksize, 4);
290 size = min(host->remain, chunk_remain);
292 chunk_remain -= size;
294 host->offset += size;
295 host->remain -= size;
298 *buffer = data & 0xFF;
304 if (host->remain == 0) {
305 if (sdhci_next_sg(host) == 0) {
306 BUG_ON(blksize != 0);
309 buffer = sdhci_sg_to_buffer(host);
314 static void sdhci_write_block_pio(struct sdhci_host *host)
316 int blksize, chunk_remain;
321 DBG("PIO writing\n");
323 blksize = host->data->blksz;
328 buffer = sdhci_sg_to_buffer(host) + host->offset;
331 size = min(host->remain, chunk_remain);
333 chunk_remain -= size;
335 host->offset += size;
336 host->remain -= size;
340 data |= (u32)*buffer << 24;
345 if (chunk_remain == 0) {
346 writel(data, host->ioaddr + SDHCI_BUFFER);
347 chunk_remain = min(blksize, 4);
350 if (host->remain == 0) {
351 if (sdhci_next_sg(host) == 0) {
352 BUG_ON(blksize != 0);
355 buffer = sdhci_sg_to_buffer(host);
360 static void sdhci_transfer_pio(struct sdhci_host *host)
366 if (host->num_sg == 0)
369 if (host->data->flags & MMC_DATA_READ)
370 mask = SDHCI_DATA_AVAILABLE;
372 mask = SDHCI_SPACE_AVAILABLE;
374 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
375 if (host->data->flags & MMC_DATA_READ)
376 sdhci_read_block_pio(host);
378 sdhci_write_block_pio(host);
380 if (host->num_sg == 0)
384 DBG("PIO transfer complete.\n");
387 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
390 unsigned target_timeout, current_timeout;
398 BUG_ON(data->blksz * data->blocks > 524288);
399 BUG_ON(data->blksz > host->mmc->max_blk_size);
400 BUG_ON(data->blocks > 65535);
403 host->data_early = 0;
406 target_timeout = data->timeout_ns / 1000 +
407 data->timeout_clks / host->clock;
410 * Figure out needed cycles.
411 * We do this in steps in order to fit inside a 32 bit int.
412 * The first step is the minimum timeout, which will have a
413 * minimum resolution of 6 bits:
414 * (1) 2^13*1000 > 2^22,
415 * (2) host->timeout_clk < 2^16
420 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
421 while (current_timeout < target_timeout) {
423 current_timeout <<= 1;
429 printk(KERN_WARNING "%s: Too large timeout requested!\n",
430 mmc_hostname(host->mmc));
434 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
436 if (host->flags & SDHCI_USE_DMA)
437 host->flags |= SDHCI_REQ_USE_DMA;
439 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
440 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
441 ((data->blksz * data->blocks) & 0x3))) {
442 DBG("Reverting to PIO because of transfer size (%d)\n",
443 data->blksz * data->blocks);
444 host->flags &= ~SDHCI_REQ_USE_DMA;
448 * The assumption here being that alignment is the same after
449 * translation to device address space.
451 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
452 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
453 (data->sg->offset & 0x3))) {
454 DBG("Reverting to PIO because of bad alignment\n");
455 host->flags &= ~SDHCI_REQ_USE_DMA;
458 if (host->flags & SDHCI_REQ_USE_DMA) {
461 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
462 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
465 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
467 host->cur_sg = data->sg;
468 host->num_sg = data->sg_len;
471 host->remain = host->cur_sg->length;
474 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
475 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
476 host->ioaddr + SDHCI_BLOCK_SIZE);
477 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
480 static void sdhci_set_transfer_mode(struct sdhci_host *host,
481 struct mmc_data *data)
488 WARN_ON(!host->data);
490 mode = SDHCI_TRNS_BLK_CNT_EN;
491 if (data->blocks > 1)
492 mode |= SDHCI_TRNS_MULTI;
493 if (data->flags & MMC_DATA_READ)
494 mode |= SDHCI_TRNS_READ;
495 if (host->flags & SDHCI_REQ_USE_DMA)
496 mode |= SDHCI_TRNS_DMA;
498 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
501 static void sdhci_finish_data(struct sdhci_host *host)
503 struct mmc_data *data;
511 if (host->flags & SDHCI_REQ_USE_DMA) {
512 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
513 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
517 * Controller doesn't count down when in single block mode.
519 if (data->blocks == 1)
520 blocks = (data->error == 0) ? 0 : 1;
522 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
523 data->bytes_xfered = data->blksz * (data->blocks - blocks);
525 if (!data->error && blocks) {
526 printk(KERN_ERR "%s: Controller signalled completion even "
527 "though there were blocks left.\n",
528 mmc_hostname(host->mmc));
534 * The controller needs a reset of internal state machines
535 * upon error conditions.
538 sdhci_reset(host, SDHCI_RESET_CMD);
539 sdhci_reset(host, SDHCI_RESET_DATA);
542 sdhci_send_command(host, data->stop);
544 tasklet_schedule(&host->finish_tasklet);
547 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
551 unsigned long timeout;
558 mask = SDHCI_CMD_INHIBIT;
559 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
560 mask |= SDHCI_DATA_INHIBIT;
562 /* We shouldn't wait for data inihibit for stop commands, even
563 though they might use busy signaling */
564 if (host->mrq->data && (cmd == host->mrq->data->stop))
565 mask &= ~SDHCI_DATA_INHIBIT;
567 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
569 printk(KERN_ERR "%s: Controller never released "
570 "inhibit bit(s).\n", mmc_hostname(host->mmc));
571 sdhci_dumpregs(host);
573 tasklet_schedule(&host->finish_tasklet);
580 mod_timer(&host->timer, jiffies + 10 * HZ);
584 sdhci_prepare_data(host, cmd->data);
586 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
588 sdhci_set_transfer_mode(host, cmd->data);
590 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
591 printk(KERN_ERR "%s: Unsupported response type!\n",
592 mmc_hostname(host->mmc));
593 cmd->error = -EINVAL;
594 tasklet_schedule(&host->finish_tasklet);
598 if (!(cmd->flags & MMC_RSP_PRESENT))
599 flags = SDHCI_CMD_RESP_NONE;
600 else if (cmd->flags & MMC_RSP_136)
601 flags = SDHCI_CMD_RESP_LONG;
602 else if (cmd->flags & MMC_RSP_BUSY)
603 flags = SDHCI_CMD_RESP_SHORT_BUSY;
605 flags = SDHCI_CMD_RESP_SHORT;
607 if (cmd->flags & MMC_RSP_CRC)
608 flags |= SDHCI_CMD_CRC;
609 if (cmd->flags & MMC_RSP_OPCODE)
610 flags |= SDHCI_CMD_INDEX;
612 flags |= SDHCI_CMD_DATA;
614 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
615 host->ioaddr + SDHCI_COMMAND);
618 static void sdhci_finish_command(struct sdhci_host *host)
622 BUG_ON(host->cmd == NULL);
624 if (host->cmd->flags & MMC_RSP_PRESENT) {
625 if (host->cmd->flags & MMC_RSP_136) {
626 /* CRC is stripped so we need to do some shifting. */
627 for (i = 0;i < 4;i++) {
628 host->cmd->resp[i] = readl(host->ioaddr +
629 SDHCI_RESPONSE + (3-i)*4) << 8;
631 host->cmd->resp[i] |=
633 SDHCI_RESPONSE + (3-i)*4-1);
636 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
640 host->cmd->error = 0;
642 if (host->data && host->data_early)
643 sdhci_finish_data(host);
645 if (!host->cmd->data)
646 tasklet_schedule(&host->finish_tasklet);
651 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
655 unsigned long timeout;
657 if (clock == host->clock)
660 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
665 for (div = 1;div < 256;div *= 2) {
666 if ((host->max_clk / div) <= clock)
671 clk = div << SDHCI_DIVIDER_SHIFT;
672 clk |= SDHCI_CLOCK_INT_EN;
673 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
677 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
678 & SDHCI_CLOCK_INT_STABLE)) {
680 printk(KERN_ERR "%s: Internal clock never "
681 "stabilised.\n", mmc_hostname(host->mmc));
682 sdhci_dumpregs(host);
689 clk |= SDHCI_CLOCK_CARD_EN;
690 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
696 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
700 if (host->power == power)
703 if (power == (unsigned short)-1) {
704 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
709 * Spec says that we should clear the power reg before setting
710 * a new value. Some controllers don't seem to like this though.
712 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
713 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
715 pwr = SDHCI_POWER_ON;
717 switch (1 << power) {
718 case MMC_VDD_165_195:
719 pwr |= SDHCI_POWER_180;
723 pwr |= SDHCI_POWER_300;
727 pwr |= SDHCI_POWER_330;
733 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
739 /*****************************************************************************\
743 \*****************************************************************************/
745 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
747 struct sdhci_host *host;
750 host = mmc_priv(mmc);
752 spin_lock_irqsave(&host->lock, flags);
754 WARN_ON(host->mrq != NULL);
756 sdhci_activate_led(host);
760 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
761 host->mrq->cmd->error = -ENOMEDIUM;
762 tasklet_schedule(&host->finish_tasklet);
764 sdhci_send_command(host, mrq->cmd);
767 spin_unlock_irqrestore(&host->lock, flags);
770 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
772 struct sdhci_host *host;
776 host = mmc_priv(mmc);
778 spin_lock_irqsave(&host->lock, flags);
781 * Reset the chip on each power off.
782 * Should clear out any weird states.
784 if (ios->power_mode == MMC_POWER_OFF) {
785 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
789 sdhci_set_clock(host, ios->clock);
791 if (ios->power_mode == MMC_POWER_OFF)
792 sdhci_set_power(host, -1);
794 sdhci_set_power(host, ios->vdd);
796 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
798 if (ios->bus_width == MMC_BUS_WIDTH_4)
799 ctrl |= SDHCI_CTRL_4BITBUS;
801 ctrl &= ~SDHCI_CTRL_4BITBUS;
803 if (ios->timing == MMC_TIMING_SD_HS)
804 ctrl |= SDHCI_CTRL_HISPD;
806 ctrl &= ~SDHCI_CTRL_HISPD;
808 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
811 * Some (ENE) controllers go apeshit on some ios operation,
812 * signalling timeout and CRC errors even on CMD0. Resetting
813 * it on each ios seems to solve the problem.
815 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
816 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
819 spin_unlock_irqrestore(&host->lock, flags);
822 static int sdhci_get_ro(struct mmc_host *mmc)
824 struct sdhci_host *host;
828 host = mmc_priv(mmc);
830 spin_lock_irqsave(&host->lock, flags);
832 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
834 spin_unlock_irqrestore(&host->lock, flags);
836 return !(present & SDHCI_WRITE_PROTECT);
839 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
841 struct sdhci_host *host;
845 host = mmc_priv(mmc);
847 spin_lock_irqsave(&host->lock, flags);
849 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
851 ier &= ~SDHCI_INT_CARD_INT;
853 ier |= SDHCI_INT_CARD_INT;
855 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
856 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
860 spin_unlock_irqrestore(&host->lock, flags);
863 static const struct mmc_host_ops sdhci_ops = {
864 .request = sdhci_request,
865 .set_ios = sdhci_set_ios,
866 .get_ro = sdhci_get_ro,
867 .enable_sdio_irq = sdhci_enable_sdio_irq,
870 /*****************************************************************************\
874 \*****************************************************************************/
876 static void sdhci_tasklet_card(unsigned long param)
878 struct sdhci_host *host;
881 host = (struct sdhci_host*)param;
883 spin_lock_irqsave(&host->lock, flags);
885 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
887 printk(KERN_ERR "%s: Card removed during transfer!\n",
888 mmc_hostname(host->mmc));
889 printk(KERN_ERR "%s: Resetting controller.\n",
890 mmc_hostname(host->mmc));
892 sdhci_reset(host, SDHCI_RESET_CMD);
893 sdhci_reset(host, SDHCI_RESET_DATA);
895 host->mrq->cmd->error = -ENOMEDIUM;
896 tasklet_schedule(&host->finish_tasklet);
900 spin_unlock_irqrestore(&host->lock, flags);
902 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
905 static void sdhci_tasklet_finish(unsigned long param)
907 struct sdhci_host *host;
909 struct mmc_request *mrq;
911 host = (struct sdhci_host*)param;
913 spin_lock_irqsave(&host->lock, flags);
915 del_timer(&host->timer);
920 * The controller needs a reset of internal state machines
921 * upon error conditions.
923 if (mrq->cmd->error ||
924 (mrq->data && (mrq->data->error ||
925 (mrq->data->stop && mrq->data->stop->error)))) {
927 /* Some controllers need this kick or reset won't work here */
928 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
931 /* This is to force an update */
934 sdhci_set_clock(host, clock);
937 /* Spec says we should do both at the same time, but Ricoh
938 controllers do not like that. */
939 sdhci_reset(host, SDHCI_RESET_CMD);
940 sdhci_reset(host, SDHCI_RESET_DATA);
947 sdhci_deactivate_led(host);
950 spin_unlock_irqrestore(&host->lock, flags);
952 mmc_request_done(host->mmc, mrq);
955 static void sdhci_timeout_timer(unsigned long data)
957 struct sdhci_host *host;
960 host = (struct sdhci_host*)data;
962 spin_lock_irqsave(&host->lock, flags);
965 printk(KERN_ERR "%s: Timeout waiting for hardware "
966 "interrupt.\n", mmc_hostname(host->mmc));
967 sdhci_dumpregs(host);
970 host->data->error = -ETIMEDOUT;
971 sdhci_finish_data(host);
974 host->cmd->error = -ETIMEDOUT;
976 host->mrq->cmd->error = -ETIMEDOUT;
978 tasklet_schedule(&host->finish_tasklet);
983 spin_unlock_irqrestore(&host->lock, flags);
986 /*****************************************************************************\
988 * Interrupt handling *
990 \*****************************************************************************/
992 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
994 BUG_ON(intmask == 0);
997 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
998 "though no command operation was in progress.\n",
999 mmc_hostname(host->mmc), (unsigned)intmask);
1000 sdhci_dumpregs(host);
1004 if (intmask & SDHCI_INT_TIMEOUT)
1005 host->cmd->error = -ETIMEDOUT;
1006 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1008 host->cmd->error = -EILSEQ;
1010 if (host->cmd->error)
1011 tasklet_schedule(&host->finish_tasklet);
1012 else if (intmask & SDHCI_INT_RESPONSE)
1013 sdhci_finish_command(host);
1016 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1018 BUG_ON(intmask == 0);
1022 * A data end interrupt is sent together with the response
1023 * for the stop command.
1025 if (intmask & SDHCI_INT_DATA_END)
1028 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1029 "though no data operation was in progress.\n",
1030 mmc_hostname(host->mmc), (unsigned)intmask);
1031 sdhci_dumpregs(host);
1036 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1037 host->data->error = -ETIMEDOUT;
1038 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1039 host->data->error = -EILSEQ;
1041 if (host->data->error)
1042 sdhci_finish_data(host);
1044 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1045 sdhci_transfer_pio(host);
1048 * We currently don't do anything fancy with DMA
1049 * boundaries, but as we can't disable the feature
1050 * we need to at least restart the transfer.
1052 if (intmask & SDHCI_INT_DMA_END)
1053 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1054 host->ioaddr + SDHCI_DMA_ADDRESS);
1056 if (intmask & SDHCI_INT_DATA_END) {
1059 * Data managed to finish before the
1060 * command completed. Make sure we do
1061 * things in the proper order.
1063 host->data_early = 1;
1065 sdhci_finish_data(host);
1071 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1074 struct sdhci_host* host = dev_id;
1078 spin_lock(&host->lock);
1080 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1082 if (!intmask || intmask == 0xffffffff) {
1087 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1089 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1090 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1091 host->ioaddr + SDHCI_INT_STATUS);
1092 tasklet_schedule(&host->card_tasklet);
1095 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1097 if (intmask & SDHCI_INT_CMD_MASK) {
1098 writel(intmask & SDHCI_INT_CMD_MASK,
1099 host->ioaddr + SDHCI_INT_STATUS);
1100 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1103 if (intmask & SDHCI_INT_DATA_MASK) {
1104 writel(intmask & SDHCI_INT_DATA_MASK,
1105 host->ioaddr + SDHCI_INT_STATUS);
1106 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1109 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1111 intmask &= ~SDHCI_INT_ERROR;
1113 if (intmask & SDHCI_INT_BUS_POWER) {
1114 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1115 mmc_hostname(host->mmc));
1116 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1119 intmask &= ~SDHCI_INT_BUS_POWER;
1121 if (intmask & SDHCI_INT_CARD_INT)
1124 intmask &= ~SDHCI_INT_CARD_INT;
1127 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1128 mmc_hostname(host->mmc), intmask);
1129 sdhci_dumpregs(host);
1131 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1134 result = IRQ_HANDLED;
1138 spin_unlock(&host->lock);
1141 * We have to delay this as it calls back into the driver.
1144 mmc_signal_sdio_irq(host->mmc);
1149 /*****************************************************************************\
1153 \*****************************************************************************/
1157 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1159 struct sdhci_chip *chip;
1162 chip = pci_get_drvdata(pdev);
1166 DBG("Suspending...\n");
1168 for (i = 0;i < chip->num_slots;i++) {
1169 if (!chip->hosts[i])
1171 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1173 for (i--;i >= 0;i--)
1174 mmc_resume_host(chip->hosts[i]->mmc);
1179 pci_save_state(pdev);
1180 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1182 for (i = 0;i < chip->num_slots;i++) {
1183 if (!chip->hosts[i])
1185 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1188 pci_disable_device(pdev);
1189 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1194 static int sdhci_resume (struct pci_dev *pdev)
1196 struct sdhci_chip *chip;
1199 chip = pci_get_drvdata(pdev);
1203 DBG("Resuming...\n");
1205 pci_set_power_state(pdev, PCI_D0);
1206 pci_restore_state(pdev);
1207 ret = pci_enable_device(pdev);
1211 for (i = 0;i < chip->num_slots;i++) {
1212 if (!chip->hosts[i])
1214 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1215 pci_set_master(pdev);
1216 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1217 IRQF_SHARED, chip->hosts[i]->slot_descr,
1221 sdhci_init(chip->hosts[i]);
1223 ret = mmc_resume_host(chip->hosts[i]->mmc);
1231 #else /* CONFIG_PM */
1233 #define sdhci_suspend NULL
1234 #define sdhci_resume NULL
1236 #endif /* CONFIG_PM */
1238 /*****************************************************************************\
1240 * Device probing/removal *
1242 \*****************************************************************************/
1244 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1247 unsigned int version;
1248 struct sdhci_chip *chip;
1249 struct mmc_host *mmc;
1250 struct sdhci_host *host;
1255 chip = pci_get_drvdata(pdev);
1258 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1262 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1264 if (first_bar > 5) {
1265 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1269 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1270 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1274 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1275 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1276 "You may experience problems.\n");
1279 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1280 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1284 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1285 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1289 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1293 host = mmc_priv(mmc);
1297 chip->hosts[slot] = host;
1299 host->bar = first_bar + slot;
1301 host->addr = pci_resource_start(pdev, host->bar);
1302 host->irq = pdev->irq;
1304 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1306 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1308 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1312 host->ioaddr = ioremap_nocache(host->addr,
1313 pci_resource_len(pdev, host->bar));
1314 if (!host->ioaddr) {
1319 sdhci_reset(host, SDHCI_RESET_ALL);
1321 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1322 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1324 printk(KERN_ERR "%s: Unknown controller version (%d). "
1325 "You may experience problems.\n", host->slot_descr,
1329 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1331 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1332 host->flags |= SDHCI_USE_DMA;
1333 else if (!(caps & SDHCI_CAN_DO_DMA))
1334 DBG("Controller doesn't have DMA capability\n");
1336 host->flags |= SDHCI_USE_DMA;
1338 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1339 (host->flags & SDHCI_USE_DMA)) {
1340 DBG("Disabling DMA as it is marked broken\n");
1341 host->flags &= ~SDHCI_USE_DMA;
1344 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1345 (host->flags & SDHCI_USE_DMA)) {
1346 printk(KERN_WARNING "%s: Will use DMA "
1347 "mode even though HW doesn't fully "
1348 "claim to support it.\n", host->slot_descr);
1351 if (host->flags & SDHCI_USE_DMA) {
1352 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1353 printk(KERN_WARNING "%s: No suitable DMA available. "
1354 "Falling back to PIO.\n", host->slot_descr);
1355 host->flags &= ~SDHCI_USE_DMA;
1359 if (host->flags & SDHCI_USE_DMA)
1360 pci_set_master(pdev);
1361 else /* XXX: Hack to get MMC layer to avoid highmem */
1365 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1366 if (host->max_clk == 0) {
1367 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1368 "frequency.\n", host->slot_descr);
1372 host->max_clk *= 1000000;
1375 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1376 if (host->timeout_clk == 0) {
1377 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1378 "frequency.\n", host->slot_descr);
1382 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1383 host->timeout_clk *= 1000;
1386 * Set host parameters.
1388 mmc->ops = &sdhci_ops;
1389 mmc->f_min = host->max_clk / 256;
1390 mmc->f_max = host->max_clk;
1391 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1393 if (caps & SDHCI_CAN_DO_HISPD)
1394 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1397 if (caps & SDHCI_CAN_VDD_330)
1398 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1399 if (caps & SDHCI_CAN_VDD_300)
1400 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1401 if (caps & SDHCI_CAN_VDD_180)
1402 mmc->ocr_avail |= MMC_VDD_165_195;
1404 if (mmc->ocr_avail == 0) {
1405 printk(KERN_ERR "%s: Hardware doesn't report any "
1406 "support voltages.\n", host->slot_descr);
1411 spin_lock_init(&host->lock);
1414 * Maximum number of segments. Hardware cannot do scatter lists.
1416 if (host->flags & SDHCI_USE_DMA)
1417 mmc->max_hw_segs = 1;
1419 mmc->max_hw_segs = 16;
1420 mmc->max_phys_segs = 16;
1423 * Maximum number of sectors in one transfer. Limited by DMA boundary
1426 mmc->max_req_size = 524288;
1429 * Maximum segment size. Could be one segment with the maximum number
1432 mmc->max_seg_size = mmc->max_req_size;
1435 * Maximum block size. This varies from controller to controller and
1436 * is specified in the capabilities register.
1438 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1439 if (mmc->max_blk_size >= 3) {
1440 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1442 mmc->max_blk_size = 512;
1444 mmc->max_blk_size = 512 << mmc->max_blk_size;
1447 * Maximum block count.
1449 mmc->max_blk_count = 65535;
1454 tasklet_init(&host->card_tasklet,
1455 sdhci_tasklet_card, (unsigned long)host);
1456 tasklet_init(&host->finish_tasklet,
1457 sdhci_tasklet_finish, (unsigned long)host);
1459 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1461 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1462 host->slot_descr, host);
1468 #ifdef CONFIG_MMC_DEBUG
1469 sdhci_dumpregs(host);
1476 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1477 host->addr, host->irq,
1478 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1483 tasklet_kill(&host->card_tasklet);
1484 tasklet_kill(&host->finish_tasklet);
1486 iounmap(host->ioaddr);
1488 pci_release_region(pdev, host->bar);
1495 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1497 struct sdhci_chip *chip;
1498 struct mmc_host *mmc;
1499 struct sdhci_host *host;
1501 chip = pci_get_drvdata(pdev);
1502 host = chip->hosts[slot];
1505 chip->hosts[slot] = NULL;
1507 mmc_remove_host(mmc);
1509 sdhci_reset(host, SDHCI_RESET_ALL);
1511 free_irq(host->irq, host);
1513 del_timer_sync(&host->timer);
1515 tasklet_kill(&host->card_tasklet);
1516 tasklet_kill(&host->finish_tasklet);
1518 iounmap(host->ioaddr);
1520 pci_release_region(pdev, host->bar);
1525 static int __devinit sdhci_probe(struct pci_dev *pdev,
1526 const struct pci_device_id *ent)
1530 struct sdhci_chip *chip;
1532 BUG_ON(pdev == NULL);
1533 BUG_ON(ent == NULL);
1535 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1537 printk(KERN_INFO DRIVER_NAME
1538 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1539 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1542 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1546 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1547 DBG("found %d slot(s)\n", slots);
1551 ret = pci_enable_device(pdev);
1555 chip = kzalloc(sizeof(struct sdhci_chip) +
1556 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1563 chip->quirks = ent->driver_data;
1566 chip->quirks = debug_quirks;
1568 chip->num_slots = slots;
1569 pci_set_drvdata(pdev, chip);
1571 for (i = 0;i < slots;i++) {
1572 ret = sdhci_probe_slot(pdev, i);
1574 for (i--;i >= 0;i--)
1575 sdhci_remove_slot(pdev, i);
1583 pci_set_drvdata(pdev, NULL);
1587 pci_disable_device(pdev);
1591 static void __devexit sdhci_remove(struct pci_dev *pdev)
1594 struct sdhci_chip *chip;
1596 chip = pci_get_drvdata(pdev);
1599 for (i = 0;i < chip->num_slots;i++)
1600 sdhci_remove_slot(pdev, i);
1602 pci_set_drvdata(pdev, NULL);
1607 pci_disable_device(pdev);
1610 static struct pci_driver sdhci_driver = {
1611 .name = DRIVER_NAME,
1612 .id_table = pci_ids,
1613 .probe = sdhci_probe,
1614 .remove = __devexit_p(sdhci_remove),
1615 .suspend = sdhci_suspend,
1616 .resume = sdhci_resume,
1619 /*****************************************************************************\
1621 * Driver init/exit *
1623 \*****************************************************************************/
1625 static int __init sdhci_drv_init(void)
1627 printk(KERN_INFO DRIVER_NAME
1628 ": Secure Digital Host Controller Interface driver\n");
1629 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1631 return pci_register_driver(&sdhci_driver);
1634 static void __exit sdhci_drv_exit(void)
1638 pci_unregister_driver(&sdhci_driver);
1641 module_init(sdhci_drv_init);
1642 module_exit(sdhci_drv_exit);
1644 module_param(debug_quirks, uint, 0444);
1646 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1647 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1648 MODULE_LICENSE("GPL");
1650 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");