drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/highmem.h>
  14 #include <linux/pci.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/scatterlist.h>
  17
  18 #include <linux/mmc/host.h>
  19
  20 #include "sdhci.h"
  21
  22 #define DRIVER_NAME "sdhci"
  23
  24 #define DBG(f, x...) \
  25         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  26
  27 static unsigned int debug_quirks = 0;
  28
  29 /*
  30  * Different quirks to handle when the hardware deviates from a strict
  31  * interpretation of the SDHCI specification.
  32  */
  33
  34 /* Controller doesn't honor resets unless we touch the clock register */
  35 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  36 /* Controller has bad caps bits, but really supports DMA */
  37 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
  38 /* Controller doesn't like some resets when there is no card inserted. */
  39 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
  40 /* Controller doesn't like clearing the power reg before a change */
  41 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
  42 /* Controller has flaky internal state so reset it on each ios change */
  43 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
  44 /* Controller has an unusable DMA engine */
  45 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
  46
  47 static const struct pci_device_id pci_ids[] __devinitdata = {
  48         {
  49                 .vendor         = PCI_VENDOR_ID_RICOH,
  50                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  51                 .subvendor      = PCI_VENDOR_ID_IBM,
  52                 .subdevice      = PCI_ANY_ID,
  53                 .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  54                                   SDHCI_QUIRK_FORCE_DMA,
  55         },
  56
  57         {
  58                 .vendor         = PCI_VENDOR_ID_RICOH,
  59                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  60                 .subvendor      = PCI_ANY_ID,
  61                 .subdevice      = PCI_ANY_ID,
  62                 .driver_data    = SDHCI_QUIRK_FORCE_DMA |
  63                                   SDHCI_QUIRK_NO_CARD_NO_RESET,
  64         },
  65
  66         {
  67                 .vendor         = PCI_VENDOR_ID_TI,
  68                 .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  69                 .subvendor      = PCI_ANY_ID,
  70                 .subdevice      = PCI_ANY_ID,
  71                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  72         },
  73
  74         {
  75                 .vendor         = PCI_VENDOR_ID_ENE,
  76                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
  77                 .subvendor      = PCI_ANY_ID,
  78                 .subdevice      = PCI_ANY_ID,
  79                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  80                                   SDHCI_QUIRK_BROKEN_DMA,
  81         },
  82
  83         {
  84                 .vendor         = PCI_VENDOR_ID_ENE,
  85                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
  86                 .subvendor      = PCI_ANY_ID,
  87                 .subdevice      = PCI_ANY_ID,
  88                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  89                                   SDHCI_QUIRK_BROKEN_DMA,
  90         },
  91
  92         {
  93                 .vendor         = PCI_VENDOR_ID_ENE,
  94                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
  95                 .subvendor      = PCI_ANY_ID,
  96                 .subdevice      = PCI_ANY_ID,
  97                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  98                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
  99         },
 100
 101         {
 102                 .vendor         = PCI_VENDOR_ID_ENE,
 103                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
 104                 .subvendor      = PCI_ANY_ID,
 105                 .subdevice      = PCI_ANY_ID,
 106                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 107                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
 108         },
 109
 110         {       /* Generic SD host controller */
 111                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
 112         },
 113
 114         { /* end: all zeroes */ },
 115 };
 116
 117 MODULE_DEVICE_TABLE(pci, pci_ids);
 118
 119 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
 120 static void sdhci_finish_data(struct sdhci_host *);
 121
 122 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 123 static void sdhci_finish_command(struct sdhci_host *);
 124
 125 static void sdhci_dumpregs(struct sdhci_host *host)
 126 {
 127         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
 128
 129         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 130                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 131                 readw(host->ioaddr + SDHCI_HOST_VERSION));
 132         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 133                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
 134                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
 135         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 136                 readl(host->ioaddr + SDHCI_ARGUMENT),
 137                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
 138         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 139                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
 140                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
 141         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 142                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
 143                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
 144         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 145                 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
 146                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
 147         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 148                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
 149                 readl(host->ioaddr + SDHCI_INT_STATUS));
 150         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 151                 readl(host->ioaddr + SDHCI_INT_ENABLE),
 152                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
 153         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 154                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
 155                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
 156         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
 157                 readl(host->ioaddr + SDHCI_CAPABILITIES),
 158                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
 159
 160         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 161 }
 162
 163 /*****************************************************************************\
 164  *                                                                           *
 165  * Low level functions                                                       *
 166  *                                                                           *
 167 \*****************************************************************************/
 168
 169 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 170 {
 171         unsigned long timeout;
 172
 173         if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 174                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 175                         SDHCI_CARD_PRESENT))
 176                         return;
 177         }
 178
 179         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
 180
 181         if (mask & SDHCI_RESET_ALL)
 182                 host->clock = 0;
 183
 184         /* Wait max 100 ms */
 185         timeout = 100;
 186
 187         /* hw clears the bit when it's done */
 188         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 189                 if (timeout == 0) {
 190                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 191                                 mmc_hostname(host->mmc), (int)mask);
 192                         sdhci_dumpregs(host);
 193                         return;
 194                 }
 195                 timeout--;
 196                 mdelay(1);
 197         }
 198 }
 199
 200 static void sdhci_init(struct sdhci_host *host)
 201 {
 202         u32 intmask;
 203
 204         sdhci_reset(host, SDHCI_RESET_ALL);
 205
 206         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 207                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 208                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 209                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 210                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 211                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
 212
 213         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 214         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 215 }
 216
 217 static void sdhci_activate_led(struct sdhci_host *host)
 218 {
 219         u8 ctrl;
 220
 221         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 222         ctrl |= SDHCI_CTRL_LED;
 223         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 224 }
 225
 226 static void sdhci_deactivate_led(struct sdhci_host *host)
 227 {
 228         u8 ctrl;
 229
 230         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 231         ctrl &= ~SDHCI_CTRL_LED;
 232         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 233 }
 234
 235 /*****************************************************************************\
 236  *                                                                           *
 237  * Core functions                                                            *
 238  *                                                                           *
 239 \*****************************************************************************/
 240
 241 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 242 {
 243         return sg_virt(host->cur_sg);
 244 }
 245
 246 static inline int sdhci_next_sg(struct sdhci_host* host)
 247 {
 248         /*
 249          * Skip to next SG entry.
 250          */
 251         host->cur_sg++;
 252         host->num_sg--;
 253
 254         /*
 255          * Any entries left?
 256          */
 257         if (host->num_sg > 0) {
 258                 host->offset = 0;
 259                 host->remain = host->cur_sg->length;
 260         }
 261
 262         return host->num_sg;
 263 }
 264
 265 static void sdhci_read_block_pio(struct sdhci_host *host)
 266 {
 267         int blksize, chunk_remain;
 268         u32 data;
 269         char *buffer;
 270         int size;
 271
 272         DBG("PIO reading\n");
 273
 274         blksize = host->data->blksz;
 275         chunk_remain = 0;
 276         data = 0;
 277
 278         buffer = sdhci_sg_to_buffer(host) + host->offset;
 279
 280         while (blksize) {
 281                 if (chunk_remain == 0) {
 282                         data = readl(host->ioaddr + SDHCI_BUFFER);
 283                         chunk_remain = min(blksize, 4);
 284                 }
 285
 286                 size = min(host->remain, chunk_remain);
 287
 288                 chunk_remain -= size;
 289                 blksize -= size;
 290                 host->offset += size;
 291                 host->remain -= size;
 292
 293                 while (size) {
 294                         *buffer = data & 0xFF;
 295                         buffer++;
 296                         data >>= 8;
 297                         size--;
 298                 }
 299
 300                 if (host->remain == 0) {
 301                         if (sdhci_next_sg(host) == 0) {
 302                                 BUG_ON(blksize != 0);
 303                                 return;
 304                         }
 305                         buffer = sdhci_sg_to_buffer(host);
 306                 }
 307         }
 308 }
 309
 310 static void sdhci_write_block_pio(struct sdhci_host *host)
 311 {
 312         int blksize, chunk_remain;
 313         u32 data;
 314         char *buffer;
 315         int bytes, size;
 316
 317         DBG("PIO writing\n");
 318
 319         blksize = host->data->blksz;
 320         chunk_remain = 4;
 321         data = 0;
 322
 323         bytes = 0;
 324         buffer = sdhci_sg_to_buffer(host) + host->offset;
 325
 326         while (blksize) {
 327                 size = min(host->remain, chunk_remain);
 328
 329                 chunk_remain -= size;
 330                 blksize -= size;
 331                 host->offset += size;
 332                 host->remain -= size;
 333
 334                 while (size) {
 335                         data >>= 8;
 336                         data |= (u32)*buffer << 24;
 337                         buffer++;
 338                         size--;
 339                 }
 340
 341                 if (chunk_remain == 0) {
 342                         writel(data, host->ioaddr + SDHCI_BUFFER);
 343                         chunk_remain = min(blksize, 4);
 344                 }
 345
 346                 if (host->remain == 0) {
 347                         if (sdhci_next_sg(host) == 0) {
 348                                 BUG_ON(blksize != 0);
 349                                 return;
 350                         }
 351                         buffer = sdhci_sg_to_buffer(host);
 352                 }
 353         }
 354 }
 355
 356 static void sdhci_transfer_pio(struct sdhci_host *host)
 357 {
 358         u32 mask;
 359
 360         BUG_ON(!host->data);
 361
 362         if (host->num_sg == 0)
 363                 return;
 364
 365         if (host->data->flags & MMC_DATA_READ)
 366                 mask = SDHCI_DATA_AVAILABLE;
 367         else
 368                 mask = SDHCI_SPACE_AVAILABLE;
 369
 370         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 371                 if (host->data->flags & MMC_DATA_READ)
 372                         sdhci_read_block_pio(host);
 373                 else
 374                         sdhci_write_block_pio(host);
 375
 376                 if (host->num_sg == 0)
 377                         break;
 378         }
 379
 380         DBG("PIO transfer complete.\n");
 381 }
 382
 383 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 384 {
 385         u8 count;
 386         unsigned target_timeout, current_timeout;
 387
 388         WARN_ON(host->data);
 389
 390         if (data == NULL)
 391                 return;
 392
 393         /* Sanity checks */
 394         BUG_ON(data->blksz * data->blocks > 524288);
 395         BUG_ON(data->blksz > host->mmc->max_blk_size);
 396         BUG_ON(data->blocks > 65535);
 397
 398         host->data = data;
 399         host->data_early = 0;
 400
 401         /* timeout in us */
 402         target_timeout = data->timeout_ns / 1000 +
 403                 data->timeout_clks / host->clock;
 404
 405         /*
 406          * Figure out needed cycles.
 407          * We do this in steps in order to fit inside a 32 bit int.
 408          * The first step is the minimum timeout, which will have a
 409          * minimum resolution of 6 bits:
 410          * (1) 2^13*1000 > 2^22,
 411          * (2) host->timeout_clk < 2^16
 412          *     =>
 413          *     (1) / (2) > 2^6
 414          */
 415         count = 0;
 416         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 417         while (current_timeout < target_timeout) {
 418                 count++;
 419                 current_timeout <<= 1;
 420                 if (count >= 0xF)
 421                         break;
 422         }
 423
 424         if (count >= 0xF) {
 425                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 426                         mmc_hostname(host->mmc));
 427                 count = 0xE;
 428         }
 429
 430         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 431
 432         if (host->flags & SDHCI_USE_DMA) {
 433                 int count;
 434
 435                 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
 436                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 437                 BUG_ON(count != 1);
 438
 439                 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
 440         } else {
 441                 host->cur_sg = data->sg;
 442                 host->num_sg = data->sg_len;
 443
 444                 host->offset = 0;
 445                 host->remain = host->cur_sg->length;
 446         }
 447
 448         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 449         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 450                 host->ioaddr + SDHCI_BLOCK_SIZE);
 451         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 452 }
 453
 454 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 455         struct mmc_data *data)
 456 {
 457         u16 mode;
 458
 459         if (data == NULL)
 460                 return;
 461
 462         WARN_ON(!host->data);
 463
 464         mode = SDHCI_TRNS_BLK_CNT_EN;
 465         if (data->blocks > 1)
 466                 mode |= SDHCI_TRNS_MULTI;
 467         if (data->flags & MMC_DATA_READ)
 468                 mode |= SDHCI_TRNS_READ;
 469         if (host->flags & SDHCI_USE_DMA)
 470                 mode |= SDHCI_TRNS_DMA;
 471
 472         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 473 }
 474
 475 static void sdhci_finish_data(struct sdhci_host *host)
 476 {
 477         struct mmc_data *data;
 478         u16 blocks;
 479
 480         BUG_ON(!host->data);
 481
 482         data = host->data;
 483         host->data = NULL;
 484
 485         if (host->flags & SDHCI_USE_DMA) {
 486                 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
 487                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 488         }
 489
 490         /*
 491          * Controller doesn't count down when in single block mode.
 492          */
 493         if (data->blocks == 1)
 494                 blocks = (data->error == 0) ? 0 : 1;
 495         else
 496                 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
 497         data->bytes_xfered = data->blksz * (data->blocks - blocks);
 498
 499         if (!data->error && blocks) {
 500                 printk(KERN_ERR "%s: Controller signalled completion even "
 501                         "though there were blocks left.\n",
 502                         mmc_hostname(host->mmc));
 503                 data->error = -EIO;
 504         }
 505
 506         if (data->stop) {
 507                 /*
 508                  * The controller needs a reset of internal state machines
 509                  * upon error conditions.
 510                  */
 511                 if (data->error) {
 512                         sdhci_reset(host, SDHCI_RESET_CMD);
 513                         sdhci_reset(host, SDHCI_RESET_DATA);
 514                 }
 515
 516                 sdhci_send_command(host, data->stop);
 517         } else
 518                 tasklet_schedule(&host->finish_tasklet);
 519 }
 520
 521 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 522 {
 523         int flags;
 524         u32 mask;
 525         unsigned long timeout;
 526
 527         WARN_ON(host->cmd);
 528
 529         /* Wait max 10 ms */
 530         timeout = 10;
 531
 532         mask = SDHCI_CMD_INHIBIT;
 533         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 534                 mask |= SDHCI_DATA_INHIBIT;
 535
 536         /* We shouldn't wait for data inihibit for stop commands, even
 537            though they might use busy signaling */
 538         if (host->mrq->data && (cmd == host->mrq->data->stop))
 539                 mask &= ~SDHCI_DATA_INHIBIT;
 540
 541         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 542                 if (timeout == 0) {
 543                         printk(KERN_ERR "%s: Controller never released "
 544                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 545                         sdhci_dumpregs(host);
 546                         cmd->error = -EIO;
 547                         tasklet_schedule(&host->finish_tasklet);
 548                         return;
 549                 }
 550                 timeout--;
 551                 mdelay(1);
 552         }
 553
 554         mod_timer(&host->timer, jiffies + 10 * HZ);
 555
 556         host->cmd = cmd;
 557
 558         sdhci_prepare_data(host, cmd->data);
 559
 560         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 561
 562         sdhci_set_transfer_mode(host, cmd->data);
 563
 564         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 565                 printk(KERN_ERR "%s: Unsupported response type!\n",
 566                         mmc_hostname(host->mmc));
 567                 cmd->error = -EINVAL;
 568                 tasklet_schedule(&host->finish_tasklet);
 569                 return;
 570         }
 571
 572         if (!(cmd->flags & MMC_RSP_PRESENT))
 573                 flags = SDHCI_CMD_RESP_NONE;
 574         else if (cmd->flags & MMC_RSP_136)
 575                 flags = SDHCI_CMD_RESP_LONG;
 576         else if (cmd->flags & MMC_RSP_BUSY)
 577                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 578         else
 579                 flags = SDHCI_CMD_RESP_SHORT;
 580
 581         if (cmd->flags & MMC_RSP_CRC)
 582                 flags |= SDHCI_CMD_CRC;
 583         if (cmd->flags & MMC_RSP_OPCODE)
 584                 flags |= SDHCI_CMD_INDEX;
 585         if (cmd->data)
 586                 flags |= SDHCI_CMD_DATA;
 587
 588         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 589                 host->ioaddr + SDHCI_COMMAND);
 590 }
 591
 592 static void sdhci_finish_command(struct sdhci_host *host)
 593 {
 594         int i;
 595
 596         BUG_ON(host->cmd == NULL);
 597
 598         if (host->cmd->flags & MMC_RSP_PRESENT) {
 599                 if (host->cmd->flags & MMC_RSP_136) {
 600                         /* CRC is stripped so we need to do some shifting. */
 601                         for (i = 0;i < 4;i++) {
 602                                 host->cmd->resp[i] = readl(host->ioaddr +
 603                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 604                                 if (i != 3)
 605                                         host->cmd->resp[i] |=
 606                                                 readb(host->ioaddr +
 607                                                 SDHCI_RESPONSE + (3-i)*4-1);
 608                         }
 609                 } else {
 610                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 611                 }
 612         }
 613
 614         host->cmd->error = 0;
 615
 616         if (host->data && host->data_early)
 617                 sdhci_finish_data(host);
 618
 619         if (!host->cmd->data)
 620                 tasklet_schedule(&host->finish_tasklet);
 621
 622         host->cmd = NULL;
 623 }
 624
 625 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 626 {
 627         int div;
 628         u16 clk;
 629         unsigned long timeout;
 630
 631         if (clock == host->clock)
 632                 return;
 633
 634         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 635
 636         if (clock == 0)
 637                 goto out;
 638
 639         for (div = 1;div < 256;div *= 2) {
 640                 if ((host->max_clk / div) <= clock)
 641                         break;
 642         }
 643         div >>= 1;
 644
 645         clk = div << SDHCI_DIVIDER_SHIFT;
 646         clk |= SDHCI_CLOCK_INT_EN;
 647         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 648
 649         /* Wait max 10 ms */
 650         timeout = 10;
 651         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 652                 & SDHCI_CLOCK_INT_STABLE)) {
 653                 if (timeout == 0) {
 654                         printk(KERN_ERR "%s: Internal clock never "
 655                                 "stabilised.\n", mmc_hostname(host->mmc));
 656                         sdhci_dumpregs(host);
 657                         return;
 658                 }
 659                 timeout--;
 660                 mdelay(1);
 661         }
 662
 663         clk |= SDHCI_CLOCK_CARD_EN;
 664         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 665
 666 out:
 667         host->clock = clock;
 668 }
 669
 670 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 671 {
 672         u8 pwr;
 673
 674         if (host->power == power)
 675                 return;
 676
 677         if (power == (unsigned short)-1) {
 678                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 679                 goto out;
 680         }
 681
 682         /*
 683          * Spec says that we should clear the power reg before setting
 684          * a new value. Some controllers don't seem to like this though.
 685          */
 686         if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 687                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 688
 689         pwr = SDHCI_POWER_ON;
 690
 691         switch (1 << power) {
 692         case MMC_VDD_165_195:
 693                 pwr |= SDHCI_POWER_180;
 694                 break;
 695         case MMC_VDD_29_30:
 696         case MMC_VDD_30_31:
 697                 pwr |= SDHCI_POWER_300;
 698                 break;
 699         case MMC_VDD_32_33:
 700         case MMC_VDD_33_34:
 701                 pwr |= SDHCI_POWER_330;
 702                 break;
 703         default:
 704                 BUG();
 705         }
 706
 707         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 708
 709 out:
 710         host->power = power;
 711 }
 712
 713 /*****************************************************************************\
 714  *                                                                           *
 715  * MMC callbacks                                                             *
 716  *                                                                           *
 717 \*****************************************************************************/
 718
 719 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 720 {
 721         struct sdhci_host *host;
 722         unsigned long flags;
 723
 724         host = mmc_priv(mmc);
 725
 726         spin_lock_irqsave(&host->lock, flags);
 727
 728         WARN_ON(host->mrq != NULL);
 729
 730         sdhci_activate_led(host);
 731
 732         host->mrq = mrq;
 733
 734         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 735                 host->mrq->cmd->error = -ENOMEDIUM;
 736                 tasklet_schedule(&host->finish_tasklet);
 737         } else
 738                 sdhci_send_command(host, mrq->cmd);
 739
 740         mmiowb();
 741         spin_unlock_irqrestore(&host->lock, flags);
 742 }
 743
 744 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 745 {
 746         struct sdhci_host *host;
 747         unsigned long flags;
 748         u8 ctrl;
 749
 750         host = mmc_priv(mmc);
 751
 752         spin_lock_irqsave(&host->lock, flags);
 753
 754         /*
 755          * Reset the chip on each power off.
 756          * Should clear out any weird states.
 757          */
 758         if (ios->power_mode == MMC_POWER_OFF) {
 759                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 760                 sdhci_init(host);
 761         }
 762
 763         sdhci_set_clock(host, ios->clock);
 764
 765         if (ios->power_mode == MMC_POWER_OFF)
 766                 sdhci_set_power(host, -1);
 767         else
 768                 sdhci_set_power(host, ios->vdd);
 769
 770         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 771
 772         if (ios->bus_width == MMC_BUS_WIDTH_4)
 773                 ctrl |= SDHCI_CTRL_4BITBUS;
 774         else
 775                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 776
 777         if (ios->timing == MMC_TIMING_SD_HS)
 778                 ctrl |= SDHCI_CTRL_HISPD;
 779         else
 780                 ctrl &= ~SDHCI_CTRL_HISPD;
 781
 782         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 783
 784         /*
 785          * Some (ENE) controllers go apeshit on some ios operation,
 786          * signalling timeout and CRC errors even on CMD0. Resetting
 787          * it on each ios seems to solve the problem.
 788          */
 789         if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
 790                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 791
 792         mmiowb();
 793         spin_unlock_irqrestore(&host->lock, flags);
 794 }
 795
 796 static int sdhci_get_ro(struct mmc_host *mmc)
 797 {
 798         struct sdhci_host *host;
 799         unsigned long flags;
 800         int present;
 801
 802         host = mmc_priv(mmc);
 803
 804         spin_lock_irqsave(&host->lock, flags);
 805
 806         present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 807
 808         spin_unlock_irqrestore(&host->lock, flags);
 809
 810         return !(present & SDHCI_WRITE_PROTECT);
 811 }
 812
 813 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 814 {
 815         struct sdhci_host *host;
 816         unsigned long flags;
 817         u32 ier;
 818
 819         host = mmc_priv(mmc);
 820
 821         spin_lock_irqsave(&host->lock, flags);
 822
 823         ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
 824
 825         ier &= ~SDHCI_INT_CARD_INT;
 826         if (enable)
 827                 ier |= SDHCI_INT_CARD_INT;
 828
 829         writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
 830         writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 831
 832         mmiowb();
 833
 834         spin_unlock_irqrestore(&host->lock, flags);
 835 }
 836
 837 static const struct mmc_host_ops sdhci_ops = {
 838         .request        = sdhci_request,
 839         .set_ios        = sdhci_set_ios,
 840         .get_ro         = sdhci_get_ro,
 841         .enable_sdio_irq = sdhci_enable_sdio_irq,
 842 };
 843
 844 /*****************************************************************************\
 845  *                                                                           *
 846  * Tasklets                                                                  *
 847  *                                                                           *
 848 \*****************************************************************************/
 849
 850 static void sdhci_tasklet_card(unsigned long param)
 851 {
 852         struct sdhci_host *host;
 853         unsigned long flags;
 854
 855         host = (struct sdhci_host*)param;
 856
 857         spin_lock_irqsave(&host->lock, flags);
 858
 859         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 860                 if (host->mrq) {
 861                         printk(KERN_ERR "%s: Card removed during transfer!\n",
 862                                 mmc_hostname(host->mmc));
 863                         printk(KERN_ERR "%s: Resetting controller.\n",
 864                                 mmc_hostname(host->mmc));
 865
 866                         sdhci_reset(host, SDHCI_RESET_CMD);
 867                         sdhci_reset(host, SDHCI_RESET_DATA);
 868
 869                         host->mrq->cmd->error = -ENOMEDIUM;
 870                         tasklet_schedule(&host->finish_tasklet);
 871                 }
 872         }
 873
 874         spin_unlock_irqrestore(&host->lock, flags);
 875
 876         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 877 }
 878
 879 static void sdhci_tasklet_finish(unsigned long param)
 880 {
 881         struct sdhci_host *host;
 882         unsigned long flags;
 883         struct mmc_request *mrq;
 884
 885         host = (struct sdhci_host*)param;
 886
 887         spin_lock_irqsave(&host->lock, flags);
 888
 889         del_timer(&host->timer);
 890
 891         mrq = host->mrq;
 892
 893         /*
 894          * The controller needs a reset of internal state machines
 895          * upon error conditions.
 896          */
 897         if (mrq->cmd->error ||
 898                 (mrq->data && (mrq->data->error ||
 899                 (mrq->data->stop && mrq->data->stop->error)))) {
 900
 901                 /* Some controllers need this kick or reset won't work here */
 902                 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
 903                         unsigned int clock;
 904
 905                         /* This is to force an update */
 906                         clock = host->clock;
 907                         host->clock = 0;
 908                         sdhci_set_clock(host, clock);
 909                 }
 910
 911                 /* Spec says we should do both at the same time, but Ricoh
 912                    controllers do not like that. */
 913                 sdhci_reset(host, SDHCI_RESET_CMD);
 914                 sdhci_reset(host, SDHCI_RESET_DATA);
 915         }
 916
 917         host->mrq = NULL;
 918         host->cmd = NULL;
 919         host->data = NULL;
 920
 921         sdhci_deactivate_led(host);
 922
 923         mmiowb();
 924         spin_unlock_irqrestore(&host->lock, flags);
 925
 926         mmc_request_done(host->mmc, mrq);
 927 }
 928
 929 static void sdhci_timeout_timer(unsigned long data)
 930 {
 931         struct sdhci_host *host;
 932         unsigned long flags;
 933
 934         host = (struct sdhci_host*)data;
 935
 936         spin_lock_irqsave(&host->lock, flags);
 937
 938         if (host->mrq) {
 939                 printk(KERN_ERR "%s: Timeout waiting for hardware "
 940                         "interrupt.\n", mmc_hostname(host->mmc));
 941                 sdhci_dumpregs(host);
 942
 943                 if (host->data) {
 944                         host->data->error = -ETIMEDOUT;
 945                         sdhci_finish_data(host);
 946                 } else {
 947                         if (host->cmd)
 948                                 host->cmd->error = -ETIMEDOUT;
 949                         else
 950                                 host->mrq->cmd->error = -ETIMEDOUT;
 951
 952                         tasklet_schedule(&host->finish_tasklet);
 953                 }
 954         }
 955
 956         mmiowb();
 957         spin_unlock_irqrestore(&host->lock, flags);
 958 }
 959
 960 /*****************************************************************************\
 961  *                                                                           *
 962  * Interrupt handling                                                        *
 963  *                                                                           *
 964 \*****************************************************************************/
 965
 966 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
 967 {
 968         BUG_ON(intmask == 0);
 969
 970         if (!host->cmd) {
 971                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
 972                         "though no command operation was in progress.\n",
 973                         mmc_hostname(host->mmc), (unsigned)intmask);
 974                 sdhci_dumpregs(host);
 975                 return;
 976         }
 977
 978         if (intmask & SDHCI_INT_TIMEOUT)
 979                 host->cmd->error = -ETIMEDOUT;
 980         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
 981                         SDHCI_INT_INDEX))
 982                 host->cmd->error = -EILSEQ;
 983
 984         if (host->cmd->error)
 985                 tasklet_schedule(&host->finish_tasklet);
 986         else if (intmask & SDHCI_INT_RESPONSE)
 987                 sdhci_finish_command(host);
 988 }
 989
 990 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 991 {
 992         BUG_ON(intmask == 0);
 993
 994         if (!host->data) {
 995                 /*
 996                  * A data end interrupt is sent together with the response
 997                  * for the stop command.
 998                  */
 999                 if (intmask & SDHCI_INT_DATA_END)
1000                         return;
1001
1002                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1003                         "though no data operation was in progress.\n",
1004                         mmc_hostname(host->mmc), (unsigned)intmask);
1005                 sdhci_dumpregs(host);
1006
1007                 return;
1008         }
1009
1010         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1011                 host->data->error = -ETIMEDOUT;
1012         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1013                 host->data->error = -EILSEQ;
1014
1015         if (host->data->error)
1016                 sdhci_finish_data(host);
1017         else {
1018                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1019                         sdhci_transfer_pio(host);
1020
1021                 /*
1022                  * We currently don't do anything fancy with DMA
1023                  * boundaries, but as we can't disable the feature
1024                  * we need to at least restart the transfer.
1025                  */
1026                 if (intmask & SDHCI_INT_DMA_END)
1027                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1028                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1029
1030                 if (intmask & SDHCI_INT_DATA_END) {
1031                         if (host->cmd) {
1032                                 /*
1033                                  * Data managed to finish before the
1034                                  * command completed. Make sure we do
1035                                  * things in the proper order.
1036                                  */
1037                                 host->data_early = 1;
1038                         } else {
1039                                 sdhci_finish_data(host);
1040                         }
1041                 }
1042         }
1043 }
1044
1045 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1046 {
1047         irqreturn_t result;
1048         struct sdhci_host* host = dev_id;
1049         u32 intmask;
1050         int cardint = 0;
1051
1052         spin_lock(&host->lock);
1053
1054         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1055
1056         if (!intmask || intmask == 0xffffffff) {
1057                 result = IRQ_NONE;
1058                 goto out;
1059         }
1060
1061         DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1062
1063         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1064                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1065                         host->ioaddr + SDHCI_INT_STATUS);
1066                 tasklet_schedule(&host->card_tasklet);
1067         }
1068
1069         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1070
1071         if (intmask & SDHCI_INT_CMD_MASK) {
1072                 writel(intmask & SDHCI_INT_CMD_MASK,
1073                         host->ioaddr + SDHCI_INT_STATUS);
1074                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1075         }
1076
1077         if (intmask & SDHCI_INT_DATA_MASK) {
1078                 writel(intmask & SDHCI_INT_DATA_MASK,
1079                         host->ioaddr + SDHCI_INT_STATUS);
1080                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1081         }
1082
1083         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1084
1085         intmask &= ~SDHCI_INT_ERROR;
1086
1087         if (intmask & SDHCI_INT_BUS_POWER) {
1088                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1089                         mmc_hostname(host->mmc));
1090                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1091         }
1092
1093         intmask &= ~SDHCI_INT_BUS_POWER;
1094
1095         if (intmask & SDHCI_INT_CARD_INT)
1096                 cardint = 1;
1097
1098         intmask &= ~SDHCI_INT_CARD_INT;
1099
1100         if (intmask) {
1101                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1102                         mmc_hostname(host->mmc), intmask);
1103                 sdhci_dumpregs(host);
1104
1105                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1106         }
1107
1108         result = IRQ_HANDLED;
1109
1110         mmiowb();
1111 out:
1112         spin_unlock(&host->lock);
1113
1114         /*
1115          * We have to delay this as it calls back into the driver.
1116          */
1117         if (cardint)
1118                 mmc_signal_sdio_irq(host->mmc);
1119
1120         return result;
1121 }
1122
1123 /*****************************************************************************\
1124  *                                                                           *
1125  * Suspend/resume                                                            *
1126  *                                                                           *
1127 \*****************************************************************************/
1128
1129 #ifdef CONFIG_PM
1130
1131 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1132 {
1133         struct sdhci_chip *chip;
1134         int i, ret;
1135
1136         chip = pci_get_drvdata(pdev);
1137         if (!chip)
1138                 return 0;
1139
1140         DBG("Suspending...\n");
1141
1142         for (i = 0;i < chip->num_slots;i++) {
1143                 if (!chip->hosts[i])
1144                         continue;
1145                 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1146                 if (ret) {
1147                         for (i--;i >= 0;i--)
1148                                 mmc_resume_host(chip->hosts[i]->mmc);
1149                         return ret;
1150                 }
1151         }
1152
1153         pci_save_state(pdev);
1154         pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1155
1156         for (i = 0;i < chip->num_slots;i++) {
1157                 if (!chip->hosts[i])
1158                         continue;
1159                 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1160         }
1161
1162         pci_disable_device(pdev);
1163         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1164
1165         return 0;
1166 }
1167
1168 static int sdhci_resume (struct pci_dev *pdev)
1169 {
1170         struct sdhci_chip *chip;
1171         int i, ret;
1172
1173         chip = pci_get_drvdata(pdev);
1174         if (!chip)
1175                 return 0;
1176
1177         DBG("Resuming...\n");
1178
1179         pci_set_power_state(pdev, PCI_D0);
1180         pci_restore_state(pdev);
1181         ret = pci_enable_device(pdev);
1182         if (ret)
1183                 return ret;
1184
1185         for (i = 0;i < chip->num_slots;i++) {
1186                 if (!chip->hosts[i])
1187                         continue;
1188                 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1189                         pci_set_master(pdev);
1190                 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1191                         IRQF_SHARED, chip->hosts[i]->slot_descr,
1192                         chip->hosts[i]);
1193                 if (ret)
1194                         return ret;
1195                 sdhci_init(chip->hosts[i]);
1196                 mmiowb();
1197                 ret = mmc_resume_host(chip->hosts[i]->mmc);
1198                 if (ret)
1199                         return ret;
1200         }
1201
1202         return 0;
1203 }
1204
1205 #else /* CONFIG_PM */
1206
1207 #define sdhci_suspend NULL
1208 #define sdhci_resume NULL
1209
1210 #endif /* CONFIG_PM */
1211
1212 /*****************************************************************************\
1213  *                                                                           *
1214  * Device probing/removal                                                    *
1215  *                                                                           *
1216 \*****************************************************************************/
1217
1218 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1219 {
1220         int ret;
1221         unsigned int version;
1222         struct sdhci_chip *chip;
1223         struct mmc_host *mmc;
1224         struct sdhci_host *host;
1225
1226         u8 first_bar;
1227         unsigned int caps;
1228
1229         chip = pci_get_drvdata(pdev);
1230         BUG_ON(!chip);
1231
1232         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1233         if (ret)
1234                 return ret;
1235
1236         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1237
1238         if (first_bar > 5) {
1239                 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1240                 return -ENODEV;
1241         }
1242
1243         if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1244                 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1245                 return -ENODEV;
1246         }
1247
1248         if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1249                 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1250                         "You may experience problems.\n");
1251         }
1252
1253         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1254                 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1255                 return -ENODEV;
1256         }
1257
1258         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1259                 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1260                 return -ENODEV;
1261         }
1262
1263         mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1264         if (!mmc)
1265                 return -ENOMEM;
1266
1267         host = mmc_priv(mmc);
1268         host->mmc = mmc;
1269
1270         host->chip = chip;
1271         chip->hosts[slot] = host;
1272
1273         host->bar = first_bar + slot;
1274
1275         host->addr = pci_resource_start(pdev, host->bar);
1276         host->irq = pdev->irq;
1277
1278         DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1279
1280         snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1281
1282         ret = pci_request_region(pdev, host->bar, host->slot_descr);
1283         if (ret)
1284                 goto free;
1285
1286         host->ioaddr = ioremap_nocache(host->addr,
1287                 pci_resource_len(pdev, host->bar));
1288         if (!host->ioaddr) {
1289                 ret = -ENOMEM;
1290                 goto release;
1291         }
1292
1293         sdhci_reset(host, SDHCI_RESET_ALL);
1294
1295         version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1296         version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1297         if (version > 1) {
1298                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1299                         "You may experience problems.\n", host->slot_descr,
1300                         version);
1301         }
1302
1303         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1304
1305         if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1306                 host->flags |= SDHCI_USE_DMA;
1307         else if (!(caps & SDHCI_CAN_DO_DMA))
1308                 DBG("Controller doesn't have DMA capability\n");
1309         else
1310                 host->flags |= SDHCI_USE_DMA;
1311
1312         if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1313                 (host->flags & SDHCI_USE_DMA)) {
1314                 DBG("Disabling DMA as it is marked broken\n");
1315                 host->flags &= ~SDHCI_USE_DMA;
1316         }
1317
1318         if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1319                 (host->flags & SDHCI_USE_DMA)) {
1320                 printk(KERN_WARNING "%s: Will use DMA "
1321                         "mode even though HW doesn't fully "
1322                         "claim to support it.\n", host->slot_descr);
1323         }
1324
1325         if (host->flags & SDHCI_USE_DMA) {
1326                 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1327                         printk(KERN_WARNING "%s: No suitable DMA available. "
1328                                 "Falling back to PIO.\n", host->slot_descr);
1329                         host->flags &= ~SDHCI_USE_DMA;
1330                 }
1331         }
1332
1333         if (host->flags & SDHCI_USE_DMA)
1334                 pci_set_master(pdev);
1335         else /* XXX: Hack to get MMC layer to avoid highmem */
1336                 pdev->dma_mask = 0;
1337
1338         host->max_clk =
1339                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1340         if (host->max_clk == 0) {
1341                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1342                         "frequency.\n", host->slot_descr);
1343                 ret = -ENODEV;
1344                 goto unmap;
1345         }
1346         host->max_clk *= 1000000;
1347
1348         host->timeout_clk =
1349                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1350         if (host->timeout_clk == 0) {
1351                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1352                         "frequency.\n", host->slot_descr);
1353                 ret = -ENODEV;
1354                 goto unmap;
1355         }
1356         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1357                 host->timeout_clk *= 1000;
1358
1359         /*
1360          * Set host parameters.
1361          */
1362         mmc->ops = &sdhci_ops;
1363         mmc->f_min = host->max_clk / 256;
1364         mmc->f_max = host->max_clk;
1365         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1366
1367         if (caps & SDHCI_CAN_DO_HISPD)
1368                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1369
1370         mmc->ocr_avail = 0;
1371         if (caps & SDHCI_CAN_VDD_330)
1372                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1373         if (caps & SDHCI_CAN_VDD_300)
1374                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1375         if (caps & SDHCI_CAN_VDD_180)
1376                 mmc->ocr_avail |= MMC_VDD_165_195;
1377
1378         if (mmc->ocr_avail == 0) {
1379                 printk(KERN_ERR "%s: Hardware doesn't report any "
1380                         "support voltages.\n", host->slot_descr);
1381                 ret = -ENODEV;
1382                 goto unmap;
1383         }
1384
1385         spin_lock_init(&host->lock);
1386
1387         /*
1388          * Maximum number of segments. Hardware cannot do scatter lists.
1389          */
1390         if (host->flags & SDHCI_USE_DMA)
1391                 mmc->max_hw_segs = 1;
1392         else
1393                 mmc->max_hw_segs = 16;
1394         mmc->max_phys_segs = 16;
1395
1396         /*
1397          * Maximum number of sectors in one transfer. Limited by DMA boundary
1398          * size (512KiB).
1399          */
1400         mmc->max_req_size = 524288;
1401
1402         /*
1403          * Maximum segment size. Could be one segment with the maximum number
1404          * of bytes.
1405          */
1406         mmc->max_seg_size = mmc->max_req_size;
1407
1408         /*
1409          * Maximum block size. This varies from controller to controller and
1410          * is specified in the capabilities register.
1411          */
1412         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1413         if (mmc->max_blk_size >= 3) {
1414                 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1415                         host->slot_descr);
1416                 mmc->max_blk_size = 512;
1417         } else
1418                 mmc->max_blk_size = 512 << mmc->max_blk_size;
1419
1420         /*
1421          * Maximum block count.
1422          */
1423         mmc->max_blk_count = 65535;
1424
1425         /*
1426          * Init tasklets.
1427          */
1428         tasklet_init(&host->card_tasklet,
1429                 sdhci_tasklet_card, (unsigned long)host);
1430         tasklet_init(&host->finish_tasklet,
1431                 sdhci_tasklet_finish, (unsigned long)host);
1432
1433         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1434
1435         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1436                 host->slot_descr, host);
1437         if (ret)
1438                 goto untasklet;
1439
1440         sdhci_init(host);
1441
1442 #ifdef CONFIG_MMC_DEBUG
1443         sdhci_dumpregs(host);
1444 #endif
1445
1446         mmiowb();
1447
1448         mmc_add_host(mmc);
1449
1450         printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1451                 host->addr, host->irq,
1452                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1453
1454         return 0;
1455
1456 untasklet:
1457         tasklet_kill(&host->card_tasklet);
1458         tasklet_kill(&host->finish_tasklet);
1459 unmap:
1460         iounmap(host->ioaddr);
1461 release:
1462         pci_release_region(pdev, host->bar);
1463 free:
1464         mmc_free_host(mmc);
1465
1466         return ret;
1467 }
1468
1469 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1470 {
1471         struct sdhci_chip *chip;
1472         struct mmc_host *mmc;
1473         struct sdhci_host *host;
1474
1475         chip = pci_get_drvdata(pdev);
1476         host = chip->hosts[slot];
1477         mmc = host->mmc;
1478
1479         chip->hosts[slot] = NULL;
1480
1481         mmc_remove_host(mmc);
1482
1483         sdhci_reset(host, SDHCI_RESET_ALL);
1484
1485         free_irq(host->irq, host);
1486
1487         del_timer_sync(&host->timer);
1488
1489         tasklet_kill(&host->card_tasklet);
1490         tasklet_kill(&host->finish_tasklet);
1491
1492         iounmap(host->ioaddr);
1493
1494         pci_release_region(pdev, host->bar);
1495
1496         mmc_free_host(mmc);
1497 }
1498
1499 static int __devinit sdhci_probe(struct pci_dev *pdev,
1500         const struct pci_device_id *ent)
1501 {
1502         int ret, i;
1503         u8 slots, rev;
1504         struct sdhci_chip *chip;
1505
1506         BUG_ON(pdev == NULL);
1507         BUG_ON(ent == NULL);
1508
1509         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1510
1511         printk(KERN_INFO DRIVER_NAME
1512                 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1513                 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1514                 (int)rev);
1515
1516         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1517         if (ret)
1518                 return ret;
1519
1520         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1521         DBG("found %d slot(s)\n", slots);
1522         if (slots == 0)
1523                 return -ENODEV;
1524
1525         ret = pci_enable_device(pdev);
1526         if (ret)
1527                 return ret;
1528
1529         chip = kzalloc(sizeof(struct sdhci_chip) +
1530                 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1531         if (!chip) {
1532                 ret = -ENOMEM;
1533                 goto err;
1534         }
1535
1536         chip->pdev = pdev;
1537         chip->quirks = ent->driver_data;
1538
1539         if (debug_quirks)
1540                 chip->quirks = debug_quirks;
1541
1542         chip->num_slots = slots;
1543         pci_set_drvdata(pdev, chip);
1544
1545         for (i = 0;i < slots;i++) {
1546                 ret = sdhci_probe_slot(pdev, i);
1547                 if (ret) {
1548                         for (i--;i >= 0;i--)
1549                                 sdhci_remove_slot(pdev, i);
1550                         goto free;
1551                 }
1552         }
1553
1554         return 0;
1555
1556 free:
1557         pci_set_drvdata(pdev, NULL);
1558         kfree(chip);
1559
1560 err:
1561         pci_disable_device(pdev);
1562         return ret;
1563 }
1564
1565 static void __devexit sdhci_remove(struct pci_dev *pdev)
1566 {
1567         int i;
1568         struct sdhci_chip *chip;
1569
1570         chip = pci_get_drvdata(pdev);
1571
1572         if (chip) {
1573                 for (i = 0;i < chip->num_slots;i++)
1574                         sdhci_remove_slot(pdev, i);
1575
1576                 pci_set_drvdata(pdev, NULL);
1577
1578                 kfree(chip);
1579         }
1580
1581         pci_disable_device(pdev);
1582 }
1583
1584 static struct pci_driver sdhci_driver = {
1585         .name =         DRIVER_NAME,
1586         .id_table =     pci_ids,
1587         .probe =        sdhci_probe,
1588         .remove =       __devexit_p(sdhci_remove),
1589         .suspend =      sdhci_suspend,
1590         .resume =       sdhci_resume,
1591 };
1592
1593 /*****************************************************************************\
1594  *                                                                           *
1595  * Driver init/exit                                                          *
1596  *                                                                           *
1597 \*****************************************************************************/
1598
1599 static int __init sdhci_drv_init(void)
1600 {
1601         printk(KERN_INFO DRIVER_NAME
1602                 ": Secure Digital Host Controller Interface driver\n");
1603         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1604
1605         return pci_register_driver(&sdhci_driver);
1606 }
1607
1608 static void __exit sdhci_drv_exit(void)
1609 {
1610         DBG("Exiting\n");
1611
1612         pci_unregister_driver(&sdhci_driver);
1613 }
1614
1615 module_init(sdhci_drv_init);
1616 module_exit(sdhci_drv_exit);
1617
1618 module_param(debug_quirks, uint, 0444);
1619
1620 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1621 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1622 MODULE_LICENSE("GPL");
1623
1624 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");