2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
22 #include <linux/leds.h>
24 #include <linux/mmc/host.h>
28 #define DRIVER_NAME "sdhci"
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35 #define SDHCI_USE_LEDS_CLASS
38 static unsigned int debug_quirks = 0;
40 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
41 static void sdhci_finish_data(struct sdhci_host *);
43 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
44 static void sdhci_finish_command(struct sdhci_host *);
46 static void sdhci_dumpregs(struct sdhci_host *host)
48 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
50 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
51 sdhci_readl(host, SDHCI_DMA_ADDRESS),
52 sdhci_readw(host, SDHCI_HOST_VERSION));
53 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
54 sdhci_readw(host, SDHCI_BLOCK_SIZE),
55 sdhci_readw(host, SDHCI_BLOCK_COUNT));
56 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
57 sdhci_readl(host, SDHCI_ARGUMENT),
58 sdhci_readw(host, SDHCI_TRANSFER_MODE));
59 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
60 sdhci_readl(host, SDHCI_PRESENT_STATE),
61 sdhci_readb(host, SDHCI_HOST_CONTROL));
62 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
63 sdhci_readb(host, SDHCI_POWER_CONTROL),
64 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
65 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
66 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
67 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
68 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
69 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
70 sdhci_readl(host, SDHCI_INT_STATUS));
71 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
72 sdhci_readl(host, SDHCI_INT_ENABLE),
73 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
74 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
75 sdhci_readw(host, SDHCI_ACMD12_ERR),
76 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
77 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT));
81 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
84 /*****************************************************************************\
86 * Low level functions *
88 \*****************************************************************************/
90 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
94 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
97 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
98 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
101 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
103 sdhci_clear_set_irqs(host, 0, irqs);
106 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
108 sdhci_clear_set_irqs(host, irqs, 0);
111 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
113 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
116 sdhci_unmask_irqs(host, irqs);
118 sdhci_mask_irqs(host, irqs);
121 static void sdhci_enable_card_detection(struct sdhci_host *host)
123 sdhci_set_card_detection(host, true);
126 static void sdhci_disable_card_detection(struct sdhci_host *host)
128 sdhci_set_card_detection(host, false);
131 static void sdhci_reset(struct sdhci_host *host, u8 mask)
133 unsigned long timeout;
135 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
136 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
141 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
143 if (mask & SDHCI_RESET_ALL)
146 /* Wait max 100 ms */
149 /* hw clears the bit when it's done */
150 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
152 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
153 mmc_hostname(host->mmc), (int)mask);
154 sdhci_dumpregs(host);
162 static void sdhci_init(struct sdhci_host *host)
164 sdhci_reset(host, SDHCI_RESET_ALL);
166 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
167 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
168 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
169 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
170 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
173 static void sdhci_reinit(struct sdhci_host *host)
176 sdhci_enable_card_detection(host);
179 static void sdhci_activate_led(struct sdhci_host *host)
183 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
184 ctrl |= SDHCI_CTRL_LED;
185 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
188 static void sdhci_deactivate_led(struct sdhci_host *host)
192 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
193 ctrl &= ~SDHCI_CTRL_LED;
194 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
197 #ifdef SDHCI_USE_LEDS_CLASS
198 static void sdhci_led_control(struct led_classdev *led,
199 enum led_brightness brightness)
201 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
204 spin_lock_irqsave(&host->lock, flags);
206 if (brightness == LED_OFF)
207 sdhci_deactivate_led(host);
209 sdhci_activate_led(host);
211 spin_unlock_irqrestore(&host->lock, flags);
215 /*****************************************************************************\
219 \*****************************************************************************/
221 static void sdhci_read_block_pio(struct sdhci_host *host)
224 size_t blksize, len, chunk;
225 u32 uninitialized_var(scratch);
228 DBG("PIO reading\n");
230 blksize = host->data->blksz;
233 local_irq_save(flags);
236 if (!sg_miter_next(&host->sg_miter))
239 len = min(host->sg_miter.length, blksize);
242 host->sg_miter.consumed = len;
244 buf = host->sg_miter.addr;
248 scratch = sdhci_readl(host, SDHCI_BUFFER);
252 *buf = scratch & 0xFF;
261 sg_miter_stop(&host->sg_miter);
263 local_irq_restore(flags);
266 static void sdhci_write_block_pio(struct sdhci_host *host)
269 size_t blksize, len, chunk;
273 DBG("PIO writing\n");
275 blksize = host->data->blksz;
279 local_irq_save(flags);
282 if (!sg_miter_next(&host->sg_miter))
285 len = min(host->sg_miter.length, blksize);
288 host->sg_miter.consumed = len;
290 buf = host->sg_miter.addr;
293 scratch |= (u32)*buf << (chunk * 8);
299 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
300 sdhci_writel(host, scratch, SDHCI_BUFFER);
307 sg_miter_stop(&host->sg_miter);
309 local_irq_restore(flags);
312 static void sdhci_transfer_pio(struct sdhci_host *host)
318 if (host->blocks == 0)
321 if (host->data->flags & MMC_DATA_READ)
322 mask = SDHCI_DATA_AVAILABLE;
324 mask = SDHCI_SPACE_AVAILABLE;
327 * Some controllers (JMicron JMB38x) mess up the buffer bits
328 * for transfers < 4 bytes. As long as it is just one block,
329 * we can ignore the bits.
331 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
332 (host->data->blocks == 1))
335 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
336 if (host->data->flags & MMC_DATA_READ)
337 sdhci_read_block_pio(host);
339 sdhci_write_block_pio(host);
342 if (host->blocks == 0)
346 DBG("PIO transfer complete.\n");
349 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
351 local_irq_save(*flags);
352 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
355 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
357 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
358 local_irq_restore(*flags);
361 static int sdhci_adma_table_pre(struct sdhci_host *host,
362 struct mmc_data *data)
369 dma_addr_t align_addr;
372 struct scatterlist *sg;
378 * The spec does not specify endianness of descriptor table.
379 * We currently guess that it is LE.
382 if (data->flags & MMC_DATA_READ)
383 direction = DMA_FROM_DEVICE;
385 direction = DMA_TO_DEVICE;
388 * The ADMA descriptor table is mapped further down as we
389 * need to fill it with data first.
392 host->align_addr = dma_map_single(mmc_dev(host->mmc),
393 host->align_buffer, 128 * 4, direction);
394 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
396 BUG_ON(host->align_addr & 0x3);
398 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
399 data->sg, data->sg_len, direction);
400 if (host->sg_count == 0)
403 desc = host->adma_desc;
404 align = host->align_buffer;
406 align_addr = host->align_addr;
408 for_each_sg(data->sg, sg, host->sg_count, i) {
409 addr = sg_dma_address(sg);
410 len = sg_dma_len(sg);
413 * The SDHCI specification states that ADMA
414 * addresses must be 32-bit aligned. If they
415 * aren't, then we use a bounce buffer for
416 * the (up to three) bytes that screw up the
419 offset = (4 - (addr & 0x3)) & 0x3;
421 if (data->flags & MMC_DATA_WRITE) {
422 buffer = sdhci_kmap_atomic(sg, &flags);
423 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
424 memcpy(align, buffer, offset);
425 sdhci_kunmap_atomic(buffer, &flags);
428 desc[7] = (align_addr >> 24) & 0xff;
429 desc[6] = (align_addr >> 16) & 0xff;
430 desc[5] = (align_addr >> 8) & 0xff;
431 desc[4] = (align_addr >> 0) & 0xff;
433 BUG_ON(offset > 65536);
435 desc[3] = (offset >> 8) & 0xff;
436 desc[2] = (offset >> 0) & 0xff;
439 desc[0] = 0x21; /* tran, valid */
450 desc[7] = (addr >> 24) & 0xff;
451 desc[6] = (addr >> 16) & 0xff;
452 desc[5] = (addr >> 8) & 0xff;
453 desc[4] = (addr >> 0) & 0xff;
457 desc[3] = (len >> 8) & 0xff;
458 desc[2] = (len >> 0) & 0xff;
461 desc[0] = 0x21; /* tran, valid */
466 * If this triggers then we have a calculation bug
469 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
473 * Add a terminating entry.
484 desc[0] = 0x03; /* nop, end, valid */
487 * Resync align buffer as we might have changed it.
489 if (data->flags & MMC_DATA_WRITE) {
490 dma_sync_single_for_device(mmc_dev(host->mmc),
491 host->align_addr, 128 * 4, direction);
494 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
495 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
496 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
498 BUG_ON(host->adma_addr & 0x3);
503 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
504 data->sg_len, direction);
506 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
512 static void sdhci_adma_table_post(struct sdhci_host *host,
513 struct mmc_data *data)
517 struct scatterlist *sg;
523 if (data->flags & MMC_DATA_READ)
524 direction = DMA_FROM_DEVICE;
526 direction = DMA_TO_DEVICE;
528 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
529 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
531 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
534 if (data->flags & MMC_DATA_READ) {
535 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
536 data->sg_len, direction);
538 align = host->align_buffer;
540 for_each_sg(data->sg, sg, host->sg_count, i) {
541 if (sg_dma_address(sg) & 0x3) {
542 size = 4 - (sg_dma_address(sg) & 0x3);
544 buffer = sdhci_kmap_atomic(sg, &flags);
545 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
546 memcpy(buffer, align, size);
547 sdhci_kunmap_atomic(buffer, &flags);
554 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
555 data->sg_len, direction);
558 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
561 unsigned target_timeout, current_timeout;
564 * If the host controller provides us with an incorrect timeout
565 * value, just skip the check and use 0xE. The hardware may take
566 * longer to time out, but that's much better than having a too-short
569 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
573 target_timeout = data->timeout_ns / 1000 +
574 data->timeout_clks / host->clock;
577 * Figure out needed cycles.
578 * We do this in steps in order to fit inside a 32 bit int.
579 * The first step is the minimum timeout, which will have a
580 * minimum resolution of 6 bits:
581 * (1) 2^13*1000 > 2^22,
582 * (2) host->timeout_clk < 2^16
587 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
588 while (current_timeout < target_timeout) {
590 current_timeout <<= 1;
596 printk(KERN_WARNING "%s: Too large timeout requested!\n",
597 mmc_hostname(host->mmc));
604 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
606 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
607 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
609 if (host->flags & SDHCI_REQ_USE_DMA)
610 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
612 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
615 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
627 BUG_ON(data->blksz * data->blocks > 524288);
628 BUG_ON(data->blksz > host->mmc->max_blk_size);
629 BUG_ON(data->blocks > 65535);
632 host->data_early = 0;
634 count = sdhci_calc_timeout(host, data);
635 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
637 if (host->flags & SDHCI_USE_DMA)
638 host->flags |= SDHCI_REQ_USE_DMA;
641 * FIXME: This doesn't account for merging when mapping the
644 if (host->flags & SDHCI_REQ_USE_DMA) {
646 struct scatterlist *sg;
649 if (host->flags & SDHCI_USE_ADMA) {
650 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
653 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
657 if (unlikely(broken)) {
658 for_each_sg(data->sg, sg, data->sg_len, i) {
659 if (sg->length & 0x3) {
660 DBG("Reverting to PIO because of "
661 "transfer size (%d)\n",
663 host->flags &= ~SDHCI_REQ_USE_DMA;
671 * The assumption here being that alignment is the same after
672 * translation to device address space.
674 if (host->flags & SDHCI_REQ_USE_DMA) {
676 struct scatterlist *sg;
679 if (host->flags & SDHCI_USE_ADMA) {
681 * As we use 3 byte chunks to work around
682 * alignment problems, we need to check this
685 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
688 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
692 if (unlikely(broken)) {
693 for_each_sg(data->sg, sg, data->sg_len, i) {
694 if (sg->offset & 0x3) {
695 DBG("Reverting to PIO because of "
697 host->flags &= ~SDHCI_REQ_USE_DMA;
704 if (host->flags & SDHCI_REQ_USE_DMA) {
705 if (host->flags & SDHCI_USE_ADMA) {
706 ret = sdhci_adma_table_pre(host, data);
709 * This only happens when someone fed
710 * us an invalid request.
713 host->flags &= ~SDHCI_REQ_USE_DMA;
715 sdhci_writel(host, host->adma_addr,
721 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
722 data->sg, data->sg_len,
723 (data->flags & MMC_DATA_READ) ?
728 * This only happens when someone fed
729 * us an invalid request.
732 host->flags &= ~SDHCI_REQ_USE_DMA;
734 WARN_ON(sg_cnt != 1);
735 sdhci_writel(host, sg_dma_address(data->sg),
742 * Always adjust the DMA selection as some controllers
743 * (e.g. JMicron) can't do PIO properly when the selection
746 if (host->version >= SDHCI_SPEC_200) {
747 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
748 ctrl &= ~SDHCI_CTRL_DMA_MASK;
749 if ((host->flags & SDHCI_REQ_USE_DMA) &&
750 (host->flags & SDHCI_USE_ADMA))
751 ctrl |= SDHCI_CTRL_ADMA32;
753 ctrl |= SDHCI_CTRL_SDMA;
754 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
757 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
758 sg_miter_start(&host->sg_miter,
759 data->sg, data->sg_len, SG_MITER_ATOMIC);
760 host->blocks = data->blocks;
763 sdhci_set_transfer_irqs(host);
765 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
766 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
767 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
770 static void sdhci_set_transfer_mode(struct sdhci_host *host,
771 struct mmc_data *data)
778 WARN_ON(!host->data);
780 mode = SDHCI_TRNS_BLK_CNT_EN;
781 if (data->blocks > 1)
782 mode |= SDHCI_TRNS_MULTI;
783 if (data->flags & MMC_DATA_READ)
784 mode |= SDHCI_TRNS_READ;
785 if (host->flags & SDHCI_REQ_USE_DMA)
786 mode |= SDHCI_TRNS_DMA;
788 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
791 static void sdhci_finish_data(struct sdhci_host *host)
793 struct mmc_data *data;
800 if (host->flags & SDHCI_REQ_USE_DMA) {
801 if (host->flags & SDHCI_USE_ADMA)
802 sdhci_adma_table_post(host, data);
804 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
805 data->sg_len, (data->flags & MMC_DATA_READ) ?
806 DMA_FROM_DEVICE : DMA_TO_DEVICE);
811 * The specification states that the block count register must
812 * be updated, but it does not specify at what point in the
813 * data flow. That makes the register entirely useless to read
814 * back so we have to assume that nothing made it to the card
815 * in the event of an error.
818 data->bytes_xfered = 0;
820 data->bytes_xfered = data->blksz * data->blocks;
824 * The controller needs a reset of internal state machines
825 * upon error conditions.
828 sdhci_reset(host, SDHCI_RESET_CMD);
829 sdhci_reset(host, SDHCI_RESET_DATA);
832 sdhci_send_command(host, data->stop);
834 tasklet_schedule(&host->finish_tasklet);
837 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
841 unsigned long timeout;
848 mask = SDHCI_CMD_INHIBIT;
849 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
850 mask |= SDHCI_DATA_INHIBIT;
852 /* We shouldn't wait for data inihibit for stop commands, even
853 though they might use busy signaling */
854 if (host->mrq->data && (cmd == host->mrq->data->stop))
855 mask &= ~SDHCI_DATA_INHIBIT;
857 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
859 printk(KERN_ERR "%s: Controller never released "
860 "inhibit bit(s).\n", mmc_hostname(host->mmc));
861 sdhci_dumpregs(host);
863 tasklet_schedule(&host->finish_tasklet);
870 mod_timer(&host->timer, jiffies + 10 * HZ);
874 sdhci_prepare_data(host, cmd->data);
876 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
878 sdhci_set_transfer_mode(host, cmd->data);
880 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
881 printk(KERN_ERR "%s: Unsupported response type!\n",
882 mmc_hostname(host->mmc));
883 cmd->error = -EINVAL;
884 tasklet_schedule(&host->finish_tasklet);
888 if (!(cmd->flags & MMC_RSP_PRESENT))
889 flags = SDHCI_CMD_RESP_NONE;
890 else if (cmd->flags & MMC_RSP_136)
891 flags = SDHCI_CMD_RESP_LONG;
892 else if (cmd->flags & MMC_RSP_BUSY)
893 flags = SDHCI_CMD_RESP_SHORT_BUSY;
895 flags = SDHCI_CMD_RESP_SHORT;
897 if (cmd->flags & MMC_RSP_CRC)
898 flags |= SDHCI_CMD_CRC;
899 if (cmd->flags & MMC_RSP_OPCODE)
900 flags |= SDHCI_CMD_INDEX;
902 flags |= SDHCI_CMD_DATA;
904 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
907 static void sdhci_finish_command(struct sdhci_host *host)
911 BUG_ON(host->cmd == NULL);
913 if (host->cmd->flags & MMC_RSP_PRESENT) {
914 if (host->cmd->flags & MMC_RSP_136) {
915 /* CRC is stripped so we need to do some shifting. */
916 for (i = 0;i < 4;i++) {
917 host->cmd->resp[i] = sdhci_readl(host,
918 SDHCI_RESPONSE + (3-i)*4) << 8;
920 host->cmd->resp[i] |=
922 SDHCI_RESPONSE + (3-i)*4-1);
925 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
929 host->cmd->error = 0;
931 if (host->data && host->data_early)
932 sdhci_finish_data(host);
934 if (!host->cmd->data)
935 tasklet_schedule(&host->finish_tasklet);
940 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
944 unsigned long timeout;
946 if (clock == host->clock)
949 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
954 for (div = 1;div < 256;div *= 2) {
955 if ((host->max_clk / div) <= clock)
960 clk = div << SDHCI_DIVIDER_SHIFT;
961 clk |= SDHCI_CLOCK_INT_EN;
962 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
966 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
967 & SDHCI_CLOCK_INT_STABLE)) {
969 printk(KERN_ERR "%s: Internal clock never "
970 "stabilised.\n", mmc_hostname(host->mmc));
971 sdhci_dumpregs(host);
978 clk |= SDHCI_CLOCK_CARD_EN;
979 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
985 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
989 if (host->power == power)
992 if (power == (unsigned short)-1) {
993 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
998 * Spec says that we should clear the power reg before setting
999 * a new value. Some controllers don't seem to like this though.
1001 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1002 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1004 pwr = SDHCI_POWER_ON;
1006 switch (1 << power) {
1007 case MMC_VDD_165_195:
1008 pwr |= SDHCI_POWER_180;
1012 pwr |= SDHCI_POWER_300;
1016 pwr |= SDHCI_POWER_330;
1023 * At least the Marvell CaFe chip gets confused if we set the voltage
1024 * and set turn on power at the same time, so set the voltage first.
1026 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
1027 sdhci_writeb(host, pwr & ~SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1029 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1032 host->power = power;
1035 /*****************************************************************************\
1039 \*****************************************************************************/
1041 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1043 struct sdhci_host *host;
1044 unsigned long flags;
1046 host = mmc_priv(mmc);
1048 spin_lock_irqsave(&host->lock, flags);
1050 WARN_ON(host->mrq != NULL);
1052 #ifndef SDHCI_USE_LEDS_CLASS
1053 sdhci_activate_led(host);
1058 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1059 || (host->flags & SDHCI_DEVICE_DEAD)) {
1060 host->mrq->cmd->error = -ENOMEDIUM;
1061 tasklet_schedule(&host->finish_tasklet);
1063 sdhci_send_command(host, mrq->cmd);
1066 spin_unlock_irqrestore(&host->lock, flags);
1069 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1071 struct sdhci_host *host;
1072 unsigned long flags;
1075 host = mmc_priv(mmc);
1077 spin_lock_irqsave(&host->lock, flags);
1079 if (host->flags & SDHCI_DEVICE_DEAD)
1083 * Reset the chip on each power off.
1084 * Should clear out any weird states.
1086 if (ios->power_mode == MMC_POWER_OFF) {
1087 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1091 sdhci_set_clock(host, ios->clock);
1093 if (ios->power_mode == MMC_POWER_OFF)
1094 sdhci_set_power(host, -1);
1096 sdhci_set_power(host, ios->vdd);
1098 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1100 if (ios->bus_width == MMC_BUS_WIDTH_4)
1101 ctrl |= SDHCI_CTRL_4BITBUS;
1103 ctrl &= ~SDHCI_CTRL_4BITBUS;
1105 if (ios->timing == MMC_TIMING_SD_HS)
1106 ctrl |= SDHCI_CTRL_HISPD;
1108 ctrl &= ~SDHCI_CTRL_HISPD;
1110 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1113 * Some (ENE) controllers go apeshit on some ios operation,
1114 * signalling timeout and CRC errors even on CMD0. Resetting
1115 * it on each ios seems to solve the problem.
1117 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1118 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1122 spin_unlock_irqrestore(&host->lock, flags);
1125 static int sdhci_get_ro(struct mmc_host *mmc)
1127 struct sdhci_host *host;
1128 unsigned long flags;
1131 host = mmc_priv(mmc);
1133 spin_lock_irqsave(&host->lock, flags);
1135 if (host->flags & SDHCI_DEVICE_DEAD)
1138 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1140 spin_unlock_irqrestore(&host->lock, flags);
1142 return !(present & SDHCI_WRITE_PROTECT);
1145 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1147 struct sdhci_host *host;
1148 unsigned long flags;
1150 host = mmc_priv(mmc);
1152 spin_lock_irqsave(&host->lock, flags);
1154 if (host->flags & SDHCI_DEVICE_DEAD)
1158 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1160 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1164 spin_unlock_irqrestore(&host->lock, flags);
1167 static const struct mmc_host_ops sdhci_ops = {
1168 .request = sdhci_request,
1169 .set_ios = sdhci_set_ios,
1170 .get_ro = sdhci_get_ro,
1171 .enable_sdio_irq = sdhci_enable_sdio_irq,
1174 /*****************************************************************************\
1178 \*****************************************************************************/
1180 static void sdhci_tasklet_card(unsigned long param)
1182 struct sdhci_host *host;
1183 unsigned long flags;
1185 host = (struct sdhci_host*)param;
1187 spin_lock_irqsave(&host->lock, flags);
1189 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1191 printk(KERN_ERR "%s: Card removed during transfer!\n",
1192 mmc_hostname(host->mmc));
1193 printk(KERN_ERR "%s: Resetting controller.\n",
1194 mmc_hostname(host->mmc));
1196 sdhci_reset(host, SDHCI_RESET_CMD);
1197 sdhci_reset(host, SDHCI_RESET_DATA);
1199 host->mrq->cmd->error = -ENOMEDIUM;
1200 tasklet_schedule(&host->finish_tasklet);
1204 spin_unlock_irqrestore(&host->lock, flags);
1206 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1209 static void sdhci_tasklet_finish(unsigned long param)
1211 struct sdhci_host *host;
1212 unsigned long flags;
1213 struct mmc_request *mrq;
1215 host = (struct sdhci_host*)param;
1217 spin_lock_irqsave(&host->lock, flags);
1219 del_timer(&host->timer);
1224 * The controller needs a reset of internal state machines
1225 * upon error conditions.
1227 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1229 (mrq->data && (mrq->data->error ||
1230 (mrq->data->stop && mrq->data->stop->error))) ||
1231 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1233 /* Some controllers need this kick or reset won't work here */
1234 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1237 /* This is to force an update */
1238 clock = host->clock;
1240 sdhci_set_clock(host, clock);
1243 /* Spec says we should do both at the same time, but Ricoh
1244 controllers do not like that. */
1245 sdhci_reset(host, SDHCI_RESET_CMD);
1246 sdhci_reset(host, SDHCI_RESET_DATA);
1253 #ifndef SDHCI_USE_LEDS_CLASS
1254 sdhci_deactivate_led(host);
1258 spin_unlock_irqrestore(&host->lock, flags);
1260 mmc_request_done(host->mmc, mrq);
1263 static void sdhci_timeout_timer(unsigned long data)
1265 struct sdhci_host *host;
1266 unsigned long flags;
1268 host = (struct sdhci_host*)data;
1270 spin_lock_irqsave(&host->lock, flags);
1273 printk(KERN_ERR "%s: Timeout waiting for hardware "
1274 "interrupt.\n", mmc_hostname(host->mmc));
1275 sdhci_dumpregs(host);
1278 host->data->error = -ETIMEDOUT;
1279 sdhci_finish_data(host);
1282 host->cmd->error = -ETIMEDOUT;
1284 host->mrq->cmd->error = -ETIMEDOUT;
1286 tasklet_schedule(&host->finish_tasklet);
1291 spin_unlock_irqrestore(&host->lock, flags);
1294 /*****************************************************************************\
1296 * Interrupt handling *
1298 \*****************************************************************************/
1300 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1302 BUG_ON(intmask == 0);
1305 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1306 "though no command operation was in progress.\n",
1307 mmc_hostname(host->mmc), (unsigned)intmask);
1308 sdhci_dumpregs(host);
1312 if (intmask & SDHCI_INT_TIMEOUT)
1313 host->cmd->error = -ETIMEDOUT;
1314 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1316 host->cmd->error = -EILSEQ;
1318 if (host->cmd->error) {
1319 tasklet_schedule(&host->finish_tasklet);
1324 * The host can send and interrupt when the busy state has
1325 * ended, allowing us to wait without wasting CPU cycles.
1326 * Unfortunately this is overloaded on the "data complete"
1327 * interrupt, so we need to take some care when handling
1330 * Note: The 1.0 specification is a bit ambiguous about this
1331 * feature so there might be some problems with older
1334 if (host->cmd->flags & MMC_RSP_BUSY) {
1335 if (host->cmd->data)
1336 DBG("Cannot wait for busy signal when also "
1337 "doing a data transfer");
1338 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1341 /* The controller does not support the end-of-busy IRQ,
1342 * fall through and take the SDHCI_INT_RESPONSE */
1345 if (intmask & SDHCI_INT_RESPONSE)
1346 sdhci_finish_command(host);
1349 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1351 BUG_ON(intmask == 0);
1355 * The "data complete" interrupt is also used to
1356 * indicate that a busy state has ended. See comment
1357 * above in sdhci_cmd_irq().
1359 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1360 if (intmask & SDHCI_INT_DATA_END) {
1361 sdhci_finish_command(host);
1366 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1367 "though no data operation was in progress.\n",
1368 mmc_hostname(host->mmc), (unsigned)intmask);
1369 sdhci_dumpregs(host);
1374 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1375 host->data->error = -ETIMEDOUT;
1376 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1377 host->data->error = -EILSEQ;
1378 else if (intmask & SDHCI_INT_ADMA_ERROR)
1379 host->data->error = -EIO;
1381 if (host->data->error)
1382 sdhci_finish_data(host);
1384 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1385 sdhci_transfer_pio(host);
1388 * We currently don't do anything fancy with DMA
1389 * boundaries, but as we can't disable the feature
1390 * we need to at least restart the transfer.
1392 if (intmask & SDHCI_INT_DMA_END)
1393 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1396 if (intmask & SDHCI_INT_DATA_END) {
1399 * Data managed to finish before the
1400 * command completed. Make sure we do
1401 * things in the proper order.
1403 host->data_early = 1;
1405 sdhci_finish_data(host);
1411 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1414 struct sdhci_host* host = dev_id;
1418 spin_lock(&host->lock);
1420 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1422 if (!intmask || intmask == 0xffffffff) {
1427 DBG("*** %s got interrupt: 0x%08x\n",
1428 mmc_hostname(host->mmc), intmask);
1430 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1431 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1432 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1433 tasklet_schedule(&host->card_tasklet);
1436 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1438 if (intmask & SDHCI_INT_CMD_MASK) {
1439 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1441 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1444 if (intmask & SDHCI_INT_DATA_MASK) {
1445 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1447 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1450 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1452 intmask &= ~SDHCI_INT_ERROR;
1454 if (intmask & SDHCI_INT_BUS_POWER) {
1455 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1456 mmc_hostname(host->mmc));
1457 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1460 intmask &= ~SDHCI_INT_BUS_POWER;
1462 if (intmask & SDHCI_INT_CARD_INT)
1465 intmask &= ~SDHCI_INT_CARD_INT;
1468 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1469 mmc_hostname(host->mmc), intmask);
1470 sdhci_dumpregs(host);
1472 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1475 result = IRQ_HANDLED;
1479 spin_unlock(&host->lock);
1482 * We have to delay this as it calls back into the driver.
1485 mmc_signal_sdio_irq(host->mmc);
1490 /*****************************************************************************\
1494 \*****************************************************************************/
1498 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1502 sdhci_disable_card_detection(host);
1504 ret = mmc_suspend_host(host->mmc, state);
1508 free_irq(host->irq, host);
1513 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1515 int sdhci_resume_host(struct sdhci_host *host)
1519 if (host->flags & SDHCI_USE_DMA) {
1520 if (host->ops->enable_dma)
1521 host->ops->enable_dma(host);
1524 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1525 mmc_hostname(host->mmc), host);
1532 ret = mmc_resume_host(host->mmc);
1536 sdhci_enable_card_detection(host);
1541 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1543 #endif /* CONFIG_PM */
1545 /*****************************************************************************\
1547 * Device allocation/registration *
1549 \*****************************************************************************/
1551 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1554 struct mmc_host *mmc;
1555 struct sdhci_host *host;
1557 WARN_ON(dev == NULL);
1559 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1561 return ERR_PTR(-ENOMEM);
1563 host = mmc_priv(mmc);
1569 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1571 int sdhci_add_host(struct sdhci_host *host)
1573 struct mmc_host *mmc;
1577 WARN_ON(host == NULL);
1584 host->quirks = debug_quirks;
1586 sdhci_reset(host, SDHCI_RESET_ALL);
1588 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1589 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1590 >> SDHCI_SPEC_VER_SHIFT;
1591 if (host->version > SDHCI_SPEC_200) {
1592 printk(KERN_ERR "%s: Unknown controller version (%d). "
1593 "You may experience problems.\n", mmc_hostname(mmc),
1597 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1599 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1600 host->flags |= SDHCI_USE_DMA;
1601 else if (!(caps & SDHCI_CAN_DO_DMA))
1602 DBG("Controller doesn't have DMA capability\n");
1604 host->flags |= SDHCI_USE_DMA;
1606 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1607 (host->flags & SDHCI_USE_DMA)) {
1608 DBG("Disabling DMA as it is marked broken\n");
1609 host->flags &= ~SDHCI_USE_DMA;
1612 if (host->flags & SDHCI_USE_DMA) {
1613 if ((host->version >= SDHCI_SPEC_200) &&
1614 (caps & SDHCI_CAN_DO_ADMA2))
1615 host->flags |= SDHCI_USE_ADMA;
1618 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1619 (host->flags & SDHCI_USE_ADMA)) {
1620 DBG("Disabling ADMA as it is marked broken\n");
1621 host->flags &= ~SDHCI_USE_ADMA;
1624 if (host->flags & SDHCI_USE_DMA) {
1625 if (host->ops->enable_dma) {
1626 if (host->ops->enable_dma(host)) {
1627 printk(KERN_WARNING "%s: No suitable DMA "
1628 "available. Falling back to PIO.\n",
1630 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
1635 if (host->flags & SDHCI_USE_ADMA) {
1637 * We need to allocate descriptors for all sg entries
1638 * (128) and potentially one alignment transfer for
1639 * each of those entries.
1641 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1642 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1643 if (!host->adma_desc || !host->align_buffer) {
1644 kfree(host->adma_desc);
1645 kfree(host->align_buffer);
1646 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1647 "buffers. Falling back to standard DMA.\n",
1649 host->flags &= ~SDHCI_USE_ADMA;
1654 * If we use DMA, then it's up to the caller to set the DMA
1655 * mask, but PIO does not need the hw shim so we set a new
1656 * mask here in that case.
1658 if (!(host->flags & SDHCI_USE_DMA)) {
1659 host->dma_mask = DMA_BIT_MASK(64);
1660 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1664 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1665 if (host->max_clk == 0) {
1666 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1667 "frequency.\n", mmc_hostname(mmc));
1670 host->max_clk *= 1000000;
1673 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1674 if (host->timeout_clk == 0) {
1675 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1676 "frequency.\n", mmc_hostname(mmc));
1679 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1680 host->timeout_clk *= 1000;
1683 * Set host parameters.
1685 mmc->ops = &sdhci_ops;
1686 mmc->f_min = host->max_clk / 256;
1687 mmc->f_max = host->max_clk;
1688 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1690 if (caps & SDHCI_CAN_DO_HISPD)
1691 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1694 if (caps & SDHCI_CAN_VDD_330)
1695 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1696 if (caps & SDHCI_CAN_VDD_300)
1697 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1698 if (caps & SDHCI_CAN_VDD_180)
1699 mmc->ocr_avail |= MMC_VDD_165_195;
1701 if (mmc->ocr_avail == 0) {
1702 printk(KERN_ERR "%s: Hardware doesn't report any "
1703 "support voltages.\n", mmc_hostname(mmc));
1707 spin_lock_init(&host->lock);
1710 * Maximum number of segments. Depends on if the hardware
1711 * can do scatter/gather or not.
1713 if (host->flags & SDHCI_USE_ADMA)
1714 mmc->max_hw_segs = 128;
1715 else if (host->flags & SDHCI_USE_DMA)
1716 mmc->max_hw_segs = 1;
1718 mmc->max_hw_segs = 128;
1719 mmc->max_phys_segs = 128;
1722 * Maximum number of sectors in one transfer. Limited by DMA boundary
1725 mmc->max_req_size = 524288;
1728 * Maximum segment size. Could be one segment with the maximum number
1729 * of bytes. When doing hardware scatter/gather, each entry cannot
1730 * be larger than 64 KiB though.
1732 if (host->flags & SDHCI_USE_ADMA)
1733 mmc->max_seg_size = 65536;
1735 mmc->max_seg_size = mmc->max_req_size;
1738 * Maximum block size. This varies from controller to controller and
1739 * is specified in the capabilities register.
1741 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1742 if (mmc->max_blk_size >= 3) {
1743 printk(KERN_WARNING "%s: Invalid maximum block size, "
1744 "assuming 512 bytes\n", mmc_hostname(mmc));
1745 mmc->max_blk_size = 512;
1747 mmc->max_blk_size = 512 << mmc->max_blk_size;
1750 * Maximum block count.
1752 mmc->max_blk_count = 65535;
1757 tasklet_init(&host->card_tasklet,
1758 sdhci_tasklet_card, (unsigned long)host);
1759 tasklet_init(&host->finish_tasklet,
1760 sdhci_tasklet_finish, (unsigned long)host);
1762 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1764 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1765 mmc_hostname(mmc), host);
1771 #ifdef CONFIG_MMC_DEBUG
1772 sdhci_dumpregs(host);
1775 #ifdef SDHCI_USE_LEDS_CLASS
1776 snprintf(host->led_name, sizeof(host->led_name),
1777 "%s::", mmc_hostname(mmc));
1778 host->led.name = host->led_name;
1779 host->led.brightness = LED_OFF;
1780 host->led.default_trigger = mmc_hostname(mmc);
1781 host->led.brightness_set = sdhci_led_control;
1783 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1792 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
1793 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1794 (host->flags & SDHCI_USE_ADMA)?"A":"",
1795 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1797 sdhci_enable_card_detection(host);
1801 #ifdef SDHCI_USE_LEDS_CLASS
1803 sdhci_reset(host, SDHCI_RESET_ALL);
1804 free_irq(host->irq, host);
1807 tasklet_kill(&host->card_tasklet);
1808 tasklet_kill(&host->finish_tasklet);
1813 EXPORT_SYMBOL_GPL(sdhci_add_host);
1815 void sdhci_remove_host(struct sdhci_host *host, int dead)
1817 unsigned long flags;
1820 spin_lock_irqsave(&host->lock, flags);
1822 host->flags |= SDHCI_DEVICE_DEAD;
1825 printk(KERN_ERR "%s: Controller removed during "
1826 " transfer!\n", mmc_hostname(host->mmc));
1828 host->mrq->cmd->error = -ENOMEDIUM;
1829 tasklet_schedule(&host->finish_tasklet);
1832 spin_unlock_irqrestore(&host->lock, flags);
1835 sdhci_disable_card_detection(host);
1837 mmc_remove_host(host->mmc);
1839 #ifdef SDHCI_USE_LEDS_CLASS
1840 led_classdev_unregister(&host->led);
1844 sdhci_reset(host, SDHCI_RESET_ALL);
1846 free_irq(host->irq, host);
1848 del_timer_sync(&host->timer);
1850 tasklet_kill(&host->card_tasklet);
1851 tasklet_kill(&host->finish_tasklet);
1853 kfree(host->adma_desc);
1854 kfree(host->align_buffer);
1856 host->adma_desc = NULL;
1857 host->align_buffer = NULL;
1860 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1862 void sdhci_free_host(struct sdhci_host *host)
1864 mmc_free_host(host->mmc);
1867 EXPORT_SYMBOL_GPL(sdhci_free_host);
1869 /*****************************************************************************\
1871 * Driver init/exit *
1873 \*****************************************************************************/
1875 static int __init sdhci_drv_init(void)
1877 printk(KERN_INFO DRIVER_NAME
1878 ": Secure Digital Host Controller Interface driver\n");
1879 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1884 static void __exit sdhci_drv_exit(void)
1888 module_init(sdhci_drv_init);
1889 module_exit(sdhci_drv_exit);
1891 module_param(debug_quirks, uint, 0444);
1893 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1894 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1895 MODULE_LICENSE("GPL");
1897 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");