drivers/mmc/host/s3cmci.c

   1 /*
   2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3  *
   4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/clk.h>
  14 #include <linux/mmc/host.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/irq.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/dma.h>
  20
  21 #include <asm/arch/regs-sdi.h>
  22 #include <asm/arch/regs-gpio.h>
  23
  24 #include <asm/plat-s3c24xx/mci.h>
  25
  26 #include "s3cmci.h"
  27
  28 #define DRIVER_NAME "s3c-mci"
  29
  30 enum dbg_channels {
  31         dbg_err   = (1 << 0),
  32         dbg_debug = (1 << 1),
  33         dbg_info  = (1 << 2),
  34         dbg_irq   = (1 << 3),
  35         dbg_sg    = (1 << 4),
  36         dbg_dma   = (1 << 5),
  37         dbg_pio   = (1 << 6),
  38         dbg_fail  = (1 << 7),
  39         dbg_conf  = (1 << 8),
  40 };
  41
  42 static const int dbgmap_err   = dbg_err | dbg_fail;
  43 static const int dbgmap_info  = dbg_info | dbg_conf;
  44 static const int dbgmap_debug = dbg_debug;
  45
  46 #define dbg(host, channels, args...)              \
  47         do {                                      \
  48         if (dbgmap_err & channels)                \
  49                 dev_err(&host->pdev->dev, args);  \
  50         else if (dbgmap_info & channels)          \
  51                 dev_info(&host->pdev->dev, args); \
  52         else if (dbgmap_debug & channels)         \
  53                 dev_dbg(&host->pdev->dev, args);  \
  54         } while (0)
  55
  56 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
  57
  58 static struct s3c2410_dma_client s3cmci_dma_client = {
  59         .name           = "s3c-mci",
  60 };
  61
  62 static void finalize_request(struct s3cmci_host *host);
  63 static void s3cmci_send_request(struct mmc_host *mmc);
  64 static void s3cmci_reset(struct s3cmci_host *host);
  65
  66 #ifdef CONFIG_MMC_DEBUG
  67
  68 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
  69 {
  70         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
  71         u32 datcon, datcnt, datsta, fsta, imask;
  72
  73         con     = readl(host->base + S3C2410_SDICON);
  74         pre     = readl(host->base + S3C2410_SDIPRE);
  75         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
  76         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
  77         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
  78         r0      = readl(host->base + S3C2410_SDIRSP0);
  79         r1      = readl(host->base + S3C2410_SDIRSP1);
  80         r2      = readl(host->base + S3C2410_SDIRSP2);
  81         r3      = readl(host->base + S3C2410_SDIRSP3);
  82         timer   = readl(host->base + S3C2410_SDITIMER);
  83         bsize   = readl(host->base + S3C2410_SDIBSIZE);
  84         datcon  = readl(host->base + S3C2410_SDIDCON);
  85         datcnt  = readl(host->base + S3C2410_SDIDCNT);
  86         datsta  = readl(host->base + S3C2410_SDIDSTA);
  87         fsta    = readl(host->base + S3C2410_SDIFSTA);
  88         imask   = readl(host->base + host->sdiimsk);
  89
  90         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
  91                                 prefix, con, pre, timer);
  92
  93         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
  94                                 prefix, cmdcon, cmdarg, cmdsta);
  95
  96         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
  97                                " DSTA:[%08x] DCNT:[%08x]\n",
  98                                 prefix, datcon, fsta, datsta, datcnt);
  99
 100         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 101                                "   R2:[%08x]   R3:[%08x]\n",
 102                                 prefix, r0, r1, r2, r3);
 103 }
 104
 105 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 106                            int stop)
 107 {
 108         snprintf(host->dbgmsg_cmd, 300,
 109                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 110                  host->ccnt, (stop ? " (STOP)" : ""),
 111                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 112
 113         if (cmd->data) {
 114                 snprintf(host->dbgmsg_dat, 300,
 115                          "#%u bsize:%u blocks:%u bytes:%u",
 116                          host->dcnt, cmd->data->blksz,
 117                          cmd->data->blocks,
 118                          cmd->data->blocks * cmd->data->blksz);
 119         } else {
 120                 host->dbgmsg_dat[0] = '\0';
 121         }
 122 }
 123
 124 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 125                         int fail)
 126 {
 127         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 128
 129         if (!cmd)
 130                 return;
 131
 132         if (cmd->error == 0) {
 133                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 134                         host->dbgmsg_cmd, cmd->resp[0]);
 135         } else {
 136                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 137                         cmd->error, host->dbgmsg_cmd, host->status);
 138         }
 139
 140         if (!cmd->data)
 141                 return;
 142
 143         if (cmd->data->error == 0) {
 144                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 145         } else {
 146                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 147                         cmd->data->error, host->dbgmsg_dat,
 148                         readl(host->base + S3C2410_SDIDCNT));
 149         }
 150 }
 151 #else
 152 static void dbg_dumpcmd(struct s3cmci_host *host,
 153                         struct mmc_command *cmd, int fail) { }
 154
 155 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 156                            int stop) { }
 157
 158 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 159
 160 #endif /* CONFIG_MMC_DEBUG */
 161
 162 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 163 {
 164         u32 newmask;
 165
 166         newmask = readl(host->base + host->sdiimsk);
 167         newmask |= imask;
 168
 169         writel(newmask, host->base + host->sdiimsk);
 170
 171         return newmask;
 172 }
 173
 174 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 175 {
 176         u32 newmask;
 177
 178         newmask = readl(host->base + host->sdiimsk);
 179         newmask &= ~imask;
 180
 181         writel(newmask, host->base + host->sdiimsk);
 182
 183         return newmask;
 184 }
 185
 186 static inline void clear_imask(struct s3cmci_host *host)
 187 {
 188         writel(0, host->base + host->sdiimsk);
 189 }
 190
 191 static inline int get_data_buffer(struct s3cmci_host *host,
 192                                   u32 *words, u32 **pointer)
 193 {
 194         struct scatterlist *sg;
 195
 196         if (host->pio_active == XFER_NONE)
 197                 return -EINVAL;
 198
 199         if ((!host->mrq) || (!host->mrq->data))
 200                 return -EINVAL;
 201
 202         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 203                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 204                       host->pio_sgptr, host->mrq->data->sg_len);
 205                 return -EBUSY;
 206         }
 207         sg = &host->mrq->data->sg[host->pio_sgptr];
 208
 209         *words = sg->length >> 2;
 210         *pointer = sg_virt(sg);
 211
 212         host->pio_sgptr++;
 213
 214         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 215             host->pio_sgptr, host->mrq->data->sg_len);
 216
 217         return 0;
 218 }
 219
 220 static inline u32 fifo_count(struct s3cmci_host *host)
 221 {
 222         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 223
 224         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 225         return fifostat >> 2;
 226 }
 227
 228 static inline u32 fifo_free(struct s3cmci_host *host)
 229 {
 230         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 231
 232         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 233         return (63 - fifostat) >> 2;
 234 }
 235
 236 static void do_pio_read(struct s3cmci_host *host)
 237 {
 238         int res;
 239         u32 fifo;
 240         void __iomem *from_ptr;
 241
 242         /* write real prescaler to host, it might be set slow to fix */
 243         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 244
 245         from_ptr = host->base + host->sdidata;
 246
 247         while ((fifo = fifo_count(host))) {
 248                 if (!host->pio_words) {
 249                         res = get_data_buffer(host, &host->pio_words,
 250                                               &host->pio_ptr);
 251                         if (res) {
 252                                 host->pio_active = XFER_NONE;
 253                                 host->complete_what = COMPLETION_FINALIZE;
 254
 255                                 dbg(host, dbg_pio, "pio_read(): "
 256                                     "complete (no more data).\n");
 257                                 return;
 258                         }
 259
 260                         dbg(host, dbg_pio,
 261                             "pio_read(): new target: [%i]@[%p]\n",
 262                             host->pio_words, host->pio_ptr);
 263                 }
 264
 265                 dbg(host, dbg_pio,
 266                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 267                     fifo, host->pio_words,
 268                     readl(host->base + S3C2410_SDIDCNT));
 269
 270                 if (fifo > host->pio_words)
 271                         fifo = host->pio_words;
 272
 273                 host->pio_words -= fifo;
 274                 host->pio_count += fifo;
 275
 276                 while (fifo--)
 277                         *(host->pio_ptr++) = readl(from_ptr);
 278         }
 279
 280         if (!host->pio_words) {
 281                 res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
 282                 if (res) {
 283                         dbg(host, dbg_pio,
 284                             "pio_read(): complete (no more buffers).\n");
 285                         host->pio_active = XFER_NONE;
 286                         host->complete_what = COMPLETION_FINALIZE;
 287
 288                         return;
 289                 }
 290         }
 291
 292         enable_imask(host,
 293                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 294 }
 295
 296 static void do_pio_write(struct s3cmci_host *host)
 297 {
 298         void __iomem *to_ptr;
 299         int res;
 300         u32 fifo;
 301
 302         to_ptr = host->base + host->sdidata;
 303
 304         while ((fifo = fifo_free(host))) {
 305                 if (!host->pio_words) {
 306                         res = get_data_buffer(host, &host->pio_words,
 307                                                         &host->pio_ptr);
 308                         if (res) {
 309                                 dbg(host, dbg_pio,
 310                                     "pio_write(): complete (no more data).\n");
 311                                 host->pio_active = XFER_NONE;
 312
 313                                 return;
 314                         }
 315
 316                         dbg(host, dbg_pio,
 317                             "pio_write(): new source: [%i]@[%p]\n",
 318                             host->pio_words, host->pio_ptr);
 319
 320                 }
 321
 322                 if (fifo > host->pio_words)
 323                         fifo = host->pio_words;
 324
 325                 host->pio_words -= fifo;
 326                 host->pio_count += fifo;
 327
 328                 while (fifo--)
 329                         writel(*(host->pio_ptr++), to_ptr);
 330         }
 331
 332         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 333 }
 334
 335 static void pio_tasklet(unsigned long data)
 336 {
 337         struct s3cmci_host *host = (struct s3cmci_host *) data;
 338
 339
 340         disable_irq(host->irq);
 341
 342         if (host->pio_active == XFER_WRITE)
 343                 do_pio_write(host);
 344
 345         if (host->pio_active == XFER_READ)
 346                 do_pio_read(host);
 347
 348         if (host->complete_what == COMPLETION_FINALIZE) {
 349                 clear_imask(host);
 350                 if (host->pio_active != XFER_NONE) {
 351                         dbg(host, dbg_err, "unfinished %s "
 352                             "- pio_count:[%u] pio_words:[%u]\n",
 353                             (host->pio_active == XFER_READ) ? "read" : "write",
 354                             host->pio_count, host->pio_words);
 355
 356                         if (host->mrq->data)
 357                                 host->mrq->data->error = -EINVAL;
 358                 }
 359
 360                 finalize_request(host);
 361         } else
 362                 enable_irq(host->irq);
 363 }
 364
 365 /*
 366  * ISR for SDI Interface IRQ
 367  * Communication between driver and ISR works as follows:
 368  *   host->mrq                  points to current request
 369  *   host->complete_what        Indicates when the request is considered done
 370  *     COMPLETION_CMDSENT         when the command was sent
 371  *     COMPLETION_RSPFIN          when a response was received
 372  *     COMPLETION_XFERFINISH      when the data transfer is finished
 373  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 374  *   host->complete_request     is the completion-object the driver waits for
 375  *
 376  * 1) Driver sets up host->mrq and host->complete_what
 377  * 2) Driver prepares the transfer
 378  * 3) Driver enables interrupts
 379  * 4) Driver starts transfer
 380  * 5) Driver waits for host->complete_rquest
 381  * 6) ISR checks for request status (errors and success)
 382  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 383  * 7) ISR completes host->complete_request
 384  * 8) ISR disables interrupts
 385  * 9) Driver wakes up and takes care of the request
 386  *
 387  * Note: "->error"-fields are expected to be set to 0 before the request
 388  *       was issued by mmc.c - therefore they are only set, when an error
 389  *       contition comes up
 390  */
 391
 392 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 393 {
 394         struct s3cmci_host *host = dev_id;
 395         struct mmc_command *cmd;
 396         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 397         u32 mci_cclear, mci_dclear;
 398         unsigned long iflags;
 399
 400         spin_lock_irqsave(&host->complete_lock, iflags);
 401
 402         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 403         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 404         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 405         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 406         mci_imsk = readl(host->base + host->sdiimsk);
 407         mci_cclear = 0;
 408         mci_dclear = 0;
 409
 410         if ((host->complete_what == COMPLETION_NONE) ||
 411             (host->complete_what == COMPLETION_FINALIZE)) {
 412                 host->status = "nothing to complete";
 413                 clear_imask(host);
 414                 goto irq_out;
 415         }
 416
 417         if (!host->mrq) {
 418                 host->status = "no active mrq";
 419                 clear_imask(host);
 420                 goto irq_out;
 421         }
 422
 423         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 424
 425         if (!cmd) {
 426                 host->status = "no active cmd";
 427                 clear_imask(host);
 428                 goto irq_out;
 429         }
 430
 431         if (!host->dodma) {
 432                 if ((host->pio_active == XFER_WRITE) &&
 433                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 434
 435                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 436                         tasklet_schedule(&host->pio_tasklet);
 437                         host->status = "pio tx";
 438                 }
 439
 440                 if ((host->pio_active == XFER_READ) &&
 441                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 442
 443                         disable_imask(host,
 444                                       S3C2410_SDIIMSK_RXFIFOHALF |
 445                                       S3C2410_SDIIMSK_RXFIFOLAST);
 446
 447                         tasklet_schedule(&host->pio_tasklet);
 448                         host->status = "pio rx";
 449                 }
 450         }
 451
 452         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 453                 cmd->error = -ETIMEDOUT;
 454                 host->status = "error: command timeout";
 455                 goto fail_transfer;
 456         }
 457
 458         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 459                 if (host->complete_what == COMPLETION_CMDSENT) {
 460                         host->status = "ok: command sent";
 461                         goto close_transfer;
 462                 }
 463
 464                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 465         }
 466
 467         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 468                 if (cmd->flags & MMC_RSP_CRC) {
 469                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 470                                 dbg(host, dbg_irq,
 471                                     "fixup: ignore CRC fail with long rsp\n");
 472                         } else {
 473                                 /* note, we used to fail the transfer
 474                                  * here, but it seems that this is just
 475                                  * the hardware getting it wrong.
 476                                  *
 477                                  * cmd->error = -EILSEQ;
 478                                  * host->status = "error: bad command crc";
 479                                  * goto fail_transfer;
 480                                 */
 481                         }
 482                 }
 483
 484                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 485         }
 486
 487         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 488                 if (host->complete_what == COMPLETION_RSPFIN) {
 489                         host->status = "ok: command response received";
 490                         goto close_transfer;
 491                 }
 492
 493                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 494                         host->complete_what = COMPLETION_XFERFINISH;
 495
 496                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 497         }
 498
 499         /* errors handled after this point are only relevant
 500            when a data transfer is in progress */
 501
 502         if (!cmd->data)
 503                 goto clear_status_bits;
 504
 505         /* Check for FIFO failure */
 506         if (host->is2440) {
 507                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 508                         host->mrq->data->error = -EILSEQ;
 509                         host->status = "error: 2440 fifo failure";
 510                         goto fail_transfer;
 511                 }
 512         } else {
 513                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 514                         cmd->data->error = -EILSEQ;
 515                         host->status = "error:  fifo failure";
 516                         goto fail_transfer;
 517                 }
 518         }
 519
 520         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 521                 cmd->data->error = -EILSEQ;
 522                 host->status = "error: bad data crc (outgoing)";
 523                 goto fail_transfer;
 524         }
 525
 526         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 527                 cmd->data->error = -EILSEQ;
 528                 host->status = "error: bad data crc (incoming)";
 529                 goto fail_transfer;
 530         }
 531
 532         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 533                 cmd->data->error = -ETIMEDOUT;
 534                 host->status = "error: data timeout";
 535                 goto fail_transfer;
 536         }
 537
 538         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 539                 if (host->complete_what == COMPLETION_XFERFINISH) {
 540                         host->status = "ok: data transfer completed";
 541                         goto close_transfer;
 542                 }
 543
 544                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 545                         host->complete_what = COMPLETION_RSPFIN;
 546
 547                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 548         }
 549
 550 clear_status_bits:
 551         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 552         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 553
 554         goto irq_out;
 555
 556 fail_transfer:
 557         host->pio_active = XFER_NONE;
 558
 559 close_transfer:
 560         host->complete_what = COMPLETION_FINALIZE;
 561
 562         clear_imask(host);
 563         tasklet_schedule(&host->pio_tasklet);
 564
 565         goto irq_out;
 566
 567 irq_out:
 568         dbg(host, dbg_irq,
 569             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 570             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 571
 572         spin_unlock_irqrestore(&host->complete_lock, iflags);
 573         return IRQ_HANDLED;
 574
 575 }
 576
 577 /*
 578  * ISR for the CardDetect Pin
 579 */
 580
 581 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
 582 {
 583         struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
 584
 585         dbg(host, dbg_irq, "card detect\n");
 586
 587         mmc_detect_change(host->mmc, 500);
 588
 589         return IRQ_HANDLED;
 590 }
 591
 592 void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch, void *buf_id,
 593                               int size, enum s3c2410_dma_buffresult result)
 594 {
 595         struct s3cmci_host *host = buf_id;
 596         unsigned long iflags;
 597         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
 598
 599         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 600         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 601         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 602         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 603
 604         BUG_ON(!host->mrq);
 605         BUG_ON(!host->mrq->data);
 606         BUG_ON(!host->dmatogo);
 607
 608         spin_lock_irqsave(&host->complete_lock, iflags);
 609
 610         if (result != S3C2410_RES_OK) {
 611                 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
 612                         "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
 613                         mci_csta, mci_dsta, mci_fsta,
 614                         mci_dcnt, result, host->dmatogo);
 615
 616                 goto fail_request;
 617         }
 618
 619         host->dmatogo--;
 620         if (host->dmatogo) {
 621                 dbg(host, dbg_dma, "DMA DONE  Size:%i DSTA:[%08x] "
 622                         "DCNT:[%08x] toGo:%u\n",
 623                         size, mci_dsta, mci_dcnt, host->dmatogo);
 624
 625                 goto out;
 626         }
 627
 628         dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
 629                 size, mci_dsta, mci_dcnt);
 630
 631         host->complete_what = COMPLETION_FINALIZE;
 632
 633 out:
 634         tasklet_schedule(&host->pio_tasklet);
 635         spin_unlock_irqrestore(&host->complete_lock, iflags);
 636         return;
 637
 638 fail_request:
 639         host->mrq->data->error = -EINVAL;
 640         host->complete_what = COMPLETION_FINALIZE;
 641         writel(0, host->base + host->sdiimsk);
 642         goto out;
 643
 644 }
 645
 646 static void finalize_request(struct s3cmci_host *host)
 647 {
 648         struct mmc_request *mrq = host->mrq;
 649         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 650         int debug_as_failure = 0;
 651
 652         if (host->complete_what != COMPLETION_FINALIZE)
 653                 return;
 654
 655         if (!mrq)
 656                 return;
 657
 658         if (cmd->data && (cmd->error == 0) &&
 659             (cmd->data->error == 0)) {
 660                 if (host->dodma && (!host->dma_complete)) {
 661                         dbg(host, dbg_dma, "DMA Missing!\n");
 662                         return;
 663                 }
 664         }
 665
 666         /* Read response from controller. */
 667         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 668         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 669         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 670         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 671
 672         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 673
 674         if (cmd->error)
 675                 debug_as_failure = 1;
 676
 677         if (cmd->data && cmd->data->error)
 678                 debug_as_failure = 1;
 679
 680         dbg_dumpcmd(host, cmd, debug_as_failure);
 681
 682         /* Cleanup controller */
 683         writel(0, host->base + S3C2410_SDICMDARG);
 684         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 685         writel(0, host->base + S3C2410_SDICMDCON);
 686         writel(0, host->base + host->sdiimsk);
 687
 688         if (cmd->data && cmd->error)
 689                 cmd->data->error = cmd->error;
 690
 691         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 692                 host->cmd_is_stop = 1;
 693                 s3cmci_send_request(host->mmc);
 694                 return;
 695         }
 696
 697         /* If we have no data transfer we are finished here */
 698         if (!mrq->data)
 699                 goto request_done;
 700
 701         /* Calulate the amout of bytes transfer if there was no error */
 702         if (mrq->data->error == 0) {
 703                 mrq->data->bytes_xfered =
 704                         (mrq->data->blocks * mrq->data->blksz);
 705         } else {
 706                 mrq->data->bytes_xfered = 0;
 707         }
 708
 709         /* If we had an error while transfering data we flush the
 710          * DMA channel and the fifo to clear out any garbage. */
 711         if (mrq->data->error != 0) {
 712                 if (host->dodma)
 713                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 714
 715                 if (host->is2440) {
 716                         /* Clear failure register and reset fifo. */
 717                         writel(S3C2440_SDIFSTA_FIFORESET |
 718                                S3C2440_SDIFSTA_FIFOFAIL,
 719                                host->base + S3C2410_SDIFSTA);
 720                 } else {
 721                         u32 mci_con;
 722
 723                         /* reset fifo */
 724                         mci_con = readl(host->base + S3C2410_SDICON);
 725                         mci_con |= S3C2410_SDICON_FIFORESET;
 726
 727                         writel(mci_con, host->base + S3C2410_SDICON);
 728                 }
 729         }
 730
 731 request_done:
 732         host->complete_what = COMPLETION_NONE;
 733         host->mrq = NULL;
 734         mmc_request_done(host->mmc, mrq);
 735 }
 736
 737
 738 void s3cmci_dma_setup(struct s3cmci_host *host, enum s3c2410_dmasrc source)
 739 {
 740         static enum s3c2410_dmasrc last_source = -1;
 741         static int setup_ok;
 742
 743         if (last_source == source)
 744                 return;
 745
 746         last_source = source;
 747
 748         s3c2410_dma_devconfig(host->dma, source, 3,
 749                               host->mem->start + host->sdidata);
 750
 751         if (!setup_ok) {
 752                 s3c2410_dma_config(host->dma, 4,
 753                         (S3C2410_DCON_HWTRIG | S3C2410_DCON_CH0_SDI));
 754                 s3c2410_dma_set_buffdone_fn(host->dma,
 755                                             s3cmci_dma_done_callback);
 756                 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
 757                 setup_ok = 1;
 758         }
 759 }
 760
 761 static void s3cmci_send_command(struct s3cmci_host *host,
 762                                         struct mmc_command *cmd)
 763 {
 764         u32 ccon, imsk;
 765
 766         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 767                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 768                 S3C2410_SDIIMSK_RESPONSECRC;
 769
 770         enable_imask(host, imsk);
 771
 772         if (cmd->data)
 773                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 774         else if (cmd->flags & MMC_RSP_PRESENT)
 775                 host->complete_what = COMPLETION_RSPFIN;
 776         else
 777                 host->complete_what = COMPLETION_CMDSENT;
 778
 779         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 780
 781         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 782         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 783
 784         if (cmd->flags & MMC_RSP_PRESENT)
 785                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 786
 787         if (cmd->flags & MMC_RSP_136)
 788                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 789
 790         writel(ccon, host->base + S3C2410_SDICMDCON);
 791 }
 792
 793 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 794 {
 795         u32 dcon, imsk, stoptries = 3;
 796
 797         /* write DCON register */
 798
 799         if (!data) {
 800                 writel(0, host->base + S3C2410_SDIDCON);
 801                 return 0;
 802         }
 803
 804         while (readl(host->base + S3C2410_SDIDSTA) &
 805                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 806
 807                 dbg(host, dbg_err,
 808                     "mci_setup_data() transfer stillin progress.\n");
 809
 810                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 811                 s3cmci_reset(host);
 812
 813                 if ((stoptries--) == 0) {
 814                         dbg_dumpregs(host, "DRF");
 815                         return -EINVAL;
 816                 }
 817         }
 818
 819         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 820
 821         if (host->dodma)
 822                 dcon |= S3C2410_SDIDCON_DMAEN;
 823
 824         if (host->bus_width == MMC_BUS_WIDTH_4)
 825                 dcon |= S3C2410_SDIDCON_WIDEBUS;
 826
 827         if (!(data->flags & MMC_DATA_STREAM))
 828                 dcon |= S3C2410_SDIDCON_BLOCKMODE;
 829
 830         if (data->flags & MMC_DATA_WRITE) {
 831                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
 832                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
 833         }
 834
 835         if (data->flags & MMC_DATA_READ) {
 836                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
 837                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
 838         }
 839
 840         if (host->is2440) {
 841                 dcon |= S3C2440_SDIDCON_DS_WORD;
 842                 dcon |= S3C2440_SDIDCON_DATSTART;
 843         }
 844
 845         writel(dcon, host->base + S3C2410_SDIDCON);
 846
 847         /* write BSIZE register */
 848
 849         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
 850
 851         /* add to IMASK register */
 852         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
 853                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
 854
 855         enable_imask(host, imsk);
 856
 857         /* write TIMER register */
 858
 859         if (host->is2440) {
 860                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
 861         } else {
 862                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
 863
 864                 /* FIX: set slow clock to prevent timeouts on read */
 865                 if (data->flags & MMC_DATA_READ)
 866                         writel(0xFF, host->base + S3C2410_SDIPRE);
 867         }
 868
 869         return 0;
 870 }
 871
 872 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
 873
 874 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
 875 {
 876         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
 877
 878         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
 879
 880         host->pio_sgptr = 0;
 881         host->pio_words = 0;
 882         host->pio_count = 0;
 883         host->pio_active = rw ? XFER_WRITE : XFER_READ;
 884
 885         if (rw) {
 886                 do_pio_write(host);
 887                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 888         } else {
 889                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
 890                              | S3C2410_SDIIMSK_RXFIFOLAST);
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
 897 {
 898         int dma_len, i;
 899         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
 900
 901         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
 902
 903         s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
 904         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 905
 906         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 907                              (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 908
 909         if (dma_len == 0)
 910                 return -ENOMEM;
 911
 912         host->dma_complete = 0;
 913         host->dmatogo = dma_len;
 914
 915         for (i = 0; i < dma_len; i++) {
 916                 int res;
 917
 918                 dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
 919                         sg_dma_address(&data->sg[i]),
 920                         sg_dma_len(&data->sg[i]));
 921
 922                 res = s3c2410_dma_enqueue(host->dma, (void *) host,
 923                                           sg_dma_address(&data->sg[i]),
 924                                           sg_dma_len(&data->sg[i]));
 925
 926                 if (res) {
 927                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 928                         return -EBUSY;
 929                 }
 930         }
 931
 932         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
 933
 934         return 0;
 935 }
 936
 937 static void s3cmci_send_request(struct mmc_host *mmc)
 938 {
 939         struct s3cmci_host *host = mmc_priv(mmc);
 940         struct mmc_request *mrq = host->mrq;
 941         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 942
 943         host->ccnt++;
 944         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
 945
 946         /* Clear command, data and fifo status registers
 947            Fifo clear only necessary on 2440, but doesn't hurt on 2410
 948         */
 949         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
 950         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
 951         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
 952
 953         if (cmd->data) {
 954                 int res = s3cmci_setup_data(host, cmd->data);
 955
 956                 host->dcnt++;
 957
 958                 if (res) {
 959                         cmd->error = -EINVAL;
 960                         cmd->data->error = -EINVAL;
 961
 962                         mmc_request_done(mmc, mrq);
 963                         return;
 964                 }
 965
 966                 if (host->dodma)
 967                         res = s3cmci_prepare_dma(host, cmd->data);
 968                 else
 969                         res = s3cmci_prepare_pio(host, cmd->data);
 970
 971                 if (res) {
 972                         cmd->error = res;
 973                         cmd->data->error = res;
 974
 975                         mmc_request_done(mmc, mrq);
 976                         return;
 977                 }
 978         }
 979
 980         /* Send command */
 981         s3cmci_send_command(host, cmd);
 982
 983         /* Enable Interrupt */
 984         enable_irq(host->irq);
 985 }
 986
 987 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 988 {
 989         struct s3cmci_host *host = mmc_priv(mmc);
 990
 991         host->status = "mmc request";
 992         host->cmd_is_stop = 0;
 993         host->mrq = mrq;
 994
 995         s3cmci_send_request(mmc);
 996 }
 997
 998 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 999 {
1000         struct s3cmci_host *host = mmc_priv(mmc);
1001         u32 mci_psc, mci_con;
1002
1003         /* Set the power state */
1004
1005         mci_con = readl(host->base + S3C2410_SDICON);
1006
1007         switch (ios->power_mode) {
1008         case MMC_POWER_ON:
1009         case MMC_POWER_UP:
1010                 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK);
1011                 s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD);
1012                 s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0);
1013                 s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
1014                 s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2);
1015                 s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3);
1016
1017                 if (host->pdata->set_power)
1018                         host->pdata->set_power(ios->power_mode, ios->vdd);
1019
1020                 if (!host->is2440)
1021                         mci_con |= S3C2410_SDICON_FIFORESET;
1022
1023                 break;
1024
1025         case MMC_POWER_OFF:
1026         default:
1027                 s3c2410_gpio_setpin(S3C2410_GPE5, 0);
1028                 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP);
1029
1030                 if (host->is2440)
1031                         mci_con |= S3C2440_SDICON_SDRESET;
1032
1033                 if (host->pdata->set_power)
1034                         host->pdata->set_power(ios->power_mode, ios->vdd);
1035
1036                 break;
1037         }
1038
1039         /* Set clock */
1040         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1041                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1042
1043                 if (host->real_rate <= ios->clock)
1044                         break;
1045         }
1046
1047         if (mci_psc > 255)
1048                 mci_psc = 255;
1049
1050         host->prescaler = mci_psc;
1051         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1052
1053         /* If requested clock is 0, real_rate will be 0, too */
1054         if (ios->clock == 0)
1055                 host->real_rate = 0;
1056
1057         /* Set CLOCK_ENABLE */
1058         if (ios->clock)
1059                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1060         else
1061                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1062
1063         writel(mci_con, host->base + S3C2410_SDICON);
1064
1065         if ((ios->power_mode == MMC_POWER_ON) ||
1066             (ios->power_mode == MMC_POWER_UP)) {
1067                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1068                         host->real_rate/1000, ios->clock/1000);
1069         } else {
1070                 dbg(host, dbg_conf, "powered down.\n");
1071         }
1072
1073         host->bus_width = ios->bus_width;
1074 }
1075
1076 static void s3cmci_reset(struct s3cmci_host *host)
1077 {
1078         u32 con = readl(host->base + S3C2410_SDICON);
1079
1080         con |= S3C2440_SDICON_SDRESET;
1081         writel(con, host->base + S3C2410_SDICON);
1082 }
1083
1084 static int s3cmci_get_ro(struct mmc_host *mmc)
1085 {
1086         struct s3cmci_host *host = mmc_priv(mmc);
1087         struct s3c24xx_mci_pdata *pdata = host->pdata;
1088         int ret;
1089
1090         if (pdata->gpio_wprotect == 0)
1091                 return 0;
1092
1093         ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
1094
1095         if (pdata->wprotect_invert)
1096                 ret = !ret;
1097
1098         return ret;
1099 }
1100
1101 static struct mmc_host_ops s3cmci_ops = {
1102         .request        = s3cmci_request,
1103         .set_ios        = s3cmci_set_ios,
1104         .get_ro         = s3cmci_get_ro,
1105 };
1106
1107 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1108         /* This is currently here to avoid a number of if (host->pdata)
1109          * checks. Any zero fields to ensure reaonable defaults are picked. */
1110 };
1111
1112 static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440)
1113 {
1114         struct s3cmci_host *host;
1115         struct mmc_host *mmc;
1116         int ret;
1117
1118         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1119         if (!mmc) {
1120                 ret = -ENOMEM;
1121                 goto probe_out;
1122         }
1123
1124         host = mmc_priv(mmc);
1125         host->mmc       = mmc;
1126         host->pdev      = pdev;
1127         host->is2440    = is2440;
1128
1129         host->pdata = pdev->dev.platform_data;
1130         if (!host->pdata) {
1131                 pdev->dev.platform_data = &s3cmci_def_pdata;
1132                 host->pdata = &s3cmci_def_pdata;
1133         }
1134
1135         spin_lock_init(&host->complete_lock);
1136         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1137
1138         if (is2440) {
1139                 host->sdiimsk   = S3C2440_SDIIMSK;
1140                 host->sdidata   = S3C2440_SDIDATA;
1141                 host->clk_div   = 1;
1142         } else {
1143                 host->sdiimsk   = S3C2410_SDIIMSK;
1144                 host->sdidata   = S3C2410_SDIDATA;
1145                 host->clk_div   = 2;
1146         }
1147
1148         host->dodma             = 0;
1149         host->complete_what     = COMPLETION_NONE;
1150         host->pio_active        = XFER_NONE;
1151
1152         host->dma               = S3CMCI_DMA;
1153         host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
1154         s3c2410_gpio_cfgpin(host->pdata->gpio_detect, S3C2410_GPIO_IRQ);
1155
1156         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1157         if (!host->mem) {
1158                 dev_err(&pdev->dev,
1159                         "failed to get io memory region resouce.\n");
1160
1161                 ret = -ENOENT;
1162                 goto probe_free_host;
1163         }
1164
1165         host->mem = request_mem_region(host->mem->start,
1166                                        RESSIZE(host->mem), pdev->name);
1167
1168         if (!host->mem) {
1169                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1170                 ret = -ENOENT;
1171                 goto probe_free_host;
1172         }
1173
1174         host->base = ioremap(host->mem->start, RESSIZE(host->mem));
1175         if (host->base == 0) {
1176                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1177                 ret = -EINVAL;
1178                 goto probe_free_mem_region;
1179         }
1180
1181         host->irq = platform_get_irq(pdev, 0);
1182         if (host->irq == 0) {
1183                 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1184                 ret = -EINVAL;
1185                 goto probe_iounmap;
1186         }
1187
1188         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1189                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1190                 ret = -ENOENT;
1191                 goto probe_iounmap;
1192         }
1193
1194         /* We get spurious interrupts even when we have set the IMSK
1195          * register to ignore everything, so use disable_irq() to make
1196          * ensure we don't lock the system with un-serviceable requests. */
1197
1198         disable_irq(host->irq);
1199
1200         s3c2410_gpio_cfgpin(host->pdata->gpio_detect, S3C2410_GPIO_IRQ);
1201         set_irq_type(host->irq_cd, IRQT_BOTHEDGE);
1202
1203         if (request_irq(host->irq_cd, s3cmci_irq_cd, 0, DRIVER_NAME, host)) {
1204                 dev_err(&pdev->dev,
1205                         "failed to request card detect interrupt.\n");
1206                 ret = -ENOENT;
1207                 goto probe_free_irq;
1208         }
1209
1210         if (host->pdata->gpio_wprotect)
1211                 s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect,
1212                                     S3C2410_GPIO_INPUT);
1213
1214         if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL)) {
1215                 dev_err(&pdev->dev, "unable to get DMA channel.\n");
1216                 ret = -EBUSY;
1217                 goto probe_free_irq_cd;
1218         }
1219
1220         host->clk = clk_get(&pdev->dev, "sdi");
1221         if (IS_ERR(host->clk)) {
1222                 dev_err(&pdev->dev, "failed to find clock source.\n");
1223                 ret = PTR_ERR(host->clk);
1224                 host->clk = NULL;
1225                 goto probe_free_host;
1226         }
1227
1228         ret = clk_enable(host->clk);
1229         if (ret) {
1230                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1231                 goto clk_free;
1232         }
1233
1234         host->clk_rate = clk_get_rate(host->clk);
1235
1236         mmc->ops        = &s3cmci_ops;
1237         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1238         mmc->caps       = MMC_CAP_4_BIT_DATA;
1239         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1240         mmc->f_max      = host->clk_rate / host->clk_div;
1241
1242         if (host->pdata->ocr_avail)
1243                 mmc->ocr_avail = host->pdata->ocr_avail;
1244
1245         mmc->max_blk_count      = 4095;
1246         mmc->max_blk_size       = 4095;
1247         mmc->max_req_size       = 4095 * 512;
1248         mmc->max_seg_size       = mmc->max_req_size;
1249
1250         mmc->max_phys_segs      = 128;
1251         mmc->max_hw_segs        = 128;
1252
1253         dbg(host, dbg_debug,
1254             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1255             (host->is2440?"2440":""),
1256             host->base, host->irq, host->irq_cd, host->dma);
1257
1258         ret = mmc_add_host(mmc);
1259         if (ret) {
1260                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1261                 goto free_dmabuf;
1262         }
1263
1264         platform_set_drvdata(pdev, mmc);
1265         dev_info(&pdev->dev, "initialisation done.\n");
1266
1267         return 0;
1268
1269  free_dmabuf:
1270         clk_disable(host->clk);
1271
1272  clk_free:
1273         clk_put(host->clk);
1274
1275  probe_free_irq_cd:
1276         free_irq(host->irq_cd, host);
1277
1278  probe_free_irq:
1279         free_irq(host->irq, host);
1280
1281  probe_iounmap:
1282         iounmap(host->base);
1283
1284  probe_free_mem_region:
1285         release_mem_region(host->mem->start, RESSIZE(host->mem));
1286
1287  probe_free_host:
1288         mmc_free_host(mmc);
1289  probe_out:
1290         return ret;
1291 }
1292
1293 static int __devexit s3cmci_remove(struct platform_device *pdev)
1294 {
1295         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1296         struct s3cmci_host      *host = mmc_priv(mmc);
1297
1298         mmc_remove_host(mmc);
1299
1300         clk_disable(host->clk);
1301         clk_put(host->clk);
1302
1303         tasklet_disable(&host->pio_tasklet);
1304         s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
1305
1306         free_irq(host->irq_cd, host);
1307         free_irq(host->irq, host);
1308
1309         iounmap(host->base);
1310         release_mem_region(host->mem->start, RESSIZE(host->mem));
1311
1312         mmc_free_host(mmc);
1313         return 0;
1314 }
1315
1316 static int __devinit s3cmci_probe_2410(struct platform_device *dev)
1317 {
1318         return s3cmci_probe(dev, 0);
1319 }
1320
1321 static int __devinit s3cmci_probe_2412(struct platform_device *dev)
1322 {
1323         return s3cmci_probe(dev, 1);
1324 }
1325
1326 static int __devinit s3cmci_probe_2440(struct platform_device *dev)
1327 {
1328         return s3cmci_probe(dev, 1);
1329 }
1330
1331 #ifdef CONFIG_PM
1332
1333 static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
1334 {
1335         struct mmc_host *mmc = platform_get_drvdata(dev);
1336
1337         return  mmc_suspend_host(mmc, state);
1338 }
1339
1340 static int s3cmci_resume(struct platform_device *dev)
1341 {
1342         struct mmc_host *mmc = platform_get_drvdata(dev);
1343
1344         return mmc_resume_host(mmc);
1345 }
1346
1347 #else /* CONFIG_PM */
1348 #define s3cmci_suspend NULL
1349 #define s3cmci_resume NULL
1350 #endif /* CONFIG_PM */
1351
1352
1353 static struct platform_driver s3cmci_driver_2410 = {
1354         .driver.name    = "s3c2410-sdi",
1355         .driver.owner   = THIS_MODULE,
1356         .probe          = s3cmci_probe_2410,
1357         .remove         = __devexit_p(s3cmci_remove),
1358         .suspend        = s3cmci_suspend,
1359         .resume         = s3cmci_resume,
1360 };
1361
1362 static struct platform_driver s3cmci_driver_2412 = {
1363         .driver.name    = "s3c2412-sdi",
1364         .driver.owner   = THIS_MODULE,
1365         .probe          = s3cmci_probe_2412,
1366         .remove         = __devexit_p(s3cmci_remove),
1367         .suspend        = s3cmci_suspend,
1368         .resume         = s3cmci_resume,
1369 };
1370
1371 static struct platform_driver s3cmci_driver_2440 = {
1372         .driver.name    = "s3c2440-sdi",
1373         .driver.owner   = THIS_MODULE,
1374         .probe          = s3cmci_probe_2440,
1375         .remove         = __devexit_p(s3cmci_remove),
1376         .suspend        = s3cmci_suspend,
1377         .resume         = s3cmci_resume,
1378 };
1379
1380
1381 static int __init s3cmci_init(void)
1382 {
1383         platform_driver_register(&s3cmci_driver_2410);
1384         platform_driver_register(&s3cmci_driver_2412);
1385         platform_driver_register(&s3cmci_driver_2440);
1386         return 0;
1387 }
1388
1389 static void __exit s3cmci_exit(void)
1390 {
1391         platform_driver_unregister(&s3cmci_driver_2410);
1392         platform_driver_unregister(&s3cmci_driver_2412);
1393         platform_driver_unregister(&s3cmci_driver_2440);
1394 }
1395
1396 module_init(s3cmci_init);
1397 module_exit(s3cmci_exit);
1398
1399 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1400 MODULE_LICENSE("GPL v2");
1401 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>");