drivers/mmc/host/s3cmci.c

   1 /*
   2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3  *
   4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/clk.h>
  14 #include <linux/mmc/host.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/cpufreq.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/dma.h>
  21
  22 #include <mach/regs-sdi.h>
  23 #include <mach/regs-gpio.h>
  24
  25 #include <asm/plat-s3c24xx/mci.h>
  26
  27 #include "s3cmci.h"
  28
  29 #define DRIVER_NAME "s3c-mci"
  30
  31 enum dbg_channels {
  32         dbg_err   = (1 << 0),
  33         dbg_debug = (1 << 1),
  34         dbg_info  = (1 << 2),
  35         dbg_irq   = (1 << 3),
  36         dbg_sg    = (1 << 4),
  37         dbg_dma   = (1 << 5),
  38         dbg_pio   = (1 << 6),
  39         dbg_fail  = (1 << 7),
  40         dbg_conf  = (1 << 8),
  41 };
  42
  43 static const int dbgmap_err   = dbg_fail;
  44 static const int dbgmap_info  = dbg_info | dbg_conf;
  45 static const int dbgmap_debug = dbg_err | dbg_debug;
  46
  47 #define dbg(host, channels, args...)              \
  48         do {                                      \
  49         if (dbgmap_err & channels)                \
  50                 dev_err(&host->pdev->dev, args);  \
  51         else if (dbgmap_info & channels)          \
  52                 dev_info(&host->pdev->dev, args); \
  53         else if (dbgmap_debug & channels)         \
  54                 dev_dbg(&host->pdev->dev, args);  \
  55         } while (0)
  56
  57 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
  58
  59 static struct s3c2410_dma_client s3cmci_dma_client = {
  60         .name           = "s3c-mci",
  61 };
  62
  63 static void finalize_request(struct s3cmci_host *host);
  64 static void s3cmci_send_request(struct mmc_host *mmc);
  65 static void s3cmci_reset(struct s3cmci_host *host);
  66
  67 #ifdef CONFIG_MMC_DEBUG
  68
  69 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
  70 {
  71         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
  72         u32 datcon, datcnt, datsta, fsta, imask;
  73
  74         con     = readl(host->base + S3C2410_SDICON);
  75         pre     = readl(host->base + S3C2410_SDIPRE);
  76         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
  77         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
  78         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
  79         r0      = readl(host->base + S3C2410_SDIRSP0);
  80         r1      = readl(host->base + S3C2410_SDIRSP1);
  81         r2      = readl(host->base + S3C2410_SDIRSP2);
  82         r3      = readl(host->base + S3C2410_SDIRSP3);
  83         timer   = readl(host->base + S3C2410_SDITIMER);
  84         bsize   = readl(host->base + S3C2410_SDIBSIZE);
  85         datcon  = readl(host->base + S3C2410_SDIDCON);
  86         datcnt  = readl(host->base + S3C2410_SDIDCNT);
  87         datsta  = readl(host->base + S3C2410_SDIDSTA);
  88         fsta    = readl(host->base + S3C2410_SDIFSTA);
  89         imask   = readl(host->base + host->sdiimsk);
  90
  91         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
  92                                 prefix, con, pre, timer);
  93
  94         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
  95                                 prefix, cmdcon, cmdarg, cmdsta);
  96
  97         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
  98                                " DSTA:[%08x] DCNT:[%08x]\n",
  99                                 prefix, datcon, fsta, datsta, datcnt);
 100
 101         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 102                                "   R2:[%08x]   R3:[%08x]\n",
 103                                 prefix, r0, r1, r2, r3);
 104 }
 105
 106 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 107                            int stop)
 108 {
 109         snprintf(host->dbgmsg_cmd, 300,
 110                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 111                  host->ccnt, (stop ? " (STOP)" : ""),
 112                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 113
 114         if (cmd->data) {
 115                 snprintf(host->dbgmsg_dat, 300,
 116                          "#%u bsize:%u blocks:%u bytes:%u",
 117                          host->dcnt, cmd->data->blksz,
 118                          cmd->data->blocks,
 119                          cmd->data->blocks * cmd->data->blksz);
 120         } else {
 121                 host->dbgmsg_dat[0] = '\0';
 122         }
 123 }
 124
 125 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 126                         int fail)
 127 {
 128         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 129
 130         if (!cmd)
 131                 return;
 132
 133         if (cmd->error == 0) {
 134                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 135                         host->dbgmsg_cmd, cmd->resp[0]);
 136         } else {
 137                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 138                         cmd->error, host->dbgmsg_cmd, host->status);
 139         }
 140
 141         if (!cmd->data)
 142                 return;
 143
 144         if (cmd->data->error == 0) {
 145                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 146         } else {
 147                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 148                         cmd->data->error, host->dbgmsg_dat,
 149                         readl(host->base + S3C2410_SDIDCNT));
 150         }
 151 }
 152 #else
 153 static void dbg_dumpcmd(struct s3cmci_host *host,
 154                         struct mmc_command *cmd, int fail) { }
 155
 156 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 157                            int stop) { }
 158
 159 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 160
 161 #endif /* CONFIG_MMC_DEBUG */
 162
 163 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 164 {
 165         u32 newmask;
 166
 167         newmask = readl(host->base + host->sdiimsk);
 168         newmask |= imask;
 169
 170         writel(newmask, host->base + host->sdiimsk);
 171
 172         return newmask;
 173 }
 174
 175 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 176 {
 177         u32 newmask;
 178
 179         newmask = readl(host->base + host->sdiimsk);
 180         newmask &= ~imask;
 181
 182         writel(newmask, host->base + host->sdiimsk);
 183
 184         return newmask;
 185 }
 186
 187 static inline void clear_imask(struct s3cmci_host *host)
 188 {
 189         writel(0, host->base + host->sdiimsk);
 190 }
 191
 192 static inline int get_data_buffer(struct s3cmci_host *host,
 193                                   u32 *words, u32 **pointer)
 194 {
 195         struct scatterlist *sg;
 196
 197         if (host->pio_active == XFER_NONE)
 198                 return -EINVAL;
 199
 200         if ((!host->mrq) || (!host->mrq->data))
 201                 return -EINVAL;
 202
 203         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 204                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 205                       host->pio_sgptr, host->mrq->data->sg_len);
 206                 return -EBUSY;
 207         }
 208         sg = &host->mrq->data->sg[host->pio_sgptr];
 209
 210         *words = sg->length >> 2;
 211         *pointer = sg_virt(sg);
 212
 213         host->pio_sgptr++;
 214
 215         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 216             host->pio_sgptr, host->mrq->data->sg_len);
 217
 218         return 0;
 219 }
 220
 221 static inline u32 fifo_count(struct s3cmci_host *host)
 222 {
 223         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 224
 225         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 226         return fifostat >> 2;
 227 }
 228
 229 static inline u32 fifo_free(struct s3cmci_host *host)
 230 {
 231         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 232
 233         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 234         return (63 - fifostat) >> 2;
 235 }
 236
 237 static void do_pio_read(struct s3cmci_host *host)
 238 {
 239         int res;
 240         u32 fifo;
 241         void __iomem *from_ptr;
 242
 243         /* write real prescaler to host, it might be set slow to fix */
 244         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 245
 246         from_ptr = host->base + host->sdidata;
 247
 248         while ((fifo = fifo_count(host))) {
 249                 if (!host->pio_words) {
 250                         res = get_data_buffer(host, &host->pio_words,
 251                                               &host->pio_ptr);
 252                         if (res) {
 253                                 host->pio_active = XFER_NONE;
 254                                 host->complete_what = COMPLETION_FINALIZE;
 255
 256                                 dbg(host, dbg_pio, "pio_read(): "
 257                                     "complete (no more data).\n");
 258                                 return;
 259                         }
 260
 261                         dbg(host, dbg_pio,
 262                             "pio_read(): new target: [%i]@[%p]\n",
 263                             host->pio_words, host->pio_ptr);
 264                 }
 265
 266                 dbg(host, dbg_pio,
 267                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 268                     fifo, host->pio_words,
 269                     readl(host->base + S3C2410_SDIDCNT));
 270
 271                 if (fifo > host->pio_words)
 272                         fifo = host->pio_words;
 273
 274                 host->pio_words -= fifo;
 275                 host->pio_count += fifo;
 276
 277                 while (fifo--)
 278                         *(host->pio_ptr++) = readl(from_ptr);
 279         }
 280
 281         if (!host->pio_words) {
 282                 res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
 283                 if (res) {
 284                         dbg(host, dbg_pio,
 285                             "pio_read(): complete (no more buffers).\n");
 286                         host->pio_active = XFER_NONE;
 287                         host->complete_what = COMPLETION_FINALIZE;
 288
 289                         return;
 290                 }
 291         }
 292
 293         enable_imask(host,
 294                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 295 }
 296
 297 static void do_pio_write(struct s3cmci_host *host)
 298 {
 299         void __iomem *to_ptr;
 300         int res;
 301         u32 fifo;
 302
 303         to_ptr = host->base + host->sdidata;
 304
 305         while ((fifo = fifo_free(host))) {
 306                 if (!host->pio_words) {
 307                         res = get_data_buffer(host, &host->pio_words,
 308                                                         &host->pio_ptr);
 309                         if (res) {
 310                                 dbg(host, dbg_pio,
 311                                     "pio_write(): complete (no more data).\n");
 312                                 host->pio_active = XFER_NONE;
 313
 314                                 return;
 315                         }
 316
 317                         dbg(host, dbg_pio,
 318                             "pio_write(): new source: [%i]@[%p]\n",
 319                             host->pio_words, host->pio_ptr);
 320
 321                 }
 322
 323                 if (fifo > host->pio_words)
 324                         fifo = host->pio_words;
 325
 326                 host->pio_words -= fifo;
 327                 host->pio_count += fifo;
 328
 329                 while (fifo--)
 330                         writel(*(host->pio_ptr++), to_ptr);
 331         }
 332
 333         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 334 }
 335
 336 static void pio_tasklet(unsigned long data)
 337 {
 338         struct s3cmci_host *host = (struct s3cmci_host *) data;
 339
 340
 341         disable_irq(host->irq);
 342
 343         if (host->pio_active == XFER_WRITE)
 344                 do_pio_write(host);
 345
 346         if (host->pio_active == XFER_READ)
 347                 do_pio_read(host);
 348
 349         if (host->complete_what == COMPLETION_FINALIZE) {
 350                 clear_imask(host);
 351                 if (host->pio_active != XFER_NONE) {
 352                         dbg(host, dbg_err, "unfinished %s "
 353                             "- pio_count:[%u] pio_words:[%u]\n",
 354                             (host->pio_active == XFER_READ) ? "read" : "write",
 355                             host->pio_count, host->pio_words);
 356
 357                         if (host->mrq->data)
 358                                 host->mrq->data->error = -EINVAL;
 359                 }
 360
 361                 finalize_request(host);
 362         } else
 363                 enable_irq(host->irq);
 364 }
 365
 366 /*
 367  * ISR for SDI Interface IRQ
 368  * Communication between driver and ISR works as follows:
 369  *   host->mrq                  points to current request
 370  *   host->complete_what        Indicates when the request is considered done
 371  *     COMPLETION_CMDSENT         when the command was sent
 372  *     COMPLETION_RSPFIN          when a response was received
 373  *     COMPLETION_XFERFINISH      when the data transfer is finished
 374  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 375  *   host->complete_request     is the completion-object the driver waits for
 376  *
 377  * 1) Driver sets up host->mrq and host->complete_what
 378  * 2) Driver prepares the transfer
 379  * 3) Driver enables interrupts
 380  * 4) Driver starts transfer
 381  * 5) Driver waits for host->complete_rquest
 382  * 6) ISR checks for request status (errors and success)
 383  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 384  * 7) ISR completes host->complete_request
 385  * 8) ISR disables interrupts
 386  * 9) Driver wakes up and takes care of the request
 387  *
 388  * Note: "->error"-fields are expected to be set to 0 before the request
 389  *       was issued by mmc.c - therefore they are only set, when an error
 390  *       contition comes up
 391  */
 392
 393 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 394 {
 395         struct s3cmci_host *host = dev_id;
 396         struct mmc_command *cmd;
 397         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 398         u32 mci_cclear, mci_dclear;
 399         unsigned long iflags;
 400
 401         spin_lock_irqsave(&host->complete_lock, iflags);
 402
 403         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 404         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 405         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 406         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 407         mci_imsk = readl(host->base + host->sdiimsk);
 408         mci_cclear = 0;
 409         mci_dclear = 0;
 410
 411         if ((host->complete_what == COMPLETION_NONE) ||
 412             (host->complete_what == COMPLETION_FINALIZE)) {
 413                 host->status = "nothing to complete";
 414                 clear_imask(host);
 415                 goto irq_out;
 416         }
 417
 418         if (!host->mrq) {
 419                 host->status = "no active mrq";
 420                 clear_imask(host);
 421                 goto irq_out;
 422         }
 423
 424         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 425
 426         if (!cmd) {
 427                 host->status = "no active cmd";
 428                 clear_imask(host);
 429                 goto irq_out;
 430         }
 431
 432         if (!host->dodma) {
 433                 if ((host->pio_active == XFER_WRITE) &&
 434                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 435
 436                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 437                         tasklet_schedule(&host->pio_tasklet);
 438                         host->status = "pio tx";
 439                 }
 440
 441                 if ((host->pio_active == XFER_READ) &&
 442                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 443
 444                         disable_imask(host,
 445                                       S3C2410_SDIIMSK_RXFIFOHALF |
 446                                       S3C2410_SDIIMSK_RXFIFOLAST);
 447
 448                         tasklet_schedule(&host->pio_tasklet);
 449                         host->status = "pio rx";
 450                 }
 451         }
 452
 453         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 454                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 455                 cmd->error = -ETIMEDOUT;
 456                 host->status = "error: command timeout";
 457                 goto fail_transfer;
 458         }
 459
 460         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 461                 if (host->complete_what == COMPLETION_CMDSENT) {
 462                         host->status = "ok: command sent";
 463                         goto close_transfer;
 464                 }
 465
 466                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 467         }
 468
 469         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 470                 if (cmd->flags & MMC_RSP_CRC) {
 471                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 472                                 dbg(host, dbg_irq,
 473                                     "fixup: ignore CRC fail with long rsp\n");
 474                         } else {
 475                                 /* note, we used to fail the transfer
 476                                  * here, but it seems that this is just
 477                                  * the hardware getting it wrong.
 478                                  *
 479                                  * cmd->error = -EILSEQ;
 480                                  * host->status = "error: bad command crc";
 481                                  * goto fail_transfer;
 482                                 */
 483                         }
 484                 }
 485
 486                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 487         }
 488
 489         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 490                 if (host->complete_what == COMPLETION_RSPFIN) {
 491                         host->status = "ok: command response received";
 492                         goto close_transfer;
 493                 }
 494
 495                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 496                         host->complete_what = COMPLETION_XFERFINISH;
 497
 498                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 499         }
 500
 501         /* errors handled after this point are only relevant
 502            when a data transfer is in progress */
 503
 504         if (!cmd->data)
 505                 goto clear_status_bits;
 506
 507         /* Check for FIFO failure */
 508         if (host->is2440) {
 509                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 510                         dbg(host, dbg_err, "FIFO failure\n");
 511                         host->mrq->data->error = -EILSEQ;
 512                         host->status = "error: 2440 fifo failure";
 513                         goto fail_transfer;
 514                 }
 515         } else {
 516                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 517                         dbg(host, dbg_err, "FIFO failure\n");
 518                         cmd->data->error = -EILSEQ;
 519                         host->status = "error:  fifo failure";
 520                         goto fail_transfer;
 521                 }
 522         }
 523
 524         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 525                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 526                 cmd->data->error = -EILSEQ;
 527                 host->status = "error: bad data crc (outgoing)";
 528                 goto fail_transfer;
 529         }
 530
 531         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 532                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 533                 cmd->data->error = -EILSEQ;
 534                 host->status = "error: bad data crc (incoming)";
 535                 goto fail_transfer;
 536         }
 537
 538         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 539                 dbg(host, dbg_err, "data timeout\n");
 540                 cmd->data->error = -ETIMEDOUT;
 541                 host->status = "error: data timeout";
 542                 goto fail_transfer;
 543         }
 544
 545         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 546                 if (host->complete_what == COMPLETION_XFERFINISH) {
 547                         host->status = "ok: data transfer completed";
 548                         goto close_transfer;
 549                 }
 550
 551                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 552                         host->complete_what = COMPLETION_RSPFIN;
 553
 554                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 555         }
 556
 557 clear_status_bits:
 558         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 559         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 560
 561         goto irq_out;
 562
 563 fail_transfer:
 564         host->pio_active = XFER_NONE;
 565
 566 close_transfer:
 567         host->complete_what = COMPLETION_FINALIZE;
 568
 569         clear_imask(host);
 570         tasklet_schedule(&host->pio_tasklet);
 571
 572         goto irq_out;
 573
 574 irq_out:
 575         dbg(host, dbg_irq,
 576             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 577             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 578
 579         spin_unlock_irqrestore(&host->complete_lock, iflags);
 580         return IRQ_HANDLED;
 581
 582 }
 583
 584 /*
 585  * ISR for the CardDetect Pin
 586 */
 587
 588 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
 589 {
 590         struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
 591
 592         dbg(host, dbg_irq, "card detect\n");
 593
 594         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 595
 596         return IRQ_HANDLED;
 597 }
 598
 599 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
 600                                      void *buf_id, int size,
 601                                      enum s3c2410_dma_buffresult result)
 602 {
 603         struct s3cmci_host *host = buf_id;
 604         unsigned long iflags;
 605         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
 606
 607         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 608         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 609         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 610         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 611
 612         BUG_ON(!host->mrq);
 613         BUG_ON(!host->mrq->data);
 614         BUG_ON(!host->dmatogo);
 615
 616         spin_lock_irqsave(&host->complete_lock, iflags);
 617
 618         if (result != S3C2410_RES_OK) {
 619                 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
 620                         "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
 621                         mci_csta, mci_dsta, mci_fsta,
 622                         mci_dcnt, result, host->dmatogo);
 623
 624                 goto fail_request;
 625         }
 626
 627         host->dmatogo--;
 628         if (host->dmatogo) {
 629                 dbg(host, dbg_dma, "DMA DONE  Size:%i DSTA:[%08x] "
 630                         "DCNT:[%08x] toGo:%u\n",
 631                         size, mci_dsta, mci_dcnt, host->dmatogo);
 632
 633                 goto out;
 634         }
 635
 636         dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
 637                 size, mci_dsta, mci_dcnt);
 638
 639         host->complete_what = COMPLETION_FINALIZE;
 640
 641 out:
 642         tasklet_schedule(&host->pio_tasklet);
 643         spin_unlock_irqrestore(&host->complete_lock, iflags);
 644         return;
 645
 646 fail_request:
 647         host->mrq->data->error = -EINVAL;
 648         host->complete_what = COMPLETION_FINALIZE;
 649         writel(0, host->base + host->sdiimsk);
 650         goto out;
 651
 652 }
 653
 654 static void finalize_request(struct s3cmci_host *host)
 655 {
 656         struct mmc_request *mrq = host->mrq;
 657         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 658         int debug_as_failure = 0;
 659
 660         if (host->complete_what != COMPLETION_FINALIZE)
 661                 return;
 662
 663         if (!mrq)
 664                 return;
 665
 666         if (cmd->data && (cmd->error == 0) &&
 667             (cmd->data->error == 0)) {
 668                 if (host->dodma && (!host->dma_complete)) {
 669                         dbg(host, dbg_dma, "DMA Missing!\n");
 670                         return;
 671                 }
 672         }
 673
 674         /* Read response from controller. */
 675         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 676         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 677         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 678         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 679
 680         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 681
 682         if (cmd->error)
 683                 debug_as_failure = 1;
 684
 685         if (cmd->data && cmd->data->error)
 686                 debug_as_failure = 1;
 687
 688         dbg_dumpcmd(host, cmd, debug_as_failure);
 689
 690         /* Cleanup controller */
 691         writel(0, host->base + S3C2410_SDICMDARG);
 692         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 693         writel(0, host->base + S3C2410_SDICMDCON);
 694         writel(0, host->base + host->sdiimsk);
 695
 696         if (cmd->data && cmd->error)
 697                 cmd->data->error = cmd->error;
 698
 699         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 700                 host->cmd_is_stop = 1;
 701                 s3cmci_send_request(host->mmc);
 702                 return;
 703         }
 704
 705         /* If we have no data transfer we are finished here */
 706         if (!mrq->data)
 707                 goto request_done;
 708
 709         /* Calulate the amout of bytes transfer if there was no error */
 710         if (mrq->data->error == 0) {
 711                 mrq->data->bytes_xfered =
 712                         (mrq->data->blocks * mrq->data->blksz);
 713         } else {
 714                 mrq->data->bytes_xfered = 0;
 715         }
 716
 717         /* If we had an error while transfering data we flush the
 718          * DMA channel and the fifo to clear out any garbage. */
 719         if (mrq->data->error != 0) {
 720                 if (host->dodma)
 721                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 722
 723                 if (host->is2440) {
 724                         /* Clear failure register and reset fifo. */
 725                         writel(S3C2440_SDIFSTA_FIFORESET |
 726                                S3C2440_SDIFSTA_FIFOFAIL,
 727                                host->base + S3C2410_SDIFSTA);
 728                 } else {
 729                         u32 mci_con;
 730
 731                         /* reset fifo */
 732                         mci_con = readl(host->base + S3C2410_SDICON);
 733                         mci_con |= S3C2410_SDICON_FIFORESET;
 734
 735                         writel(mci_con, host->base + S3C2410_SDICON);
 736                 }
 737         }
 738
 739 request_done:
 740         host->complete_what = COMPLETION_NONE;
 741         host->mrq = NULL;
 742         mmc_request_done(host->mmc, mrq);
 743 }
 744
 745 static void s3cmci_dma_setup(struct s3cmci_host *host,
 746                              enum s3c2410_dmasrc source)
 747 {
 748         static enum s3c2410_dmasrc last_source = -1;
 749         static int setup_ok;
 750
 751         if (last_source == source)
 752                 return;
 753
 754         last_source = source;
 755
 756         s3c2410_dma_devconfig(host->dma, source, 3,
 757                               host->mem->start + host->sdidata);
 758
 759         if (!setup_ok) {
 760                 s3c2410_dma_config(host->dma, 4,
 761                         (S3C2410_DCON_HWTRIG | S3C2410_DCON_CH0_SDI));
 762                 s3c2410_dma_set_buffdone_fn(host->dma,
 763                                             s3cmci_dma_done_callback);
 764                 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
 765                 setup_ok = 1;
 766         }
 767 }
 768
 769 static void s3cmci_send_command(struct s3cmci_host *host,
 770                                         struct mmc_command *cmd)
 771 {
 772         u32 ccon, imsk;
 773
 774         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 775                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 776                 S3C2410_SDIIMSK_RESPONSECRC;
 777
 778         enable_imask(host, imsk);
 779
 780         if (cmd->data)
 781                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 782         else if (cmd->flags & MMC_RSP_PRESENT)
 783                 host->complete_what = COMPLETION_RSPFIN;
 784         else
 785                 host->complete_what = COMPLETION_CMDSENT;
 786
 787         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 788
 789         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 790         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 791
 792         if (cmd->flags & MMC_RSP_PRESENT)
 793                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 794
 795         if (cmd->flags & MMC_RSP_136)
 796                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 797
 798         writel(ccon, host->base + S3C2410_SDICMDCON);
 799 }
 800
 801 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 802 {
 803         u32 dcon, imsk, stoptries = 3;
 804
 805         /* write DCON register */
 806
 807         if (!data) {
 808                 writel(0, host->base + S3C2410_SDIDCON);
 809                 return 0;
 810         }
 811
 812         if ((data->blksz & 3) != 0) {
 813                 /* We cannot deal with unaligned blocks with more than
 814                  * one block being transfered. */
 815
 816                 if (data->blocks > 1)
 817                         return -EINVAL;
 818
 819                 /* No support yet for non-word block transfers. */
 820                 return -EINVAL;
 821         }
 822
 823         while (readl(host->base + S3C2410_SDIDSTA) &
 824                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 825
 826                 dbg(host, dbg_err,
 827                     "mci_setup_data() transfer stillin progress.\n");
 828
 829                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 830                 s3cmci_reset(host);
 831
 832                 if ((stoptries--) == 0) {
 833                         dbg_dumpregs(host, "DRF");
 834                         return -EINVAL;
 835                 }
 836         }
 837
 838         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 839
 840         if (host->dodma)
 841                 dcon |= S3C2410_SDIDCON_DMAEN;
 842
 843         if (host->bus_width == MMC_BUS_WIDTH_4)
 844                 dcon |= S3C2410_SDIDCON_WIDEBUS;
 845
 846         if (!(data->flags & MMC_DATA_STREAM))
 847                 dcon |= S3C2410_SDIDCON_BLOCKMODE;
 848
 849         if (data->flags & MMC_DATA_WRITE) {
 850                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
 851                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
 852         }
 853
 854         if (data->flags & MMC_DATA_READ) {
 855                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
 856                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
 857         }
 858
 859         if (host->is2440) {
 860                 dcon |= S3C2440_SDIDCON_DS_WORD;
 861                 dcon |= S3C2440_SDIDCON_DATSTART;
 862         }
 863
 864         writel(dcon, host->base + S3C2410_SDIDCON);
 865
 866         /* write BSIZE register */
 867
 868         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
 869
 870         /* add to IMASK register */
 871         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
 872                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
 873
 874         enable_imask(host, imsk);
 875
 876         /* write TIMER register */
 877
 878         if (host->is2440) {
 879                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
 880         } else {
 881                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
 882
 883                 /* FIX: set slow clock to prevent timeouts on read */
 884                 if (data->flags & MMC_DATA_READ)
 885                         writel(0xFF, host->base + S3C2410_SDIPRE);
 886         }
 887
 888         return 0;
 889 }
 890
 891 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
 892
 893 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
 894 {
 895         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
 896
 897         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
 898
 899         host->pio_sgptr = 0;
 900         host->pio_words = 0;
 901         host->pio_count = 0;
 902         host->pio_active = rw ? XFER_WRITE : XFER_READ;
 903
 904         if (rw) {
 905                 do_pio_write(host);
 906                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 907         } else {
 908                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
 909                              | S3C2410_SDIIMSK_RXFIFOLAST);
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
 916 {
 917         int dma_len, i;
 918         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
 919
 920         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
 921
 922         s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
 923         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 924
 925         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 926                              (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 927
 928         if (dma_len == 0)
 929                 return -ENOMEM;
 930
 931         host->dma_complete = 0;
 932         host->dmatogo = dma_len;
 933
 934         for (i = 0; i < dma_len; i++) {
 935                 int res;
 936
 937                 dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
 938                         sg_dma_address(&data->sg[i]),
 939                         sg_dma_len(&data->sg[i]));
 940
 941                 res = s3c2410_dma_enqueue(host->dma, (void *) host,
 942                                           sg_dma_address(&data->sg[i]),
 943                                           sg_dma_len(&data->sg[i]));
 944
 945                 if (res) {
 946                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 947                         return -EBUSY;
 948                 }
 949         }
 950
 951         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
 952
 953         return 0;
 954 }
 955
 956 static void s3cmci_send_request(struct mmc_host *mmc)
 957 {
 958         struct s3cmci_host *host = mmc_priv(mmc);
 959         struct mmc_request *mrq = host->mrq;
 960         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 961
 962         host->ccnt++;
 963         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
 964
 965         /* Clear command, data and fifo status registers
 966            Fifo clear only necessary on 2440, but doesn't hurt on 2410
 967         */
 968         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
 969         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
 970         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
 971
 972         if (cmd->data) {
 973                 int res = s3cmci_setup_data(host, cmd->data);
 974
 975                 host->dcnt++;
 976
 977                 if (res) {
 978                         dbg(host, dbg_err, "setup data error %d\n", res);
 979                         cmd->error = res;
 980                         cmd->data->error = res;
 981
 982                         mmc_request_done(mmc, mrq);
 983                         return;
 984                 }
 985
 986                 if (host->dodma)
 987                         res = s3cmci_prepare_dma(host, cmd->data);
 988                 else
 989                         res = s3cmci_prepare_pio(host, cmd->data);
 990
 991                 if (res) {
 992                         dbg(host, dbg_err, "data prepare error %d\n", res);
 993                         cmd->error = res;
 994                         cmd->data->error = res;
 995
 996                         mmc_request_done(mmc, mrq);
 997                         return;
 998                 }
 999         }
1000
1001         /* Send command */
1002         s3cmci_send_command(host, cmd);
1003
1004         /* Enable Interrupt */
1005         enable_irq(host->irq);
1006 }
1007
1008 static int s3cmci_card_present(struct mmc_host *mmc)
1009 {
1010         struct s3cmci_host *host = mmc_priv(mmc);
1011         struct s3c24xx_mci_pdata *pdata = host->pdata;
1012         int ret;
1013
1014         if (pdata->gpio_detect == 0)
1015                 return -ENOSYS;
1016
1017         ret = s3c2410_gpio_getpin(pdata->gpio_detect) ? 0 : 1;
1018         return ret ^ pdata->detect_invert;
1019 }
1020
1021 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1022 {
1023         struct s3cmci_host *host = mmc_priv(mmc);
1024
1025         host->status = "mmc request";
1026         host->cmd_is_stop = 0;
1027         host->mrq = mrq;
1028
1029         if (s3cmci_card_present(mmc) == 0) {
1030                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1031                 host->mrq->cmd->error = -ENOMEDIUM;
1032                 mmc_request_done(mmc, mrq);
1033         } else
1034                 s3cmci_send_request(mmc);
1035 }
1036
1037 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1038 {
1039         u32 mci_psc;
1040
1041         /* Set clock */
1042         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1043                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1044
1045                 if (host->real_rate <= ios->clock)
1046                         break;
1047         }
1048
1049         if (mci_psc > 255)
1050                 mci_psc = 255;
1051
1052         host->prescaler = mci_psc;
1053         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1054
1055         /* If requested clock is 0, real_rate will be 0, too */
1056         if (ios->clock == 0)
1057                 host->real_rate = 0;
1058 }
1059
1060 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1061 {
1062         struct s3cmci_host *host = mmc_priv(mmc);
1063         u32 mci_con;
1064
1065         /* Set the power state */
1066
1067         mci_con = readl(host->base + S3C2410_SDICON);
1068
1069         switch (ios->power_mode) {
1070         case MMC_POWER_ON:
1071         case MMC_POWER_UP:
1072                 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK);
1073                 s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD);
1074                 s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0);
1075                 s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
1076                 s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2);
1077                 s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3);
1078
1079                 if (host->pdata->set_power)
1080                         host->pdata->set_power(ios->power_mode, ios->vdd);
1081
1082                 if (!host->is2440)
1083                         mci_con |= S3C2410_SDICON_FIFORESET;
1084
1085                 break;
1086
1087         case MMC_POWER_OFF:
1088         default:
1089                 s3c2410_gpio_setpin(S3C2410_GPE5, 0);
1090                 s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_OUTP);
1091
1092                 if (host->is2440)
1093                         mci_con |= S3C2440_SDICON_SDRESET;
1094
1095                 if (host->pdata->set_power)
1096                         host->pdata->set_power(ios->power_mode, ios->vdd);
1097
1098                 break;
1099         }
1100
1101         s3cmci_set_clk(host, ios);
1102
1103         /* Set CLOCK_ENABLE */
1104         if (ios->clock)
1105                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1106         else
1107                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1108
1109         writel(mci_con, host->base + S3C2410_SDICON);
1110
1111         if ((ios->power_mode == MMC_POWER_ON) ||
1112             (ios->power_mode == MMC_POWER_UP)) {
1113                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1114                         host->real_rate/1000, ios->clock/1000);
1115         } else {
1116                 dbg(host, dbg_conf, "powered down.\n");
1117         }
1118
1119         host->bus_width = ios->bus_width;
1120 }
1121
1122 static void s3cmci_reset(struct s3cmci_host *host)
1123 {
1124         u32 con = readl(host->base + S3C2410_SDICON);
1125
1126         con |= S3C2440_SDICON_SDRESET;
1127         writel(con, host->base + S3C2410_SDICON);
1128 }
1129
1130 static int s3cmci_get_ro(struct mmc_host *mmc)
1131 {
1132         struct s3cmci_host *host = mmc_priv(mmc);
1133         struct s3c24xx_mci_pdata *pdata = host->pdata;
1134         int ret;
1135
1136         if (pdata->gpio_wprotect == 0)
1137                 return 0;
1138
1139         ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
1140
1141         if (pdata->wprotect_invert)
1142                 ret = !ret;
1143
1144         return ret;
1145 }
1146
1147 static struct mmc_host_ops s3cmci_ops = {
1148         .request        = s3cmci_request,
1149         .set_ios        = s3cmci_set_ios,
1150         .get_ro         = s3cmci_get_ro,
1151         .get_cd         = s3cmci_card_present,
1152 };
1153
1154 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1155         /* This is currently here to avoid a number of if (host->pdata)
1156          * checks. Any zero fields to ensure reaonable defaults are picked. */
1157 };
1158
1159 #ifdef CONFIG_CPU_FREQ
1160
1161 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1162                                      unsigned long val, void *data)
1163 {
1164         struct s3cmci_host *host;
1165         struct mmc_host *mmc;
1166         unsigned long newclk;
1167         unsigned long flags;
1168
1169         host = container_of(nb, struct s3cmci_host, freq_transition);
1170         newclk = clk_get_rate(host->clk);
1171         mmc = host->mmc;
1172
1173         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1174             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1175                 spin_lock_irqsave(&mmc->lock, flags);
1176
1177                 host->clk_rate = newclk;
1178
1179                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1180                     mmc->ios.clock != 0)
1181                         s3cmci_set_clk(host, &mmc->ios);
1182
1183                 spin_unlock_irqrestore(&mmc->lock, flags);
1184         }
1185
1186         return 0;
1187 }
1188
1189 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1190 {
1191         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1192
1193         return cpufreq_register_notifier(&host->freq_transition,
1194                                          CPUFREQ_TRANSITION_NOTIFIER);
1195 }
1196
1197 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1198 {
1199         cpufreq_unregister_notifier(&host->freq_transition,
1200                                     CPUFREQ_TRANSITION_NOTIFIER);
1201 }
1202
1203 #else
1204 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1205 {
1206         return 0;
1207 }
1208
1209 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1210 {
1211 }
1212 #endif
1213
1214 static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440)
1215 {
1216         struct s3cmci_host *host;
1217         struct mmc_host *mmc;
1218         int ret;
1219
1220         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1221         if (!mmc) {
1222                 ret = -ENOMEM;
1223                 goto probe_out;
1224         }
1225
1226         host = mmc_priv(mmc);
1227         host->mmc       = mmc;
1228         host->pdev      = pdev;
1229         host->is2440    = is2440;
1230
1231         host->pdata = pdev->dev.platform_data;
1232         if (!host->pdata) {
1233                 pdev->dev.platform_data = &s3cmci_def_pdata;
1234                 host->pdata = &s3cmci_def_pdata;
1235         }
1236
1237         spin_lock_init(&host->complete_lock);
1238         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1239
1240         if (is2440) {
1241                 host->sdiimsk   = S3C2440_SDIIMSK;
1242                 host->sdidata   = S3C2440_SDIDATA;
1243                 host->clk_div   = 1;
1244         } else {
1245                 host->sdiimsk   = S3C2410_SDIIMSK;
1246                 host->sdidata   = S3C2410_SDIDATA;
1247                 host->clk_div   = 2;
1248         }
1249
1250         host->dodma             = 0;
1251         host->complete_what     = COMPLETION_NONE;
1252         host->pio_active        = XFER_NONE;
1253
1254         host->dma               = S3CMCI_DMA;
1255
1256         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1257         if (!host->mem) {
1258                 dev_err(&pdev->dev,
1259                         "failed to get io memory region resouce.\n");
1260
1261                 ret = -ENOENT;
1262                 goto probe_free_host;
1263         }
1264
1265         host->mem = request_mem_region(host->mem->start,
1266                                        RESSIZE(host->mem), pdev->name);
1267
1268         if (!host->mem) {
1269                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1270                 ret = -ENOENT;
1271                 goto probe_free_host;
1272         }
1273
1274         host->base = ioremap(host->mem->start, RESSIZE(host->mem));
1275         if (!host->base) {
1276                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1277                 ret = -EINVAL;
1278                 goto probe_free_mem_region;
1279         }
1280
1281         host->irq = platform_get_irq(pdev, 0);
1282         if (host->irq == 0) {
1283                 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1284                 ret = -EINVAL;
1285                 goto probe_iounmap;
1286         }
1287
1288         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1289                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1290                 ret = -ENOENT;
1291                 goto probe_iounmap;
1292         }
1293
1294         /* We get spurious interrupts even when we have set the IMSK
1295          * register to ignore everything, so use disable_irq() to make
1296          * ensure we don't lock the system with un-serviceable requests. */
1297
1298         disable_irq(host->irq);
1299
1300         host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
1301
1302         if (host->irq_cd >= 0) {
1303                 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1304                                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1305                                 DRIVER_NAME, host)) {
1306                         dev_err(&pdev->dev, "can't get card detect irq.\n");
1307                         ret = -ENOENT;
1308                         goto probe_free_irq;
1309                 }
1310         } else {
1311                 dev_warn(&pdev->dev, "host detect has no irq available\n");
1312                 s3c2410_gpio_cfgpin(host->pdata->gpio_detect,
1313                                     S3C2410_GPIO_INPUT);
1314         }
1315
1316         if (host->pdata->gpio_wprotect)
1317                 s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect,
1318                                     S3C2410_GPIO_INPUT);
1319
1320         if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) {
1321                 dev_err(&pdev->dev, "unable to get DMA channel.\n");
1322                 ret = -EBUSY;
1323                 goto probe_free_irq_cd;
1324         }
1325
1326         host->clk = clk_get(&pdev->dev, "sdi");
1327         if (IS_ERR(host->clk)) {
1328                 dev_err(&pdev->dev, "failed to find clock source.\n");
1329                 ret = PTR_ERR(host->clk);
1330                 host->clk = NULL;
1331                 goto probe_free_host;
1332         }
1333
1334         ret = clk_enable(host->clk);
1335         if (ret) {
1336                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1337                 goto clk_free;
1338         }
1339
1340         host->clk_rate = clk_get_rate(host->clk);
1341
1342         mmc->ops        = &s3cmci_ops;
1343         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1344         mmc->caps       = MMC_CAP_4_BIT_DATA;
1345         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1346         mmc->f_max      = host->clk_rate / host->clk_div;
1347
1348         if (host->pdata->ocr_avail)
1349                 mmc->ocr_avail = host->pdata->ocr_avail;
1350
1351         mmc->max_blk_count      = 4095;
1352         mmc->max_blk_size       = 4095;
1353         mmc->max_req_size       = 4095 * 512;
1354         mmc->max_seg_size       = mmc->max_req_size;
1355
1356         mmc->max_phys_segs      = 128;
1357         mmc->max_hw_segs        = 128;
1358
1359         dbg(host, dbg_debug,
1360             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1361             (host->is2440?"2440":""),
1362             host->base, host->irq, host->irq_cd, host->dma);
1363
1364         ret = s3cmci_cpufreq_register(host);
1365         if (ret) {
1366                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1367                 goto free_dmabuf;
1368         }
1369
1370         ret = mmc_add_host(mmc);
1371         if (ret) {
1372                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1373                 goto free_cpufreq;
1374         }
1375
1376         platform_set_drvdata(pdev, mmc);
1377         dev_info(&pdev->dev, "initialisation done.\n");
1378
1379         return 0;
1380
1381  free_cpufreq:
1382         s3cmci_cpufreq_deregister(host);
1383
1384  free_dmabuf:
1385         clk_disable(host->clk);
1386
1387  clk_free:
1388         clk_put(host->clk);
1389
1390  probe_free_irq_cd:
1391         if (host->irq_cd >= 0)
1392                 free_irq(host->irq_cd, host);
1393
1394  probe_free_irq:
1395         free_irq(host->irq, host);
1396
1397  probe_iounmap:
1398         iounmap(host->base);
1399
1400  probe_free_mem_region:
1401         release_mem_region(host->mem->start, RESSIZE(host->mem));
1402
1403  probe_free_host:
1404         mmc_free_host(mmc);
1405  probe_out:
1406         return ret;
1407 }
1408
1409 static void s3cmci_shutdown(struct platform_device *pdev)
1410 {
1411         struct mmc_host *mmc = platform_get_drvdata(pdev);
1412         struct s3cmci_host *host = mmc_priv(mmc);
1413
1414         if (host->irq_cd >= 0)
1415                 free_irq(host->irq_cd, host);
1416
1417         s3cmci_cpufreq_deregister(host);
1418         mmc_remove_host(mmc);
1419         clk_disable(host->clk);
1420 }
1421
1422 static int __devexit s3cmci_remove(struct platform_device *pdev)
1423 {
1424         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1425         struct s3cmci_host      *host = mmc_priv(mmc);
1426
1427         s3cmci_shutdown(pdev);
1428
1429         clk_put(host->clk);
1430
1431         tasklet_disable(&host->pio_tasklet);
1432         s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
1433
1434         free_irq(host->irq, host);
1435
1436         iounmap(host->base);
1437         release_mem_region(host->mem->start, RESSIZE(host->mem));
1438
1439         mmc_free_host(mmc);
1440         return 0;
1441 }
1442
1443 static int __devinit s3cmci_2410_probe(struct platform_device *dev)
1444 {
1445         return s3cmci_probe(dev, 0);
1446 }
1447
1448 static int __devinit s3cmci_2412_probe(struct platform_device *dev)
1449 {
1450         return s3cmci_probe(dev, 1);
1451 }
1452
1453 static int __devinit s3cmci_2440_probe(struct platform_device *dev)
1454 {
1455         return s3cmci_probe(dev, 1);
1456 }
1457
1458 #ifdef CONFIG_PM
1459
1460 static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
1461 {
1462         struct mmc_host *mmc = platform_get_drvdata(dev);
1463
1464         return  mmc_suspend_host(mmc, state);
1465 }
1466
1467 static int s3cmci_resume(struct platform_device *dev)
1468 {
1469         struct mmc_host *mmc = platform_get_drvdata(dev);
1470
1471         return mmc_resume_host(mmc);
1472 }
1473
1474 #else /* CONFIG_PM */
1475 #define s3cmci_suspend NULL
1476 #define s3cmci_resume NULL
1477 #endif /* CONFIG_PM */
1478
1479
1480 static struct platform_driver s3cmci_2410_driver = {
1481         .driver.name    = "s3c2410-sdi",
1482         .driver.owner   = THIS_MODULE,
1483         .probe          = s3cmci_2410_probe,
1484         .remove         = __devexit_p(s3cmci_remove),
1485         .shutdown       = s3cmci_shutdown,
1486         .suspend        = s3cmci_suspend,
1487         .resume         = s3cmci_resume,
1488 };
1489
1490 static struct platform_driver s3cmci_2412_driver = {
1491         .driver.name    = "s3c2412-sdi",
1492         .driver.owner   = THIS_MODULE,
1493         .probe          = s3cmci_2412_probe,
1494         .remove         = __devexit_p(s3cmci_remove),
1495         .shutdown       = s3cmci_shutdown,
1496         .suspend        = s3cmci_suspend,
1497         .resume         = s3cmci_resume,
1498 };
1499
1500 static struct platform_driver s3cmci_2440_driver = {
1501         .driver.name    = "s3c2440-sdi",
1502         .driver.owner   = THIS_MODULE,
1503         .probe          = s3cmci_2440_probe,
1504         .remove         = __devexit_p(s3cmci_remove),
1505         .shutdown       = s3cmci_shutdown,
1506         .suspend        = s3cmci_suspend,
1507         .resume         = s3cmci_resume,
1508 };
1509
1510
1511 static int __init s3cmci_init(void)
1512 {
1513         platform_driver_register(&s3cmci_2410_driver);
1514         platform_driver_register(&s3cmci_2412_driver);
1515         platform_driver_register(&s3cmci_2440_driver);
1516         return 0;
1517 }
1518
1519 static void __exit s3cmci_exit(void)
1520 {
1521         platform_driver_unregister(&s3cmci_2410_driver);
1522         platform_driver_unregister(&s3cmci_2412_driver);
1523         platform_driver_unregister(&s3cmci_2440_driver);
1524 }
1525
1526 module_init(s3cmci_init);
1527 module_exit(s3cmci_exit);
1528
1529 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1530 MODULE_LICENSE("GPL v2");
1531 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>");
1532 MODULE_ALIAS("platform:s3c2410-sdi");
1533 MODULE_ALIAS("platform:s3c2412-sdi");
1534 MODULE_ALIAS("platform:s3c2440-sdi");