drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <asm/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <asm/hardware.h>
  32 #include <asm/arch/board.h>
  33 #include <asm/arch/mmc.h>
  34 #include <asm/arch/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1<<26)
  55 #define VS30                    (1<<25)
  56 #define SDVS18                  (0x5<<9)
  57 #define SDVS30                  (0x6<<9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1<<8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1<<2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define INT_EN_MASK             0x307F0033
  68 #define INIT_STREAM             (1<<1)
  69 #define DP_SELECT               (1<<21)
  70 #define DDIR                    (1<<4)
  71 #define DMA_EN                  0x1
  72 #define MSBS                    1<<5
  73 #define BCE                     1<<1
  74 #define FOUR_BIT                1 << 1
  75 #define CC                      0x1
  76 #define TC                      0x02
  77 #define OD                      0x1
  78 #define ERR                     (1 << 15)
  79 #define CMD_TIMEOUT             (1 << 16)
  80 #define DATA_TIMEOUT            (1 << 20)
  81 #define CMD_CRC                 (1 << 17)
  82 #define DATA_CRC                (1 << 21)
  83 #define CARD_ERR                (1 << 28)
  84 #define STAT_CLEAR              0xFFFFFFFF
  85 #define INIT_STREAM_CMD         0x00000000
  86 #define DUAL_VOLT_OCR_BIT       7
  87 #define SRC                     (1 << 25)
  88
  89 #define OMAP_MMC1_DEVID         1
  90 #define OMAP_MMC2_DEVID         2
  91 #define OMAP_MMC_DATADIR_NONE   0
  92 #define OMAP_MMC_DATADIR_READ   1
  93 #define OMAP_MMC_DATADIR_WRITE  2
  94 #define MMC_TIMEOUT_MS          20
  95 #define OMAP_MMC_MASTER_CLOCK   96000000
  96 #define DRIVER_NAME             "mmci-omap"
  97 /*
  98  * slot_id is device id - 1, device id is a static value
  99  * of 1 to represent device 1 etc..
 100  */
 101 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 102
 103 /*
 104  * MMC Host controller read/write API's
 105  */
 106 #define OMAP_HSMMC_READ(base, reg)      \
 107         __raw_readl((base) + OMAP_HSMMC_##reg)
 108
 109 #define OMAP_HSMMC_WRITE(base, reg, val) \
 110         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 111
 112 struct mmc_omap_host {
 113         struct  device          *dev;
 114         struct  mmc_host        *mmc;
 115         struct  mmc_request     *mrq;
 116         struct  mmc_command     *cmd;
 117         struct  mmc_data        *data;
 118         struct  clk             *fclk;
 119         struct  clk             *iclk;
 120         struct  clk             *dbclk;
 121         struct  semaphore       sem;
 122         struct  work_struct     mmc_carddetect_work;
 123         void    __iomem         *base;
 124         resource_size_t         mapbase;
 125         unsigned int            id;
 126         unsigned int            dma_len;
 127         unsigned int            dma_dir;
 128         unsigned char           bus_mode;
 129         unsigned char           datadir;
 130         u32                     *buffer;
 131         u32                     bytesleft;
 132         int                     suspended;
 133         int                     irq;
 134         int                     carddetect;
 135         int                     use_dma, dma_ch;
 136         int                     initstr;
 137         int                     slot_id;
 138         int                     dbclk_enabled;
 139         struct  omap_mmc_platform_data  *pdata;
 140 };
 141
 142 /*
 143  * Stop clock to the card
 144  */
 145 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 146 {
 147         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 148                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 149         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 150                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 151 }
 152
 153 /*
 154  * Send init stream sequence to card
 155  * before sending IDLE command
 156  */
 157 static void send_init_stream(struct mmc_omap_host *host)
 158 {
 159         int reg = 0;
 160         unsigned long timeout;
 161
 162         disable_irq(host->irq);
 163         OMAP_HSMMC_WRITE(host->base, CON,
 164                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 165         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 166
 167         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 168         while ((reg != CC) && time_before(jiffies, timeout))
 169                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 170
 171         OMAP_HSMMC_WRITE(host->base, CON,
 172                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 173         enable_irq(host->irq);
 174 }
 175
 176 /*
 177  * Configure the response type and send the cmd.
 178  */
 179 static void
 180 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 181         struct mmc_data *data)
 182 {
 183         int cmdreg = 0, resptype = 0, cmdtype = 0;
 184
 185         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 186                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 187         host->cmd = cmd;
 188
 189         /*
 190          * Clear status bits and enable interrupts
 191          */
 192         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 193         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 194         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 195
 196         if (cmd->flags & MMC_RSP_PRESENT) {
 197                 if (cmd->flags & MMC_RSP_136)
 198                         resptype = 1;
 199                 else
 200                         resptype = 2;
 201         }
 202
 203         /*
 204          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 205          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 206          */
 207         if (cmd->opcode == 12)
 208                 cmdtype = 0x3;
 209
 210         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 211
 212         if (data) {
 213                 cmdreg |= DP_SELECT | MSBS | BCE;
 214                 if (data->flags & MMC_DATA_READ)
 215                         cmdreg |= DDIR;
 216                 else
 217                         cmdreg &= ~(DDIR);
 218         }
 219
 220         if (host->use_dma)
 221                 cmdreg |= DMA_EN;
 222
 223         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 224         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 225 }
 226
 227 /*
 228  * Notify the transfer complete to MMC core
 229  */
 230 static void
 231 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 232 {
 233         host->data = NULL;
 234
 235         if (host->use_dma && host->dma_ch != -1)
 236                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 237                         host->dma_dir);
 238
 239         host->datadir = OMAP_MMC_DATADIR_NONE;
 240
 241         if (!data->error)
 242                 data->bytes_xfered += data->blocks * (data->blksz);
 243         else
 244                 data->bytes_xfered = 0;
 245
 246         if (!data->stop) {
 247                 host->mrq = NULL;
 248                 mmc_request_done(host->mmc, data->mrq);
 249                 return;
 250         }
 251         mmc_omap_start_command(host, data->stop, NULL);
 252 }
 253
 254 /*
 255  * Notify the core about command completion
 256  */
 257 static void
 258 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 259 {
 260         host->cmd = NULL;
 261
 262         if (cmd->flags & MMC_RSP_PRESENT) {
 263                 if (cmd->flags & MMC_RSP_136) {
 264                         /* response type 2 */
 265                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 266                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 267                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 268                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 269                 } else {
 270                         /* response types 1, 1b, 3, 4, 5, 6 */
 271                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 272                 }
 273         }
 274         if (host->data == NULL || cmd->error) {
 275                 host->mrq = NULL;
 276                 mmc_request_done(host->mmc, cmd->mrq);
 277         }
 278 }
 279
 280 /*
 281  * DMA clean up for command errors
 282  */
 283 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 284 {
 285         host->data->error = -ETIMEDOUT;
 286
 287         if (host->use_dma && host->dma_ch != -1) {
 288                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 289                         host->dma_dir);
 290                 omap_free_dma(host->dma_ch);
 291                 host->dma_ch = -1;
 292                 up(&host->sem);
 293         }
 294         host->data = NULL;
 295         host->datadir = OMAP_MMC_DATADIR_NONE;
 296 }
 297
 298 /*
 299  * MMC controller IRQ handler
 300  */
 301 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 302 {
 303         struct mmc_omap_host *host = dev_id;
 304         int end_cmd = 0, end_trans = 0, status;
 305
 306         if (host->cmd == NULL && host->data == NULL) {
 307                 OMAP_HSMMC_WRITE(host->base, STAT,
 308                         OMAP_HSMMC_READ(host->base, STAT));
 309                 return IRQ_HANDLED;
 310         }
 311
 312         status = OMAP_HSMMC_READ(host->base, STAT);
 313         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 314
 315         if (status & ERR) {
 316                 if ((status & CMD_TIMEOUT) ||
 317                         (status & CMD_CRC)) {
 318                         if (host->cmd) {
 319                                 if (status & CMD_TIMEOUT) {
 320                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 321                                                 OMAP_HSMMC_READ(host->base,
 322                                                                 SYSCTL) | SRC);
 323                                         while (OMAP_HSMMC_READ(host->base,
 324                                                                 SYSCTL) & SRC) ;
 325                                         host->cmd->error = -ETIMEDOUT;
 326                                 } else {
 327                                         host->cmd->error = -EILSEQ;
 328                                 }
 329                                 end_cmd = 1;
 330                         }
 331                         if (host->data)
 332                                 mmc_dma_cleanup(host);
 333                 }
 334                 if ((status & DATA_TIMEOUT) ||
 335                         (status & DATA_CRC)) {
 336                         if (host->data) {
 337                                 if (status & DATA_TIMEOUT)
 338                                         mmc_dma_cleanup(host);
 339                                 else
 340                                         host->data->error = -EILSEQ;
 341                                 end_trans = 1;
 342                         }
 343                 }
 344                 if (status & CARD_ERR) {
 345                         dev_dbg(mmc_dev(host->mmc),
 346                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 347                         if (host->cmd)
 348                                 end_cmd = 1;
 349                         if (host->data)
 350                                 end_trans = 1;
 351                 }
 352         }
 353
 354         OMAP_HSMMC_WRITE(host->base, STAT, status);
 355
 356         if (end_cmd || (status & CC))
 357                 mmc_omap_cmd_done(host, host->cmd);
 358         if (end_trans || (status & TC))
 359                 mmc_omap_xfer_done(host, host->data);
 360
 361         return IRQ_HANDLED;
 362 }
 363
 364 /*
 365  * Switch MMC operating voltage
 366  */
 367 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 368 {
 369         u32 reg_val = 0;
 370         int ret;
 371
 372         /* Disable the clocks */
 373         clk_disable(host->fclk);
 374         clk_disable(host->iclk);
 375         clk_disable(host->dbclk);
 376
 377         /* Turn the power off */
 378         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 379         if (ret != 0)
 380                 goto err;
 381
 382         /* Turn the power ON with given VDD 1.8 or 3.0v */
 383         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 384         if (ret != 0)
 385                 goto err;
 386
 387         clk_enable(host->fclk);
 388         clk_enable(host->iclk);
 389         clk_enable(host->dbclk);
 390
 391         OMAP_HSMMC_WRITE(host->base, HCTL,
 392                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 393         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 394         /*
 395          * If a MMC dual voltage card is detected, the set_ios fn calls
 396          * this fn with VDD bit set for 1.8V. Upon card removal from the
 397          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 398          *
 399          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 400          * set in HCTL.
 401          */
 402         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 403                                 ((1 << vdd) == MMC_VDD_33_34)))
 404                 reg_val |= SDVS30;
 405         if ((1 << vdd) == MMC_VDD_165_195)
 406                 reg_val |= SDVS18;
 407
 408         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 409
 410         OMAP_HSMMC_WRITE(host->base, HCTL,
 411                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 412
 413         return 0;
 414 err:
 415         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 416         return ret;
 417 }
 418
 419 /*
 420  * Work Item to notify the core about card insertion/removal
 421  */
 422 static void mmc_omap_detect(struct work_struct *work)
 423 {
 424         u16 vdd = 0;
 425         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 426                                                 mmc_carddetect_work);
 427
 428         if (host->carddetect) {
 429                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 430                         /*
 431                          * Set the VDD back to 3V when the card is removed
 432                          * before the set_ios fn turns off the power.
 433                          */
 434                         vdd = fls(host->mmc->ocr_avail) - 1;
 435                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 436                                 host->mmc->ios.vdd = vdd;
 437                 }
 438                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 439         } else
 440                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 441 }
 442
 443 /*
 444  * ISR for handling card insertion and removal
 445  */
 446 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 447 {
 448         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 449
 450         host->carddetect = mmc_slot(host).card_detect(irq);
 451         schedule_work(&host->mmc_carddetect_work);
 452
 453         return IRQ_HANDLED;
 454 }
 455
 456 /*
 457  * DMA call back function
 458  */
 459 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 460 {
 461         struct mmc_omap_host *host = data;
 462
 463         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 464                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 465
 466         if (host->dma_ch < 0)
 467                 return;
 468
 469         omap_free_dma(host->dma_ch);
 470         host->dma_ch = -1;
 471         /*
 472          * DMA Callback: run in interrupt context.
 473          * mutex_unlock will through a kernel warning if used.
 474          */
 475         up(&host->sem);
 476 }
 477
 478 /*
 479  * Configure dma src and destination parameters
 480  */
 481 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 482                                 struct mmc_data *data)
 483 {
 484         if (sync_dir == 0) {
 485                 omap_set_dma_dest_params(host->dma_ch, 0,
 486                         OMAP_DMA_AMODE_CONSTANT,
 487                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 488                 omap_set_dma_src_params(host->dma_ch, 0,
 489                         OMAP_DMA_AMODE_POST_INC,
 490                         sg_dma_address(&data->sg[0]), 0, 0);
 491         } else {
 492                 omap_set_dma_src_params(host->dma_ch, 0,
 493                         OMAP_DMA_AMODE_CONSTANT,
 494                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 495                 omap_set_dma_dest_params(host->dma_ch, 0,
 496                         OMAP_DMA_AMODE_POST_INC,
 497                         sg_dma_address(&data->sg[0]), 0, 0);
 498         }
 499         return 0;
 500 }
 501 /*
 502  * Routine to configure and start DMA for the MMC card
 503  */
 504 static int
 505 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 506 {
 507         int sync_dev, sync_dir = 0;
 508         int dma_ch = 0, ret = 0, err = 1;
 509         struct mmc_data *data = req->data;
 510
 511         /*
 512          * If for some reason the DMA transfer is still active,
 513          * we wait for timeout period and free the dma
 514          */
 515         if (host->dma_ch != -1) {
 516                 set_current_state(TASK_UNINTERRUPTIBLE);
 517                 schedule_timeout(100);
 518                 if (down_trylock(&host->sem)) {
 519                         omap_free_dma(host->dma_ch);
 520                         host->dma_ch = -1;
 521                         up(&host->sem);
 522                         return err;
 523                 }
 524         } else {
 525                 if (down_trylock(&host->sem))
 526                         return err;
 527         }
 528
 529         if (!(data->flags & MMC_DATA_WRITE)) {
 530                 host->dma_dir = DMA_FROM_DEVICE;
 531                 if (host->id == OMAP_MMC1_DEVID)
 532                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 533                 else
 534                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 535         } else {
 536                 host->dma_dir = DMA_TO_DEVICE;
 537                 if (host->id == OMAP_MMC1_DEVID)
 538                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 539                 else
 540                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 541         }
 542
 543         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 544                         host, &dma_ch);
 545         if (ret != 0) {
 546                 dev_dbg(mmc_dev(host->mmc),
 547                         "%s: omap_request_dma() failed with %d\n",
 548                         mmc_hostname(host->mmc), ret);
 549                 return ret;
 550         }
 551
 552         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 553                         data->sg_len, host->dma_dir);
 554         host->dma_ch = dma_ch;
 555
 556         if (!(data->flags & MMC_DATA_WRITE))
 557                 mmc_omap_config_dma_param(1, host, data);
 558         else
 559                 mmc_omap_config_dma_param(0, host, data);
 560
 561         if ((data->blksz % 4) == 0)
 562                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 563                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 564                         sync_dev, sync_dir);
 565         else
 566                 /* REVISIT: The MMC buffer increments only when MSB is written.
 567                  * Return error for blksz which is non multiple of four.
 568                  */
 569                 return -EINVAL;
 570
 571         omap_start_dma(dma_ch);
 572         return 0;
 573 }
 574
 575 /*
 576  * Configure block length for MMC/SD cards and initiate the transfer.
 577  */
 578 static int
 579 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 580 {
 581         int ret;
 582         host->data = req->data;
 583
 584         if (req->data == NULL) {
 585                 host->datadir = OMAP_MMC_DATADIR_NONE;
 586                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 587                 return 0;
 588         }
 589
 590         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 591                                         | (req->data->blocks << 16));
 592
 593         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 594                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 595
 596         if (host->use_dma) {
 597                 ret = mmc_omap_start_dma_transfer(host, req);
 598                 if (ret != 0) {
 599                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 600                         return ret;
 601                 }
 602         }
 603         return 0;
 604 }
 605
 606 /*
 607  * Request function. for read/write operation
 608  */
 609 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 610 {
 611         struct mmc_omap_host *host = mmc_priv(mmc);
 612
 613         WARN_ON(host->mrq != NULL);
 614         host->mrq = req;
 615         mmc_omap_prepare_data(host, req);
 616         mmc_omap_start_command(host, req->cmd, req->data);
 617 }
 618
 619
 620 /* Routine to configure clock values. Exposed API to core */
 621 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 622 {
 623         struct mmc_omap_host *host = mmc_priv(mmc);
 624         u16 dsor = 0;
 625         unsigned long regval;
 626         unsigned long timeout;
 627
 628         switch (ios->power_mode) {
 629         case MMC_POWER_OFF:
 630                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 631                 break;
 632         case MMC_POWER_UP:
 633                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 634                 break;
 635         }
 636
 637         switch (mmc->ios.bus_width) {
 638         case MMC_BUS_WIDTH_4:
 639                 OMAP_HSMMC_WRITE(host->base, HCTL,
 640                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 641                 break;
 642         case MMC_BUS_WIDTH_1:
 643                 OMAP_HSMMC_WRITE(host->base, HCTL,
 644                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 645                 break;
 646         }
 647
 648         if (host->id == OMAP_MMC1_DEVID) {
 649                 /* Only MMC1 can operate at 3V/1.8V */
 650                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 651                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 652                                 /*
 653                                  * The mmc_select_voltage fn of the core does
 654                                  * not seem to set the power_mode to
 655                                  * MMC_POWER_UP upon recalculating the voltage.
 656                                  * vdd 1.8v.
 657                                  */
 658                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 659                                         dev_dbg(mmc_dev(host->mmc),
 660                                                 "Switch operation failed\n");
 661                 }
 662         }
 663
 664         if (ios->clock) {
 665                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 666                 if (dsor < 1)
 667                         dsor = 1;
 668
 669                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 670                         dsor++;
 671
 672                 if (dsor > 250)
 673                         dsor = 250;
 674         }
 675         omap_mmc_stop_clock(host);
 676         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 677         regval = regval & ~(CLKD_MASK);
 678         regval = regval | (dsor << 6) | (DTO << 16);
 679         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 680         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 681                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 682
 683         /* Wait till the ICS bit is set */
 684         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 685         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 686                 && time_before(jiffies, timeout))
 687                 msleep(1);
 688
 689         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 690                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 691
 692         if (ios->power_mode == MMC_POWER_ON)
 693                 send_init_stream(host);
 694
 695         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 696                 OMAP_HSMMC_WRITE(host->base, CON,
 697                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 698 }
 699 /* NOTE: Read only switch not supported yet */
 700 static struct mmc_host_ops mmc_omap_ops = {
 701         .request = omap_mmc_request,
 702         .set_ios = omap_mmc_set_ios,
 703 };
 704
 705 static int __init omap_mmc_probe(struct platform_device *pdev)
 706 {
 707         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 708         struct mmc_host *mmc;
 709         struct mmc_omap_host *host = NULL;
 710         struct resource *res;
 711         int ret = 0, irq;
 712         u32 hctl, capa;
 713
 714         if (pdata == NULL) {
 715                 dev_err(&pdev->dev, "Platform Data is missing\n");
 716                 return -ENXIO;
 717         }
 718
 719         if (pdata->nr_slots == 0) {
 720                 dev_err(&pdev->dev, "No Slots\n");
 721                 return -ENXIO;
 722         }
 723
 724         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 725         irq = platform_get_irq(pdev, 0);
 726         if (res == NULL || irq < 0)
 727                 return -ENXIO;
 728
 729         res = request_mem_region(res->start, res->end - res->start + 1,
 730                                                         pdev->name);
 731         if (res == NULL)
 732                 return -EBUSY;
 733
 734         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 735         if (!mmc) {
 736                 ret = -ENOMEM;
 737                 goto err;
 738         }
 739
 740         host            = mmc_priv(mmc);
 741         host->mmc       = mmc;
 742         host->pdata     = pdata;
 743         host->use_dma   = 1;
 744         host->dma_ch    = -1;
 745         host->irq       = irq;
 746         host->id        = pdev->id;
 747         host->slot_id   = 0;
 748         host->mapbase   = res->start;
 749         host->base      = ioremap(host->mapbase, SZ_4K);
 750         mmc->ops        = &mmc_omap_ops;
 751         mmc->f_min      = 400000;
 752         mmc->f_max      = 52000000;
 753
 754         sema_init(&host->sem, 1);
 755
 756         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 757         if (IS_ERR(host->iclk)) {
 758                 ret = PTR_ERR(host->iclk);
 759                 host->iclk = NULL;
 760                 goto err;
 761         }
 762         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 763         if (IS_ERR(host->fclk)) {
 764                 ret = PTR_ERR(host->fclk);
 765                 host->fclk = NULL;
 766                 clk_put(host->iclk);
 767                 goto err;
 768         }
 769
 770         if (clk_enable(host->fclk) != 0)
 771                 goto err;
 772
 773         if (clk_enable(host->iclk) != 0) {
 774                 clk_disable(host->fclk);
 775                 clk_put(host->fclk);
 776                 goto err;
 777         }
 778
 779         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 780         /*
 781          * MMC can still work without debounce clock.
 782          */
 783         if (IS_ERR(host->dbclk))
 784                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 785         else
 786                 if (clk_enable(host->dbclk) != 0)
 787                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 788                                                         " clk failed\n");
 789                 else
 790                         host->dbclk_enabled = 1;
 791
 792 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 793         mmc->max_phys_segs = 1;
 794         mmc->max_hw_segs = 1;
 795 #endif
 796         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 797         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 798         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 799         mmc->max_seg_size = mmc->max_req_size;
 800
 801         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 802         mmc->caps |= MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
 803                                 MMC_CAP_SD_HIGHSPEED;
 804
 805         if (pdata->conf.wire4)
 806                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 807
 808         /* Only MMC1 supports 3.0V */
 809         if (host->id == OMAP_MMC1_DEVID) {
 810                 hctl = SDVS30;
 811                 capa = VS30 | VS18;
 812         } else {
 813                 hctl = SDVS18;
 814                 capa = VS18;
 815         }
 816
 817         OMAP_HSMMC_WRITE(host->base, HCTL,
 818                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 819
 820         OMAP_HSMMC_WRITE(host->base, CAPA,
 821                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 822
 823         /* Set the controller to AUTO IDLE mode */
 824         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 825                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 826
 827         /* Set SD bus power bit */
 828         OMAP_HSMMC_WRITE(host->base, HCTL,
 829                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 830
 831         /* Request IRQ for MMC operations */
 832         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name,
 833                          host);
 834         if (ret) {
 835                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
 836                 goto irq_err;
 837         }
 838
 839         /* Request IRQ for card detect */
 840         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
 841                 ret = request_irq(mmc_slot(host).card_detect_irq,
 842                                   omap_mmc_cd_handler, IRQF_DISABLED, "MMC CD",
 843                                   host);
 844                 if (ret) {
 845                         dev_dbg(mmc_dev(host->mmc),
 846                                 "Unable to grab MMC CD IRQ");
 847                         free_irq(host->irq, host);
 848                         goto irq_err;
 849                 }
 850         }
 851
 852         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 853         if (pdata->init != NULL) {
 854                 if (pdata->init(&pdev->dev) != 0) {
 855                         free_irq(mmc_slot(host).card_detect_irq, host);
 856                         free_irq(host->irq, host);
 857                         goto irq_err;
 858                 }
 859         }
 860
 861         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 862         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 863
 864         platform_set_drvdata(pdev, host);
 865         mmc_add_host(mmc);
 866
 867         return 0;
 868
 869 err:
 870         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
 871         if (host)
 872                 mmc_free_host(mmc);
 873         return ret;
 874
 875 irq_err:
 876         dev_dbg(mmc_dev(host->mmc), "Unable to configure MMC IRQs\n");
 877         clk_disable(host->fclk);
 878         clk_disable(host->iclk);
 879         clk_put(host->fclk);
 880         clk_put(host->iclk);
 881         if (host->dbclk_enabled) {
 882                 clk_disable(host->dbclk);
 883                 clk_put(host->dbclk);
 884         }
 885
 886         if (host)
 887                 mmc_free_host(mmc);
 888         return ret;
 889 }
 890
 891 static int omap_mmc_remove(struct platform_device *pdev)
 892 {
 893         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 894
 895         platform_set_drvdata(pdev, NULL);
 896         if (host) {
 897                 if (host->pdata->cleanup)
 898                         host->pdata->cleanup(&pdev->dev);
 899                 free_irq(host->irq, host);
 900                 if (mmc_slot(host).card_detect_irq)
 901                         free_irq(mmc_slot(host).card_detect_irq, host);
 902                 flush_scheduled_work();
 903
 904                 clk_disable(host->fclk);
 905                 clk_disable(host->iclk);
 906                 clk_put(host->fclk);
 907                 clk_put(host->iclk);
 908                 if (host->dbclk_enabled) {
 909                         clk_disable(host->dbclk);
 910                         clk_put(host->dbclk);
 911                 }
 912
 913                 mmc_free_host(host->mmc);
 914         }
 915
 916         return 0;
 917 }
 918
 919 #ifdef CONFIG_PM
 920 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
 921 {
 922         int ret = 0;
 923         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 924
 925         if (host && host->suspended)
 926                 return 0;
 927
 928         if (host) {
 929                 ret = mmc_suspend_host(host->mmc, state);
 930                 if (ret == 0) {
 931                         host->suspended = 1;
 932
 933                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 934                         OMAP_HSMMC_WRITE(host->base, IE, 0);
 935
 936                         ret = host->pdata->suspend(&pdev->dev, host->slot_id);
 937                         if (ret)
 938                                 dev_dbg(mmc_dev(host->mmc),
 939                                         "Unable to handle MMC board"
 940                                         " level suspend\n");
 941
 942                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 943                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 944                                         OMAP_HSMMC_READ(host->base, HCTL)
 945                                         & SDVSCLR);
 946                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 947                                         OMAP_HSMMC_READ(host->base, HCTL)
 948                                         | SDVS30);
 949                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 950                                         OMAP_HSMMC_READ(host->base, HCTL)
 951                                         | SDBP);
 952                         }
 953
 954                         clk_disable(host->fclk);
 955                         clk_disable(host->iclk);
 956                         clk_disable(host->dbclk);
 957                 }
 958
 959         }
 960         return ret;
 961 }
 962
 963 /* Routine to resume the MMC device */
 964 static int omap_mmc_resume(struct platform_device *pdev)
 965 {
 966         int ret = 0;
 967         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 968
 969         if (host && !host->suspended)
 970                 return 0;
 971
 972         if (host) {
 973
 974                 ret = clk_enable(host->fclk);
 975                 if (ret)
 976                         goto clk_en_err;
 977
 978                 ret = clk_enable(host->iclk);
 979                 if (ret) {
 980                         clk_disable(host->fclk);
 981                         clk_put(host->fclk);
 982                         goto clk_en_err;
 983                 }
 984
 985                 if (clk_enable(host->dbclk) != 0)
 986                         dev_dbg(mmc_dev(host->mmc),
 987                                         "Enabling debounce clk failed\n");
 988
 989                 ret = host->pdata->resume(&pdev->dev, host->slot_id);
 990                 if (ret)
 991                         dev_dbg(mmc_dev(host->mmc),
 992                                         "Unmask interrupt failed\n");
 993
 994                 /* Notify the core to resume the host */
 995                 ret = mmc_resume_host(host->mmc);
 996                 if (ret == 0)
 997                         host->suspended = 0;
 998         }
 999
1000         return ret;
1001
1002 clk_en_err:
1003         dev_dbg(mmc_dev(host->mmc),
1004                 "Failed to enable MMC clocks during resume\n");
1005         return ret;
1006 }
1007
1008 #else
1009 #define omap_mmc_suspend        NULL
1010 #define omap_mmc_resume         NULL
1011 #endif
1012
1013 static struct platform_driver omap_mmc_driver = {
1014         .probe          = omap_mmc_probe,
1015         .remove         = omap_mmc_remove,
1016         .suspend        = omap_mmc_suspend,
1017         .resume         = omap_mmc_resume,
1018         .driver         = {
1019                 .name = DRIVER_NAME,
1020                 .owner = THIS_MODULE,
1021         },
1022 };
1023
1024 static int __init omap_mmc_init(void)
1025 {
1026         /* Register the MMC driver */
1027         return platform_driver_register(&omap_mmc_driver);
1028 }
1029
1030 static void __exit omap_mmc_cleanup(void)
1031 {
1032         /* Unregister MMC driver */
1033         platform_driver_unregister(&omap_mmc_driver);
1034 }
1035
1036 module_init(omap_mmc_init);
1037 module_exit(omap_mmc_cleanup);
1038
1039 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1040 MODULE_LICENSE("GPL");
1041 MODULE_ALIAS("platform:" DRIVER_NAME);
1042 MODULE_AUTHOR("Texas Instruments Inc");