drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <mach/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVS33                  (0x7 << 9)
  59 #define SDVS_MASK               0x00000E00
  60 #define SDVSCLR                 0xFFFFF1FF
  61 #define SDVSDET                 0x00000400
  62 #define AUTOIDLE                0x1
  63 #define SDBP                    (1 << 8)
  64 #define DTO                     0xe
  65 #define ICE                     0x1
  66 #define ICS                     0x2
  67 #define CEN                     (1 << 2)
  68 #define CLKD_MASK               0x0000FFC0
  69 #define CLKD_SHIFT              6
  70 #define DTO_MASK                0x000F0000
  71 #define DTO_SHIFT               16
  72 #define INT_EN_MASK             0x307F0033
  73 #define INIT_STREAM             (1 << 1)
  74 #define DP_SELECT               (1 << 21)
  75 #define DDIR                    (1 << 4)
  76 #define DMA_EN                  0x1
  77 #define MSBS                    (1 << 5)
  78 #define BCE                     (1 << 1)
  79 #define FOUR_BIT                (1 << 1)
  80 #define DW8                     (1 << 5)
  81 #define CC                      0x1
  82 #define TC                      0x02
  83 #define OD                      0x1
  84 #define ERR                     (1 << 15)
  85 #define CMD_TIMEOUT             (1 << 16)
  86 #define DATA_TIMEOUT            (1 << 20)
  87 #define CMD_CRC                 (1 << 17)
  88 #define DATA_CRC                (1 << 21)
  89 #define CARD_ERR                (1 << 28)
  90 #define STAT_CLEAR              0xFFFFFFFF
  91 #define INIT_STREAM_CMD         0x00000000
  92 #define DUAL_VOLT_OCR_BIT       7
  93 #define SRC                     (1 << 25)
  94 #define SRD                     (1 << 26)
  95
  96 /*
  97  * FIXME: Most likely all the data using these _DEVID defines should come
  98  * from the platform_data, or implemented in controller and slot specific
  99  * functions.
 100  */
 101 #define OMAP_MMC1_DEVID         0
 102 #define OMAP_MMC2_DEVID         1
 103
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap-hs"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 struct mmc_omap_host {
 125         struct  device          *dev;
 126         struct  mmc_host        *mmc;
 127         struct  mmc_request     *mrq;
 128         struct  mmc_command     *cmd;
 129         struct  mmc_data        *data;
 130         struct  clk             *fclk;
 131         struct  clk             *iclk;
 132         struct  clk             *dbclk;
 133         struct  semaphore       sem;
 134         struct  work_struct     mmc_carddetect_work;
 135         void    __iomem         *base;
 136         resource_size_t         mapbase;
 137         unsigned int            id;
 138         unsigned int            dma_len;
 139         unsigned int            dma_sg_idx;
 140         unsigned char           bus_mode;
 141         u32                     *buffer;
 142         u32                     bytesleft;
 143         int                     suspended;
 144         int                     irq;
 145         int                     carddetect;
 146         int                     use_dma, dma_ch;
 147         int                     slot_id;
 148         int                     dbclk_enabled;
 149         int                     response_busy;
 150         struct  omap_mmc_platform_data  *pdata;
 151 };
 152
 153 /*
 154  * Stop clock to the card
 155  */
 156 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 157 {
 158         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 159                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 160         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 161                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 162 }
 163
 164 /*
 165  * Send init stream sequence to card
 166  * before sending IDLE command
 167  */
 168 static void send_init_stream(struct mmc_omap_host *host)
 169 {
 170         int reg = 0;
 171         unsigned long timeout;
 172
 173         disable_irq(host->irq);
 174         OMAP_HSMMC_WRITE(host->base, CON,
 175                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 176         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 177
 178         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 179         while ((reg != CC) && time_before(jiffies, timeout))
 180                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 181
 182         OMAP_HSMMC_WRITE(host->base, CON,
 183                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 184         enable_irq(host->irq);
 185 }
 186
 187 static inline
 188 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 189 {
 190         int r = 1;
 191
 192         if (host->pdata->slots[host->slot_id].get_cover_state)
 193                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 194                         host->slot_id);
 195         return r;
 196 }
 197
 198 static ssize_t
 199 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 200                            char *buf)
 201 {
 202         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 203         struct mmc_omap_host *host = mmc_priv(mmc);
 204
 205         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 206                        "open");
 207 }
 208
 209 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 210
 211 static ssize_t
 212 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 213                         char *buf)
 214 {
 215         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 216         struct mmc_omap_host *host = mmc_priv(mmc);
 217         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 218
 219         return sprintf(buf, "slot:%s\n", slot.name);
 220 }
 221
 222 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 223
 224 /*
 225  * Configure the response type and send the cmd.
 226  */
 227 static void
 228 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 229         struct mmc_data *data)
 230 {
 231         int cmdreg = 0, resptype = 0, cmdtype = 0;
 232
 233         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 234                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 235         host->cmd = cmd;
 236
 237         /*
 238          * Clear status bits and enable interrupts
 239          */
 240         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 241         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 242         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 243
 244         host->response_busy = 0;
 245         if (cmd->flags & MMC_RSP_PRESENT) {
 246                 if (cmd->flags & MMC_RSP_136)
 247                         resptype = 1;
 248                 else if (cmd->flags & MMC_RSP_BUSY) {
 249                         resptype = 3;
 250                         host->response_busy = 1;
 251                 } else
 252                         resptype = 2;
 253         }
 254
 255         /*
 256          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 257          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 258          * a val of 0x3, rest 0x0.
 259          */
 260         if (cmd == host->mrq->stop)
 261                 cmdtype = 0x3;
 262
 263         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 264
 265         if (data) {
 266                 cmdreg |= DP_SELECT | MSBS | BCE;
 267                 if (data->flags & MMC_DATA_READ)
 268                         cmdreg |= DDIR;
 269                 else
 270                         cmdreg &= ~(DDIR);
 271         }
 272
 273         if (host->use_dma)
 274                 cmdreg |= DMA_EN;
 275
 276         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 277         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 278 }
 279
 280 static int
 281 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 282 {
 283         if (data->flags & MMC_DATA_WRITE)
 284                 return DMA_TO_DEVICE;
 285         else
 286                 return DMA_FROM_DEVICE;
 287 }
 288
 289 /*
 290  * Notify the transfer complete to MMC core
 291  */
 292 static void
 293 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 294 {
 295         if (!data) {
 296                 struct mmc_request *mrq = host->mrq;
 297
 298                 host->mrq = NULL;
 299                 mmc_omap_fclk_lazy_disable(host);
 300                 mmc_request_done(host->mmc, mrq);
 301                 return;
 302         }
 303
 304         host->data = NULL;
 305
 306         if (host->use_dma && host->dma_ch != -1)
 307                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 308                         mmc_omap_get_dma_dir(host, data));
 309
 310         if (!data->error)
 311                 data->bytes_xfered += data->blocks * (data->blksz);
 312         else
 313                 data->bytes_xfered = 0;
 314
 315         if (!data->stop) {
 316                 host->mrq = NULL;
 317                 mmc_request_done(host->mmc, data->mrq);
 318                 return;
 319         }
 320         mmc_omap_start_command(host, data->stop, NULL);
 321 }
 322
 323 /*
 324  * Notify the core about command completion
 325  */
 326 static void
 327 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 328 {
 329         host->cmd = NULL;
 330
 331         if (cmd->flags & MMC_RSP_PRESENT) {
 332                 if (cmd->flags & MMC_RSP_136) {
 333                         /* response type 2 */
 334                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 335                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 336                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 337                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 338                 } else {
 339                         /* response types 1, 1b, 3, 4, 5, 6 */
 340                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 341                 }
 342         }
 343         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 344                 host->mrq = NULL;
 345                 mmc_request_done(host->mmc, cmd->mrq);
 346         }
 347 }
 348
 349 /*
 350  * DMA clean up for command errors
 351  */
 352 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 353 {
 354         host->data->error = errno;
 355
 356         if (host->use_dma && host->dma_ch != -1) {
 357                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 358                         mmc_omap_get_dma_dir(host, host->data));
 359                 omap_free_dma(host->dma_ch);
 360                 host->dma_ch = -1;
 361                 up(&host->sem);
 362         }
 363         host->data = NULL;
 364 }
 365
 366 /*
 367  * Readable error output
 368  */
 369 #ifdef CONFIG_MMC_DEBUG
 370 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 371 {
 372         /* --- means reserved bit without definition at documentation */
 373         static const char *mmc_omap_status_bits[] = {
 374                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 375                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 376                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 377                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 378         };
 379         char res[256];
 380         char *buf = res;
 381         int len, i;
 382
 383         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 384         buf += len;
 385
 386         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 387                 if (status & (1 << i)) {
 388                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 389                         buf += len;
 390                 }
 391
 392         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 393 }
 394 #endif  /* CONFIG_MMC_DEBUG */
 395
 396 /*
 397  * MMC controller internal state machines reset
 398  *
 399  * Used to reset command or data internal state machines, using respectively
 400  *  SRC or SRD bit of SYSCTL register
 401  * Can be called from interrupt context
 402  */
 403 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 404                 unsigned long bit)
 405 {
 406         unsigned long i = 0;
 407         unsigned long limit = (loops_per_jiffy *
 408                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 409
 410         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 411                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 412
 413         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 414                 (i++ < limit))
 415                 cpu_relax();
 416
 417         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 418                 dev_err(mmc_dev(host->mmc),
 419                         "Timeout waiting on controller reset in %s\n",
 420                         __func__);
 421 }
 422
 423 /*
 424  * MMC controller IRQ handler
 425  */
 426 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 427 {
 428         struct mmc_omap_host *host = dev_id;
 429         struct mmc_data *data;
 430         int end_cmd = 0, end_trans = 0, status;
 431
 432         if (host->mrq == NULL) {
 433                 OMAP_HSMMC_WRITE(host->base, STAT,
 434                         OMAP_HSMMC_READ(host->base, STAT));
 435                 return IRQ_HANDLED;
 436         }
 437
 438         data = host->data;
 439         status = OMAP_HSMMC_READ(host->base, STAT);
 440         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 441
 442         if (status & ERR) {
 443 #ifdef CONFIG_MMC_DEBUG
 444                 mmc_omap_report_irq(host, status);
 445 #endif
 446                 if ((status & CMD_TIMEOUT) ||
 447                         (status & CMD_CRC)) {
 448                         if (host->cmd) {
 449                                 if (status & CMD_TIMEOUT) {
 450                                         mmc_omap_reset_controller_fsm(host, SRC);
 451                                         host->cmd->error = -ETIMEDOUT;
 452                                 } else {
 453                                         host->cmd->error = -EILSEQ;
 454                                 }
 455                                 end_cmd = 1;
 456                         }
 457                         if (host->data || host->response_busy) {
 458                                 if (host->data)
 459                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 460                                 host->response_busy = 0;
 461                                 mmc_omap_reset_controller_fsm(host, SRD);
 462                         }
 463                 }
 464                 if ((status & DATA_TIMEOUT) ||
 465                         (status & DATA_CRC)) {
 466                         if (host->data || host->response_busy) {
 467                                 int err = (status & DATA_TIMEOUT) ?
 468                                                 -ETIMEDOUT : -EILSEQ;
 469
 470                                 if (host->data)
 471                                         mmc_dma_cleanup(host, err);
 472                                 else
 473                                         host->mrq->cmd->error = err;
 474                                 host->response_busy = 0;
 475                                 mmc_omap_reset_controller_fsm(host, SRD);
 476                                 end_trans = 1;
 477                         }
 478                 }
 479                 if (status & CARD_ERR) {
 480                         dev_dbg(mmc_dev(host->mmc),
 481                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 482                         if (host->cmd)
 483                                 end_cmd = 1;
 484                         if (host->data)
 485                                 end_trans = 1;
 486                 }
 487         }
 488
 489         OMAP_HSMMC_WRITE(host->base, STAT, status);
 490
 491         if (end_cmd || (status & CC))
 492                 mmc_omap_cmd_done(host, host->cmd);
 493         if (end_trans || (status & TC))
 494                 mmc_omap_xfer_done(host, data);
 495
 496         return IRQ_HANDLED;
 497 }
 498
 499 /*
 500  * Switch MMC interface voltage ... only relevant for MMC1.
 501  *
 502  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 503  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 504  * Some chips, like eMMC ones, use internal transceivers.
 505  */
 506 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 507 {
 508         u32 reg_val = 0;
 509         int ret;
 510
 511         /* Disable the clocks */
 512         clk_disable(host->fclk);
 513         clk_disable(host->iclk);
 514         clk_disable(host->dbclk);
 515
 516         /* Turn the power off */
 517         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 518         if (ret != 0)
 519                 goto err;
 520
 521         /* Turn the power ON with given VDD 1.8 or 3.0v */
 522         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 523         if (ret != 0)
 524                 goto err;
 525
 526         clk_enable(host->fclk);
 527         clk_enable(host->iclk);
 528         clk_enable(host->dbclk);
 529
 530         OMAP_HSMMC_WRITE(host->base, HCTL,
 531                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 532         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 533
 534         /*
 535          * If a MMC dual voltage card is detected, the set_ios fn calls
 536          * this fn with VDD bit set for 1.8V. Upon card removal from the
 537          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 538          *
 539          * Cope with a bit of slop in the range ... per data sheets:
 540          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 541          *    but recommended values are 1.71V to 1.89V
 542          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 543          *    but recommended values are 2.7V to 3.3V
 544          *
 545          * Board setup code shouldn't permit anything very out-of-range.
 546          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 547          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 548          */
 549         if ((1 << vdd) <= MMC_VDD_23_24)
 550                 reg_val |= SDVS18;
 551         else
 552                 reg_val |= SDVS30;
 553
 554         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 555
 556         OMAP_HSMMC_WRITE(host->base, HCTL,
 557                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 558
 559         return 0;
 560 err:
 561         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 562         return ret;
 563 }
 564
 565 /*
 566  * Work Item to notify the core about card insertion/removal
 567  */
 568 static void mmc_omap_detect(struct work_struct *work)
 569 {
 570         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 571                                                 mmc_carddetect_work);
 572         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 573
 574         if (mmc_slot(host).card_detect)
 575                 host->carddetect = slot->card_detect(slot->card_detect_irq);
 576         else
 577                 host->carddetect = -ENOSYS;
 578
 579         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 580         if (host->carddetect) {
 581                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 582         } else {
 583                 mmc_omap_reset_controller_fsm(host, SRD);
 584                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 585         }
 586 }
 587
 588 /*
 589  * ISR for handling card insertion and removal
 590  */
 591 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 592 {
 593         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 594
 595         schedule_work(&host->mmc_carddetect_work);
 596
 597         return IRQ_HANDLED;
 598 }
 599
 600 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 601                                      struct mmc_data *data)
 602 {
 603         int sync_dev;
 604
 605         if (data->flags & MMC_DATA_WRITE) {
 606                 if (host->id == OMAP_MMC1_DEVID)
 607                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 608                 else
 609                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 610         } else {
 611                 if (host->id == OMAP_MMC1_DEVID)
 612                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 613                 else
 614                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 615         }
 616         return sync_dev;
 617 }
 618
 619 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 620                                        struct mmc_data *data,
 621                                        struct scatterlist *sgl)
 622 {
 623         int blksz, nblk, dma_ch;
 624
 625         dma_ch = host->dma_ch;
 626         if (data->flags & MMC_DATA_WRITE) {
 627                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 628                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 629                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 630                         sg_dma_address(sgl), 0, 0);
 631         } else {
 632                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 633                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 634                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 635                         sg_dma_address(sgl), 0, 0);
 636         }
 637
 638         blksz = host->data->blksz;
 639         nblk = sg_dma_len(sgl) / blksz;
 640
 641         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 642                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 643                         mmc_omap_get_dma_sync_dev(host, data),
 644                         !(data->flags & MMC_DATA_WRITE));
 645
 646         omap_start_dma(dma_ch);
 647 }
 648
 649 /*
 650  * DMA call back function
 651  */
 652 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 653 {
 654         struct mmc_omap_host *host = data;
 655
 656         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 657                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 658
 659         if (host->dma_ch < 0)
 660                 return;
 661
 662         host->dma_sg_idx++;
 663         if (host->dma_sg_idx < host->dma_len) {
 664                 /* Fire up the next transfer. */
 665                 mmc_omap_config_dma_params(host, host->data,
 666                                            host->data->sg + host->dma_sg_idx);
 667                 return;
 668         }
 669
 670         omap_free_dma(host->dma_ch);
 671         host->dma_ch = -1;
 672         /*
 673          * DMA Callback: run in interrupt context.
 674          * mutex_unlock will through a kernel warning if used.
 675          */
 676         up(&host->sem);
 677 }
 678
 679 /*
 680  * Routine to configure and start DMA for the MMC card
 681  */
 682 static int
 683 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 684 {
 685         int dma_ch = 0, ret = 0, err = 1, i;
 686         struct mmc_data *data = req->data;
 687
 688         /* Sanity check: all the SG entries must be aligned by block size. */
 689         for (i = 0; i < host->dma_len; i++) {
 690                 struct scatterlist *sgl;
 691
 692                 sgl = data->sg + i;
 693                 if (sgl->length % data->blksz)
 694                         return -EINVAL;
 695         }
 696         if ((data->blksz % 4) != 0)
 697                 /* REVISIT: The MMC buffer increments only when MSB is written.
 698                  * Return error for blksz which is non multiple of four.
 699                  */
 700                 return -EINVAL;
 701
 702         /*
 703          * If for some reason the DMA transfer is still active,
 704          * we wait for timeout period and free the dma
 705          */
 706         if (host->dma_ch != -1) {
 707                 set_current_state(TASK_UNINTERRUPTIBLE);
 708                 schedule_timeout(100);
 709                 if (down_trylock(&host->sem)) {
 710                         omap_free_dma(host->dma_ch);
 711                         host->dma_ch = -1;
 712                         up(&host->sem);
 713                         return err;
 714                 }
 715         } else {
 716                 if (down_trylock(&host->sem))
 717                         return err;
 718         }
 719
 720         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 721                                mmc_omap_dma_cb,host, &dma_ch);
 722         if (ret != 0) {
 723                 dev_err(mmc_dev(host->mmc),
 724                         "%s: omap_request_dma() failed with %d\n",
 725                         mmc_hostname(host->mmc), ret);
 726                 return ret;
 727         }
 728
 729         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 730                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 731         host->dma_ch = dma_ch;
 732         host->dma_sg_idx = 0;
 733
 734         mmc_omap_config_dma_params(host, data, data->sg);
 735
 736         return 0;
 737 }
 738
 739 static void set_data_timeout(struct mmc_omap_host *host,
 740                              struct mmc_request *req)
 741 {
 742         unsigned int timeout, cycle_ns;
 743         uint32_t reg, clkd, dto = 0;
 744
 745         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 746         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 747         if (clkd == 0)
 748                 clkd = 1;
 749
 750         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 751         timeout = req->data->timeout_ns / cycle_ns;
 752         timeout += req->data->timeout_clks;
 753         if (timeout) {
 754                 while ((timeout & 0x80000000) == 0) {
 755                         dto += 1;
 756                         timeout <<= 1;
 757                 }
 758                 dto = 31 - dto;
 759                 timeout <<= 1;
 760                 if (timeout && dto)
 761                         dto += 1;
 762                 if (dto >= 13)
 763                         dto -= 13;
 764                 else
 765                         dto = 0;
 766                 if (dto > 14)
 767                         dto = 14;
 768         }
 769
 770         reg &= ~DTO_MASK;
 771         reg |= dto << DTO_SHIFT;
 772         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 773 }
 774
 775 /*
 776  * Configure block length for MMC/SD cards and initiate the transfer.
 777  */
 778 static int
 779 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 780 {
 781         int ret;
 782         host->data = req->data;
 783
 784         if (req->data == NULL) {
 785                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 786                 return 0;
 787         }
 788
 789         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 790                                         | (req->data->blocks << 16));
 791         set_data_timeout(host, req);
 792
 793         if (host->use_dma) {
 794                 ret = mmc_omap_start_dma_transfer(host, req);
 795                 if (ret != 0) {
 796                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 797                         return ret;
 798                 }
 799         }
 800         return 0;
 801 }
 802
 803 /*
 804  * Request function. for read/write operation
 805  */
 806 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 807 {
 808         struct mmc_omap_host *host = mmc_priv(mmc);
 809
 810         WARN_ON(host->mrq != NULL);
 811         host->mrq = req;
 812         mmc_omap_prepare_data(host, req);
 813         mmc_omap_start_command(host, req->cmd, req->data);
 814 }
 815
 816
 817 /* Routine to configure clock values. Exposed API to core */
 818 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 819 {
 820         struct mmc_omap_host *host = mmc_priv(mmc);
 821         u16 dsor = 0;
 822         unsigned long regval;
 823         unsigned long timeout;
 824         u32 con;
 825
 826         switch (ios->power_mode) {
 827         case MMC_POWER_OFF:
 828                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 829                 break;
 830         case MMC_POWER_UP:
 831                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 832                 break;
 833         }
 834
 835         con = OMAP_HSMMC_READ(host->base, CON);
 836         switch (mmc->ios.bus_width) {
 837         case MMC_BUS_WIDTH_8:
 838                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 839                 break;
 840         case MMC_BUS_WIDTH_4:
 841                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 842                 OMAP_HSMMC_WRITE(host->base, HCTL,
 843                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 844                 break;
 845         case MMC_BUS_WIDTH_1:
 846                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 847                 OMAP_HSMMC_WRITE(host->base, HCTL,
 848                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 849                 break;
 850         }
 851
 852         if (host->id == OMAP_MMC1_DEVID) {
 853                 /* Only MMC1 can interface at 3V without some flavor
 854                  * of external transceiver; but they all handle 1.8V.
 855                  */
 856                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 857                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 858                                 /*
 859                                  * The mmc_select_voltage fn of the core does
 860                                  * not seem to set the power_mode to
 861                                  * MMC_POWER_UP upon recalculating the voltage.
 862                                  * vdd 1.8v.
 863                                  */
 864                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 865                                         dev_dbg(mmc_dev(host->mmc),
 866                                                 "Switch operation failed\n");
 867                 }
 868         }
 869
 870         if (ios->clock) {
 871                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 872                 if (dsor < 1)
 873                         dsor = 1;
 874
 875                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 876                         dsor++;
 877
 878                 if (dsor > 250)
 879                         dsor = 250;
 880         }
 881         omap_mmc_stop_clock(host);
 882         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 883         regval = regval & ~(CLKD_MASK);
 884         regval = regval | (dsor << 6) | (DTO << 16);
 885         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 886         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 887                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 888
 889         /* Wait till the ICS bit is set */
 890         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 891         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 892                 && time_before(jiffies, timeout))
 893                 msleep(1);
 894
 895         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 896                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 897
 898         if (ios->power_mode == MMC_POWER_ON)
 899                 send_init_stream(host);
 900
 901         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 902                 OMAP_HSMMC_WRITE(host->base, CON,
 903                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 904 }
 905
 906 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 907 {
 908         struct mmc_omap_host *host = mmc_priv(mmc);
 909         struct omap_mmc_platform_data *pdata = host->pdata;
 910
 911         if (!pdata->slots[0].card_detect)
 912                 return -ENOSYS;
 913         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 914 }
 915
 916 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 917 {
 918         struct mmc_omap_host *host = mmc_priv(mmc);
 919         struct omap_mmc_platform_data *pdata = host->pdata;
 920
 921         if (!pdata->slots[0].get_ro)
 922                 return -ENOSYS;
 923         return pdata->slots[0].get_ro(host->dev, 0);
 924 }
 925
 926 static void omap_hsmmc_init(struct mmc_omap_host *host)
 927 {
 928         u32 hctl, capa, value;
 929
 930         /* Only MMC1 supports 3.0V */
 931         if (host->id == OMAP_MMC1_DEVID) {
 932                 hctl = SDVS30;
 933                 capa = VS30 | VS18;
 934         } else {
 935                 hctl = SDVS18;
 936                 capa = VS18;
 937         }
 938
 939         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
 940         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
 941
 942         value = OMAP_HSMMC_READ(host->base, CAPA);
 943         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
 944
 945         /* Set the controller to AUTO IDLE mode */
 946         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
 947         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
 948
 949         /* Set SD bus power bit */
 950         value = OMAP_HSMMC_READ(host->base, HCTL);
 951         OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP);
 952 }
 953
 954 static struct mmc_host_ops mmc_omap_ops = {
 955         .request = omap_mmc_request,
 956         .set_ios = omap_mmc_set_ios,
 957         .get_cd = omap_hsmmc_get_cd,
 958         .get_ro = omap_hsmmc_get_ro,
 959         /* NYET -- enable_sdio_irq */
 960 };
 961
 962 static int __init omap_mmc_probe(struct platform_device *pdev)
 963 {
 964         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 965         struct mmc_host *mmc;
 966         struct mmc_omap_host *host = NULL;
 967         struct resource *res;
 968         int ret = 0, irq;
 969
 970         if (pdata == NULL) {
 971                 dev_err(&pdev->dev, "Platform Data is missing\n");
 972                 return -ENXIO;
 973         }
 974
 975         if (pdata->nr_slots == 0) {
 976                 dev_err(&pdev->dev, "No Slots\n");
 977                 return -ENXIO;
 978         }
 979
 980         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 981         irq = platform_get_irq(pdev, 0);
 982         if (res == NULL || irq < 0)
 983                 return -ENXIO;
 984
 985         res = request_mem_region(res->start, res->end - res->start + 1,
 986                                                         pdev->name);
 987         if (res == NULL)
 988                 return -EBUSY;
 989
 990         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 991         if (!mmc) {
 992                 ret = -ENOMEM;
 993                 goto err;
 994         }
 995
 996         host            = mmc_priv(mmc);
 997         host->mmc       = mmc;
 998         host->pdata     = pdata;
 999         host->dev       = &pdev->dev;
1000         host->use_dma   = 1;
1001         host->dev->dma_mask = &pdata->dma_mask;
1002         host->dma_ch    = -1;
1003         host->irq       = irq;
1004         host->id        = pdev->id;
1005         host->slot_id   = 0;
1006         host->mapbase   = res->start;
1007         host->base      = ioremap(host->mapbase, SZ_4K);
1008
1009         platform_set_drvdata(pdev, host);
1010         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1011
1012         mmc->ops        = &mmc_omap_ops;
1013         mmc->f_min      = 400000;
1014         mmc->f_max      = 52000000;
1015
1016         sema_init(&host->sem, 1);
1017
1018         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
1019         if (IS_ERR(host->iclk)) {
1020                 ret = PTR_ERR(host->iclk);
1021                 host->iclk = NULL;
1022                 goto err1;
1023         }
1024         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
1025         if (IS_ERR(host->fclk)) {
1026                 ret = PTR_ERR(host->fclk);
1027                 host->fclk = NULL;
1028                 clk_put(host->iclk);
1029                 goto err1;
1030         }
1031
1032         if (clk_enable(host->fclk) != 0) {
1033                 clk_put(host->iclk);
1034                 clk_put(host->fclk);
1035                 goto err1;
1036         }
1037
1038         if (clk_enable(host->iclk) != 0) {
1039                 clk_disable(host->fclk);
1040                 clk_put(host->iclk);
1041                 clk_put(host->fclk);
1042                 goto err1;
1043         }
1044
1045         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1046         /*
1047          * MMC can still work without debounce clock.
1048          */
1049         if (IS_ERR(host->dbclk))
1050                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1051         else
1052                 if (clk_enable(host->dbclk) != 0)
1053                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1054                                                         " clk failed\n");
1055                 else
1056                         host->dbclk_enabled = 1;
1057
1058         /* Since we do only SG emulation, we can have as many segs
1059          * as we want. */
1060         mmc->max_phys_segs = 1024;
1061         mmc->max_hw_segs = 1024;
1062
1063         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1064         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1065         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1066         mmc->max_seg_size = mmc->max_req_size;
1067
1068         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1069         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1070
1071         if (pdata->slots[host->slot_id].wires >= 8)
1072                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1073         else if (pdata->slots[host->slot_id].wires >= 4)
1074                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1075
1076         omap_hsmmc_init(host);
1077
1078         /* Request IRQ for MMC operations */
1079         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1080                         mmc_hostname(mmc), host);
1081         if (ret) {
1082                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1083                 goto err_irq;
1084         }
1085
1086         if (pdata->init != NULL) {
1087                 if (pdata->init(&pdev->dev) != 0) {
1088                         dev_dbg(mmc_dev(host->mmc),
1089                                 "Unable to configure MMC IRQs\n");
1090                         goto err_irq_cd_init;
1091                 }
1092         }
1093
1094         /* Request IRQ for card detect */
1095         if ((mmc_slot(host).card_detect_irq)) {
1096                 ret = request_irq(mmc_slot(host).card_detect_irq,
1097                                   omap_mmc_cd_handler,
1098                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1099                                           | IRQF_DISABLED,
1100                                   mmc_hostname(mmc), host);
1101                 if (ret) {
1102                         dev_dbg(mmc_dev(host->mmc),
1103                                 "Unable to grab MMC CD IRQ\n");
1104                         goto err_irq_cd;
1105                 }
1106         }
1107
1108         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1109         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1110
1111         mmc_add_host(mmc);
1112
1113         if (host->pdata->slots[host->slot_id].name != NULL) {
1114                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1115                 if (ret < 0)
1116                         goto err_slot_name;
1117         }
1118         if (mmc_slot(host).card_detect_irq &&
1119             host->pdata->slots[host->slot_id].get_cover_state) {
1120                 ret = device_create_file(&mmc->class_dev,
1121                                         &dev_attr_cover_switch);
1122                 if (ret < 0)
1123                         goto err_cover_switch;
1124         }
1125
1126         return 0;
1127
1128 err_cover_switch:
1129         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1130 err_slot_name:
1131         mmc_remove_host(mmc);
1132 err_irq_cd:
1133         free_irq(mmc_slot(host).card_detect_irq, host);
1134 err_irq_cd_init:
1135         free_irq(host->irq, host);
1136 err_irq:
1137         clk_disable(host->fclk);
1138         clk_disable(host->iclk);
1139         clk_put(host->fclk);
1140         clk_put(host->iclk);
1141         if (host->dbclk_enabled) {
1142                 clk_disable(host->dbclk);
1143                 clk_put(host->dbclk);
1144         }
1145
1146 err1:
1147         iounmap(host->base);
1148 err:
1149         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1150         release_mem_region(res->start, res->end - res->start + 1);
1151         if (host)
1152                 mmc_free_host(mmc);
1153         return ret;
1154 }
1155
1156 static int omap_mmc_remove(struct platform_device *pdev)
1157 {
1158         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1159         struct resource *res;
1160
1161         if (host) {
1162                 mmc_remove_host(host->mmc);
1163                 if (host->pdata->cleanup)
1164                         host->pdata->cleanup(&pdev->dev);
1165                 free_irq(host->irq, host);
1166                 if (mmc_slot(host).card_detect_irq)
1167                         free_irq(mmc_slot(host).card_detect_irq, host);
1168                 flush_scheduled_work();
1169
1170                 clk_disable(host->fclk);
1171                 clk_disable(host->iclk);
1172                 clk_put(host->fclk);
1173                 clk_put(host->iclk);
1174                 if (host->dbclk_enabled) {
1175                         clk_disable(host->dbclk);
1176                         clk_put(host->dbclk);
1177                 }
1178
1179                 mmc_free_host(host->mmc);
1180                 iounmap(host->base);
1181         }
1182
1183         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184         if (res)
1185                 release_mem_region(res->start, res->end - res->start + 1);
1186         platform_set_drvdata(pdev, NULL);
1187
1188         return 0;
1189 }
1190
1191 #ifdef CONFIG_PM
1192 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1193 {
1194         int ret = 0;
1195         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1196
1197         if (host && host->suspended)
1198                 return 0;
1199
1200         if (host) {
1201                 ret = mmc_suspend_host(host->mmc, state);
1202                 if (ret == 0) {
1203                         host->suspended = 1;
1204
1205                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1206                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1207
1208                         if (host->pdata->suspend) {
1209                                 ret = host->pdata->suspend(&pdev->dev,
1210                                                                 host->slot_id);
1211                                 if (ret)
1212                                         dev_dbg(mmc_dev(host->mmc),
1213                                                 "Unable to handle MMC board"
1214                                                 " level suspend\n");
1215                         }
1216
1217                         if (host->id == OMAP_MMC1_DEVID
1218                                         && !(OMAP_HSMMC_READ(host->base, HCTL)
1219                                                         & SDVSDET)) {
1220                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1221                                         OMAP_HSMMC_READ(host->base, HCTL)
1222                                         & SDVSCLR);
1223                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1224                                         OMAP_HSMMC_READ(host->base, HCTL)
1225                                         | SDVS30);
1226                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1227                                         OMAP_HSMMC_READ(host->base, HCTL)
1228                                         | SDBP);
1229                         }
1230
1231                         clk_disable(host->fclk);
1232                         clk_disable(host->iclk);
1233                         clk_disable(host->dbclk);
1234                 }
1235
1236         }
1237         return ret;
1238 }
1239
1240 /* Routine to resume the MMC device */
1241 static int omap_mmc_resume(struct platform_device *pdev)
1242 {
1243         int ret = 0;
1244         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1245
1246         if (host && !host->suspended)
1247                 return 0;
1248
1249         if (host) {
1250
1251                 ret = clk_enable(host->fclk);
1252                 if (ret)
1253                         goto clk_en_err;
1254
1255                 ret = clk_enable(host->iclk);
1256                 if (ret) {
1257                         clk_disable(host->fclk);
1258                         clk_put(host->fclk);
1259                         goto clk_en_err;
1260                 }
1261
1262                 if (clk_enable(host->dbclk) != 0)
1263                         dev_dbg(mmc_dev(host->mmc),
1264                                         "Enabling debounce clk failed\n");
1265
1266                 omap_hsmmc_init(host);
1267
1268                 if (host->pdata->resume) {
1269                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1270                         if (ret)
1271                                 dev_dbg(mmc_dev(host->mmc),
1272                                         "Unmask interrupt failed\n");
1273                 }
1274
1275                 /* Notify the core to resume the host */
1276                 ret = mmc_resume_host(host->mmc);
1277                 if (ret == 0)
1278                         host->suspended = 0;
1279         }
1280
1281         return ret;
1282
1283 clk_en_err:
1284         dev_dbg(mmc_dev(host->mmc),
1285                 "Failed to enable MMC clocks during resume\n");
1286         return ret;
1287 }
1288
1289 #else
1290 #define omap_mmc_suspend        NULL
1291 #define omap_mmc_resume         NULL
1292 #endif
1293
1294 static struct platform_driver omap_mmc_driver = {
1295         .probe          = omap_mmc_probe,
1296         .remove         = omap_mmc_remove,
1297         .suspend        = omap_mmc_suspend,
1298         .resume         = omap_mmc_resume,
1299         .driver         = {
1300                 .name = DRIVER_NAME,
1301                 .owner = THIS_MODULE,
1302         },
1303 };
1304
1305 static int __init omap_mmc_init(void)
1306 {
1307         /* Register the MMC driver */
1308         return platform_driver_register(&omap_mmc_driver);
1309 }
1310
1311 static void __exit omap_mmc_cleanup(void)
1312 {
1313         /* Unregister MMC driver */
1314         platform_driver_unregister(&omap_mmc_driver);
1315 }
1316
1317 module_init(omap_mmc_init);
1318 module_exit(omap_mmc_cleanup);
1319
1320 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1321 MODULE_LICENSE("GPL");
1322 MODULE_ALIAS("platform:" DRIVER_NAME);
1323 MODULE_AUTHOR("Texas Instruments Inc");