drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <asm/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <asm/hardware.h>
  32 #include <asm/arch/board.h>
  33 #include <asm/arch/mmc.h>
  34 #include <asm/arch/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1<<26)
  55 #define VS30                    (1<<25)
  56 #define SDVS18                  (0x5<<9)
  57 #define SDVS30                  (0x6<<9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1<<8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1<<2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define INT_EN_MASK             0x307F0033
  68 #define INIT_STREAM             (1<<1)
  69 #define DP_SELECT               (1<<21)
  70 #define DDIR                    (1<<4)
  71 #define DMA_EN                  0x1
  72 #define MSBS                    1<<5
  73 #define BCE                     1<<1
  74 #define FOUR_BIT                1 << 1
  75 #define CC                      0x1
  76 #define TC                      0x02
  77 #define OD                      0x1
  78 #define ERR                     (1 << 15)
  79 #define CMD_TIMEOUT             (1 << 16)
  80 #define DATA_TIMEOUT            (1 << 20)
  81 #define CMD_CRC                 (1 << 17)
  82 #define DATA_CRC                (1 << 21)
  83 #define CARD_ERR                (1 << 28)
  84 #define STAT_CLEAR              0xFFFFFFFF
  85 #define INIT_STREAM_CMD         0x00000000
  86 #define DUAL_VOLT_OCR_BIT       7
  87 #define SRC                     (1 << 25)
  88 #define SRD                     (1 << 26)
  89
  90 #define OMAP_MMC1_DEVID         1
  91 #define OMAP_MMC2_DEVID         2
  92 #define OMAP_MMC_DATADIR_NONE   0
  93 #define OMAP_MMC_DATADIR_READ   1
  94 #define OMAP_MMC_DATADIR_WRITE  2
  95 #define MMC_TIMEOUT_MS          20
  96 #define OMAP_MMC_MASTER_CLOCK   96000000
  97 #define DRIVER_NAME             "mmci-omap"
  98 /*
  99  * slot_id is device id - 1, device id is a static value
 100  * of 1 to represent device 1 etc..
 101  */
 102 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 103
 104 /*
 105  * MMC Host controller read/write API's
 106  */
 107 #define OMAP_HSMMC_READ(base, reg)      \
 108         __raw_readl((base) + OMAP_HSMMC_##reg)
 109
 110 #define OMAP_HSMMC_WRITE(base, reg, val) \
 111         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 112
 113 struct mmc_omap_host {
 114         struct  device          *dev;
 115         struct  mmc_host        *mmc;
 116         struct  mmc_request     *mrq;
 117         struct  mmc_command     *cmd;
 118         struct  mmc_data        *data;
 119         struct  clk             *fclk;
 120         struct  clk             *iclk;
 121         struct  clk             *dbclk;
 122         struct  semaphore       sem;
 123         struct  work_struct     mmc_carddetect_work;
 124         void    __iomem         *base;
 125         resource_size_t         mapbase;
 126         unsigned int            id;
 127         unsigned int            dma_len;
 128         unsigned int            dma_dir;
 129         unsigned char           bus_mode;
 130         unsigned char           datadir;
 131         u32                     *buffer;
 132         u32                     bytesleft;
 133         int                     suspended;
 134         int                     irq;
 135         int                     carddetect;
 136         int                     use_dma, dma_ch;
 137         int                     initstr;
 138         int                     slot_id;
 139         int                     dbclk_enabled;
 140         struct  omap_mmc_platform_data  *pdata;
 141 };
 142
 143 /*
 144  * Stop clock to the card
 145  */
 146 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 147 {
 148         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 149                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 150         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 151                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 152 }
 153
 154 /*
 155  * Send init stream sequence to card
 156  * before sending IDLE command
 157  */
 158 static void send_init_stream(struct mmc_omap_host *host)
 159 {
 160         int reg = 0;
 161         unsigned long timeout;
 162
 163         disable_irq(host->irq);
 164         OMAP_HSMMC_WRITE(host->base, CON,
 165                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 166         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 167
 168         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 169         while ((reg != CC) && time_before(jiffies, timeout))
 170                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 171
 172         OMAP_HSMMC_WRITE(host->base, CON,
 173                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 174         enable_irq(host->irq);
 175 }
 176
 177 /*
 178  * Configure the response type and send the cmd.
 179  */
 180 static void
 181 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 182         struct mmc_data *data)
 183 {
 184         int cmdreg = 0, resptype = 0, cmdtype = 0;
 185
 186         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 187                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 188         host->cmd = cmd;
 189
 190         /*
 191          * Clear status bits and enable interrupts
 192          */
 193         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 194         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 195         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 196
 197         if (cmd->flags & MMC_RSP_PRESENT) {
 198                 if (cmd->flags & MMC_RSP_136)
 199                         resptype = 1;
 200                 else
 201                         resptype = 2;
 202         }
 203
 204         /*
 205          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 206          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 207          */
 208         if (cmd->opcode == 12)
 209                 cmdtype = 0x3;
 210
 211         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 212
 213         if (data) {
 214                 cmdreg |= DP_SELECT | MSBS | BCE;
 215                 if (data->flags & MMC_DATA_READ)
 216                         cmdreg |= DDIR;
 217                 else
 218                         cmdreg &= ~(DDIR);
 219         }
 220
 221         if (host->use_dma)
 222                 cmdreg |= DMA_EN;
 223
 224         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 225         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 226 }
 227
 228 /*
 229  * Notify the transfer complete to MMC core
 230  */
 231 static void
 232 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 233 {
 234         host->data = NULL;
 235
 236         if (host->use_dma && host->dma_ch != -1)
 237                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 238                         host->dma_dir);
 239
 240         host->datadir = OMAP_MMC_DATADIR_NONE;
 241
 242         if (!data->error)
 243                 data->bytes_xfered += data->blocks * (data->blksz);
 244         else
 245                 data->bytes_xfered = 0;
 246
 247         if (!data->stop) {
 248                 host->mrq = NULL;
 249                 mmc_request_done(host->mmc, data->mrq);
 250                 return;
 251         }
 252         mmc_omap_start_command(host, data->stop, NULL);
 253 }
 254
 255 /*
 256  * Notify the core about command completion
 257  */
 258 static void
 259 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 260 {
 261         host->cmd = NULL;
 262
 263         if (cmd->flags & MMC_RSP_PRESENT) {
 264                 if (cmd->flags & MMC_RSP_136) {
 265                         /* response type 2 */
 266                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 267                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 268                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 269                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 270                 } else {
 271                         /* response types 1, 1b, 3, 4, 5, 6 */
 272                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 273                 }
 274         }
 275         if (host->data == NULL || cmd->error) {
 276                 host->mrq = NULL;
 277                 mmc_request_done(host->mmc, cmd->mrq);
 278         }
 279 }
 280
 281 /*
 282  * DMA clean up for command errors
 283  */
 284 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 285 {
 286         host->data->error = -ETIMEDOUT;
 287
 288         if (host->use_dma && host->dma_ch != -1) {
 289                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 290                         host->dma_dir);
 291                 omap_free_dma(host->dma_ch);
 292                 host->dma_ch = -1;
 293                 up(&host->sem);
 294         }
 295         host->data = NULL;
 296         host->datadir = OMAP_MMC_DATADIR_NONE;
 297 }
 298
 299 /*
 300  * MMC controller IRQ handler
 301  */
 302 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 303 {
 304         struct mmc_omap_host *host = dev_id;
 305         struct mmc_data *data;
 306         int end_cmd = 0, end_trans = 0, status;
 307
 308         if (host->cmd == NULL && host->data == NULL) {
 309                 OMAP_HSMMC_WRITE(host->base, STAT,
 310                         OMAP_HSMMC_READ(host->base, STAT));
 311                 return IRQ_HANDLED;
 312         }
 313
 314         data = host->data;
 315         status = OMAP_HSMMC_READ(host->base, STAT);
 316         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 317
 318         if (status & ERR) {
 319                 if ((status & CMD_TIMEOUT) ||
 320                         (status & CMD_CRC)) {
 321                         if (host->cmd) {
 322                                 if (status & CMD_TIMEOUT) {
 323                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 324                                                 OMAP_HSMMC_READ(host->base,
 325                                                                 SYSCTL) | SRC);
 326                                         while (OMAP_HSMMC_READ(host->base,
 327                                                                 SYSCTL) & SRC) ;
 328                                         host->cmd->error = -ETIMEDOUT;
 329                                 } else {
 330                                         host->cmd->error = -EILSEQ;
 331                                 }
 332                                 end_cmd = 1;
 333                         }
 334                         if (host->data)
 335                                 mmc_dma_cleanup(host);
 336                 }
 337                 if ((status & DATA_TIMEOUT) ||
 338                         (status & DATA_CRC)) {
 339                         if (host->data) {
 340                                 if (status & DATA_TIMEOUT)
 341                                         mmc_dma_cleanup(host);
 342                                 else
 343                                         host->data->error = -EILSEQ;
 344                                 end_trans = 1;
 345                         }
 346                 }
 347                 if (status & CARD_ERR) {
 348                         dev_dbg(mmc_dev(host->mmc),
 349                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 350                         if (host->cmd)
 351                                 end_cmd = 1;
 352                         if (host->data)
 353                                 end_trans = 1;
 354                 }
 355         }
 356
 357         OMAP_HSMMC_WRITE(host->base, STAT, status);
 358
 359         if (end_cmd || (status & CC))
 360                 mmc_omap_cmd_done(host, host->cmd);
 361         if (end_trans || (status & TC))
 362                 mmc_omap_xfer_done(host, data);
 363
 364         return IRQ_HANDLED;
 365 }
 366
 367 /*
 368  * Switch MMC operating voltage
 369  */
 370 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 371 {
 372         u32 reg_val = 0;
 373         int ret;
 374
 375         /* Disable the clocks */
 376         clk_disable(host->fclk);
 377         clk_disable(host->iclk);
 378         clk_disable(host->dbclk);
 379
 380         /* Turn the power off */
 381         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 382         if (ret != 0)
 383                 goto err;
 384
 385         /* Turn the power ON with given VDD 1.8 or 3.0v */
 386         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 387         if (ret != 0)
 388                 goto err;
 389
 390         clk_enable(host->fclk);
 391         clk_enable(host->iclk);
 392         clk_enable(host->dbclk);
 393
 394         OMAP_HSMMC_WRITE(host->base, HCTL,
 395                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 396         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 397         /*
 398          * If a MMC dual voltage card is detected, the set_ios fn calls
 399          * this fn with VDD bit set for 1.8V. Upon card removal from the
 400          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 401          *
 402          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 403          * set in HCTL.
 404          */
 405         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 406                                 ((1 << vdd) == MMC_VDD_33_34)))
 407                 reg_val |= SDVS30;
 408         if ((1 << vdd) == MMC_VDD_165_195)
 409                 reg_val |= SDVS18;
 410
 411         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 412
 413         OMAP_HSMMC_WRITE(host->base, HCTL,
 414                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 415
 416         return 0;
 417 err:
 418         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 419         return ret;
 420 }
 421
 422 /*
 423  * Work Item to notify the core about card insertion/removal
 424  */
 425 static void mmc_omap_detect(struct work_struct *work)
 426 {
 427         u16 vdd = 0;
 428         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 429                                                 mmc_carddetect_work);
 430
 431         if (host->carddetect) {
 432                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 433                         /*
 434                          * Set the VDD back to 3V when the card is removed
 435                          * before the set_ios fn turns off the power.
 436                          */
 437                         vdd = fls(host->mmc->ocr_avail) - 1;
 438                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 439                                 host->mmc->ios.vdd = vdd;
 440                 }
 441                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 442         } else {
 443                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 444                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 445                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 446                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 447         }
 448 }
 449
 450 /*
 451  * ISR for handling card insertion and removal
 452  */
 453 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 454 {
 455         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 456
 457         host->carddetect = mmc_slot(host).card_detect(irq);
 458         schedule_work(&host->mmc_carddetect_work);
 459
 460         return IRQ_HANDLED;
 461 }
 462
 463 /*
 464  * DMA call back function
 465  */
 466 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 467 {
 468         struct mmc_omap_host *host = data;
 469
 470         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 471                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 472
 473         if (host->dma_ch < 0)
 474                 return;
 475
 476         omap_free_dma(host->dma_ch);
 477         host->dma_ch = -1;
 478         /*
 479          * DMA Callback: run in interrupt context.
 480          * mutex_unlock will through a kernel warning if used.
 481          */
 482         up(&host->sem);
 483 }
 484
 485 /*
 486  * Configure dma src and destination parameters
 487  */
 488 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 489                                 struct mmc_data *data)
 490 {
 491         if (sync_dir == 0) {
 492                 omap_set_dma_dest_params(host->dma_ch, 0,
 493                         OMAP_DMA_AMODE_CONSTANT,
 494                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 495                 omap_set_dma_src_params(host->dma_ch, 0,
 496                         OMAP_DMA_AMODE_POST_INC,
 497                         sg_dma_address(&data->sg[0]), 0, 0);
 498         } else {
 499                 omap_set_dma_src_params(host->dma_ch, 0,
 500                         OMAP_DMA_AMODE_CONSTANT,
 501                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 502                 omap_set_dma_dest_params(host->dma_ch, 0,
 503                         OMAP_DMA_AMODE_POST_INC,
 504                         sg_dma_address(&data->sg[0]), 0, 0);
 505         }
 506         return 0;
 507 }
 508 /*
 509  * Routine to configure and start DMA for the MMC card
 510  */
 511 static int
 512 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 513 {
 514         int sync_dev, sync_dir = 0;
 515         int dma_ch = 0, ret = 0, err = 1;
 516         struct mmc_data *data = req->data;
 517
 518         /*
 519          * If for some reason the DMA transfer is still active,
 520          * we wait for timeout period and free the dma
 521          */
 522         if (host->dma_ch != -1) {
 523                 set_current_state(TASK_UNINTERRUPTIBLE);
 524                 schedule_timeout(100);
 525                 if (down_trylock(&host->sem)) {
 526                         omap_free_dma(host->dma_ch);
 527                         host->dma_ch = -1;
 528                         up(&host->sem);
 529                         return err;
 530                 }
 531         } else {
 532                 if (down_trylock(&host->sem))
 533                         return err;
 534         }
 535
 536         if (!(data->flags & MMC_DATA_WRITE)) {
 537                 host->dma_dir = DMA_FROM_DEVICE;
 538                 if (host->id == OMAP_MMC1_DEVID)
 539                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 540                 else
 541                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 542         } else {
 543                 host->dma_dir = DMA_TO_DEVICE;
 544                 if (host->id == OMAP_MMC1_DEVID)
 545                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 546                 else
 547                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 548         }
 549
 550         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 551                         host, &dma_ch);
 552         if (ret != 0) {
 553                 dev_dbg(mmc_dev(host->mmc),
 554                         "%s: omap_request_dma() failed with %d\n",
 555                         mmc_hostname(host->mmc), ret);
 556                 return ret;
 557         }
 558
 559         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 560                         data->sg_len, host->dma_dir);
 561         host->dma_ch = dma_ch;
 562
 563         if (!(data->flags & MMC_DATA_WRITE))
 564                 mmc_omap_config_dma_param(1, host, data);
 565         else
 566                 mmc_omap_config_dma_param(0, host, data);
 567
 568         if ((data->blksz % 4) == 0)
 569                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 570                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 571                         sync_dev, sync_dir);
 572         else
 573                 /* REVISIT: The MMC buffer increments only when MSB is written.
 574                  * Return error for blksz which is non multiple of four.
 575                  */
 576                 return -EINVAL;
 577
 578         omap_start_dma(dma_ch);
 579         return 0;
 580 }
 581
 582 /*
 583  * Configure block length for MMC/SD cards and initiate the transfer.
 584  */
 585 static int
 586 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 587 {
 588         int ret;
 589         host->data = req->data;
 590
 591         if (req->data == NULL) {
 592                 host->datadir = OMAP_MMC_DATADIR_NONE;
 593                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 594                 return 0;
 595         }
 596
 597         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 598                                         | (req->data->blocks << 16));
 599
 600         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 601                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 602
 603         if (host->use_dma) {
 604                 ret = mmc_omap_start_dma_transfer(host, req);
 605                 if (ret != 0) {
 606                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 607                         return ret;
 608                 }
 609         }
 610         return 0;
 611 }
 612
 613 /*
 614  * Request function. for read/write operation
 615  */
 616 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 617 {
 618         struct mmc_omap_host *host = mmc_priv(mmc);
 619
 620         WARN_ON(host->mrq != NULL);
 621         host->mrq = req;
 622         mmc_omap_prepare_data(host, req);
 623         mmc_omap_start_command(host, req->cmd, req->data);
 624 }
 625
 626
 627 /* Routine to configure clock values. Exposed API to core */
 628 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 629 {
 630         struct mmc_omap_host *host = mmc_priv(mmc);
 631         u16 dsor = 0;
 632         unsigned long regval;
 633         unsigned long timeout;
 634
 635         switch (ios->power_mode) {
 636         case MMC_POWER_OFF:
 637                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 638                 break;
 639         case MMC_POWER_UP:
 640                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 641                 break;
 642         }
 643
 644         switch (mmc->ios.bus_width) {
 645         case MMC_BUS_WIDTH_4:
 646                 OMAP_HSMMC_WRITE(host->base, HCTL,
 647                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 648                 break;
 649         case MMC_BUS_WIDTH_1:
 650                 OMAP_HSMMC_WRITE(host->base, HCTL,
 651                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 652                 break;
 653         }
 654
 655         if (host->id == OMAP_MMC1_DEVID) {
 656                 /* Only MMC1 can operate at 3V/1.8V */
 657                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 658                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 659                                 /*
 660                                  * The mmc_select_voltage fn of the core does
 661                                  * not seem to set the power_mode to
 662                                  * MMC_POWER_UP upon recalculating the voltage.
 663                                  * vdd 1.8v.
 664                                  */
 665                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 666                                         dev_dbg(mmc_dev(host->mmc),
 667                                                 "Switch operation failed\n");
 668                 }
 669         }
 670
 671         if (ios->clock) {
 672                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 673                 if (dsor < 1)
 674                         dsor = 1;
 675
 676                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 677                         dsor++;
 678
 679                 if (dsor > 250)
 680                         dsor = 250;
 681         }
 682         omap_mmc_stop_clock(host);
 683         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 684         regval = regval & ~(CLKD_MASK);
 685         regval = regval | (dsor << 6) | (DTO << 16);
 686         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 687         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 688                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 689
 690         /* Wait till the ICS bit is set */
 691         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 692         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 693                 && time_before(jiffies, timeout))
 694                 msleep(1);
 695
 696         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 697                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 698
 699         if (ios->power_mode == MMC_POWER_ON)
 700                 send_init_stream(host);
 701
 702         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 703                 OMAP_HSMMC_WRITE(host->base, CON,
 704                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 705 }
 706 /* NOTE: Read only switch not supported yet */
 707 static struct mmc_host_ops mmc_omap_ops = {
 708         .request = omap_mmc_request,
 709         .set_ios = omap_mmc_set_ios,
 710 };
 711
 712 static int __init omap_mmc_probe(struct platform_device *pdev)
 713 {
 714         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 715         struct mmc_host *mmc;
 716         struct mmc_omap_host *host = NULL;
 717         struct resource *res;
 718         int ret = 0, irq;
 719         u32 hctl, capa;
 720
 721         if (pdata == NULL) {
 722                 dev_err(&pdev->dev, "Platform Data is missing\n");
 723                 return -ENXIO;
 724         }
 725
 726         if (pdata->nr_slots == 0) {
 727                 dev_err(&pdev->dev, "No Slots\n");
 728                 return -ENXIO;
 729         }
 730
 731         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 732         irq = platform_get_irq(pdev, 0);
 733         if (res == NULL || irq < 0)
 734                 return -ENXIO;
 735
 736         res = request_mem_region(res->start, res->end - res->start + 1,
 737                                                         pdev->name);
 738         if (res == NULL)
 739                 return -EBUSY;
 740
 741         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 742         if (!mmc) {
 743                 ret = -ENOMEM;
 744                 goto err;
 745         }
 746
 747         host            = mmc_priv(mmc);
 748         host->mmc       = mmc;
 749         host->pdata     = pdata;
 750         host->use_dma   = 1;
 751         host->dma_ch    = -1;
 752         host->irq       = irq;
 753         host->id        = pdev->id;
 754         host->slot_id   = 0;
 755         host->mapbase   = res->start;
 756         host->base      = ioremap(host->mapbase, SZ_4K);
 757         mmc->ops        = &mmc_omap_ops;
 758         mmc->f_min      = 400000;
 759         mmc->f_max      = 52000000;
 760
 761         sema_init(&host->sem, 1);
 762
 763         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 764         if (IS_ERR(host->iclk)) {
 765                 ret = PTR_ERR(host->iclk);
 766                 host->iclk = NULL;
 767                 goto err;
 768         }
 769         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 770         if (IS_ERR(host->fclk)) {
 771                 ret = PTR_ERR(host->fclk);
 772                 host->fclk = NULL;
 773                 clk_put(host->iclk);
 774                 goto err;
 775         }
 776
 777         if (clk_enable(host->fclk) != 0)
 778                 goto err;
 779
 780         if (clk_enable(host->iclk) != 0) {
 781                 clk_disable(host->fclk);
 782                 clk_put(host->fclk);
 783                 goto err;
 784         }
 785
 786         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 787         /*
 788          * MMC can still work without debounce clock.
 789          */
 790         if (IS_ERR(host->dbclk))
 791                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 792         else
 793                 if (clk_enable(host->dbclk) != 0)
 794                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 795                                                         " clk failed\n");
 796                 else
 797                         host->dbclk_enabled = 1;
 798
 799 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 800         mmc->max_phys_segs = 1;
 801         mmc->max_hw_segs = 1;
 802 #endif
 803         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 804         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 805         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 806         mmc->max_seg_size = mmc->max_req_size;
 807
 808         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 809         mmc->caps |= MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
 810                                 MMC_CAP_SD_HIGHSPEED;
 811
 812         if (pdata->conf.wire4)
 813                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 814
 815         /* Only MMC1 supports 3.0V */
 816         if (host->id == OMAP_MMC1_DEVID) {
 817                 hctl = SDVS30;
 818                 capa = VS30 | VS18;
 819         } else {
 820                 hctl = SDVS18;
 821                 capa = VS18;
 822         }
 823
 824         OMAP_HSMMC_WRITE(host->base, HCTL,
 825                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 826
 827         OMAP_HSMMC_WRITE(host->base, CAPA,
 828                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 829
 830         /* Set the controller to AUTO IDLE mode */
 831         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 832                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 833
 834         /* Set SD bus power bit */
 835         OMAP_HSMMC_WRITE(host->base, HCTL,
 836                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 837
 838         /* Request IRQ for MMC operations */
 839         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name,
 840                          host);
 841         if (ret) {
 842                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
 843                 goto irq_err;
 844         }
 845
 846         /* Request IRQ for card detect */
 847         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
 848                 ret = request_irq(mmc_slot(host).card_detect_irq,
 849                                   omap_mmc_cd_handler, IRQF_DISABLED, "MMC CD",
 850                                   host);
 851                 if (ret) {
 852                         dev_dbg(mmc_dev(host->mmc),
 853                                 "Unable to grab MMC CD IRQ");
 854                         free_irq(host->irq, host);
 855                         goto irq_err;
 856                 }
 857         }
 858
 859         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 860         if (pdata->init != NULL) {
 861                 if (pdata->init(&pdev->dev) != 0) {
 862                         free_irq(mmc_slot(host).card_detect_irq, host);
 863                         free_irq(host->irq, host);
 864                         goto irq_err;
 865                 }
 866         }
 867
 868         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 869         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 870
 871         platform_set_drvdata(pdev, host);
 872         mmc_add_host(mmc);
 873
 874         return 0;
 875
 876 err:
 877         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
 878         if (host)
 879                 mmc_free_host(mmc);
 880         return ret;
 881
 882 irq_err:
 883         dev_dbg(mmc_dev(host->mmc), "Unable to configure MMC IRQs\n");
 884         clk_disable(host->fclk);
 885         clk_disable(host->iclk);
 886         clk_put(host->fclk);
 887         clk_put(host->iclk);
 888         if (host->dbclk_enabled) {
 889                 clk_disable(host->dbclk);
 890                 clk_put(host->dbclk);
 891         }
 892
 893         if (host)
 894                 mmc_free_host(mmc);
 895         return ret;
 896 }
 897
 898 static int omap_mmc_remove(struct platform_device *pdev)
 899 {
 900         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 901
 902         platform_set_drvdata(pdev, NULL);
 903         if (host) {
 904                 if (host->pdata->cleanup)
 905                         host->pdata->cleanup(&pdev->dev);
 906                 free_irq(host->irq, host);
 907                 if (mmc_slot(host).card_detect_irq)
 908                         free_irq(mmc_slot(host).card_detect_irq, host);
 909                 flush_scheduled_work();
 910
 911                 clk_disable(host->fclk);
 912                 clk_disable(host->iclk);
 913                 clk_put(host->fclk);
 914                 clk_put(host->iclk);
 915                 if (host->dbclk_enabled) {
 916                         clk_disable(host->dbclk);
 917                         clk_put(host->dbclk);
 918                 }
 919
 920                 mmc_free_host(host->mmc);
 921         }
 922
 923         return 0;
 924 }
 925
 926 #ifdef CONFIG_PM
 927 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
 928 {
 929         int ret = 0;
 930         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 931
 932         if (host && host->suspended)
 933                 return 0;
 934
 935         if (host) {
 936                 ret = mmc_suspend_host(host->mmc, state);
 937                 if (ret == 0) {
 938                         host->suspended = 1;
 939
 940                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 941                         OMAP_HSMMC_WRITE(host->base, IE, 0);
 942
 943                         ret = host->pdata->suspend(&pdev->dev, host->slot_id);
 944                         if (ret)
 945                                 dev_dbg(mmc_dev(host->mmc),
 946                                         "Unable to handle MMC board"
 947                                         " level suspend\n");
 948
 949                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 950                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 951                                         OMAP_HSMMC_READ(host->base, HCTL)
 952                                         & SDVSCLR);
 953                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 954                                         OMAP_HSMMC_READ(host->base, HCTL)
 955                                         | SDVS30);
 956                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 957                                         OMAP_HSMMC_READ(host->base, HCTL)
 958                                         | SDBP);
 959                         }
 960
 961                         clk_disable(host->fclk);
 962                         clk_disable(host->iclk);
 963                         clk_disable(host->dbclk);
 964                 }
 965
 966         }
 967         return ret;
 968 }
 969
 970 /* Routine to resume the MMC device */
 971 static int omap_mmc_resume(struct platform_device *pdev)
 972 {
 973         int ret = 0;
 974         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 975
 976         if (host && !host->suspended)
 977                 return 0;
 978
 979         if (host) {
 980
 981                 ret = clk_enable(host->fclk);
 982                 if (ret)
 983                         goto clk_en_err;
 984
 985                 ret = clk_enable(host->iclk);
 986                 if (ret) {
 987                         clk_disable(host->fclk);
 988                         clk_put(host->fclk);
 989                         goto clk_en_err;
 990                 }
 991
 992                 if (clk_enable(host->dbclk) != 0)
 993                         dev_dbg(mmc_dev(host->mmc),
 994                                         "Enabling debounce clk failed\n");
 995
 996                 ret = host->pdata->resume(&pdev->dev, host->slot_id);
 997                 if (ret)
 998                         dev_dbg(mmc_dev(host->mmc),
 999                                         "Unmask interrupt failed\n");
1000
1001                 /* Notify the core to resume the host */
1002                 ret = mmc_resume_host(host->mmc);
1003                 if (ret == 0)
1004                         host->suspended = 0;
1005         }
1006
1007         return ret;
1008
1009 clk_en_err:
1010         dev_dbg(mmc_dev(host->mmc),
1011                 "Failed to enable MMC clocks during resume\n");
1012         return ret;
1013 }
1014
1015 #else
1016 #define omap_mmc_suspend        NULL
1017 #define omap_mmc_resume         NULL
1018 #endif
1019
1020 static struct platform_driver omap_mmc_driver = {
1021         .probe          = omap_mmc_probe,
1022         .remove         = omap_mmc_remove,
1023         .suspend        = omap_mmc_suspend,
1024         .resume         = omap_mmc_resume,
1025         .driver         = {
1026                 .name = DRIVER_NAME,
1027                 .owner = THIS_MODULE,
1028         },
1029 };
1030
1031 static int __init omap_mmc_init(void)
1032 {
1033         /* Register the MMC driver */
1034         return platform_driver_register(&omap_mmc_driver);
1035 }
1036
1037 static void __exit omap_mmc_cleanup(void)
1038 {
1039         /* Unregister MMC driver */
1040         platform_driver_unregister(&omap_mmc_driver);
1041 }
1042
1043 module_init(omap_mmc_init);
1044 module_exit(omap_mmc_cleanup);
1045
1046 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1047 MODULE_LICENSE("GPL");
1048 MODULE_ALIAS("platform:" DRIVER_NAME);
1049 MODULE_AUTHOR("Texas Instruments Inc");