2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
29 #include <linux/semaphore.h>
31 #include <mach/hardware.h>
32 #include <mach/board.h>
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
56 #define SDVS18 (0x5<<9)
57 #define SDVS30 (0x6<<9)
58 #define SDVSCLR 0xFFFFF1FF
59 #define SDVSDET 0x00000400
66 #define CLKD_MASK 0x0000FFC0
67 #define INT_EN_MASK 0x307F0033
68 #define INIT_STREAM (1<<1)
69 #define DP_SELECT (1<<21)
74 #define FOUR_BIT 1 << 1
79 #define CMD_TIMEOUT (1 << 16)
80 #define DATA_TIMEOUT (1 << 20)
81 #define CMD_CRC (1 << 17)
82 #define DATA_CRC (1 << 21)
83 #define CARD_ERR (1 << 28)
84 #define STAT_CLEAR 0xFFFFFFFF
85 #define INIT_STREAM_CMD 0x00000000
86 #define DUAL_VOLT_OCR_BIT 7
91 * FIXME: Most likely all the data using these _DEVID defines should come
92 * from the platform_data, or implemented in controller and slot specific
95 #define OMAP_MMC1_DEVID 0
96 #define OMAP_MMC2_DEVID 1
98 #define OMAP_MMC_DATADIR_NONE 0
99 #define OMAP_MMC_DATADIR_READ 1
100 #define OMAP_MMC_DATADIR_WRITE 2
101 #define MMC_TIMEOUT_MS 20
102 #define OMAP_MMC_MASTER_CLOCK 96000000
103 #define DRIVER_NAME "mmci-omap"
106 * One controller can have multiple slots, like on some omap boards using
107 * omap.c controller driver. Luckily this is not currently done on any known
108 * omap_hsmmc.c device.
110 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
113 * MMC Host controller read/write API's
115 #define OMAP_HSMMC_READ(base, reg) \
116 __raw_readl((base) + OMAP_HSMMC_##reg)
118 #define OMAP_HSMMC_WRITE(base, reg, val) \
119 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
121 struct mmc_omap_host {
123 struct mmc_host *mmc;
124 struct mmc_request *mrq;
125 struct mmc_command *cmd;
126 struct mmc_data *data;
130 struct semaphore sem;
131 struct work_struct mmc_carddetect_work;
133 resource_size_t mapbase;
135 unsigned int dma_len;
136 unsigned int dma_dir;
137 unsigned char bus_mode;
138 unsigned char datadir;
148 struct omap_mmc_platform_data *pdata;
152 * Stop clock to the card
154 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
156 OMAP_HSMMC_WRITE(host->base, SYSCTL,
157 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
158 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
159 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
163 * Send init stream sequence to card
164 * before sending IDLE command
166 static void send_init_stream(struct mmc_omap_host *host)
169 unsigned long timeout;
171 disable_irq(host->irq);
172 OMAP_HSMMC_WRITE(host->base, CON,
173 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
174 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
176 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
177 while ((reg != CC) && time_before(jiffies, timeout))
178 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
180 OMAP_HSMMC_WRITE(host->base, CON,
181 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
182 enable_irq(host->irq);
186 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
188 if (host->pdata->slots[host->slot_id].get_cover_state)
189 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
194 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
197 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
198 struct mmc_omap_host *host = mmc_priv(mmc);
200 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
204 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
207 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
210 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
211 struct mmc_omap_host *host = mmc_priv(mmc);
212 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
214 return sprintf(buf, "slot:%s\n", slot.name);
217 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
220 * Configure the response type and send the cmd.
223 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
224 struct mmc_data *data)
226 int cmdreg = 0, resptype = 0, cmdtype = 0;
228 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
229 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
233 * Clear status bits and enable interrupts
235 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
236 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
237 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
239 if (cmd->flags & MMC_RSP_PRESENT) {
240 if (cmd->flags & MMC_RSP_136)
247 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
248 * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
250 if (cmd->opcode == 12)
253 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
256 cmdreg |= DP_SELECT | MSBS | BCE;
257 if (data->flags & MMC_DATA_READ)
266 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
267 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
271 * Notify the transfer complete to MMC core
274 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
278 if (host->use_dma && host->dma_ch != -1)
279 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
282 host->datadir = OMAP_MMC_DATADIR_NONE;
285 data->bytes_xfered += data->blocks * (data->blksz);
287 data->bytes_xfered = 0;
291 mmc_request_done(host->mmc, data->mrq);
294 mmc_omap_start_command(host, data->stop, NULL);
298 * Notify the core about command completion
301 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
305 if (cmd->flags & MMC_RSP_PRESENT) {
306 if (cmd->flags & MMC_RSP_136) {
307 /* response type 2 */
308 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
309 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
310 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
311 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
313 /* response types 1, 1b, 3, 4, 5, 6 */
314 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
317 if (host->data == NULL || cmd->error) {
319 mmc_request_done(host->mmc, cmd->mrq);
324 * DMA clean up for command errors
326 static void mmc_dma_cleanup(struct mmc_omap_host *host)
328 host->data->error = -ETIMEDOUT;
330 if (host->use_dma && host->dma_ch != -1) {
331 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
333 omap_free_dma(host->dma_ch);
338 host->datadir = OMAP_MMC_DATADIR_NONE;
342 * Readable error output
344 #ifdef CONFIG_MMC_DEBUG
345 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
347 /* --- means reserved bit without definition at documentation */
348 static const char *mmc_omap_status_bits[] = {
349 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
350 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
351 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
352 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
356 dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
358 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
359 if (status & (1 << i))
361 * KERN_* facility is not used here because this should
362 * print a single line.
364 printk(" %s", mmc_omap_status_bits[i]);
369 #endif /* CONFIG_MMC_DEBUG */
373 * MMC controller IRQ handler
375 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
377 struct mmc_omap_host *host = dev_id;
378 struct mmc_data *data;
379 int end_cmd = 0, end_trans = 0, status;
381 if (host->cmd == NULL && host->data == NULL) {
382 OMAP_HSMMC_WRITE(host->base, STAT,
383 OMAP_HSMMC_READ(host->base, STAT));
388 status = OMAP_HSMMC_READ(host->base, STAT);
389 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
392 #ifdef CONFIG_MMC_DEBUG
393 mmc_omap_report_irq(host, status);
395 if ((status & CMD_TIMEOUT) ||
396 (status & CMD_CRC)) {
398 if (status & CMD_TIMEOUT) {
399 OMAP_HSMMC_WRITE(host->base, SYSCTL,
400 OMAP_HSMMC_READ(host->base,
402 while (OMAP_HSMMC_READ(host->base,
404 host->cmd->error = -ETIMEDOUT;
406 host->cmd->error = -EILSEQ;
411 mmc_dma_cleanup(host);
413 if ((status & DATA_TIMEOUT) ||
414 (status & DATA_CRC)) {
416 if (status & DATA_TIMEOUT)
417 mmc_dma_cleanup(host);
419 host->data->error = -EILSEQ;
423 if (status & CARD_ERR) {
424 dev_dbg(mmc_dev(host->mmc),
425 "Ignoring card err CMD%d\n", host->cmd->opcode);
433 OMAP_HSMMC_WRITE(host->base, STAT, status);
435 if (end_cmd || (status & CC))
436 mmc_omap_cmd_done(host, host->cmd);
437 if (end_trans || (status & TC))
438 mmc_omap_xfer_done(host, data);
444 * Switch MMC operating voltage
446 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
451 /* Disable the clocks */
452 clk_disable(host->fclk);
453 clk_disable(host->iclk);
454 clk_disable(host->dbclk);
456 /* Turn the power off */
457 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
461 /* Turn the power ON with given VDD 1.8 or 3.0v */
462 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
466 clk_enable(host->fclk);
467 clk_enable(host->iclk);
468 clk_enable(host->dbclk);
470 OMAP_HSMMC_WRITE(host->base, HCTL,
471 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
472 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
474 * If a MMC dual voltage card is detected, the set_ios fn calls
475 * this fn with VDD bit set for 1.8V. Upon card removal from the
476 * slot, mmc_omap_detect fn sets the VDD back to 3V.
478 * Only MMC1 supports 3.0V. MMC2 will not function if SDVS30 is
481 if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
482 ((1 << vdd) == MMC_VDD_33_34)))
484 if ((1 << vdd) == MMC_VDD_165_195)
487 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
489 OMAP_HSMMC_WRITE(host->base, HCTL,
490 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
494 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
499 * Work Item to notify the core about card insertion/removal
501 static void mmc_omap_detect(struct work_struct *work)
504 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
505 mmc_carddetect_work);
507 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
508 if (host->carddetect) {
509 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
511 * Set the VDD back to 3V when the card is removed
512 * before the set_ios fn turns off the power.
514 vdd = fls(host->mmc->ocr_avail) - 1;
515 if (omap_mmc_switch_opcond(host, vdd) != 0)
516 host->mmc->ios.vdd = vdd;
518 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
520 OMAP_HSMMC_WRITE(host->base, SYSCTL,
521 OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
522 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
523 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
528 * ISR for handling card insertion and removal
530 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
532 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
534 host->carddetect = mmc_slot(host).card_detect(irq);
535 schedule_work(&host->mmc_carddetect_work);
541 * DMA call back function
543 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
545 struct mmc_omap_host *host = data;
547 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
548 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
550 if (host->dma_ch < 0)
553 omap_free_dma(host->dma_ch);
556 * DMA Callback: run in interrupt context.
557 * mutex_unlock will through a kernel warning if used.
563 * Configure dma src and destination parameters
565 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
566 struct mmc_data *data)
569 omap_set_dma_dest_params(host->dma_ch, 0,
570 OMAP_DMA_AMODE_CONSTANT,
571 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
572 omap_set_dma_src_params(host->dma_ch, 0,
573 OMAP_DMA_AMODE_POST_INC,
574 sg_dma_address(&data->sg[0]), 0, 0);
576 omap_set_dma_src_params(host->dma_ch, 0,
577 OMAP_DMA_AMODE_CONSTANT,
578 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
579 omap_set_dma_dest_params(host->dma_ch, 0,
580 OMAP_DMA_AMODE_POST_INC,
581 sg_dma_address(&data->sg[0]), 0, 0);
586 * Routine to configure and start DMA for the MMC card
589 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
591 int sync_dev, sync_dir = 0;
592 int dma_ch = 0, ret = 0, err = 1;
593 struct mmc_data *data = req->data;
596 * If for some reason the DMA transfer is still active,
597 * we wait for timeout period and free the dma
599 if (host->dma_ch != -1) {
600 set_current_state(TASK_UNINTERRUPTIBLE);
601 schedule_timeout(100);
602 if (down_trylock(&host->sem)) {
603 omap_free_dma(host->dma_ch);
609 if (down_trylock(&host->sem))
613 if (!(data->flags & MMC_DATA_WRITE)) {
614 host->dma_dir = DMA_FROM_DEVICE;
615 if (host->id == OMAP_MMC1_DEVID)
616 sync_dev = OMAP24XX_DMA_MMC1_RX;
618 sync_dev = OMAP24XX_DMA_MMC2_RX;
620 host->dma_dir = DMA_TO_DEVICE;
621 if (host->id == OMAP_MMC1_DEVID)
622 sync_dev = OMAP24XX_DMA_MMC1_TX;
624 sync_dev = OMAP24XX_DMA_MMC2_TX;
627 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
630 dev_dbg(mmc_dev(host->mmc),
631 "%s: omap_request_dma() failed with %d\n",
632 mmc_hostname(host->mmc), ret);
636 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, host->dma_dir);
638 host->dma_ch = dma_ch;
640 if (!(data->flags & MMC_DATA_WRITE))
641 mmc_omap_config_dma_param(1, host, data);
643 mmc_omap_config_dma_param(0, host, data);
645 if ((data->blksz % 4) == 0)
646 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
647 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
650 /* REVISIT: The MMC buffer increments only when MSB is written.
651 * Return error for blksz which is non multiple of four.
655 omap_start_dma(dma_ch);
660 * Configure block length for MMC/SD cards and initiate the transfer.
663 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
666 host->data = req->data;
668 if (req->data == NULL) {
669 host->datadir = OMAP_MMC_DATADIR_NONE;
670 OMAP_HSMMC_WRITE(host->base, BLK, 0);
674 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
675 | (req->data->blocks << 16));
677 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
678 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
681 ret = mmc_omap_start_dma_transfer(host, req);
683 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
691 * Request function. for read/write operation
693 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
695 struct mmc_omap_host *host = mmc_priv(mmc);
697 WARN_ON(host->mrq != NULL);
699 mmc_omap_prepare_data(host, req);
700 mmc_omap_start_command(host, req->cmd, req->data);
704 /* Routine to configure clock values. Exposed API to core */
705 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
707 struct mmc_omap_host *host = mmc_priv(mmc);
709 unsigned long regval;
710 unsigned long timeout;
712 switch (ios->power_mode) {
714 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
717 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
721 switch (mmc->ios.bus_width) {
722 case MMC_BUS_WIDTH_4:
723 OMAP_HSMMC_WRITE(host->base, HCTL,
724 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
726 case MMC_BUS_WIDTH_1:
727 OMAP_HSMMC_WRITE(host->base, HCTL,
728 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
732 if (host->id == OMAP_MMC1_DEVID) {
733 /* Only MMC1 can operate at 3V/1.8V */
734 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
735 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
737 * The mmc_select_voltage fn of the core does
738 * not seem to set the power_mode to
739 * MMC_POWER_UP upon recalculating the voltage.
742 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
743 dev_dbg(mmc_dev(host->mmc),
744 "Switch operation failed\n");
749 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
753 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
759 omap_mmc_stop_clock(host);
760 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
761 regval = regval & ~(CLKD_MASK);
762 regval = regval | (dsor << 6) | (DTO << 16);
763 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
764 OMAP_HSMMC_WRITE(host->base, SYSCTL,
765 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
767 /* Wait till the ICS bit is set */
768 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
769 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
770 && time_before(jiffies, timeout))
773 OMAP_HSMMC_WRITE(host->base, SYSCTL,
774 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
776 if (ios->power_mode == MMC_POWER_ON)
777 send_init_stream(host);
779 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
780 OMAP_HSMMC_WRITE(host->base, CON,
781 OMAP_HSMMC_READ(host->base, CON) | OD);
783 /* NOTE: Read only switch not supported yet */
784 static struct mmc_host_ops mmc_omap_ops = {
785 .request = omap_mmc_request,
786 .set_ios = omap_mmc_set_ios,
789 static int __init omap_mmc_probe(struct platform_device *pdev)
791 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
792 struct mmc_host *mmc;
793 struct mmc_omap_host *host = NULL;
794 struct resource *res;
799 dev_err(&pdev->dev, "Platform Data is missing\n");
803 if (pdata->nr_slots == 0) {
804 dev_err(&pdev->dev, "No Slots\n");
808 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
809 irq = platform_get_irq(pdev, 0);
810 if (res == NULL || irq < 0)
813 res = request_mem_region(res->start, res->end - res->start + 1,
818 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
824 host = mmc_priv(mmc);
827 host->dev = &pdev->dev;
829 host->dev->dma_mask = &pdata->dma_mask;
834 host->mapbase = res->start;
835 host->base = ioremap(host->mapbase, SZ_4K);
836 mmc->ops = &mmc_omap_ops;
838 mmc->f_max = 52000000;
840 sema_init(&host->sem, 1);
842 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
843 if (IS_ERR(host->iclk)) {
844 ret = PTR_ERR(host->iclk);
848 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
849 if (IS_ERR(host->fclk)) {
850 ret = PTR_ERR(host->fclk);
856 if (clk_enable(host->fclk) != 0) {
862 if (clk_enable(host->iclk) != 0) {
863 clk_disable(host->fclk);
869 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
871 * MMC can still work without debounce clock.
873 if (IS_ERR(host->dbclk))
874 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
876 if (clk_enable(host->dbclk) != 0)
877 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
880 host->dbclk_enabled = 1;
882 #ifdef CONFIG_MMC_BLOCK_BOUNCE
883 mmc->max_phys_segs = 1;
884 mmc->max_hw_segs = 1;
886 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
887 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
888 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
889 mmc->max_seg_size = mmc->max_req_size;
891 mmc->ocr_avail = mmc_slot(host).ocr_mask;
892 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
894 if (pdata->slots[host->slot_id].wire4)
895 mmc->caps |= MMC_CAP_4_BIT_DATA;
897 /* Only MMC1 supports 3.0V */
898 if (host->id == OMAP_MMC1_DEVID) {
906 OMAP_HSMMC_WRITE(host->base, HCTL,
907 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
909 OMAP_HSMMC_WRITE(host->base, CAPA,
910 OMAP_HSMMC_READ(host->base, CAPA) | capa);
912 /* Set the controller to AUTO IDLE mode */
913 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
914 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
916 /* Set SD bus power bit */
917 OMAP_HSMMC_WRITE(host->base, HCTL,
918 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
920 /* Request IRQ for MMC operations */
921 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
922 mmc_hostname(mmc), host);
924 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
928 /* Request IRQ for card detect */
929 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
930 ret = request_irq(mmc_slot(host).card_detect_irq,
932 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
934 mmc_hostname(mmc), host);
936 dev_dbg(mmc_dev(host->mmc),
937 "Unable to grab MMC CD IRQ\n");
942 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
943 if (pdata->init != NULL) {
944 if (pdata->init(&pdev->dev) != 0) {
945 dev_dbg(mmc_dev(host->mmc),
946 "Unable to configure MMC IRQs\n");
947 goto err_irq_cd_init;
951 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
952 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
954 platform_set_drvdata(pdev, host);
957 if (host->pdata->slots[host->slot_id].name != NULL) {
958 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
962 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
963 host->pdata->slots[host->slot_id].get_cover_state) {
964 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
966 goto err_cover_switch;
972 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
974 mmc_remove_host(mmc);
976 free_irq(mmc_slot(host).card_detect_irq, host);
978 free_irq(host->irq, host);
980 clk_disable(host->fclk);
981 clk_disable(host->iclk);
984 if (host->dbclk_enabled) {
985 clk_disable(host->dbclk);
986 clk_put(host->dbclk);
992 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
993 release_mem_region(res->start, res->end - res->start + 1);
999 static int omap_mmc_remove(struct platform_device *pdev)
1001 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1002 struct resource *res;
1005 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1007 * Set the vdd back to 3V,
1008 * applicable for dual volt support.
1010 vdd = fls(host->mmc->ocr_avail) - 1;
1011 if (omap_mmc_switch_opcond(host, vdd) != 0)
1012 host->mmc->ios.vdd = vdd;
1015 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017 release_mem_region(res->start, res->end - res->start + 1);
1019 platform_set_drvdata(pdev, NULL);
1021 mmc_remove_host(host->mmc);
1022 if (host->pdata->cleanup)
1023 host->pdata->cleanup(&pdev->dev);
1024 free_irq(host->irq, host);
1025 if (mmc_slot(host).card_detect_irq)
1026 free_irq(mmc_slot(host).card_detect_irq, host);
1027 flush_scheduled_work();
1029 clk_disable(host->fclk);
1030 clk_disable(host->iclk);
1031 clk_put(host->fclk);
1032 clk_put(host->iclk);
1033 if (host->dbclk_enabled) {
1034 clk_disable(host->dbclk);
1035 clk_put(host->dbclk);
1038 mmc_free_host(host->mmc);
1039 iounmap(host->base);
1046 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1049 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1051 if (host && host->suspended)
1055 ret = mmc_suspend_host(host->mmc, state);
1057 host->suspended = 1;
1059 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1060 OMAP_HSMMC_WRITE(host->base, IE, 0);
1062 if (host->pdata->suspend) {
1063 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1065 dev_dbg(mmc_dev(host->mmc),
1066 "Unable to handle MMC board"
1067 " level suspend\n");
1070 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1071 OMAP_HSMMC_WRITE(host->base, HCTL,
1072 OMAP_HSMMC_READ(host->base, HCTL)
1074 OMAP_HSMMC_WRITE(host->base, HCTL,
1075 OMAP_HSMMC_READ(host->base, HCTL)
1077 OMAP_HSMMC_WRITE(host->base, HCTL,
1078 OMAP_HSMMC_READ(host->base, HCTL)
1082 clk_disable(host->fclk);
1083 clk_disable(host->iclk);
1084 clk_disable(host->dbclk);
1091 /* Routine to resume the MMC device */
1092 static int omap_mmc_resume(struct platform_device *pdev)
1095 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1097 if (host && !host->suspended)
1102 ret = clk_enable(host->fclk);
1106 ret = clk_enable(host->iclk);
1108 clk_disable(host->fclk);
1109 clk_put(host->fclk);
1113 if (clk_enable(host->dbclk) != 0)
1114 dev_dbg(mmc_dev(host->mmc),
1115 "Enabling debounce clk failed\n");
1117 if (host->pdata->resume) {
1118 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1120 dev_dbg(mmc_dev(host->mmc),
1121 "Unmask interrupt failed\n");
1124 /* Notify the core to resume the host */
1125 ret = mmc_resume_host(host->mmc);
1127 host->suspended = 0;
1133 dev_dbg(mmc_dev(host->mmc),
1134 "Failed to enable MMC clocks during resume\n");
1139 #define omap_mmc_suspend NULL
1140 #define omap_mmc_resume NULL
1143 static struct platform_driver omap_mmc_driver = {
1144 .probe = omap_mmc_probe,
1145 .remove = omap_mmc_remove,
1146 .suspend = omap_mmc_suspend,
1147 .resume = omap_mmc_resume,
1149 .name = DRIVER_NAME,
1150 .owner = THIS_MODULE,
1154 static int __init omap_mmc_init(void)
1156 /* Register the MMC driver */
1157 return platform_driver_register(&omap_mmc_driver);
1160 static void __exit omap_mmc_cleanup(void)
1162 /* Unregister MMC driver */
1163 platform_driver_unregister(&omap_mmc_driver);
1166 module_init(omap_mmc_init);
1167 module_exit(omap_mmc_cleanup);
1169 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1170 MODULE_LICENSE("GPL");
1171 MODULE_ALIAS("platform:" DRIVER_NAME);
1172 MODULE_AUTHOR("Texas Instruments Inc");