drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define OMAP_MMC_DATADIR_NONE   0
 102 #define OMAP_MMC_DATADIR_READ   1
 103 #define OMAP_MMC_DATADIR_WRITE  2
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 struct mmc_omap_host {
 125         struct  device          *dev;
 126         struct  mmc_host        *mmc;
 127         struct  mmc_request     *mrq;
 128         struct  mmc_command     *cmd;
 129         struct  mmc_data        *data;
 130         struct  clk             *fclk;
 131         struct  clk             *iclk;
 132         struct  clk             *dbclk;
 133         struct  semaphore       sem;
 134         struct  work_struct     mmc_carddetect_work;
 135         void    __iomem         *base;
 136         resource_size_t         mapbase;
 137         unsigned int            id;
 138         unsigned int            dma_len;
 139         unsigned int            dma_dir;
 140         unsigned char           bus_mode;
 141         unsigned char           datadir;
 142         u32                     *buffer;
 143         u32                     bytesleft;
 144         int                     suspended;
 145         int                     irq;
 146         int                     carddetect;
 147         int                     use_dma, dma_ch;
 148         int                     initstr;
 149         int                     slot_id;
 150         int                     dbclk_enabled;
 151         struct  omap_mmc_platform_data  *pdata;
 152 };
 153
 154 /*
 155  * Stop clock to the card
 156  */
 157 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 158 {
 159         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 160                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 161         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 162                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 163 }
 164
 165 /*
 166  * Send init stream sequence to card
 167  * before sending IDLE command
 168  */
 169 static void send_init_stream(struct mmc_omap_host *host)
 170 {
 171         int reg = 0;
 172         unsigned long timeout;
 173
 174         disable_irq(host->irq);
 175         OMAP_HSMMC_WRITE(host->base, CON,
 176                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 177         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 178
 179         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 180         while ((reg != CC) && time_before(jiffies, timeout))
 181                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 182
 183         OMAP_HSMMC_WRITE(host->base, CON,
 184                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 185         enable_irq(host->irq);
 186 }
 187
 188 static inline
 189 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 190 {
 191         if (host->pdata->slots[host->slot_id].get_cover_state)
 192                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 193         return 1;
 194 }
 195
 196 static ssize_t
 197 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 198                            char *buf)
 199 {
 200         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 201         struct mmc_omap_host *host = mmc_priv(mmc);
 202
 203         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 204                        "open");
 205 }
 206
 207 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 208
 209 static ssize_t
 210 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 211                         char *buf)
 212 {
 213         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 214         struct mmc_omap_host *host = mmc_priv(mmc);
 215         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 216
 217         return sprintf(buf, "slot:%s\n", slot.name);
 218 }
 219
 220 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 221
 222 /*
 223  * Configure the response type and send the cmd.
 224  */
 225 static void
 226 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 227         struct mmc_data *data)
 228 {
 229         int cmdreg = 0, resptype = 0, cmdtype = 0;
 230
 231         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 232                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 233         host->cmd = cmd;
 234
 235         /*
 236          * Clear status bits and enable interrupts
 237          */
 238         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 239         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 240         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 241
 242         if (cmd->flags & MMC_RSP_PRESENT) {
 243                 if (cmd->flags & MMC_RSP_136)
 244                         resptype = 1;
 245                 else
 246                         resptype = 2;
 247         }
 248
 249         /*
 250          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 251          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 252          */
 253         if (cmd->opcode == 12)
 254                 cmdtype = 0x3;
 255
 256         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 257
 258         if (data) {
 259                 cmdreg |= DP_SELECT | MSBS | BCE;
 260                 if (data->flags & MMC_DATA_READ)
 261                         cmdreg |= DDIR;
 262                 else
 263                         cmdreg &= ~(DDIR);
 264         }
 265
 266         if (host->use_dma)
 267                 cmdreg |= DMA_EN;
 268
 269         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 270         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 271 }
 272
 273 /*
 274  * Notify the transfer complete to MMC core
 275  */
 276 static void
 277 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 278 {
 279         host->data = NULL;
 280
 281         if (host->use_dma && host->dma_ch != -1)
 282                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 283                         host->dma_dir);
 284
 285         host->datadir = OMAP_MMC_DATADIR_NONE;
 286
 287         if (!data->error)
 288                 data->bytes_xfered += data->blocks * (data->blksz);
 289         else
 290                 data->bytes_xfered = 0;
 291
 292         if (!data->stop) {
 293                 host->mrq = NULL;
 294                 mmc_request_done(host->mmc, data->mrq);
 295                 return;
 296         }
 297         mmc_omap_start_command(host, data->stop, NULL);
 298 }
 299
 300 /*
 301  * Notify the core about command completion
 302  */
 303 static void
 304 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 305 {
 306         host->cmd = NULL;
 307
 308         if (cmd->flags & MMC_RSP_PRESENT) {
 309                 if (cmd->flags & MMC_RSP_136) {
 310                         /* response type 2 */
 311                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 312                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 313                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 314                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 315                 } else {
 316                         /* response types 1, 1b, 3, 4, 5, 6 */
 317                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 318                 }
 319         }
 320         if (host->data == NULL || cmd->error) {
 321                 host->mrq = NULL;
 322                 mmc_request_done(host->mmc, cmd->mrq);
 323         }
 324 }
 325
 326 /*
 327  * DMA clean up for command errors
 328  */
 329 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 330 {
 331         host->data->error = -ETIMEDOUT;
 332
 333         if (host->use_dma && host->dma_ch != -1) {
 334                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 335                         host->dma_dir);
 336                 omap_free_dma(host->dma_ch);
 337                 host->dma_ch = -1;
 338                 up(&host->sem);
 339         }
 340         host->data = NULL;
 341         host->datadir = OMAP_MMC_DATADIR_NONE;
 342 }
 343
 344 /*
 345  * Readable error output
 346  */
 347 #ifdef CONFIG_MMC_DEBUG
 348 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 349 {
 350         /* --- means reserved bit without definition at documentation */
 351         static const char *mmc_omap_status_bits[] = {
 352                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 353                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 354                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 355                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 356         };
 357         int i;
 358
 359         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 360
 361         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 362                 if (status & (1 << i))
 363                         /*
 364                          * KERN_* facility is not used here because this should
 365                          * print a single line.
 366                          */
 367                         printk(" %s", mmc_omap_status_bits[i]);
 368
 369         printk("\n");
 370
 371 }
 372 #endif  /* CONFIG_MMC_DEBUG */
 373
 374
 375 /*
 376  * MMC controller IRQ handler
 377  */
 378 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 379 {
 380         struct mmc_omap_host *host = dev_id;
 381         struct mmc_data *data;
 382         int end_cmd = 0, end_trans = 0, status;
 383
 384         if (host->cmd == NULL && host->data == NULL) {
 385                 OMAP_HSMMC_WRITE(host->base, STAT,
 386                         OMAP_HSMMC_READ(host->base, STAT));
 387                 return IRQ_HANDLED;
 388         }
 389
 390         data = host->data;
 391         status = OMAP_HSMMC_READ(host->base, STAT);
 392         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 393
 394         if (status & ERR) {
 395 #ifdef CONFIG_MMC_DEBUG
 396                 mmc_omap_report_irq(host, status);
 397 #endif
 398                 if ((status & CMD_TIMEOUT) ||
 399                         (status & CMD_CRC)) {
 400                         if (host->cmd) {
 401                                 if (status & CMD_TIMEOUT) {
 402                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 403                                                 OMAP_HSMMC_READ(host->base,
 404                                                                 SYSCTL) | SRC);
 405                                         while (OMAP_HSMMC_READ(host->base,
 406                                                                 SYSCTL) & SRC) ;
 407                                         host->cmd->error = -ETIMEDOUT;
 408                                 } else {
 409                                         host->cmd->error = -EILSEQ;
 410                                 }
 411                                 end_cmd = 1;
 412                         }
 413                         if (host->data)
 414                                 mmc_dma_cleanup(host);
 415                 }
 416                 if ((status & DATA_TIMEOUT) ||
 417                         (status & DATA_CRC)) {
 418                         if (host->data) {
 419                                 if (status & DATA_TIMEOUT)
 420                                         mmc_dma_cleanup(host);
 421                                 else
 422                                         host->data->error = -EILSEQ;
 423                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 424                                         OMAP_HSMMC_READ(host->base,
 425                                                         SYSCTL) | SRD);
 426                                 while (OMAP_HSMMC_READ(host->base,
 427                                                         SYSCTL) & SRD) ;
 428                                 end_trans = 1;
 429                         }
 430                 }
 431                 if (status & CARD_ERR) {
 432                         dev_dbg(mmc_dev(host->mmc),
 433                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 434                         if (host->cmd)
 435                                 end_cmd = 1;
 436                         if (host->data)
 437                                 end_trans = 1;
 438                 }
 439         }
 440
 441         OMAP_HSMMC_WRITE(host->base, STAT, status);
 442
 443         if (end_cmd || (status & CC))
 444                 mmc_omap_cmd_done(host, host->cmd);
 445         if (end_trans || (status & TC))
 446                 mmc_omap_xfer_done(host, data);
 447
 448         return IRQ_HANDLED;
 449 }
 450
 451 /*
 452  * Switch MMC operating voltage
 453  */
 454 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 455 {
 456         u32 reg_val = 0;
 457         int ret;
 458
 459         /* Disable the clocks */
 460         clk_disable(host->fclk);
 461         clk_disable(host->iclk);
 462         clk_disable(host->dbclk);
 463
 464         /* Turn the power off */
 465         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 466         if (ret != 0)
 467                 goto err;
 468
 469         /* Turn the power ON with given VDD 1.8 or 3.0v */
 470         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 471         if (ret != 0)
 472                 goto err;
 473
 474         clk_enable(host->fclk);
 475         clk_enable(host->iclk);
 476         clk_enable(host->dbclk);
 477
 478         OMAP_HSMMC_WRITE(host->base, HCTL,
 479                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 480         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 481         /*
 482          * If a MMC dual voltage card is detected, the set_ios fn calls
 483          * this fn with VDD bit set for 1.8V. Upon card removal from the
 484          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 485          *
 486          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 487          * set in HCTL.
 488          */
 489         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 490                                 ((1 << vdd) == MMC_VDD_33_34)))
 491                 reg_val |= SDVS30;
 492         if ((1 << vdd) == MMC_VDD_165_195)
 493                 reg_val |= SDVS18;
 494
 495         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 496
 497         OMAP_HSMMC_WRITE(host->base, HCTL,
 498                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 499
 500         return 0;
 501 err:
 502         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 503         return ret;
 504 }
 505
 506 /*
 507  * Work Item to notify the core about card insertion/removal
 508  */
 509 static void mmc_omap_detect(struct work_struct *work)
 510 {
 511         u16 vdd = 0;
 512         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 513                                                 mmc_carddetect_work);
 514
 515         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 516         if (host->carddetect) {
 517                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 518                         /*
 519                          * Set the VDD back to 3V when the card is removed
 520                          * before the set_ios fn turns off the power.
 521                          */
 522                         vdd = fls(host->mmc->ocr_avail) - 1;
 523                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 524                                 host->mmc->ios.vdd = vdd;
 525                 }
 526                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 527         } else {
 528                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 529                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 530                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 531                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 532         }
 533 }
 534
 535 /*
 536  * ISR for handling card insertion and removal
 537  */
 538 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 539 {
 540         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 541
 542         host->carddetect = mmc_slot(host).card_detect(irq);
 543         schedule_work(&host->mmc_carddetect_work);
 544
 545         return IRQ_HANDLED;
 546 }
 547
 548 /*
 549  * DMA call back function
 550  */
 551 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 552 {
 553         struct mmc_omap_host *host = data;
 554
 555         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 556                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 557
 558         if (host->dma_ch < 0)
 559                 return;
 560
 561         omap_free_dma(host->dma_ch);
 562         host->dma_ch = -1;
 563         /*
 564          * DMA Callback: run in interrupt context.
 565          * mutex_unlock will through a kernel warning if used.
 566          */
 567         up(&host->sem);
 568 }
 569
 570 /*
 571  * Configure dma src and destination parameters
 572  */
 573 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 574                                 struct mmc_data *data)
 575 {
 576         if (sync_dir == 0) {
 577                 omap_set_dma_dest_params(host->dma_ch, 0,
 578                         OMAP_DMA_AMODE_CONSTANT,
 579                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 580                 omap_set_dma_src_params(host->dma_ch, 0,
 581                         OMAP_DMA_AMODE_POST_INC,
 582                         sg_dma_address(&data->sg[0]), 0, 0);
 583         } else {
 584                 omap_set_dma_src_params(host->dma_ch, 0,
 585                         OMAP_DMA_AMODE_CONSTANT,
 586                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 587                 omap_set_dma_dest_params(host->dma_ch, 0,
 588                         OMAP_DMA_AMODE_POST_INC,
 589                         sg_dma_address(&data->sg[0]), 0, 0);
 590         }
 591         return 0;
 592 }
 593 /*
 594  * Routine to configure and start DMA for the MMC card
 595  */
 596 static int
 597 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 598 {
 599         int sync_dev, sync_dir = 0;
 600         int dma_ch = 0, ret = 0, err = 1;
 601         struct mmc_data *data = req->data;
 602
 603         /*
 604          * If for some reason the DMA transfer is still active,
 605          * we wait for timeout period and free the dma
 606          */
 607         if (host->dma_ch != -1) {
 608                 set_current_state(TASK_UNINTERRUPTIBLE);
 609                 schedule_timeout(100);
 610                 if (down_trylock(&host->sem)) {
 611                         omap_free_dma(host->dma_ch);
 612                         host->dma_ch = -1;
 613                         up(&host->sem);
 614                         return err;
 615                 }
 616         } else {
 617                 if (down_trylock(&host->sem))
 618                         return err;
 619         }
 620
 621         if (!(data->flags & MMC_DATA_WRITE)) {
 622                 host->dma_dir = DMA_FROM_DEVICE;
 623                 if (host->id == OMAP_MMC1_DEVID)
 624                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 625                 else
 626                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 627         } else {
 628                 host->dma_dir = DMA_TO_DEVICE;
 629                 if (host->id == OMAP_MMC1_DEVID)
 630                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 631                 else
 632                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 633         }
 634
 635         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 636                         host, &dma_ch);
 637         if (ret != 0) {
 638                 dev_dbg(mmc_dev(host->mmc),
 639                         "%s: omap_request_dma() failed with %d\n",
 640                         mmc_hostname(host->mmc), ret);
 641                 return ret;
 642         }
 643
 644         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 645                         data->sg_len, host->dma_dir);
 646         host->dma_ch = dma_ch;
 647
 648         if (!(data->flags & MMC_DATA_WRITE))
 649                 mmc_omap_config_dma_param(1, host, data);
 650         else
 651                 mmc_omap_config_dma_param(0, host, data);
 652
 653         if ((data->blksz % 4) == 0)
 654                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 655                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 656                         sync_dev, sync_dir);
 657         else
 658                 /* REVISIT: The MMC buffer increments only when MSB is written.
 659                  * Return error for blksz which is non multiple of four.
 660                  */
 661                 return -EINVAL;
 662
 663         omap_start_dma(dma_ch);
 664         return 0;
 665 }
 666
 667 static void set_data_timeout(struct mmc_omap_host *host,
 668                              struct mmc_request *req)
 669 {
 670         unsigned int timeout, cycle_ns;
 671         uint32_t reg, clkd, dto = 0;
 672
 673         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 674         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 675         if (clkd == 0)
 676                 clkd = 1;
 677
 678         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 679         timeout = req->data->timeout_ns / cycle_ns;
 680         timeout += req->data->timeout_clks;
 681         if (timeout) {
 682                 while ((timeout & 0x80000000) == 0) {
 683                         dto += 1;
 684                         timeout <<= 1;
 685                 }
 686                 dto = 31 - dto;
 687                 timeout <<= 1;
 688                 if (timeout && dto)
 689                         dto += 1;
 690                 if (dto >= 13)
 691                         dto -= 13;
 692                 else
 693                         dto = 0;
 694                 if (dto > 14)
 695                         dto = 14;
 696         }
 697
 698         reg &= ~DTO_MASK;
 699         reg |= dto << DTO_SHIFT;
 700         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 701 }
 702
 703 /*
 704  * Configure block length for MMC/SD cards and initiate the transfer.
 705  */
 706 static int
 707 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 708 {
 709         int ret;
 710         host->data = req->data;
 711
 712         if (req->data == NULL) {
 713                 host->datadir = OMAP_MMC_DATADIR_NONE;
 714                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 715                 return 0;
 716         }
 717
 718         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 719                                         | (req->data->blocks << 16));
 720         set_data_timeout(host, req);
 721
 722         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 723                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 724
 725         if (host->use_dma) {
 726                 ret = mmc_omap_start_dma_transfer(host, req);
 727                 if (ret != 0) {
 728                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 729                         return ret;
 730                 }
 731         }
 732         return 0;
 733 }
 734
 735 /*
 736  * Request function. for read/write operation
 737  */
 738 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 739 {
 740         struct mmc_omap_host *host = mmc_priv(mmc);
 741
 742         WARN_ON(host->mrq != NULL);
 743         host->mrq = req;
 744         mmc_omap_prepare_data(host, req);
 745         mmc_omap_start_command(host, req->cmd, req->data);
 746 }
 747
 748
 749 /* Routine to configure clock values. Exposed API to core */
 750 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 751 {
 752         struct mmc_omap_host *host = mmc_priv(mmc);
 753         u16 dsor = 0;
 754         unsigned long regval;
 755         unsigned long timeout;
 756
 757         switch (ios->power_mode) {
 758         case MMC_POWER_OFF:
 759                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 760                 break;
 761         case MMC_POWER_UP:
 762                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 763                 break;
 764         }
 765
 766         switch (mmc->ios.bus_width) {
 767         case MMC_BUS_WIDTH_4:
 768                 OMAP_HSMMC_WRITE(host->base, HCTL,
 769                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 770                 break;
 771         case MMC_BUS_WIDTH_1:
 772                 OMAP_HSMMC_WRITE(host->base, HCTL,
 773                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 774                 break;
 775         }
 776
 777         if (host->id == OMAP_MMC1_DEVID) {
 778                 /* Only MMC1 can operate at 3V/1.8V */
 779                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 780                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 781                                 /*
 782                                  * The mmc_select_voltage fn of the core does
 783                                  * not seem to set the power_mode to
 784                                  * MMC_POWER_UP upon recalculating the voltage.
 785                                  * vdd 1.8v.
 786                                  */
 787                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 788                                         dev_dbg(mmc_dev(host->mmc),
 789                                                 "Switch operation failed\n");
 790                 }
 791         }
 792
 793         if (ios->clock) {
 794                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 795                 if (dsor < 1)
 796                         dsor = 1;
 797
 798                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 799                         dsor++;
 800
 801                 if (dsor > 250)
 802                         dsor = 250;
 803         }
 804         omap_mmc_stop_clock(host);
 805         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 806         regval = regval & ~(CLKD_MASK);
 807         regval = regval | (dsor << 6) | (DTO << 16);
 808         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 809         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 810                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 811
 812         /* Wait till the ICS bit is set */
 813         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 814         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 815                 && time_before(jiffies, timeout))
 816                 msleep(1);
 817
 818         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 819                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 820
 821         if (ios->power_mode == MMC_POWER_ON)
 822                 send_init_stream(host);
 823
 824         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 825                 OMAP_HSMMC_WRITE(host->base, CON,
 826                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 827 }
 828 /* NOTE: Read only switch not supported yet */
 829 static struct mmc_host_ops mmc_omap_ops = {
 830         .request = omap_mmc_request,
 831         .set_ios = omap_mmc_set_ios,
 832 };
 833
 834 static int __init omap_mmc_probe(struct platform_device *pdev)
 835 {
 836         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 837         struct mmc_host *mmc;
 838         struct mmc_omap_host *host = NULL;
 839         struct resource *res;
 840         int ret = 0, irq;
 841         u32 hctl, capa;
 842
 843         if (pdata == NULL) {
 844                 dev_err(&pdev->dev, "Platform Data is missing\n");
 845                 return -ENXIO;
 846         }
 847
 848         if (pdata->nr_slots == 0) {
 849                 dev_err(&pdev->dev, "No Slots\n");
 850                 return -ENXIO;
 851         }
 852
 853         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 854         irq = platform_get_irq(pdev, 0);
 855         if (res == NULL || irq < 0)
 856                 return -ENXIO;
 857
 858         res = request_mem_region(res->start, res->end - res->start + 1,
 859                                                         pdev->name);
 860         if (res == NULL)
 861                 return -EBUSY;
 862
 863         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 864         if (!mmc) {
 865                 ret = -ENOMEM;
 866                 goto err;
 867         }
 868
 869         host            = mmc_priv(mmc);
 870         host->mmc       = mmc;
 871         host->pdata     = pdata;
 872         host->dev       = &pdev->dev;
 873         host->use_dma   = 1;
 874         host->dev->dma_mask = &pdata->dma_mask;
 875         host->dma_ch    = -1;
 876         host->irq       = irq;
 877         host->id        = pdev->id;
 878         host->slot_id   = 0;
 879         host->mapbase   = res->start;
 880         host->base      = ioremap(host->mapbase, SZ_4K);
 881         mmc->ops        = &mmc_omap_ops;
 882         mmc->f_min      = 400000;
 883         mmc->f_max      = 52000000;
 884
 885         sema_init(&host->sem, 1);
 886
 887         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 888         if (IS_ERR(host->iclk)) {
 889                 ret = PTR_ERR(host->iclk);
 890                 host->iclk = NULL;
 891                 goto err1;
 892         }
 893         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 894         if (IS_ERR(host->fclk)) {
 895                 ret = PTR_ERR(host->fclk);
 896                 host->fclk = NULL;
 897                 clk_put(host->iclk);
 898                 goto err1;
 899         }
 900
 901         if (clk_enable(host->fclk) != 0) {
 902                 clk_put(host->iclk);
 903                 clk_put(host->fclk);
 904                 goto err1;
 905         }
 906
 907         if (clk_enable(host->iclk) != 0) {
 908                 clk_disable(host->fclk);
 909                 clk_put(host->iclk);
 910                 clk_put(host->fclk);
 911                 goto err1;
 912         }
 913
 914         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 915         /*
 916          * MMC can still work without debounce clock.
 917          */
 918         if (IS_ERR(host->dbclk))
 919                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 920         else
 921                 if (clk_enable(host->dbclk) != 0)
 922                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 923                                                         " clk failed\n");
 924                 else
 925                         host->dbclk_enabled = 1;
 926
 927 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 928         mmc->max_phys_segs = 1;
 929         mmc->max_hw_segs = 1;
 930 #endif
 931         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 932         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 933         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 934         mmc->max_seg_size = mmc->max_req_size;
 935
 936         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 937         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
 938
 939         if (pdata->slots[host->slot_id].wire4)
 940                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 941
 942         /* Only MMC1 supports 3.0V */
 943         if (host->id == OMAP_MMC1_DEVID) {
 944                 hctl = SDVS30;
 945                 capa = VS30 | VS18;
 946         } else {
 947                 hctl = SDVS18;
 948                 capa = VS18;
 949         }
 950
 951         OMAP_HSMMC_WRITE(host->base, HCTL,
 952                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 953
 954         OMAP_HSMMC_WRITE(host->base, CAPA,
 955                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 956
 957         /* Set the controller to AUTO IDLE mode */
 958         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 959                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 960
 961         /* Set SD bus power bit */
 962         OMAP_HSMMC_WRITE(host->base, HCTL,
 963                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 964
 965         /* Request IRQ for MMC operations */
 966         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
 967                         mmc_hostname(mmc), host);
 968         if (ret) {
 969                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
 970                 goto err_irq;
 971         }
 972
 973         /* Request IRQ for card detect */
 974         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
 975                 ret = request_irq(mmc_slot(host).card_detect_irq,
 976                                   omap_mmc_cd_handler,
 977                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
 978                                           | IRQF_DISABLED,
 979                                   mmc_hostname(mmc), host);
 980                 if (ret) {
 981                         dev_dbg(mmc_dev(host->mmc),
 982                                 "Unable to grab MMC CD IRQ\n");
 983                         goto err_irq_cd;
 984                 }
 985         }
 986
 987         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 988         if (pdata->init != NULL) {
 989                 if (pdata->init(&pdev->dev) != 0) {
 990                         dev_dbg(mmc_dev(host->mmc),
 991                                 "Unable to configure MMC IRQs\n");
 992                         goto err_irq_cd_init;
 993                 }
 994         }
 995
 996         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 997         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 998
 999         platform_set_drvdata(pdev, host);
1000         mmc_add_host(mmc);
1001
1002         if (host->pdata->slots[host->slot_id].name != NULL) {
1003                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1004                 if (ret < 0)
1005                         goto err_slot_name;
1006         }
1007         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1008                         host->pdata->slots[host->slot_id].get_cover_state) {
1009                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1010                 if (ret < 0)
1011                         goto err_cover_switch;
1012         }
1013
1014         return 0;
1015
1016 err_cover_switch:
1017         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1018 err_slot_name:
1019         mmc_remove_host(mmc);
1020 err_irq_cd_init:
1021         free_irq(mmc_slot(host).card_detect_irq, host);
1022 err_irq_cd:
1023         free_irq(host->irq, host);
1024 err_irq:
1025         clk_disable(host->fclk);
1026         clk_disable(host->iclk);
1027         clk_put(host->fclk);
1028         clk_put(host->iclk);
1029         if (host->dbclk_enabled) {
1030                 clk_disable(host->dbclk);
1031                 clk_put(host->dbclk);
1032         }
1033
1034 err1:
1035         iounmap(host->base);
1036 err:
1037         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1038         release_mem_region(res->start, res->end - res->start + 1);
1039         if (host)
1040                 mmc_free_host(mmc);
1041         return ret;
1042 }
1043
1044 static int omap_mmc_remove(struct platform_device *pdev)
1045 {
1046         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1047         struct resource *res;
1048         u16 vdd = 0;
1049
1050         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1051         /*
1052          * Set the vdd back to 3V,
1053          * applicable for dual volt support.
1054          */
1055                 vdd = fls(host->mmc->ocr_avail) - 1;
1056                 if (omap_mmc_switch_opcond(host, vdd) != 0)
1057                         host->mmc->ios.vdd = vdd;
1058         }
1059
1060         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1061         if (res)
1062                 release_mem_region(res->start, res->end - res->start + 1);
1063
1064         platform_set_drvdata(pdev, NULL);
1065         if (host) {
1066                 mmc_remove_host(host->mmc);
1067                 if (host->pdata->cleanup)
1068                         host->pdata->cleanup(&pdev->dev);
1069                 free_irq(host->irq, host);
1070                 if (mmc_slot(host).card_detect_irq)
1071                         free_irq(mmc_slot(host).card_detect_irq, host);
1072                 flush_scheduled_work();
1073
1074                 clk_disable(host->fclk);
1075                 clk_disable(host->iclk);
1076                 clk_put(host->fclk);
1077                 clk_put(host->iclk);
1078                 if (host->dbclk_enabled) {
1079                         clk_disable(host->dbclk);
1080                         clk_put(host->dbclk);
1081                 }
1082
1083                 mmc_free_host(host->mmc);
1084                 iounmap(host->base);
1085         }
1086
1087         return 0;
1088 }
1089
1090 #ifdef CONFIG_PM
1091 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1092 {
1093         int ret = 0;
1094         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1095
1096         if (host && host->suspended)
1097                 return 0;
1098
1099         if (host) {
1100                 ret = mmc_suspend_host(host->mmc, state);
1101                 if (ret == 0) {
1102                         host->suspended = 1;
1103
1104                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1105                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1106
1107                         if (host->pdata->suspend) {
1108                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1109                                 if (ret)
1110                                         dev_dbg(mmc_dev(host->mmc),
1111                                                 "Unable to handle MMC board"
1112                                                 " level suspend\n");
1113                         }
1114
1115                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1116                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1117                                         OMAP_HSMMC_READ(host->base, HCTL)
1118                                         & SDVSCLR);
1119                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1120                                         OMAP_HSMMC_READ(host->base, HCTL)
1121                                         | SDVS30);
1122                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1123                                         OMAP_HSMMC_READ(host->base, HCTL)
1124                                         | SDBP);
1125                         }
1126
1127                         clk_disable(host->fclk);
1128                         clk_disable(host->iclk);
1129                         clk_disable(host->dbclk);
1130                 }
1131
1132         }
1133         return ret;
1134 }
1135
1136 /* Routine to resume the MMC device */
1137 static int omap_mmc_resume(struct platform_device *pdev)
1138 {
1139         int ret = 0;
1140         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1141
1142         if (host && !host->suspended)
1143                 return 0;
1144
1145         if (host) {
1146
1147                 ret = clk_enable(host->fclk);
1148                 if (ret)
1149                         goto clk_en_err;
1150
1151                 ret = clk_enable(host->iclk);
1152                 if (ret) {
1153                         clk_disable(host->fclk);
1154                         clk_put(host->fclk);
1155                         goto clk_en_err;
1156                 }
1157
1158                 if (clk_enable(host->dbclk) != 0)
1159                         dev_dbg(mmc_dev(host->mmc),
1160                                         "Enabling debounce clk failed\n");
1161
1162                 if (host->pdata->resume) {
1163                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1164                         if (ret)
1165                                 dev_dbg(mmc_dev(host->mmc),
1166                                         "Unmask interrupt failed\n");
1167                 }
1168
1169                 /* Notify the core to resume the host */
1170                 ret = mmc_resume_host(host->mmc);
1171                 if (ret == 0)
1172                         host->suspended = 0;
1173         }
1174
1175         return ret;
1176
1177 clk_en_err:
1178         dev_dbg(mmc_dev(host->mmc),
1179                 "Failed to enable MMC clocks during resume\n");
1180         return ret;
1181 }
1182
1183 #else
1184 #define omap_mmc_suspend        NULL
1185 #define omap_mmc_resume         NULL
1186 #endif
1187
1188 static struct platform_driver omap_mmc_driver = {
1189         .probe          = omap_mmc_probe,
1190         .remove         = omap_mmc_remove,
1191         .suspend        = omap_mmc_suspend,
1192         .resume         = omap_mmc_resume,
1193         .driver         = {
1194                 .name = DRIVER_NAME,
1195                 .owner = THIS_MODULE,
1196         },
1197 };
1198
1199 static int __init omap_mmc_init(void)
1200 {
1201         /* Register the MMC driver */
1202         return platform_driver_register(&omap_mmc_driver);
1203 }
1204
1205 static void __exit omap_mmc_cleanup(void)
1206 {
1207         /* Unregister MMC driver */
1208         platform_driver_unregister(&omap_mmc_driver);
1209 }
1210
1211 module_init(omap_mmc_init);
1212 module_exit(omap_mmc_cleanup);
1213
1214 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1215 MODULE_LICENSE("GPL");
1216 MODULE_ALIAS("platform:" DRIVER_NAME);
1217 MODULE_AUTHOR("Texas Instruments Inc");