drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1<<26)
  55 #define VS30                    (1<<25)
  56 #define SDVS18                  (0x5<<9)
  57 #define SDVS30                  (0x6<<9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1<<8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1<<2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define INT_EN_MASK             0x307F0033
  68 #define INIT_STREAM             (1<<1)
  69 #define DP_SELECT               (1<<21)
  70 #define DDIR                    (1<<4)
  71 #define DMA_EN                  0x1
  72 #define MSBS                    1<<5
  73 #define BCE                     1<<1
  74 #define FOUR_BIT                1 << 1
  75 #define CC                      0x1
  76 #define TC                      0x02
  77 #define OD                      0x1
  78 #define ERR                     (1 << 15)
  79 #define CMD_TIMEOUT             (1 << 16)
  80 #define DATA_TIMEOUT            (1 << 20)
  81 #define CMD_CRC                 (1 << 17)
  82 #define DATA_CRC                (1 << 21)
  83 #define CARD_ERR                (1 << 28)
  84 #define STAT_CLEAR              0xFFFFFFFF
  85 #define INIT_STREAM_CMD         0x00000000
  86 #define DUAL_VOLT_OCR_BIT       7
  87 #define SRC                     (1 << 25)
  88 #define SRD                     (1 << 26)
  89
  90 /*
  91  * FIXME: Most likely all the data using these _DEVID defines should come
  92  * from the platform_data, or implemented in controller and slot specific
  93  * functions.
  94  */
  95 #define OMAP_MMC1_DEVID         0
  96 #define OMAP_MMC2_DEVID         1
  97
  98 #define OMAP_MMC_DATADIR_NONE   0
  99 #define OMAP_MMC_DATADIR_READ   1
 100 #define OMAP_MMC_DATADIR_WRITE  2
 101 #define MMC_TIMEOUT_MS          20
 102 #define OMAP_MMC_MASTER_CLOCK   96000000
 103 #define DRIVER_NAME             "mmci-omap"
 104
 105 /*
 106  * One controller can have multiple slots, like on some omap boards using
 107  * omap.c controller driver. Luckily this is not currently done on any known
 108  * omap_hsmmc.c device.
 109  */
 110 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 111
 112 /*
 113  * MMC Host controller read/write API's
 114  */
 115 #define OMAP_HSMMC_READ(base, reg)      \
 116         __raw_readl((base) + OMAP_HSMMC_##reg)
 117
 118 #define OMAP_HSMMC_WRITE(base, reg, val) \
 119         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 120
 121 struct mmc_omap_host {
 122         struct  device          *dev;
 123         struct  mmc_host        *mmc;
 124         struct  mmc_request     *mrq;
 125         struct  mmc_command     *cmd;
 126         struct  mmc_data        *data;
 127         struct  clk             *fclk;
 128         struct  clk             *iclk;
 129         struct  clk             *dbclk;
 130         struct  semaphore       sem;
 131         struct  work_struct     mmc_carddetect_work;
 132         void    __iomem         *base;
 133         resource_size_t         mapbase;
 134         unsigned int            id;
 135         unsigned int            dma_len;
 136         unsigned int            dma_dir;
 137         unsigned char           bus_mode;
 138         unsigned char           datadir;
 139         u32                     *buffer;
 140         u32                     bytesleft;
 141         int                     suspended;
 142         int                     irq;
 143         int                     carddetect;
 144         int                     use_dma, dma_ch;
 145         int                     initstr;
 146         int                     slot_id;
 147         int                     dbclk_enabled;
 148         struct  omap_mmc_platform_data  *pdata;
 149 };
 150
 151 /*
 152  * Stop clock to the card
 153  */
 154 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 155 {
 156         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 157                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 158         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 159                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 160 }
 161
 162 /*
 163  * Send init stream sequence to card
 164  * before sending IDLE command
 165  */
 166 static void send_init_stream(struct mmc_omap_host *host)
 167 {
 168         int reg = 0;
 169         unsigned long timeout;
 170
 171         disable_irq(host->irq);
 172         OMAP_HSMMC_WRITE(host->base, CON,
 173                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 174         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 175
 176         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 177         while ((reg != CC) && time_before(jiffies, timeout))
 178                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 179
 180         OMAP_HSMMC_WRITE(host->base, CON,
 181                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 182         enable_irq(host->irq);
 183 }
 184
 185 static inline
 186 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 187 {
 188         if (host->pdata->slots[host->slot_id].get_cover_state)
 189                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 190         return 1;
 191 }
 192
 193 static ssize_t
 194 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 195                            char *buf)
 196 {
 197         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 198         struct mmc_omap_host *host = mmc_priv(mmc);
 199
 200         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 201                        "open");
 202 }
 203
 204 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 205
 206 static ssize_t
 207 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 208                         char *buf)
 209 {
 210         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 211         struct mmc_omap_host *host = mmc_priv(mmc);
 212         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 213
 214         return sprintf(buf, "slot:%s\n", slot.name);
 215 }
 216
 217 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 218
 219 /*
 220  * Configure the response type and send the cmd.
 221  */
 222 static void
 223 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 224         struct mmc_data *data)
 225 {
 226         int cmdreg = 0, resptype = 0, cmdtype = 0;
 227
 228         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 229                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 230         host->cmd = cmd;
 231
 232         /*
 233          * Clear status bits and enable interrupts
 234          */
 235         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 236         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 237         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 238
 239         if (cmd->flags & MMC_RSP_PRESENT) {
 240                 if (cmd->flags & MMC_RSP_136)
 241                         resptype = 1;
 242                 else
 243                         resptype = 2;
 244         }
 245
 246         /*
 247          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 248          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 249          */
 250         if (cmd->opcode == 12)
 251                 cmdtype = 0x3;
 252
 253         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 254
 255         if (data) {
 256                 cmdreg |= DP_SELECT | MSBS | BCE;
 257                 if (data->flags & MMC_DATA_READ)
 258                         cmdreg |= DDIR;
 259                 else
 260                         cmdreg &= ~(DDIR);
 261         }
 262
 263         if (host->use_dma)
 264                 cmdreg |= DMA_EN;
 265
 266         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 267         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 268 }
 269
 270 /*
 271  * Notify the transfer complete to MMC core
 272  */
 273 static void
 274 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 275 {
 276         host->data = NULL;
 277
 278         if (host->use_dma && host->dma_ch != -1)
 279                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 280                         host->dma_dir);
 281
 282         host->datadir = OMAP_MMC_DATADIR_NONE;
 283
 284         if (!data->error)
 285                 data->bytes_xfered += data->blocks * (data->blksz);
 286         else
 287                 data->bytes_xfered = 0;
 288
 289         if (!data->stop) {
 290                 host->mrq = NULL;
 291                 mmc_request_done(host->mmc, data->mrq);
 292                 return;
 293         }
 294         mmc_omap_start_command(host, data->stop, NULL);
 295 }
 296
 297 /*
 298  * Notify the core about command completion
 299  */
 300 static void
 301 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 302 {
 303         host->cmd = NULL;
 304
 305         if (cmd->flags & MMC_RSP_PRESENT) {
 306                 if (cmd->flags & MMC_RSP_136) {
 307                         /* response type 2 */
 308                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 309                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 310                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 311                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 312                 } else {
 313                         /* response types 1, 1b, 3, 4, 5, 6 */
 314                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 315                 }
 316         }
 317         if (host->data == NULL || cmd->error) {
 318                 host->mrq = NULL;
 319                 mmc_request_done(host->mmc, cmd->mrq);
 320         }
 321 }
 322
 323 /*
 324  * DMA clean up for command errors
 325  */
 326 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 327 {
 328         host->data->error = -ETIMEDOUT;
 329
 330         if (host->use_dma && host->dma_ch != -1) {
 331                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 332                         host->dma_dir);
 333                 omap_free_dma(host->dma_ch);
 334                 host->dma_ch = -1;
 335                 up(&host->sem);
 336         }
 337         host->data = NULL;
 338         host->datadir = OMAP_MMC_DATADIR_NONE;
 339 }
 340
 341 /*
 342  * Readable error output
 343  */
 344 #ifdef CONFIG_MMC_DEBUG
 345 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 346 {
 347         /* --- means reserved bit without definition at documentation */
 348         static const char *mmc_omap_status_bits[] = {
 349                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 350                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 351                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 352                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 353         };
 354         int i;
 355
 356         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 357
 358         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 359                 if (status & (1 << i))
 360                         /*
 361                          * KERN_* facility is not used here because this should
 362                          * print a single line.
 363                          */
 364                         printk(" %s", mmc_omap_status_bits[i]);
 365
 366         printk("\n");
 367
 368 }
 369 #endif  /* CONFIG_MMC_DEBUG */
 370
 371
 372 /*
 373  * MMC controller IRQ handler
 374  */
 375 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 376 {
 377         struct mmc_omap_host *host = dev_id;
 378         struct mmc_data *data;
 379         int end_cmd = 0, end_trans = 0, status;
 380
 381         if (host->cmd == NULL && host->data == NULL) {
 382                 OMAP_HSMMC_WRITE(host->base, STAT,
 383                         OMAP_HSMMC_READ(host->base, STAT));
 384                 return IRQ_HANDLED;
 385         }
 386
 387         data = host->data;
 388         status = OMAP_HSMMC_READ(host->base, STAT);
 389         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 390
 391         if (status & ERR) {
 392 #ifdef CONFIG_MMC_DEBUG
 393                 mmc_omap_report_irq(host, status);
 394 #endif
 395                 if ((status & CMD_TIMEOUT) ||
 396                         (status & CMD_CRC)) {
 397                         if (host->cmd) {
 398                                 if (status & CMD_TIMEOUT) {
 399                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 400                                                 OMAP_HSMMC_READ(host->base,
 401                                                                 SYSCTL) | SRC);
 402                                         while (OMAP_HSMMC_READ(host->base,
 403                                                                 SYSCTL) & SRC) ;
 404                                         host->cmd->error = -ETIMEDOUT;
 405                                 } else {
 406                                         host->cmd->error = -EILSEQ;
 407                                 }
 408                                 end_cmd = 1;
 409                         }
 410                         if (host->data)
 411                                 mmc_dma_cleanup(host);
 412                 }
 413                 if ((status & DATA_TIMEOUT) ||
 414                         (status & DATA_CRC)) {
 415                         if (host->data) {
 416                                 if (status & DATA_TIMEOUT)
 417                                         mmc_dma_cleanup(host);
 418                                 else
 419                                         host->data->error = -EILSEQ;
 420                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 421                                         OMAP_HSMMC_READ(host->base,
 422                                                         SYSCTL) | SRD);
 423                                 while (OMAP_HSMMC_READ(host->base,
 424                                                         SYSCTL) & SRD) ;
 425                                 end_trans = 1;
 426                         }
 427                 }
 428                 if (status & CARD_ERR) {
 429                         dev_dbg(mmc_dev(host->mmc),
 430                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 431                         if (host->cmd)
 432                                 end_cmd = 1;
 433                         if (host->data)
 434                                 end_trans = 1;
 435                 }
 436         }
 437
 438         OMAP_HSMMC_WRITE(host->base, STAT, status);
 439
 440         if (end_cmd || (status & CC))
 441                 mmc_omap_cmd_done(host, host->cmd);
 442         if (end_trans || (status & TC))
 443                 mmc_omap_xfer_done(host, data);
 444
 445         return IRQ_HANDLED;
 446 }
 447
 448 /*
 449  * Switch MMC operating voltage
 450  */
 451 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 452 {
 453         u32 reg_val = 0;
 454         int ret;
 455
 456         /* Disable the clocks */
 457         clk_disable(host->fclk);
 458         clk_disable(host->iclk);
 459         clk_disable(host->dbclk);
 460
 461         /* Turn the power off */
 462         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 463         if (ret != 0)
 464                 goto err;
 465
 466         /* Turn the power ON with given VDD 1.8 or 3.0v */
 467         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 468         if (ret != 0)
 469                 goto err;
 470
 471         clk_enable(host->fclk);
 472         clk_enable(host->iclk);
 473         clk_enable(host->dbclk);
 474
 475         OMAP_HSMMC_WRITE(host->base, HCTL,
 476                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 477         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 478         /*
 479          * If a MMC dual voltage card is detected, the set_ios fn calls
 480          * this fn with VDD bit set for 1.8V. Upon card removal from the
 481          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 482          *
 483          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 484          * set in HCTL.
 485          */
 486         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 487                                 ((1 << vdd) == MMC_VDD_33_34)))
 488                 reg_val |= SDVS30;
 489         if ((1 << vdd) == MMC_VDD_165_195)
 490                 reg_val |= SDVS18;
 491
 492         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 493
 494         OMAP_HSMMC_WRITE(host->base, HCTL,
 495                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 496
 497         return 0;
 498 err:
 499         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 500         return ret;
 501 }
 502
 503 /*
 504  * Work Item to notify the core about card insertion/removal
 505  */
 506 static void mmc_omap_detect(struct work_struct *work)
 507 {
 508         u16 vdd = 0;
 509         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 510                                                 mmc_carddetect_work);
 511
 512         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 513         if (host->carddetect) {
 514                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 515                         /*
 516                          * Set the VDD back to 3V when the card is removed
 517                          * before the set_ios fn turns off the power.
 518                          */
 519                         vdd = fls(host->mmc->ocr_avail) - 1;
 520                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 521                                 host->mmc->ios.vdd = vdd;
 522                 }
 523                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 524         } else {
 525                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 526                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 527                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 528                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 529         }
 530 }
 531
 532 /*
 533  * ISR for handling card insertion and removal
 534  */
 535 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 536 {
 537         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 538
 539         host->carddetect = mmc_slot(host).card_detect(irq);
 540         schedule_work(&host->mmc_carddetect_work);
 541
 542         return IRQ_HANDLED;
 543 }
 544
 545 /*
 546  * DMA call back function
 547  */
 548 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 549 {
 550         struct mmc_omap_host *host = data;
 551
 552         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 553                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 554
 555         if (host->dma_ch < 0)
 556                 return;
 557
 558         omap_free_dma(host->dma_ch);
 559         host->dma_ch = -1;
 560         /*
 561          * DMA Callback: run in interrupt context.
 562          * mutex_unlock will through a kernel warning if used.
 563          */
 564         up(&host->sem);
 565 }
 566
 567 /*
 568  * Configure dma src and destination parameters
 569  */
 570 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 571                                 struct mmc_data *data)
 572 {
 573         if (sync_dir == 0) {
 574                 omap_set_dma_dest_params(host->dma_ch, 0,
 575                         OMAP_DMA_AMODE_CONSTANT,
 576                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 577                 omap_set_dma_src_params(host->dma_ch, 0,
 578                         OMAP_DMA_AMODE_POST_INC,
 579                         sg_dma_address(&data->sg[0]), 0, 0);
 580         } else {
 581                 omap_set_dma_src_params(host->dma_ch, 0,
 582                         OMAP_DMA_AMODE_CONSTANT,
 583                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 584                 omap_set_dma_dest_params(host->dma_ch, 0,
 585                         OMAP_DMA_AMODE_POST_INC,
 586                         sg_dma_address(&data->sg[0]), 0, 0);
 587         }
 588         return 0;
 589 }
 590 /*
 591  * Routine to configure and start DMA for the MMC card
 592  */
 593 static int
 594 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 595 {
 596         int sync_dev, sync_dir = 0;
 597         int dma_ch = 0, ret = 0, err = 1;
 598         struct mmc_data *data = req->data;
 599
 600         /*
 601          * If for some reason the DMA transfer is still active,
 602          * we wait for timeout period and free the dma
 603          */
 604         if (host->dma_ch != -1) {
 605                 set_current_state(TASK_UNINTERRUPTIBLE);
 606                 schedule_timeout(100);
 607                 if (down_trylock(&host->sem)) {
 608                         omap_free_dma(host->dma_ch);
 609                         host->dma_ch = -1;
 610                         up(&host->sem);
 611                         return err;
 612                 }
 613         } else {
 614                 if (down_trylock(&host->sem))
 615                         return err;
 616         }
 617
 618         if (!(data->flags & MMC_DATA_WRITE)) {
 619                 host->dma_dir = DMA_FROM_DEVICE;
 620                 if (host->id == OMAP_MMC1_DEVID)
 621                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 622                 else
 623                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 624         } else {
 625                 host->dma_dir = DMA_TO_DEVICE;
 626                 if (host->id == OMAP_MMC1_DEVID)
 627                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 628                 else
 629                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 630         }
 631
 632         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 633                         host, &dma_ch);
 634         if (ret != 0) {
 635                 dev_dbg(mmc_dev(host->mmc),
 636                         "%s: omap_request_dma() failed with %d\n",
 637                         mmc_hostname(host->mmc), ret);
 638                 return ret;
 639         }
 640
 641         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 642                         data->sg_len, host->dma_dir);
 643         host->dma_ch = dma_ch;
 644
 645         if (!(data->flags & MMC_DATA_WRITE))
 646                 mmc_omap_config_dma_param(1, host, data);
 647         else
 648                 mmc_omap_config_dma_param(0, host, data);
 649
 650         if ((data->blksz % 4) == 0)
 651                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 652                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 653                         sync_dev, sync_dir);
 654         else
 655                 /* REVISIT: The MMC buffer increments only when MSB is written.
 656                  * Return error for blksz which is non multiple of four.
 657                  */
 658                 return -EINVAL;
 659
 660         omap_start_dma(dma_ch);
 661         return 0;
 662 }
 663
 664 /*
 665  * Configure block length for MMC/SD cards and initiate the transfer.
 666  */
 667 static int
 668 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 669 {
 670         int ret;
 671         host->data = req->data;
 672
 673         if (req->data == NULL) {
 674                 host->datadir = OMAP_MMC_DATADIR_NONE;
 675                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 676                 return 0;
 677         }
 678
 679         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 680                                         | (req->data->blocks << 16));
 681
 682         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 683                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 684
 685         if (host->use_dma) {
 686                 ret = mmc_omap_start_dma_transfer(host, req);
 687                 if (ret != 0) {
 688                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 689                         return ret;
 690                 }
 691         }
 692         return 0;
 693 }
 694
 695 /*
 696  * Request function. for read/write operation
 697  */
 698 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 699 {
 700         struct mmc_omap_host *host = mmc_priv(mmc);
 701
 702         WARN_ON(host->mrq != NULL);
 703         host->mrq = req;
 704         mmc_omap_prepare_data(host, req);
 705         mmc_omap_start_command(host, req->cmd, req->data);
 706 }
 707
 708
 709 /* Routine to configure clock values. Exposed API to core */
 710 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 711 {
 712         struct mmc_omap_host *host = mmc_priv(mmc);
 713         u16 dsor = 0;
 714         unsigned long regval;
 715         unsigned long timeout;
 716
 717         switch (ios->power_mode) {
 718         case MMC_POWER_OFF:
 719                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 720                 break;
 721         case MMC_POWER_UP:
 722                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 723                 break;
 724         }
 725
 726         switch (mmc->ios.bus_width) {
 727         case MMC_BUS_WIDTH_4:
 728                 OMAP_HSMMC_WRITE(host->base, HCTL,
 729                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 730                 break;
 731         case MMC_BUS_WIDTH_1:
 732                 OMAP_HSMMC_WRITE(host->base, HCTL,
 733                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 734                 break;
 735         }
 736
 737         if (host->id == OMAP_MMC1_DEVID) {
 738                 /* Only MMC1 can operate at 3V/1.8V */
 739                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 740                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 741                                 /*
 742                                  * The mmc_select_voltage fn of the core does
 743                                  * not seem to set the power_mode to
 744                                  * MMC_POWER_UP upon recalculating the voltage.
 745                                  * vdd 1.8v.
 746                                  */
 747                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 748                                         dev_dbg(mmc_dev(host->mmc),
 749                                                 "Switch operation failed\n");
 750                 }
 751         }
 752
 753         if (ios->clock) {
 754                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 755                 if (dsor < 1)
 756                         dsor = 1;
 757
 758                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 759                         dsor++;
 760
 761                 if (dsor > 250)
 762                         dsor = 250;
 763         }
 764         omap_mmc_stop_clock(host);
 765         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 766         regval = regval & ~(CLKD_MASK);
 767         regval = regval | (dsor << 6) | (DTO << 16);
 768         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 769         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 770                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 771
 772         /* Wait till the ICS bit is set */
 773         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 774         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 775                 && time_before(jiffies, timeout))
 776                 msleep(1);
 777
 778         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 779                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 780
 781         if (ios->power_mode == MMC_POWER_ON)
 782                 send_init_stream(host);
 783
 784         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 785                 OMAP_HSMMC_WRITE(host->base, CON,
 786                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 787 }
 788 /* NOTE: Read only switch not supported yet */
 789 static struct mmc_host_ops mmc_omap_ops = {
 790         .request = omap_mmc_request,
 791         .set_ios = omap_mmc_set_ios,
 792 };
 793
 794 static int __init omap_mmc_probe(struct platform_device *pdev)
 795 {
 796         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 797         struct mmc_host *mmc;
 798         struct mmc_omap_host *host = NULL;
 799         struct resource *res;
 800         int ret = 0, irq;
 801         u32 hctl, capa;
 802
 803         if (pdata == NULL) {
 804                 dev_err(&pdev->dev, "Platform Data is missing\n");
 805                 return -ENXIO;
 806         }
 807
 808         if (pdata->nr_slots == 0) {
 809                 dev_err(&pdev->dev, "No Slots\n");
 810                 return -ENXIO;
 811         }
 812
 813         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 814         irq = platform_get_irq(pdev, 0);
 815         if (res == NULL || irq < 0)
 816                 return -ENXIO;
 817
 818         res = request_mem_region(res->start, res->end - res->start + 1,
 819                                                         pdev->name);
 820         if (res == NULL)
 821                 return -EBUSY;
 822
 823         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 824         if (!mmc) {
 825                 ret = -ENOMEM;
 826                 goto err;
 827         }
 828
 829         host            = mmc_priv(mmc);
 830         host->mmc       = mmc;
 831         host->pdata     = pdata;
 832         host->dev       = &pdev->dev;
 833         host->use_dma   = 1;
 834         host->dev->dma_mask = &pdata->dma_mask;
 835         host->dma_ch    = -1;
 836         host->irq       = irq;
 837         host->id        = pdev->id;
 838         host->slot_id   = 0;
 839         host->mapbase   = res->start;
 840         host->base      = ioremap(host->mapbase, SZ_4K);
 841         mmc->ops        = &mmc_omap_ops;
 842         mmc->f_min      = 400000;
 843         mmc->f_max      = 52000000;
 844
 845         sema_init(&host->sem, 1);
 846
 847         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 848         if (IS_ERR(host->iclk)) {
 849                 ret = PTR_ERR(host->iclk);
 850                 host->iclk = NULL;
 851                 goto err1;
 852         }
 853         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 854         if (IS_ERR(host->fclk)) {
 855                 ret = PTR_ERR(host->fclk);
 856                 host->fclk = NULL;
 857                 clk_put(host->iclk);
 858                 goto err1;
 859         }
 860
 861         if (clk_enable(host->fclk) != 0) {
 862                 clk_put(host->iclk);
 863                 clk_put(host->fclk);
 864                 goto err1;
 865         }
 866
 867         if (clk_enable(host->iclk) != 0) {
 868                 clk_disable(host->fclk);
 869                 clk_put(host->iclk);
 870                 clk_put(host->fclk);
 871                 goto err1;
 872         }
 873
 874         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 875         /*
 876          * MMC can still work without debounce clock.
 877          */
 878         if (IS_ERR(host->dbclk))
 879                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 880         else
 881                 if (clk_enable(host->dbclk) != 0)
 882                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 883                                                         " clk failed\n");
 884                 else
 885                         host->dbclk_enabled = 1;
 886
 887 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 888         mmc->max_phys_segs = 1;
 889         mmc->max_hw_segs = 1;
 890 #endif
 891         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 892         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 893         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 894         mmc->max_seg_size = mmc->max_req_size;
 895
 896         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 897         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
 898
 899         if (pdata->slots[host->slot_id].wire4)
 900                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 901
 902         /* Only MMC1 supports 3.0V */
 903         if (host->id == OMAP_MMC1_DEVID) {
 904                 hctl = SDVS30;
 905                 capa = VS30 | VS18;
 906         } else {
 907                 hctl = SDVS18;
 908                 capa = VS18;
 909         }
 910
 911         OMAP_HSMMC_WRITE(host->base, HCTL,
 912                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 913
 914         OMAP_HSMMC_WRITE(host->base, CAPA,
 915                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 916
 917         /* Set the controller to AUTO IDLE mode */
 918         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 919                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 920
 921         /* Set SD bus power bit */
 922         OMAP_HSMMC_WRITE(host->base, HCTL,
 923                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 924
 925         /* Request IRQ for MMC operations */
 926         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
 927                         mmc_hostname(mmc), host);
 928         if (ret) {
 929                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
 930                 goto err_irq;
 931         }
 932
 933         /* Request IRQ for card detect */
 934         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
 935                 ret = request_irq(mmc_slot(host).card_detect_irq,
 936                                   omap_mmc_cd_handler,
 937                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
 938                                           | IRQF_DISABLED,
 939                                   mmc_hostname(mmc), host);
 940                 if (ret) {
 941                         dev_dbg(mmc_dev(host->mmc),
 942                                 "Unable to grab MMC CD IRQ\n");
 943                         goto err_irq_cd;
 944                 }
 945         }
 946
 947         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 948         if (pdata->init != NULL) {
 949                 if (pdata->init(&pdev->dev) != 0) {
 950                         dev_dbg(mmc_dev(host->mmc),
 951                                 "Unable to configure MMC IRQs\n");
 952                         goto err_irq_cd_init;
 953                 }
 954         }
 955
 956         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 957         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 958
 959         platform_set_drvdata(pdev, host);
 960         mmc_add_host(mmc);
 961
 962         if (host->pdata->slots[host->slot_id].name != NULL) {
 963                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
 964                 if (ret < 0)
 965                         goto err_slot_name;
 966         }
 967         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
 968                         host->pdata->slots[host->slot_id].get_cover_state) {
 969                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
 970                 if (ret < 0)
 971                         goto err_cover_switch;
 972         }
 973
 974         return 0;
 975
 976 err_cover_switch:
 977         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
 978 err_slot_name:
 979         mmc_remove_host(mmc);
 980 err_irq_cd_init:
 981         free_irq(mmc_slot(host).card_detect_irq, host);
 982 err_irq_cd:
 983         free_irq(host->irq, host);
 984 err_irq:
 985         clk_disable(host->fclk);
 986         clk_disable(host->iclk);
 987         clk_put(host->fclk);
 988         clk_put(host->iclk);
 989         if (host->dbclk_enabled) {
 990                 clk_disable(host->dbclk);
 991                 clk_put(host->dbclk);
 992         }
 993
 994 err1:
 995         iounmap(host->base);
 996 err:
 997         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
 998         release_mem_region(res->start, res->end - res->start + 1);
 999         if (host)
1000                 mmc_free_host(mmc);
1001         return ret;
1002 }
1003
1004 static int omap_mmc_remove(struct platform_device *pdev)
1005 {
1006         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1007         struct resource *res;
1008         u16 vdd = 0;
1009
1010         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1011         /*
1012          * Set the vdd back to 3V,
1013          * applicable for dual volt support.
1014          */
1015                 vdd = fls(host->mmc->ocr_avail) - 1;
1016                 if (omap_mmc_switch_opcond(host, vdd) != 0)
1017                         host->mmc->ios.vdd = vdd;
1018         }
1019
1020         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1021         if (res)
1022                 release_mem_region(res->start, res->end - res->start + 1);
1023
1024         platform_set_drvdata(pdev, NULL);
1025         if (host) {
1026                 mmc_remove_host(host->mmc);
1027                 if (host->pdata->cleanup)
1028                         host->pdata->cleanup(&pdev->dev);
1029                 free_irq(host->irq, host);
1030                 if (mmc_slot(host).card_detect_irq)
1031                         free_irq(mmc_slot(host).card_detect_irq, host);
1032                 flush_scheduled_work();
1033
1034                 clk_disable(host->fclk);
1035                 clk_disable(host->iclk);
1036                 clk_put(host->fclk);
1037                 clk_put(host->iclk);
1038                 if (host->dbclk_enabled) {
1039                         clk_disable(host->dbclk);
1040                         clk_put(host->dbclk);
1041                 }
1042
1043                 mmc_free_host(host->mmc);
1044                 iounmap(host->base);
1045         }
1046
1047         return 0;
1048 }
1049
1050 #ifdef CONFIG_PM
1051 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1052 {
1053         int ret = 0;
1054         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1055
1056         if (host && host->suspended)
1057                 return 0;
1058
1059         if (host) {
1060                 ret = mmc_suspend_host(host->mmc, state);
1061                 if (ret == 0) {
1062                         host->suspended = 1;
1063
1064                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1065                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1066
1067                         if (host->pdata->suspend) {
1068                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1069                                 if (ret)
1070                                         dev_dbg(mmc_dev(host->mmc),
1071                                                 "Unable to handle MMC board"
1072                                                 " level suspend\n");
1073                         }
1074
1075                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1076                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1077                                         OMAP_HSMMC_READ(host->base, HCTL)
1078                                         & SDVSCLR);
1079                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1080                                         OMAP_HSMMC_READ(host->base, HCTL)
1081                                         | SDVS30);
1082                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1083                                         OMAP_HSMMC_READ(host->base, HCTL)
1084                                         | SDBP);
1085                         }
1086
1087                         clk_disable(host->fclk);
1088                         clk_disable(host->iclk);
1089                         clk_disable(host->dbclk);
1090                 }
1091
1092         }
1093         return ret;
1094 }
1095
1096 /* Routine to resume the MMC device */
1097 static int omap_mmc_resume(struct platform_device *pdev)
1098 {
1099         int ret = 0;
1100         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1101
1102         if (host && !host->suspended)
1103                 return 0;
1104
1105         if (host) {
1106
1107                 ret = clk_enable(host->fclk);
1108                 if (ret)
1109                         goto clk_en_err;
1110
1111                 ret = clk_enable(host->iclk);
1112                 if (ret) {
1113                         clk_disable(host->fclk);
1114                         clk_put(host->fclk);
1115                         goto clk_en_err;
1116                 }
1117
1118                 if (clk_enable(host->dbclk) != 0)
1119                         dev_dbg(mmc_dev(host->mmc),
1120                                         "Enabling debounce clk failed\n");
1121
1122                 if (host->pdata->resume) {
1123                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1124                         if (ret)
1125                                 dev_dbg(mmc_dev(host->mmc),
1126                                         "Unmask interrupt failed\n");
1127                 }
1128
1129                 /* Notify the core to resume the host */
1130                 ret = mmc_resume_host(host->mmc);
1131                 if (ret == 0)
1132                         host->suspended = 0;
1133         }
1134
1135         return ret;
1136
1137 clk_en_err:
1138         dev_dbg(mmc_dev(host->mmc),
1139                 "Failed to enable MMC clocks during resume\n");
1140         return ret;
1141 }
1142
1143 #else
1144 #define omap_mmc_suspend        NULL
1145 #define omap_mmc_resume         NULL
1146 #endif
1147
1148 static struct platform_driver omap_mmc_driver = {
1149         .probe          = omap_mmc_probe,
1150         .remove         = omap_mmc_remove,
1151         .suspend        = omap_mmc_suspend,
1152         .resume         = omap_mmc_resume,
1153         .driver         = {
1154                 .name = DRIVER_NAME,
1155                 .owner = THIS_MODULE,
1156         },
1157 };
1158
1159 static int __init omap_mmc_init(void)
1160 {
1161         /* Register the MMC driver */
1162         return platform_driver_register(&omap_mmc_driver);
1163 }
1164
1165 static void __exit omap_mmc_cleanup(void)
1166 {
1167         /* Unregister MMC driver */
1168         platform_driver_unregister(&omap_mmc_driver);
1169 }
1170
1171 module_init(omap_mmc_init);
1172 module_exit(omap_mmc_cleanup);
1173
1174 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1175 MODULE_LICENSE("GPL");
1176 MODULE_ALIAS("platform:" DRIVER_NAME);
1177 MODULE_AUTHOR("Texas Instruments Inc");