2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
29 #include <linux/semaphore.h>
31 #include <mach/hardware.h>
32 #include <mach/board.h>
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
54 #define VS18 (1 << 26)
55 #define VS30 (1 << 25)
56 #define SDVS18 (0x5 << 9)
57 #define SDVS30 (0x6 << 9)
58 #define SDVSCLR 0xFFFFF1FF
59 #define SDVSDET 0x00000400
66 #define CLKD_MASK 0x0000FFC0
68 #define DTO_MASK 0x000F0000
70 #define INT_EN_MASK 0x307F0033
71 #define INIT_STREAM (1 << 1)
72 #define DP_SELECT (1 << 21)
77 #define FOUR_BIT (1 << 1)
82 #define CMD_TIMEOUT (1 << 16)
83 #define DATA_TIMEOUT (1 << 20)
84 #define CMD_CRC (1 << 17)
85 #define DATA_CRC (1 << 21)
86 #define CARD_ERR (1 << 28)
87 #define STAT_CLEAR 0xFFFFFFFF
88 #define INIT_STREAM_CMD 0x00000000
89 #define DUAL_VOLT_OCR_BIT 7
94 * FIXME: Most likely all the data using these _DEVID defines should come
95 * from the platform_data, or implemented in controller and slot specific
98 #define OMAP_MMC1_DEVID 0
99 #define OMAP_MMC2_DEVID 1
101 #define OMAP_MMC_DATADIR_NONE 0
102 #define OMAP_MMC_DATADIR_READ 1
103 #define OMAP_MMC_DATADIR_WRITE 2
104 #define MMC_TIMEOUT_MS 20
105 #define OMAP_MMC_MASTER_CLOCK 96000000
106 #define DRIVER_NAME "mmci-omap"
109 * One controller can have multiple slots, like on some omap boards using
110 * omap.c controller driver. Luckily this is not currently done on any known
111 * omap_hsmmc.c device.
113 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
116 * MMC Host controller read/write API's
118 #define OMAP_HSMMC_READ(base, reg) \
119 __raw_readl((base) + OMAP_HSMMC_##reg)
121 #define OMAP_HSMMC_WRITE(base, reg, val) \
122 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
125 #define IDLE_TIMEOUT (jiffies_to_msecs(10))
127 struct mmc_omap_host {
129 struct mmc_host *mmc;
130 struct mmc_request *mrq;
131 struct mmc_command *cmd;
132 struct mmc_data *data;
136 struct semaphore sem;
137 struct work_struct mmc_carddetect_work;
139 resource_size_t mapbase;
141 unsigned int dma_len;
142 unsigned int dma_dir;
143 unsigned char bus_mode;
144 unsigned char datadir;
155 struct timer_list idle_timer;
156 spinlock_t clk_lock; /* for changing enabled state */
157 unsigned int fclk_enabled:1;
159 struct omap_mmc_platform_data *pdata;
162 static int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
167 spin_lock_irqsave(&host->clk_lock, flags);
168 del_timer(&host->idle_timer);
169 if (host->fclk_enabled != state) {
171 ret = clk_enable(host->fclk);
175 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
177 clk_disable(host->fclk);
178 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
180 host->fclk_enabled = state;
184 spin_unlock_irqrestore(&host->clk_lock, flags);
188 static void mmc_omap_idle_timer(unsigned long data)
190 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
192 mmc_omap_fclk_state(host, OFF);
196 * Stop clock to the card
198 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
200 OMAP_HSMMC_WRITE(host->base, SYSCTL,
201 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
202 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
203 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
207 * Send init stream sequence to card
208 * before sending IDLE command
210 static void send_init_stream(struct mmc_omap_host *host)
213 unsigned long timeout;
215 disable_irq(host->irq);
216 OMAP_HSMMC_WRITE(host->base, CON,
217 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
218 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
220 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
221 while ((reg != CC) && time_before(jiffies, timeout))
222 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
224 OMAP_HSMMC_WRITE(host->base, CON,
225 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
226 enable_irq(host->irq);
230 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
232 if (host->pdata->slots[host->slot_id].get_cover_state)
233 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
238 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
241 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
242 struct mmc_omap_host *host = mmc_priv(mmc);
244 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
248 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
251 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
254 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
255 struct mmc_omap_host *host = mmc_priv(mmc);
256 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
258 return sprintf(buf, "slot:%s\n", slot.name);
261 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
264 * Configure the response type and send the cmd.
267 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
268 struct mmc_data *data)
270 int cmdreg = 0, resptype = 0, cmdtype = 0;
272 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
273 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
277 * Clear status bits and enable interrupts
279 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
280 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
281 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
283 if (cmd->flags & MMC_RSP_PRESENT) {
284 if (cmd->flags & MMC_RSP_136)
291 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
292 * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
294 if (cmd->opcode == 12)
297 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
300 cmdreg |= DP_SELECT | MSBS | BCE;
301 if (data->flags & MMC_DATA_READ)
310 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
311 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
315 * Notify the transfer complete to MMC core
318 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
322 if (host->use_dma && host->dma_ch != -1)
323 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
326 host->datadir = OMAP_MMC_DATADIR_NONE;
329 data->bytes_xfered += data->blocks * (data->blksz);
331 data->bytes_xfered = 0;
335 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
336 mmc_request_done(host->mmc, data->mrq);
339 mmc_omap_start_command(host, data->stop, NULL);
343 * Notify the core about command completion
346 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
350 if (cmd->flags & MMC_RSP_PRESENT) {
351 if (cmd->flags & MMC_RSP_136) {
352 /* response type 2 */
353 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
354 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
355 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
356 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
358 /* response types 1, 1b, 3, 4, 5, 6 */
359 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
362 if (host->data == NULL || cmd->error) {
364 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
365 mmc_request_done(host->mmc, cmd->mrq);
370 * DMA clean up for command errors
372 static void mmc_dma_cleanup(struct mmc_omap_host *host)
374 host->data->error = -ETIMEDOUT;
376 if (host->use_dma && host->dma_ch != -1) {
377 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
379 omap_free_dma(host->dma_ch);
384 host->datadir = OMAP_MMC_DATADIR_NONE;
388 * Readable error output
390 #ifdef CONFIG_MMC_DEBUG
391 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
393 /* --- means reserved bit without definition at documentation */
394 static const char *mmc_omap_status_bits[] = {
395 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
396 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
397 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
398 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
402 dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
404 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
405 if (status & (1 << i))
407 * KERN_* facility is not used here because this should
408 * print a single line.
410 printk(" %s", mmc_omap_status_bits[i]);
415 #endif /* CONFIG_MMC_DEBUG */
419 * MMC controller IRQ handler
421 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
423 struct mmc_omap_host *host = dev_id;
424 struct mmc_data *data;
425 int end_cmd = 0, end_trans = 0, status;
427 if (host->cmd == NULL && host->data == NULL) {
428 OMAP_HSMMC_WRITE(host->base, STAT,
429 OMAP_HSMMC_READ(host->base, STAT));
434 status = OMAP_HSMMC_READ(host->base, STAT);
435 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
438 #ifdef CONFIG_MMC_DEBUG
439 mmc_omap_report_irq(host, status);
441 if ((status & CMD_TIMEOUT) ||
442 (status & CMD_CRC)) {
444 if (status & CMD_TIMEOUT) {
445 OMAP_HSMMC_WRITE(host->base, SYSCTL,
446 OMAP_HSMMC_READ(host->base,
448 while (OMAP_HSMMC_READ(host->base,
450 host->cmd->error = -ETIMEDOUT;
452 host->cmd->error = -EILSEQ;
457 mmc_dma_cleanup(host);
459 if ((status & DATA_TIMEOUT) ||
460 (status & DATA_CRC)) {
462 if (status & DATA_TIMEOUT)
463 mmc_dma_cleanup(host);
465 host->data->error = -EILSEQ;
466 OMAP_HSMMC_WRITE(host->base, SYSCTL,
467 OMAP_HSMMC_READ(host->base,
469 while (OMAP_HSMMC_READ(host->base,
474 if (status & CARD_ERR) {
475 dev_dbg(mmc_dev(host->mmc),
476 "Ignoring card err CMD%d\n", host->cmd->opcode);
484 OMAP_HSMMC_WRITE(host->base, STAT, status);
486 if (end_cmd || (status & CC))
487 mmc_omap_cmd_done(host, host->cmd);
488 if (end_trans || (status & TC))
489 mmc_omap_xfer_done(host, data);
495 * Switch MMC operating voltage
497 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
502 /* Disable the clocks */
503 mmc_omap_fclk_state(host, OFF);
504 clk_disable(host->iclk);
505 clk_disable(host->dbclk);
507 /* Turn the power off */
508 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
512 /* Turn the power ON with given VDD 1.8 or 3.0v */
513 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
517 mmc_omap_fclk_state(host, ON);
518 clk_enable(host->iclk);
519 clk_enable(host->dbclk);
521 OMAP_HSMMC_WRITE(host->base, HCTL,
522 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
523 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
525 * If a MMC dual voltage card is detected, the set_ios fn calls
526 * this fn with VDD bit set for 1.8V. Upon card removal from the
527 * slot, mmc_omap_detect fn sets the VDD back to 3V.
529 * Only MMC1 supports 3.0V. MMC2 will not function if SDVS30 is
532 if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
533 ((1 << vdd) == MMC_VDD_33_34)))
535 if ((1 << vdd) == MMC_VDD_165_195)
538 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
540 OMAP_HSMMC_WRITE(host->base, HCTL,
541 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
545 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
550 * Work Item to notify the core about card insertion/removal
552 static void mmc_omap_detect(struct work_struct *work)
555 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
556 mmc_carddetect_work);
558 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
559 mmc_omap_fclk_state(host, ON);
560 if (host->carddetect) {
561 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
563 * Set the VDD back to 3V when the card is removed
564 * before the set_ios fn turns off the power.
566 vdd = fls(host->mmc->ocr_avail) - 1;
567 if (omap_mmc_switch_opcond(host, vdd) != 0)
568 host->mmc->ios.vdd = vdd;
570 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
572 OMAP_HSMMC_WRITE(host->base, SYSCTL,
573 OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
574 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
575 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
577 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
581 * ISR for handling card insertion and removal
583 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
585 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
587 host->carddetect = mmc_slot(host).card_detect(irq);
588 schedule_work(&host->mmc_carddetect_work);
594 * DMA call back function
596 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
598 struct mmc_omap_host *host = data;
600 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
601 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
603 if (host->dma_ch < 0)
606 omap_free_dma(host->dma_ch);
609 * DMA Callback: run in interrupt context.
610 * mutex_unlock will through a kernel warning if used.
616 * Configure dma src and destination parameters
618 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
619 struct mmc_data *data)
622 omap_set_dma_dest_params(host->dma_ch, 0,
623 OMAP_DMA_AMODE_CONSTANT,
624 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
625 omap_set_dma_src_params(host->dma_ch, 0,
626 OMAP_DMA_AMODE_POST_INC,
627 sg_dma_address(&data->sg[0]), 0, 0);
629 omap_set_dma_src_params(host->dma_ch, 0,
630 OMAP_DMA_AMODE_CONSTANT,
631 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
632 omap_set_dma_dest_params(host->dma_ch, 0,
633 OMAP_DMA_AMODE_POST_INC,
634 sg_dma_address(&data->sg[0]), 0, 0);
639 * Routine to configure and start DMA for the MMC card
642 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
644 int sync_dev, sync_dir = 0;
645 int dma_ch = 0, ret = 0, err = 1;
646 struct mmc_data *data = req->data;
649 * If for some reason the DMA transfer is still active,
650 * we wait for timeout period and free the dma
652 if (host->dma_ch != -1) {
653 set_current_state(TASK_UNINTERRUPTIBLE);
654 schedule_timeout(100);
655 if (down_trylock(&host->sem)) {
656 omap_free_dma(host->dma_ch);
662 if (down_trylock(&host->sem))
666 if (!(data->flags & MMC_DATA_WRITE)) {
667 host->dma_dir = DMA_FROM_DEVICE;
668 if (host->id == OMAP_MMC1_DEVID)
669 sync_dev = OMAP24XX_DMA_MMC1_RX;
671 sync_dev = OMAP24XX_DMA_MMC2_RX;
673 host->dma_dir = DMA_TO_DEVICE;
674 if (host->id == OMAP_MMC1_DEVID)
675 sync_dev = OMAP24XX_DMA_MMC1_TX;
677 sync_dev = OMAP24XX_DMA_MMC2_TX;
680 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
683 dev_dbg(mmc_dev(host->mmc),
684 "%s: omap_request_dma() failed with %d\n",
685 mmc_hostname(host->mmc), ret);
689 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
690 data->sg_len, host->dma_dir);
691 host->dma_ch = dma_ch;
693 if (!(data->flags & MMC_DATA_WRITE))
694 mmc_omap_config_dma_param(1, host, data);
696 mmc_omap_config_dma_param(0, host, data);
698 if ((data->blksz % 4) == 0)
699 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
700 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
703 /* REVISIT: The MMC buffer increments only when MSB is written.
704 * Return error for blksz which is non multiple of four.
708 omap_start_dma(dma_ch);
712 static void set_data_timeout(struct mmc_omap_host *host,
713 struct mmc_request *req)
715 unsigned int timeout, cycle_ns;
716 uint32_t reg, clkd, dto = 0;
718 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
719 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
723 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
724 timeout = req->data->timeout_ns / cycle_ns;
725 timeout += req->data->timeout_clks;
727 while ((timeout & 0x80000000) == 0) {
744 reg |= dto << DTO_SHIFT;
745 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
749 * Configure block length for MMC/SD cards and initiate the transfer.
752 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
755 host->data = req->data;
757 if (req->data == NULL) {
758 host->datadir = OMAP_MMC_DATADIR_NONE;
759 OMAP_HSMMC_WRITE(host->base, BLK, 0);
763 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
764 | (req->data->blocks << 16));
765 set_data_timeout(host, req);
767 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
768 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
771 ret = mmc_omap_start_dma_transfer(host, req);
773 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
781 * Request function. for read/write operation
783 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
785 struct mmc_omap_host *host = mmc_priv(mmc);
787 WARN_ON(host->mrq != NULL);
789 mmc_omap_fclk_state(host, ON);
790 mmc_omap_prepare_data(host, req);
791 mmc_omap_start_command(host, req->cmd, req->data);
794 /* Routine to configure clock values. Exposed API to core */
795 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
797 struct mmc_omap_host *host = mmc_priv(mmc);
799 unsigned long regval;
800 unsigned long timeout;
802 mmc_omap_fclk_state(host, ON);
804 switch (ios->power_mode) {
806 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
809 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
813 switch (mmc->ios.bus_width) {
814 case MMC_BUS_WIDTH_4:
815 OMAP_HSMMC_WRITE(host->base, HCTL,
816 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
818 case MMC_BUS_WIDTH_1:
819 OMAP_HSMMC_WRITE(host->base, HCTL,
820 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
824 if (host->id == OMAP_MMC1_DEVID) {
825 /* Only MMC1 can operate at 3V/1.8V */
826 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
827 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
829 * The mmc_select_voltage fn of the core does
830 * not seem to set the power_mode to
831 * MMC_POWER_UP upon recalculating the voltage.
834 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
835 dev_dbg(mmc_dev(host->mmc),
836 "Switch operation failed\n");
841 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
845 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
851 omap_mmc_stop_clock(host);
852 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
853 regval = regval & ~(CLKD_MASK);
854 regval = regval | (dsor << 6) | (DTO << 16);
855 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
856 OMAP_HSMMC_WRITE(host->base, SYSCTL,
857 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
859 /* Wait till the ICS bit is set */
860 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
861 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
862 && time_before(jiffies, timeout))
865 OMAP_HSMMC_WRITE(host->base, SYSCTL,
866 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
868 if (ios->power_mode == MMC_POWER_ON)
869 send_init_stream(host);
871 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
872 OMAP_HSMMC_WRITE(host->base, CON,
873 OMAP_HSMMC_READ(host->base, CON) | OD);
875 if (ios->power_mode == MMC_POWER_OFF)
876 mmc_omap_fclk_state(host, OFF);
878 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
881 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
883 struct mmc_omap_host *host = mmc_priv(mmc);
884 struct omap_mmc_platform_data *pdata = host->pdata;
886 if (!pdata->slots[0].card_detect)
888 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
891 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
893 struct mmc_omap_host *host = mmc_priv(mmc);
894 struct omap_mmc_platform_data *pdata = host->pdata;
896 if (!pdata->slots[0].get_ro)
898 return pdata->slots[0].get_ro(host->dev, 0);
901 static struct mmc_host_ops mmc_omap_ops = {
902 .request = omap_mmc_request,
903 .set_ios = omap_mmc_set_ios,
904 .get_cd = omap_hsmmc_get_cd,
905 .get_ro = omap_hsmmc_get_ro,
906 /* NYET -- enable_sdio_irq */
909 static int __init omap_mmc_probe(struct platform_device *pdev)
911 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
912 struct mmc_host *mmc;
913 struct mmc_omap_host *host = NULL;
914 struct resource *res;
915 int ret = 0, irq, reg;
919 dev_err(&pdev->dev, "Platform Data is missing\n");
923 if (pdata->nr_slots == 0) {
924 dev_err(&pdev->dev, "No Slots\n");
928 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
929 irq = platform_get_irq(pdev, 0);
930 if (res == NULL || irq < 0)
933 res = request_mem_region(res->start, res->end - res->start + 1,
938 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
944 host = mmc_priv(mmc);
947 host->dev = &pdev->dev;
949 host->dev->dma_mask = &pdata->dma_mask;
954 host->mapbase = res->start;
955 host->base = ioremap(host->mapbase, SZ_4K);
957 platform_set_drvdata(pdev, host);
958 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
960 mmc->ops = &mmc_omap_ops;
962 mmc->f_max = 52000000;
964 sema_init(&host->sem, 1);
966 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
967 if (IS_ERR(host->iclk)) {
968 ret = PTR_ERR(host->iclk);
972 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
973 if (IS_ERR(host->fclk)) {
974 ret = PTR_ERR(host->fclk);
980 spin_lock_init(&host->clk_lock);
981 setup_timer(&host->idle_timer, mmc_omap_idle_timer,
982 (unsigned long) host);
984 if (mmc_omap_fclk_state(host, ON) != 0) {
989 if (clk_enable(host->iclk) != 0) {
990 mmc_omap_fclk_state(host, OFF);
996 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
998 * MMC can still work without debounce clock.
1000 if (IS_ERR(host->dbclk))
1001 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1003 if (clk_enable(host->dbclk) != 0)
1004 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1007 host->dbclk_enabled = 1;
1009 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1010 mmc->max_phys_segs = 1;
1011 mmc->max_hw_segs = 1;
1013 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1014 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1015 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1016 mmc->max_seg_size = mmc->max_req_size;
1018 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1019 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1021 if (pdata->slots[host->slot_id].wires >= 4)
1022 mmc->caps |= MMC_CAP_4_BIT_DATA;
1024 /* Only MMC1 supports 3.0V */
1025 if (host->id == OMAP_MMC1_DEVID) {
1033 OMAP_HSMMC_WRITE(host->base, HCTL,
1034 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1036 OMAP_HSMMC_WRITE(host->base, CAPA,
1037 OMAP_HSMMC_READ(host->base, CAPA) | capa);
1039 /* Set the controller to AUTO IDLE mode */
1040 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1041 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1043 /* Set SD bus power bit */
1044 OMAP_HSMMC_WRITE(host->base, HCTL,
1045 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1047 /* Request IRQ for MMC operations */
1048 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1049 mmc_hostname(mmc), host);
1051 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1055 if (pdata->init != NULL) {
1056 if (pdata->init(&pdev->dev) != 0) {
1057 dev_dbg(mmc_dev(host->mmc),
1058 "Unable to configure MMC IRQs\n");
1059 goto err_irq_cd_init;
1063 /* Request IRQ for card detect */
1064 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1065 ret = request_irq(mmc_slot(host).card_detect_irq,
1066 omap_mmc_cd_handler,
1067 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1069 mmc_hostname(mmc), host);
1071 dev_dbg(mmc_dev(host->mmc),
1072 "Unable to grab MMC CD IRQ\n");
1077 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1078 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1082 if (host->pdata->slots[host->slot_id].name != NULL) {
1083 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1087 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1088 host->pdata->slots[host->slot_id].get_cover_state) {
1089 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1091 goto err_cover_switch;
1093 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
1098 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1100 mmc_remove_host(mmc);
1102 free_irq(mmc_slot(host).card_detect_irq, host);
1104 free_irq(host->irq, host);
1106 mmc_omap_fclk_state(host, OFF);
1107 clk_disable(host->iclk);
1108 clk_put(host->fclk);
1109 clk_put(host->iclk);
1110 if (host->dbclk_enabled) {
1111 clk_disable(host->dbclk);
1112 clk_put(host->dbclk);
1116 iounmap(host->base);
1118 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1119 release_mem_region(res->start, res->end - res->start + 1);
1125 static int omap_mmc_remove(struct platform_device *pdev)
1127 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1128 struct resource *res;
1131 mmc_omap_fclk_state(host, ON);
1132 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1134 * Set the vdd back to 3V,
1135 * applicable for dual volt support.
1137 vdd = fls(host->mmc->ocr_avail) - 1;
1138 if (omap_mmc_switch_opcond(host, vdd) != 0)
1139 host->mmc->ios.vdd = vdd;
1142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1144 release_mem_region(res->start, res->end - res->start + 1);
1146 platform_set_drvdata(pdev, NULL);
1148 mmc_remove_host(host->mmc);
1149 if (host->pdata->cleanup)
1150 host->pdata->cleanup(&pdev->dev);
1151 free_irq(host->irq, host);
1152 if (mmc_slot(host).card_detect_irq)
1153 free_irq(mmc_slot(host).card_detect_irq, host);
1154 flush_scheduled_work();
1156 mmc_omap_fclk_state(host, OFF);
1157 clk_disable(host->iclk);
1158 clk_put(host->fclk);
1159 clk_put(host->iclk);
1160 if (host->dbclk_enabled) {
1161 clk_disable(host->dbclk);
1162 clk_put(host->dbclk);
1165 mmc_free_host(host->mmc);
1166 iounmap(host->base);
1173 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1176 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1178 if (host && host->suspended)
1182 mmc_omap_fclk_state(host, ON);
1184 ret = mmc_suspend_host(host->mmc, state);
1186 host->suspended = 1;
1188 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1189 OMAP_HSMMC_WRITE(host->base, IE, 0);
1191 if (host->pdata->suspend) {
1192 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1194 dev_dbg(mmc_dev(host->mmc),
1195 "Unable to handle MMC board"
1196 " level suspend\n");
1199 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1200 OMAP_HSMMC_WRITE(host->base, HCTL,
1201 OMAP_HSMMC_READ(host->base, HCTL)
1203 OMAP_HSMMC_WRITE(host->base, HCTL,
1204 OMAP_HSMMC_READ(host->base, HCTL)
1206 OMAP_HSMMC_WRITE(host->base, HCTL,
1207 OMAP_HSMMC_READ(host->base, HCTL)
1211 mmc_omap_fclk_state(host, OFF);
1212 clk_disable(host->iclk);
1213 clk_disable(host->dbclk);
1220 /* Routine to resume the MMC device */
1221 static int omap_mmc_resume(struct platform_device *pdev)
1224 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1226 if (host && !host->suspended)
1231 if (mmc_omap_fclk_state(host, ON) != 0)
1234 ret = clk_enable(host->iclk);
1236 mmc_omap_fclk_state(host, OFF);
1237 clk_put(host->fclk);
1241 if (clk_enable(host->dbclk) != 0)
1242 dev_dbg(mmc_dev(host->mmc),
1243 "Enabling debounce clk failed\n");
1245 if (host->pdata->resume) {
1246 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1248 dev_dbg(mmc_dev(host->mmc),
1249 "Unmask interrupt failed\n");
1252 /* Notify the core to resume the host */
1253 ret = mmc_resume_host(host->mmc);
1255 host->suspended = 0;
1257 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
1263 dev_dbg(mmc_dev(host->mmc),
1264 "Failed to enable MMC clocks during resume\n");
1269 #define omap_mmc_suspend NULL
1270 #define omap_mmc_resume NULL
1273 static struct platform_driver omap_mmc_driver = {
1274 .probe = omap_mmc_probe,
1275 .remove = omap_mmc_remove,
1276 .suspend = omap_mmc_suspend,
1277 .resume = omap_mmc_resume,
1279 .name = DRIVER_NAME,
1280 .owner = THIS_MODULE,
1284 static int __init omap_mmc_init(void)
1286 /* Register the MMC driver */
1287 return platform_driver_register(&omap_mmc_driver);
1290 static void __exit omap_mmc_cleanup(void)
1292 /* Unregister MMC driver */
1293 platform_driver_unregister(&omap_mmc_driver);
1296 module_init(omap_mmc_init);
1297 module_exit(omap_mmc_cleanup);
1299 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1300 MODULE_LICENSE("GPL");
1301 MODULE_ALIAS("platform:" DRIVER_NAME);
1302 MODULE_AUTHOR("Texas Instruments Inc");