drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define OMAP_MMC_DATADIR_NONE   0
 102 #define OMAP_MMC_DATADIR_READ   1
 103 #define OMAP_MMC_DATADIR_WRITE  2
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 enum {OFF = 0, ON};
 125 #define IDLE_TIMEOUT (5*HZ)
 126
 127 struct mmc_omap_host {
 128         struct  device          *dev;
 129         struct  mmc_host        *mmc;
 130         struct  mmc_request     *mrq;
 131         struct  mmc_command     *cmd;
 132         struct  mmc_data        *data;
 133         struct  clk             *fclk;
 134         struct  clk             *iclk;
 135         struct  clk             *dbclk;
 136         struct  semaphore       sem;
 137         struct  work_struct     mmc_carddetect_work;
 138         void    __iomem         *base;
 139         resource_size_t         mapbase;
 140         unsigned int            id;
 141         unsigned int            dma_len;
 142         unsigned int            dma_dir;
 143         unsigned char           bus_mode;
 144         unsigned char           datadir;
 145         u32                     *buffer;
 146         u32                     bytesleft;
 147         int                     suspended;
 148         int                     irq;
 149         int                     carddetect;
 150         int                     use_dma, dma_ch;
 151         int                     initstr;
 152         int                     slot_id;
 153         int                     dbclk_enabled;
 154
 155         struct timer_list       idle_timer;
 156         spinlock_t              clk_lock;     /* for changing enabled state */
 157         int                     fclk_enabled:1;
 158
 159         struct  omap_mmc_platform_data  *pdata;
 160 };
 161
 162 int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
 163 {
 164         unsigned long flags;
 165         int ret;
 166
 167         spin_lock_irqsave(&host->clk_lock, flags);
 168         if (host->fclk_enabled != state) {
 169                 if (state == ON) {
 170                         if (host->fclk_enabled == OFF) {
 171                                 ret = clk_enable(host->fclk);
 172                                 if (ret != 0)
 173                                         return ret;
 174                                 dev_dbg(mmc_dev(host->mmc),
 175                                         "mmc_fclk: enabled\n");
 176                         }
 177                         /* Revisit: Change the timer bump based on real
 178                            MMC usage characteristics */
 179                         mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 180                 } else {
 181                         clk_disable(host->fclk);
 182                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
 183                         del_timer(&host->idle_timer);
 184                 }
 185                 host->fclk_enabled = state;
 186         }
 187         spin_unlock_irqrestore(&host->clk_lock, flags);
 188         return 0;
 189 }
 190
 191 static void mmc_omap_idle_timer(unsigned long data)
 192 {
 193         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 194
 195         mmc_omap_fclk_state(host, OFF);
 196 }
 197
 198 /*
 199  * Stop clock to the card
 200  */
 201 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 202 {
 203         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 204                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 205         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 206                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 207 }
 208
 209 /*
 210  * Send init stream sequence to card
 211  * before sending IDLE command
 212  */
 213 static void send_init_stream(struct mmc_omap_host *host)
 214 {
 215         int reg = 0;
 216         unsigned long timeout;
 217
 218         disable_irq(host->irq);
 219         OMAP_HSMMC_WRITE(host->base, CON,
 220                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 221         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 222
 223         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 224         while ((reg != CC) && time_before(jiffies, timeout))
 225                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 226
 227         OMAP_HSMMC_WRITE(host->base, CON,
 228                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 229         enable_irq(host->irq);
 230 }
 231
 232 static inline
 233 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 234 {
 235         if (host->pdata->slots[host->slot_id].get_cover_state)
 236                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 237         return 1;
 238 }
 239
 240 static ssize_t
 241 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 242                            char *buf)
 243 {
 244         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 245         struct mmc_omap_host *host = mmc_priv(mmc);
 246
 247         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 248                        "open");
 249 }
 250
 251 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 252
 253 static ssize_t
 254 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 255                         char *buf)
 256 {
 257         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 258         struct mmc_omap_host *host = mmc_priv(mmc);
 259         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 260
 261         return sprintf(buf, "slot:%s\n", slot.name);
 262 }
 263
 264 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 265
 266 /*
 267  * Configure the response type and send the cmd.
 268  */
 269 static void
 270 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 271         struct mmc_data *data)
 272 {
 273         int cmdreg = 0, resptype = 0, cmdtype = 0;
 274
 275         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 276                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 277         host->cmd = cmd;
 278
 279         /*
 280          * Clear status bits and enable interrupts
 281          */
 282         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 283         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 284         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 285
 286         if (cmd->flags & MMC_RSP_PRESENT) {
 287                 if (cmd->flags & MMC_RSP_136)
 288                         resptype = 1;
 289                 else
 290                         resptype = 2;
 291         }
 292
 293         /*
 294          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 295          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 296          */
 297         if (cmd->opcode == 12)
 298                 cmdtype = 0x3;
 299
 300         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 301
 302         if (data) {
 303                 cmdreg |= DP_SELECT | MSBS | BCE;
 304                 if (data->flags & MMC_DATA_READ)
 305                         cmdreg |= DDIR;
 306                 else
 307                         cmdreg &= ~(DDIR);
 308         }
 309
 310         if (host->use_dma)
 311                 cmdreg |= DMA_EN;
 312
 313         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 314         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 315 }
 316
 317 /*
 318  * Notify the transfer complete to MMC core
 319  */
 320 static void
 321 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 322 {
 323         host->data = NULL;
 324
 325         if (host->use_dma && host->dma_ch != -1)
 326                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 327                         host->dma_dir);
 328
 329         host->datadir = OMAP_MMC_DATADIR_NONE;
 330
 331         if (!data->error)
 332                 data->bytes_xfered += data->blocks * (data->blksz);
 333         else
 334                 data->bytes_xfered = 0;
 335
 336         if (!data->stop) {
 337                 host->mrq = NULL;
 338                 mmc_request_done(host->mmc, data->mrq);
 339                 return;
 340         }
 341         mmc_omap_start_command(host, data->stop, NULL);
 342 }
 343
 344 /*
 345  * Notify the core about command completion
 346  */
 347 static void
 348 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 349 {
 350         host->cmd = NULL;
 351
 352         if (cmd->flags & MMC_RSP_PRESENT) {
 353                 if (cmd->flags & MMC_RSP_136) {
 354                         /* response type 2 */
 355                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 356                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 357                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 358                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 359                 } else {
 360                         /* response types 1, 1b, 3, 4, 5, 6 */
 361                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 362                 }
 363         }
 364         if (host->data == NULL || cmd->error) {
 365                 host->mrq = NULL;
 366                 mmc_request_done(host->mmc, cmd->mrq);
 367         }
 368 }
 369
 370 /*
 371  * DMA clean up for command errors
 372  */
 373 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 374 {
 375         host->data->error = -ETIMEDOUT;
 376
 377         if (host->use_dma && host->dma_ch != -1) {
 378                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 379                         host->dma_dir);
 380                 omap_free_dma(host->dma_ch);
 381                 host->dma_ch = -1;
 382                 up(&host->sem);
 383         }
 384         host->data = NULL;
 385         host->datadir = OMAP_MMC_DATADIR_NONE;
 386 }
 387
 388 /*
 389  * Readable error output
 390  */
 391 #ifdef CONFIG_MMC_DEBUG
 392 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 393 {
 394         /* --- means reserved bit without definition at documentation */
 395         static const char *mmc_omap_status_bits[] = {
 396                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 397                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 398                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 399                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 400         };
 401         int i;
 402
 403         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 404
 405         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 406                 if (status & (1 << i))
 407                         /*
 408                          * KERN_* facility is not used here because this should
 409                          * print a single line.
 410                          */
 411                         printk(" %s", mmc_omap_status_bits[i]);
 412
 413         printk("\n");
 414
 415 }
 416 #endif  /* CONFIG_MMC_DEBUG */
 417
 418
 419 /*
 420  * MMC controller IRQ handler
 421  */
 422 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 423 {
 424         struct mmc_omap_host *host = dev_id;
 425         struct mmc_data *data;
 426         int end_cmd = 0, end_trans = 0, status;
 427
 428         if (host->cmd == NULL && host->data == NULL) {
 429                 OMAP_HSMMC_WRITE(host->base, STAT,
 430                         OMAP_HSMMC_READ(host->base, STAT));
 431                 return IRQ_HANDLED;
 432         }
 433
 434         data = host->data;
 435         status = OMAP_HSMMC_READ(host->base, STAT);
 436         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 437
 438         if (status & ERR) {
 439 #ifdef CONFIG_MMC_DEBUG
 440                 mmc_omap_report_irq(host, status);
 441 #endif
 442                 if ((status & CMD_TIMEOUT) ||
 443                         (status & CMD_CRC)) {
 444                         if (host->cmd) {
 445                                 if (status & CMD_TIMEOUT) {
 446                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 447                                                 OMAP_HSMMC_READ(host->base,
 448                                                                 SYSCTL) | SRC);
 449                                         while (OMAP_HSMMC_READ(host->base,
 450                                                                 SYSCTL) & SRC) ;
 451                                         host->cmd->error = -ETIMEDOUT;
 452                                 } else {
 453                                         host->cmd->error = -EILSEQ;
 454                                 }
 455                                 end_cmd = 1;
 456                         }
 457                         if (host->data)
 458                                 mmc_dma_cleanup(host);
 459                 }
 460                 if ((status & DATA_TIMEOUT) ||
 461                         (status & DATA_CRC)) {
 462                         if (host->data) {
 463                                 if (status & DATA_TIMEOUT)
 464                                         mmc_dma_cleanup(host);
 465                                 else
 466                                         host->data->error = -EILSEQ;
 467                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 468                                         OMAP_HSMMC_READ(host->base,
 469                                                         SYSCTL) | SRD);
 470                                 while (OMAP_HSMMC_READ(host->base,
 471                                                         SYSCTL) & SRD) ;
 472                                 end_trans = 1;
 473                         }
 474                 }
 475                 if (status & CARD_ERR) {
 476                         dev_dbg(mmc_dev(host->mmc),
 477                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 478                         if (host->cmd)
 479                                 end_cmd = 1;
 480                         if (host->data)
 481                                 end_trans = 1;
 482                 }
 483         }
 484
 485         OMAP_HSMMC_WRITE(host->base, STAT, status);
 486
 487         if (end_cmd || (status & CC))
 488                 mmc_omap_cmd_done(host, host->cmd);
 489         if (end_trans || (status & TC))
 490                 mmc_omap_xfer_done(host, data);
 491
 492         return IRQ_HANDLED;
 493 }
 494
 495 /*
 496  * Switch MMC operating voltage
 497  */
 498 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 499 {
 500         u32 reg_val = 0;
 501         int ret;
 502
 503         /* Disable the clocks */
 504         mmc_omap_fclk_state(host, OFF);
 505         clk_disable(host->iclk);
 506         clk_disable(host->dbclk);
 507
 508         /* Turn the power off */
 509         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 510         if (ret != 0)
 511                 goto err;
 512
 513         /* Turn the power ON with given VDD 1.8 or 3.0v */
 514         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 515         if (ret != 0)
 516                 goto err;
 517
 518         mmc_omap_fclk_state(host, ON);
 519         clk_enable(host->iclk);
 520         clk_enable(host->dbclk);
 521
 522         OMAP_HSMMC_WRITE(host->base, HCTL,
 523                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 524         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 525         /*
 526          * If a MMC dual voltage card is detected, the set_ios fn calls
 527          * this fn with VDD bit set for 1.8V. Upon card removal from the
 528          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 529          *
 530          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 531          * set in HCTL.
 532          */
 533         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 534                                 ((1 << vdd) == MMC_VDD_33_34)))
 535                 reg_val |= SDVS30;
 536         if ((1 << vdd) == MMC_VDD_165_195)
 537                 reg_val |= SDVS18;
 538
 539         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 540
 541         OMAP_HSMMC_WRITE(host->base, HCTL,
 542                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 543
 544         return 0;
 545 err:
 546         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 547         return ret;
 548 }
 549
 550 /*
 551  * Work Item to notify the core about card insertion/removal
 552  */
 553 static void mmc_omap_detect(struct work_struct *work)
 554 {
 555         u16 vdd = 0;
 556         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 557                                                 mmc_carddetect_work);
 558
 559         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 560         if (host->carddetect) {
 561                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 562                         /*
 563                          * Set the VDD back to 3V when the card is removed
 564                          * before the set_ios fn turns off the power.
 565                          */
 566                         vdd = fls(host->mmc->ocr_avail) - 1;
 567                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 568                                 host->mmc->ios.vdd = vdd;
 569                 }
 570                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 571         } else {
 572                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 573                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 574                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 575                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 576         }
 577 }
 578
 579 /*
 580  * ISR for handling card insertion and removal
 581  */
 582 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 583 {
 584         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 585
 586         host->carddetect = mmc_slot(host).card_detect(irq);
 587         schedule_work(&host->mmc_carddetect_work);
 588
 589         return IRQ_HANDLED;
 590 }
 591
 592 /*
 593  * DMA call back function
 594  */
 595 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 596 {
 597         struct mmc_omap_host *host = data;
 598
 599         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 600                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 601
 602         if (host->dma_ch < 0)
 603                 return;
 604
 605         omap_free_dma(host->dma_ch);
 606         host->dma_ch = -1;
 607         /*
 608          * DMA Callback: run in interrupt context.
 609          * mutex_unlock will through a kernel warning if used.
 610          */
 611         up(&host->sem);
 612 }
 613
 614 /*
 615  * Configure dma src and destination parameters
 616  */
 617 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 618                                 struct mmc_data *data)
 619 {
 620         if (sync_dir == 0) {
 621                 omap_set_dma_dest_params(host->dma_ch, 0,
 622                         OMAP_DMA_AMODE_CONSTANT,
 623                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 624                 omap_set_dma_src_params(host->dma_ch, 0,
 625                         OMAP_DMA_AMODE_POST_INC,
 626                         sg_dma_address(&data->sg[0]), 0, 0);
 627         } else {
 628                 omap_set_dma_src_params(host->dma_ch, 0,
 629                         OMAP_DMA_AMODE_CONSTANT,
 630                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 631                 omap_set_dma_dest_params(host->dma_ch, 0,
 632                         OMAP_DMA_AMODE_POST_INC,
 633                         sg_dma_address(&data->sg[0]), 0, 0);
 634         }
 635         return 0;
 636 }
 637 /*
 638  * Routine to configure and start DMA for the MMC card
 639  */
 640 static int
 641 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 642 {
 643         int sync_dev, sync_dir = 0;
 644         int dma_ch = 0, ret = 0, err = 1;
 645         struct mmc_data *data = req->data;
 646
 647         /*
 648          * If for some reason the DMA transfer is still active,
 649          * we wait for timeout period and free the dma
 650          */
 651         if (host->dma_ch != -1) {
 652                 set_current_state(TASK_UNINTERRUPTIBLE);
 653                 schedule_timeout(100);
 654                 if (down_trylock(&host->sem)) {
 655                         omap_free_dma(host->dma_ch);
 656                         host->dma_ch = -1;
 657                         up(&host->sem);
 658                         return err;
 659                 }
 660         } else {
 661                 if (down_trylock(&host->sem))
 662                         return err;
 663         }
 664
 665         if (!(data->flags & MMC_DATA_WRITE)) {
 666                 host->dma_dir = DMA_FROM_DEVICE;
 667                 if (host->id == OMAP_MMC1_DEVID)
 668                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 669                 else
 670                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 671         } else {
 672                 host->dma_dir = DMA_TO_DEVICE;
 673                 if (host->id == OMAP_MMC1_DEVID)
 674                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 675                 else
 676                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 677         }
 678
 679         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 680                         host, &dma_ch);
 681         if (ret != 0) {
 682                 dev_dbg(mmc_dev(host->mmc),
 683                         "%s: omap_request_dma() failed with %d\n",
 684                         mmc_hostname(host->mmc), ret);
 685                 return ret;
 686         }
 687
 688         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 689                         data->sg_len, host->dma_dir);
 690         host->dma_ch = dma_ch;
 691
 692         if (!(data->flags & MMC_DATA_WRITE))
 693                 mmc_omap_config_dma_param(1, host, data);
 694         else
 695                 mmc_omap_config_dma_param(0, host, data);
 696
 697         if ((data->blksz % 4) == 0)
 698                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 699                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 700                         sync_dev, sync_dir);
 701         else
 702                 /* REVISIT: The MMC buffer increments only when MSB is written.
 703                  * Return error for blksz which is non multiple of four.
 704                  */
 705                 return -EINVAL;
 706
 707         omap_start_dma(dma_ch);
 708         return 0;
 709 }
 710
 711 static void set_data_timeout(struct mmc_omap_host *host,
 712                              struct mmc_request *req)
 713 {
 714         unsigned int timeout, cycle_ns;
 715         uint32_t reg, clkd, dto = 0;
 716
 717         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 718         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 719         if (clkd == 0)
 720                 clkd = 1;
 721
 722         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 723         timeout = req->data->timeout_ns / cycle_ns;
 724         timeout += req->data->timeout_clks;
 725         if (timeout) {
 726                 while ((timeout & 0x80000000) == 0) {
 727                         dto += 1;
 728                         timeout <<= 1;
 729                 }
 730                 dto = 31 - dto;
 731                 timeout <<= 1;
 732                 if (timeout && dto)
 733                         dto += 1;
 734                 if (dto >= 13)
 735                         dto -= 13;
 736                 else
 737                         dto = 0;
 738                 if (dto > 14)
 739                         dto = 14;
 740         }
 741
 742         reg &= ~DTO_MASK;
 743         reg |= dto << DTO_SHIFT;
 744         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 745 }
 746
 747 /*
 748  * Configure block length for MMC/SD cards and initiate the transfer.
 749  */
 750 static int
 751 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 752 {
 753         int ret;
 754         host->data = req->data;
 755
 756         if (req->data == NULL) {
 757                 host->datadir = OMAP_MMC_DATADIR_NONE;
 758                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 759                 return 0;
 760         }
 761
 762         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 763                                         | (req->data->blocks << 16));
 764         set_data_timeout(host, req);
 765
 766         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 767                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 768
 769         if (host->use_dma) {
 770                 ret = mmc_omap_start_dma_transfer(host, req);
 771                 if (ret != 0) {
 772                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 773                         return ret;
 774                 }
 775         }
 776         return 0;
 777 }
 778
 779 /*
 780  * Request function. for read/write operation
 781  */
 782 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 783 {
 784         struct mmc_omap_host *host = mmc_priv(mmc);
 785
 786         WARN_ON(host->mrq != NULL);
 787         host->mrq = req;
 788         mmc_omap_prepare_data(host, req);
 789         mmc_omap_fclk_state(host, ON);
 790         mmc_omap_start_command(host, req->cmd, req->data);
 791 }
 792
 793 /* Routine to configure clock values. Exposed API to core */
 794 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 795 {
 796         struct mmc_omap_host *host = mmc_priv(mmc);
 797         u16 dsor = 0;
 798         unsigned long regval;
 799         unsigned long timeout;
 800
 801         switch (ios->power_mode) {
 802         case MMC_POWER_OFF:
 803                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 804                 break;
 805         case MMC_POWER_UP:
 806                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 807                 break;
 808         }
 809
 810         switch (mmc->ios.bus_width) {
 811         case MMC_BUS_WIDTH_4:
 812                 OMAP_HSMMC_WRITE(host->base, HCTL,
 813                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 814                 break;
 815         case MMC_BUS_WIDTH_1:
 816                 OMAP_HSMMC_WRITE(host->base, HCTL,
 817                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 818                 break;
 819         }
 820
 821         if (host->id == OMAP_MMC1_DEVID) {
 822                 /* Only MMC1 can operate at 3V/1.8V */
 823                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 824                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 825                                 /*
 826                                  * The mmc_select_voltage fn of the core does
 827                                  * not seem to set the power_mode to
 828                                  * MMC_POWER_UP upon recalculating the voltage.
 829                                  * vdd 1.8v.
 830                                  */
 831                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 832                                         dev_dbg(mmc_dev(host->mmc),
 833                                                 "Switch operation failed\n");
 834                 }
 835         }
 836
 837         if (ios->clock) {
 838                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 839                 if (dsor < 1)
 840                         dsor = 1;
 841
 842                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 843                         dsor++;
 844
 845                 if (dsor > 250)
 846                         dsor = 250;
 847         }
 848         omap_mmc_stop_clock(host);
 849         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 850         regval = regval & ~(CLKD_MASK);
 851         regval = regval | (dsor << 6) | (DTO << 16);
 852         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 853         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 854                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 855
 856         /* Wait till the ICS bit is set */
 857         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 858         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 859                 && time_before(jiffies, timeout))
 860                 msleep(1);
 861
 862         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 863                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 864
 865         if (ios->power_mode == MMC_POWER_ON)
 866                 send_init_stream(host);
 867
 868         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 869                 OMAP_HSMMC_WRITE(host->base, CON,
 870                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 871
 872 }
 873
 874 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 875 {
 876         struct mmc_omap_host *host = mmc_priv(mmc);
 877         struct omap_mmc_platform_data *pdata = host->pdata;
 878
 879         if (!pdata->slots[0].card_detect)
 880                 return -ENOSYS;
 881         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 882 }
 883
 884 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 885 {
 886         struct mmc_omap_host *host = mmc_priv(mmc);
 887         struct omap_mmc_platform_data *pdata = host->pdata;
 888
 889         if (!pdata->slots[0].get_ro)
 890                 return -ENOSYS;
 891         return pdata->slots[0].get_ro(host->dev, 0);
 892 }
 893
 894 static struct mmc_host_ops mmc_omap_ops = {
 895         .request = omap_mmc_request,
 896         .set_ios = omap_mmc_set_ios,
 897         .get_cd = omap_hsmmc_get_cd,
 898         .get_ro = omap_hsmmc_get_ro,
 899         /* NYET -- enable_sdio_irq */
 900 };
 901
 902 static int __init omap_mmc_probe(struct platform_device *pdev)
 903 {
 904         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 905         struct mmc_host *mmc;
 906         struct mmc_omap_host *host = NULL;
 907         struct resource *res;
 908         int ret = 0, irq, reg;
 909         u32 hctl, capa;
 910
 911         if (pdata == NULL) {
 912                 dev_err(&pdev->dev, "Platform Data is missing\n");
 913                 return -ENXIO;
 914         }
 915
 916         if (pdata->nr_slots == 0) {
 917                 dev_err(&pdev->dev, "No Slots\n");
 918                 return -ENXIO;
 919         }
 920
 921         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 922         irq = platform_get_irq(pdev, 0);
 923         if (res == NULL || irq < 0)
 924                 return -ENXIO;
 925
 926         res = request_mem_region(res->start, res->end - res->start + 1,
 927                                                         pdev->name);
 928         if (res == NULL)
 929                 return -EBUSY;
 930
 931         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 932         if (!mmc) {
 933                 ret = -ENOMEM;
 934                 goto err;
 935         }
 936
 937         host            = mmc_priv(mmc);
 938         host->mmc       = mmc;
 939         host->pdata     = pdata;
 940         host->dev       = &pdev->dev;
 941         host->use_dma   = 1;
 942         host->dev->dma_mask = &pdata->dma_mask;
 943         host->dma_ch    = -1;
 944         host->irq       = irq;
 945         host->id        = pdev->id;
 946         host->slot_id   = 0;
 947         host->mapbase   = res->start;
 948         host->base      = ioremap(host->mapbase, SZ_4K);
 949
 950         platform_set_drvdata(pdev, host);
 951         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 952
 953         mmc->ops        = &mmc_omap_ops;
 954         mmc->f_min      = 400000;
 955         mmc->f_max      = 52000000;
 956
 957         sema_init(&host->sem, 1);
 958
 959         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 960         if (IS_ERR(host->iclk)) {
 961                 ret = PTR_ERR(host->iclk);
 962                 host->iclk = NULL;
 963                 goto err1;
 964         }
 965         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 966         if (IS_ERR(host->fclk)) {
 967                 ret = PTR_ERR(host->fclk);
 968                 host->fclk = NULL;
 969                 clk_put(host->iclk);
 970                 goto err1;
 971         }
 972
 973         spin_lock_init(&host->clk_lock);
 974         setup_timer(&host->idle_timer, mmc_omap_idle_timer,
 975                     (unsigned long) host);
 976
 977         if (mmc_omap_fclk_state(host, ON) != 0) {
 978                 clk_put(host->iclk);
 979                 clk_put(host->fclk);
 980                 goto err1;
 981         }
 982         if (clk_enable(host->iclk) != 0) {
 983                 mmc_omap_fclk_state(host, OFF);
 984                 clk_put(host->iclk);
 985                 clk_put(host->fclk);
 986                 goto err1;
 987         }
 988
 989         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 990         /*
 991          * MMC can still work without debounce clock.
 992          */
 993         if (IS_ERR(host->dbclk))
 994                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 995         else
 996                 if (clk_enable(host->dbclk) != 0)
 997                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 998                                                         " clk failed\n");
 999                 else
1000                         host->dbclk_enabled = 1;
1001
1002 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1003         mmc->max_phys_segs = 1;
1004         mmc->max_hw_segs = 1;
1005 #endif
1006         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1007         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1008         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1009         mmc->max_seg_size = mmc->max_req_size;
1010
1011         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1012         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1013
1014         if (pdata->slots[host->slot_id].wires >= 4)
1015                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1016
1017         /* Only MMC1 supports 3.0V */
1018         if (host->id == OMAP_MMC1_DEVID) {
1019                 hctl = SDVS30;
1020                 capa = VS30 | VS18;
1021         } else {
1022                 hctl = SDVS18;
1023                 capa = VS18;
1024         }
1025
1026         OMAP_HSMMC_WRITE(host->base, HCTL,
1027                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1028
1029         OMAP_HSMMC_WRITE(host->base, CAPA,
1030                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1031
1032         /* Set the controller to AUTO IDLE mode */
1033         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1034                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1035
1036         /* Set SD bus power bit */
1037         OMAP_HSMMC_WRITE(host->base, HCTL,
1038                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1039
1040         /* Request IRQ for MMC operations */
1041         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1042                         mmc_hostname(mmc), host);
1043         if (ret) {
1044                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1045                 goto err_irq;
1046         }
1047
1048         if (pdata->init != NULL) {
1049                 if (pdata->init(&pdev->dev) != 0) {
1050                         dev_dbg(mmc_dev(host->mmc),
1051                                 "Unable to configure MMC IRQs\n");
1052                         goto err_irq_cd_init;
1053                 }
1054         }
1055
1056         /* Request IRQ for card detect */
1057         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1058                 ret = request_irq(mmc_slot(host).card_detect_irq,
1059                                   omap_mmc_cd_handler,
1060                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1061                                           | IRQF_DISABLED,
1062                                   mmc_hostname(mmc), host);
1063                 if (ret) {
1064                         dev_dbg(mmc_dev(host->mmc),
1065                                 "Unable to grab MMC CD IRQ\n");
1066                         goto err_irq_cd;
1067                 }
1068         }
1069
1070         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1071         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1072
1073         mmc_add_host(mmc);
1074
1075         if (host->pdata->slots[host->slot_id].name != NULL) {
1076                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1077                 if (ret < 0)
1078                         goto err_slot_name;
1079         }
1080         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1081                         host->pdata->slots[host->slot_id].get_cover_state) {
1082                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1083                 if (ret < 0)
1084                         goto err_cover_switch;
1085         }
1086
1087         return 0;
1088
1089 err_cover_switch:
1090         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1091 err_slot_name:
1092         mmc_remove_host(mmc);
1093 err_irq_cd:
1094         free_irq(mmc_slot(host).card_detect_irq, host);
1095 err_irq_cd_init:
1096         free_irq(host->irq, host);
1097 err_irq:
1098         mmc_omap_fclk_state(host, OFF);
1099         clk_disable(host->iclk);
1100         clk_put(host->fclk);
1101         clk_put(host->iclk);
1102         if (host->dbclk_enabled) {
1103                 clk_disable(host->dbclk);
1104                 clk_put(host->dbclk);
1105         }
1106
1107 err1:
1108         iounmap(host->base);
1109 err:
1110         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1111         release_mem_region(res->start, res->end - res->start + 1);
1112         if (host)
1113                 mmc_free_host(mmc);
1114         return ret;
1115 }
1116
1117 static int omap_mmc_remove(struct platform_device *pdev)
1118 {
1119         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1120         struct resource *res;
1121         u16 vdd = 0;
1122
1123         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1124         /*
1125          * Set the vdd back to 3V,
1126          * applicable for dual volt support.
1127          */
1128                 vdd = fls(host->mmc->ocr_avail) - 1;
1129                 if (omap_mmc_switch_opcond(host, vdd) != 0)
1130                         host->mmc->ios.vdd = vdd;
1131         }
1132
1133         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1134         if (res)
1135                 release_mem_region(res->start, res->end - res->start + 1);
1136
1137         platform_set_drvdata(pdev, NULL);
1138         if (host) {
1139                 mmc_remove_host(host->mmc);
1140                 if (host->pdata->cleanup)
1141                         host->pdata->cleanup(&pdev->dev);
1142                 free_irq(host->irq, host);
1143                 if (mmc_slot(host).card_detect_irq)
1144                         free_irq(mmc_slot(host).card_detect_irq, host);
1145                 flush_scheduled_work();
1146
1147                 mmc_omap_fclk_state(host, OFF);
1148                 clk_disable(host->iclk);
1149                 clk_put(host->fclk);
1150                 clk_put(host->iclk);
1151                 if (host->dbclk_enabled) {
1152                         clk_disable(host->dbclk);
1153                         clk_put(host->dbclk);
1154                 }
1155
1156                 mmc_free_host(host->mmc);
1157                 iounmap(host->base);
1158         }
1159
1160         return 0;
1161 }
1162
1163 #ifdef CONFIG_PM
1164 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1165 {
1166         int ret = 0;
1167         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1168
1169         if (host && host->suspended)
1170                 return 0;
1171
1172         if (host) {
1173                 ret = mmc_suspend_host(host->mmc, state);
1174                 if (ret == 0) {
1175                         host->suspended = 1;
1176
1177                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1178                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1179
1180                         if (host->pdata->suspend) {
1181                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1182                                 if (ret)
1183                                         dev_dbg(mmc_dev(host->mmc),
1184                                                 "Unable to handle MMC board"
1185                                                 " level suspend\n");
1186                         }
1187
1188                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1189                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1190                                         OMAP_HSMMC_READ(host->base, HCTL)
1191                                         & SDVSCLR);
1192                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1193                                         OMAP_HSMMC_READ(host->base, HCTL)
1194                                         | SDVS30);
1195                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1196                                         OMAP_HSMMC_READ(host->base, HCTL)
1197                                         | SDBP);
1198                         }
1199
1200                         mmc_omap_fclk_state(host, OFF);
1201                         clk_disable(host->iclk);
1202                         clk_disable(host->dbclk);
1203                 }
1204
1205         }
1206         return ret;
1207 }
1208
1209 /* Routine to resume the MMC device */
1210 static int omap_mmc_resume(struct platform_device *pdev)
1211 {
1212         int ret = 0;
1213         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1214
1215         if (host && !host->suspended)
1216                 return 0;
1217
1218         if (host) {
1219
1220                 if (mmc_omap_fclk_state(host, ON) != 0)
1221                         goto clk_en_err;
1222
1223                 ret = clk_enable(host->iclk);
1224                 if (ret) {
1225                         mmc_omap_fclk_state(host, OFF);
1226                         clk_put(host->fclk);
1227                         goto clk_en_err;
1228                 }
1229
1230                 if (clk_enable(host->dbclk) != 0)
1231                         dev_dbg(mmc_dev(host->mmc),
1232                                         "Enabling debounce clk failed\n");
1233
1234                 if (host->pdata->resume) {
1235                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1236                         if (ret)
1237                                 dev_dbg(mmc_dev(host->mmc),
1238                                         "Unmask interrupt failed\n");
1239                 }
1240
1241                 /* Notify the core to resume the host */
1242                 ret = mmc_resume_host(host->mmc);
1243                 if (ret == 0)
1244                         host->suspended = 0;
1245         }
1246
1247         return ret;
1248
1249 clk_en_err:
1250         dev_dbg(mmc_dev(host->mmc),
1251                 "Failed to enable MMC clocks during resume\n");
1252         return ret;
1253 }
1254
1255 #else
1256 #define omap_mmc_suspend        NULL
1257 #define omap_mmc_resume         NULL
1258 #endif
1259
1260 static struct platform_driver omap_mmc_driver = {
1261         .probe          = omap_mmc_probe,
1262         .remove         = omap_mmc_remove,
1263         .suspend        = omap_mmc_suspend,
1264         .resume         = omap_mmc_resume,
1265         .driver         = {
1266                 .name = DRIVER_NAME,
1267                 .owner = THIS_MODULE,
1268         },
1269 };
1270
1271 static int __init omap_mmc_init(void)
1272 {
1273         /* Register the MMC driver */
1274         return platform_driver_register(&omap_mmc_driver);
1275 }
1276
1277 static void __exit omap_mmc_cleanup(void)
1278 {
1279         /* Unregister MMC driver */
1280         platform_driver_unregister(&omap_mmc_driver);
1281 }
1282
1283 module_init(omap_mmc_init);
1284 module_exit(omap_mmc_cleanup);
1285
1286 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1287 MODULE_LICENSE("GPL");
1288 MODULE_ALIAS("platform:" DRIVER_NAME);
1289 MODULE_AUTHOR("Texas Instruments Inc");