2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
29 #include <linux/semaphore.h>
31 #include <mach/hardware.h>
32 #include <mach/board.h>
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
56 #define SDVS18 (0x5<<9)
57 #define SDVS30 (0x6<<9)
58 #define SDVSCLR 0xFFFFF1FF
59 #define SDVSDET 0x00000400
66 #define CLKD_MASK 0x0000FFC0
67 #define INT_EN_MASK 0x307F0033
68 #define INIT_STREAM (1<<1)
69 #define DP_SELECT (1<<21)
74 #define FOUR_BIT 1 << 1
79 #define CMD_TIMEOUT (1 << 16)
80 #define DATA_TIMEOUT (1 << 20)
81 #define CMD_CRC (1 << 17)
82 #define DATA_CRC (1 << 21)
83 #define CARD_ERR (1 << 28)
84 #define STAT_CLEAR 0xFFFFFFFF
85 #define INIT_STREAM_CMD 0x00000000
86 #define DUAL_VOLT_OCR_BIT 7
90 #define OMAP_MMC1_DEVID 1
91 #define OMAP_MMC2_DEVID 2
92 #define OMAP_MMC_DATADIR_NONE 0
93 #define OMAP_MMC_DATADIR_READ 1
94 #define OMAP_MMC_DATADIR_WRITE 2
95 #define MMC_TIMEOUT_MS 20
96 #define OMAP_MMC_MASTER_CLOCK 96000000
97 #define DRIVER_NAME "mmci-omap"
99 * slot_id is device id - 1, device id is a static value
100 * of 1 to represent device 1 etc..
102 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
105 * MMC Host controller read/write API's
107 #define OMAP_HSMMC_READ(base, reg) \
108 __raw_readl((base) + OMAP_HSMMC_##reg)
110 #define OMAP_HSMMC_WRITE(base, reg, val) \
111 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
113 struct mmc_omap_host {
115 struct mmc_host *mmc;
116 struct mmc_request *mrq;
117 struct mmc_command *cmd;
118 struct mmc_data *data;
122 struct semaphore sem;
123 struct work_struct mmc_carddetect_work;
125 resource_size_t mapbase;
127 unsigned int dma_len;
128 unsigned int dma_dir;
129 unsigned char bus_mode;
130 unsigned char datadir;
140 struct omap_mmc_platform_data *pdata;
144 * Stop clock to the card
146 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
148 OMAP_HSMMC_WRITE(host->base, SYSCTL,
149 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
150 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
151 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
155 * Send init stream sequence to card
156 * before sending IDLE command
158 static void send_init_stream(struct mmc_omap_host *host)
161 unsigned long timeout;
163 disable_irq(host->irq);
164 OMAP_HSMMC_WRITE(host->base, CON,
165 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
166 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
168 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
169 while ((reg != CC) && time_before(jiffies, timeout))
170 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
172 OMAP_HSMMC_WRITE(host->base, CON,
173 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
174 enable_irq(host->irq);
178 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
180 if (host->pdata->slots[host->slot_id].get_cover_state)
181 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
186 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
189 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
190 struct mmc_omap_host *host = mmc_priv(mmc);
192 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
196 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
199 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
202 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
203 struct mmc_omap_host *host = mmc_priv(mmc);
204 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
206 return sprintf(buf, "slot:%s\n", slot.name);
209 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
212 * Configure the response type and send the cmd.
215 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
216 struct mmc_data *data)
218 int cmdreg = 0, resptype = 0, cmdtype = 0;
220 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
221 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
225 * Clear status bits and enable interrupts
227 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
228 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
229 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
231 if (cmd->flags & MMC_RSP_PRESENT) {
232 if (cmd->flags & MMC_RSP_136)
239 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
240 * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
242 if (cmd->opcode == 12)
245 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
248 cmdreg |= DP_SELECT | MSBS | BCE;
249 if (data->flags & MMC_DATA_READ)
258 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
259 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
263 * Notify the transfer complete to MMC core
266 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
270 if (host->use_dma && host->dma_ch != -1)
271 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
274 host->datadir = OMAP_MMC_DATADIR_NONE;
277 data->bytes_xfered += data->blocks * (data->blksz);
279 data->bytes_xfered = 0;
283 mmc_request_done(host->mmc, data->mrq);
286 mmc_omap_start_command(host, data->stop, NULL);
290 * Notify the core about command completion
293 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
297 if (cmd->flags & MMC_RSP_PRESENT) {
298 if (cmd->flags & MMC_RSP_136) {
299 /* response type 2 */
300 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
301 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
302 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
303 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
305 /* response types 1, 1b, 3, 4, 5, 6 */
306 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
309 if (host->data == NULL || cmd->error) {
311 mmc_request_done(host->mmc, cmd->mrq);
316 * DMA clean up for command errors
318 static void mmc_dma_cleanup(struct mmc_omap_host *host)
320 host->data->error = -ETIMEDOUT;
322 if (host->use_dma && host->dma_ch != -1) {
323 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
325 omap_free_dma(host->dma_ch);
330 host->datadir = OMAP_MMC_DATADIR_NONE;
334 * Readable error output
336 #ifdef CONFIG_MMC_DEBUG
337 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
339 /* --- means reserved bit without definition at documentation */
340 static const char *mmc_omap_status_bits[] = {
341 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
342 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
343 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
344 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
348 dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
350 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
351 if (status & (1 << i))
353 * KERN_* facility is not used here because this should
354 * print a single line.
356 printk(" %s", mmc_omap_status_bits[i]);
361 #endif /* CONFIG_MMC_DEBUG */
365 * MMC controller IRQ handler
367 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
369 struct mmc_omap_host *host = dev_id;
370 struct mmc_data *data;
371 int end_cmd = 0, end_trans = 0, status;
373 if (host->cmd == NULL && host->data == NULL) {
374 OMAP_HSMMC_WRITE(host->base, STAT,
375 OMAP_HSMMC_READ(host->base, STAT));
380 status = OMAP_HSMMC_READ(host->base, STAT);
381 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
384 #ifdef CONFIG_MMC_DEBUG
385 mmc_omap_report_irq(host, status);
387 if ((status & CMD_TIMEOUT) ||
388 (status & CMD_CRC)) {
390 if (status & CMD_TIMEOUT) {
391 OMAP_HSMMC_WRITE(host->base, SYSCTL,
392 OMAP_HSMMC_READ(host->base,
394 while (OMAP_HSMMC_READ(host->base,
396 host->cmd->error = -ETIMEDOUT;
398 host->cmd->error = -EILSEQ;
403 mmc_dma_cleanup(host);
405 if ((status & DATA_TIMEOUT) ||
406 (status & DATA_CRC)) {
408 if (status & DATA_TIMEOUT)
409 mmc_dma_cleanup(host);
411 host->data->error = -EILSEQ;
415 if (status & CARD_ERR) {
416 dev_dbg(mmc_dev(host->mmc),
417 "Ignoring card err CMD%d\n", host->cmd->opcode);
425 OMAP_HSMMC_WRITE(host->base, STAT, status);
427 if (end_cmd || (status & CC))
428 mmc_omap_cmd_done(host, host->cmd);
429 if (end_trans || (status & TC))
430 mmc_omap_xfer_done(host, data);
436 * Switch MMC operating voltage
438 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
443 /* Disable the clocks */
444 clk_disable(host->fclk);
445 clk_disable(host->iclk);
446 clk_disable(host->dbclk);
448 /* Turn the power off */
449 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
453 /* Turn the power ON with given VDD 1.8 or 3.0v */
454 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
458 clk_enable(host->fclk);
459 clk_enable(host->iclk);
460 clk_enable(host->dbclk);
462 OMAP_HSMMC_WRITE(host->base, HCTL,
463 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
464 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
466 * If a MMC dual voltage card is detected, the set_ios fn calls
467 * this fn with VDD bit set for 1.8V. Upon card removal from the
468 * slot, mmc_omap_detect fn sets the VDD back to 3V.
470 * Only MMC1 supports 3.0V. MMC2 will not function if SDVS30 is
473 if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
474 ((1 << vdd) == MMC_VDD_33_34)))
476 if ((1 << vdd) == MMC_VDD_165_195)
479 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
481 OMAP_HSMMC_WRITE(host->base, HCTL,
482 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
486 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
491 * Work Item to notify the core about card insertion/removal
493 static void mmc_omap_detect(struct work_struct *work)
496 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
497 mmc_carddetect_work);
499 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
500 if (host->carddetect) {
501 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
503 * Set the VDD back to 3V when the card is removed
504 * before the set_ios fn turns off the power.
506 vdd = fls(host->mmc->ocr_avail) - 1;
507 if (omap_mmc_switch_opcond(host, vdd) != 0)
508 host->mmc->ios.vdd = vdd;
510 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
512 OMAP_HSMMC_WRITE(host->base, SYSCTL,
513 OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
514 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
515 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
520 * ISR for handling card insertion and removal
522 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
524 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
526 host->carddetect = mmc_slot(host).card_detect(irq);
527 schedule_work(&host->mmc_carddetect_work);
533 * DMA call back function
535 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
537 struct mmc_omap_host *host = data;
539 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
540 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
542 if (host->dma_ch < 0)
545 omap_free_dma(host->dma_ch);
548 * DMA Callback: run in interrupt context.
549 * mutex_unlock will through a kernel warning if used.
555 * Configure dma src and destination parameters
557 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
558 struct mmc_data *data)
561 omap_set_dma_dest_params(host->dma_ch, 0,
562 OMAP_DMA_AMODE_CONSTANT,
563 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
564 omap_set_dma_src_params(host->dma_ch, 0,
565 OMAP_DMA_AMODE_POST_INC,
566 sg_dma_address(&data->sg[0]), 0, 0);
568 omap_set_dma_src_params(host->dma_ch, 0,
569 OMAP_DMA_AMODE_CONSTANT,
570 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
571 omap_set_dma_dest_params(host->dma_ch, 0,
572 OMAP_DMA_AMODE_POST_INC,
573 sg_dma_address(&data->sg[0]), 0, 0);
578 * Routine to configure and start DMA for the MMC card
581 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
583 int sync_dev, sync_dir = 0;
584 int dma_ch = 0, ret = 0, err = 1;
585 struct mmc_data *data = req->data;
588 * If for some reason the DMA transfer is still active,
589 * we wait for timeout period and free the dma
591 if (host->dma_ch != -1) {
592 set_current_state(TASK_UNINTERRUPTIBLE);
593 schedule_timeout(100);
594 if (down_trylock(&host->sem)) {
595 omap_free_dma(host->dma_ch);
601 if (down_trylock(&host->sem))
605 if (!(data->flags & MMC_DATA_WRITE)) {
606 host->dma_dir = DMA_FROM_DEVICE;
607 if (host->id == OMAP_MMC1_DEVID)
608 sync_dev = OMAP24XX_DMA_MMC1_RX;
610 sync_dev = OMAP24XX_DMA_MMC2_RX;
612 host->dma_dir = DMA_TO_DEVICE;
613 if (host->id == OMAP_MMC1_DEVID)
614 sync_dev = OMAP24XX_DMA_MMC1_TX;
616 sync_dev = OMAP24XX_DMA_MMC2_TX;
619 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
622 dev_dbg(mmc_dev(host->mmc),
623 "%s: omap_request_dma() failed with %d\n",
624 mmc_hostname(host->mmc), ret);
628 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
629 data->sg_len, host->dma_dir);
630 host->dma_ch = dma_ch;
632 if (!(data->flags & MMC_DATA_WRITE))
633 mmc_omap_config_dma_param(1, host, data);
635 mmc_omap_config_dma_param(0, host, data);
637 if ((data->blksz % 4) == 0)
638 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
639 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
642 /* REVISIT: The MMC buffer increments only when MSB is written.
643 * Return error for blksz which is non multiple of four.
647 omap_start_dma(dma_ch);
652 * Configure block length for MMC/SD cards and initiate the transfer.
655 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
658 host->data = req->data;
660 if (req->data == NULL) {
661 host->datadir = OMAP_MMC_DATADIR_NONE;
662 OMAP_HSMMC_WRITE(host->base, BLK, 0);
666 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
667 | (req->data->blocks << 16));
669 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
670 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
673 ret = mmc_omap_start_dma_transfer(host, req);
675 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
683 * Request function. for read/write operation
685 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
687 struct mmc_omap_host *host = mmc_priv(mmc);
689 WARN_ON(host->mrq != NULL);
691 mmc_omap_prepare_data(host, req);
692 mmc_omap_start_command(host, req->cmd, req->data);
696 /* Routine to configure clock values. Exposed API to core */
697 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
699 struct mmc_omap_host *host = mmc_priv(mmc);
701 unsigned long regval;
702 unsigned long timeout;
704 switch (ios->power_mode) {
706 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
709 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
713 switch (mmc->ios.bus_width) {
714 case MMC_BUS_WIDTH_4:
715 OMAP_HSMMC_WRITE(host->base, HCTL,
716 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
718 case MMC_BUS_WIDTH_1:
719 OMAP_HSMMC_WRITE(host->base, HCTL,
720 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
724 if (host->id == OMAP_MMC1_DEVID) {
725 /* Only MMC1 can operate at 3V/1.8V */
726 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
727 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
729 * The mmc_select_voltage fn of the core does
730 * not seem to set the power_mode to
731 * MMC_POWER_UP upon recalculating the voltage.
734 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
735 dev_dbg(mmc_dev(host->mmc),
736 "Switch operation failed\n");
741 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
745 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
751 omap_mmc_stop_clock(host);
752 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
753 regval = regval & ~(CLKD_MASK);
754 regval = regval | (dsor << 6) | (DTO << 16);
755 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
756 OMAP_HSMMC_WRITE(host->base, SYSCTL,
757 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
759 /* Wait till the ICS bit is set */
760 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
761 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
762 && time_before(jiffies, timeout))
765 OMAP_HSMMC_WRITE(host->base, SYSCTL,
766 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
768 if (ios->power_mode == MMC_POWER_ON)
769 send_init_stream(host);
771 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
772 OMAP_HSMMC_WRITE(host->base, CON,
773 OMAP_HSMMC_READ(host->base, CON) | OD);
775 /* NOTE: Read only switch not supported yet */
776 static struct mmc_host_ops mmc_omap_ops = {
777 .request = omap_mmc_request,
778 .set_ios = omap_mmc_set_ios,
781 static int __init omap_mmc_probe(struct platform_device *pdev)
783 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
784 struct mmc_host *mmc;
785 struct mmc_omap_host *host = NULL;
786 struct resource *res;
791 dev_err(&pdev->dev, "Platform Data is missing\n");
795 if (pdata->nr_slots == 0) {
796 dev_err(&pdev->dev, "No Slots\n");
800 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801 irq = platform_get_irq(pdev, 0);
802 if (res == NULL || irq < 0)
805 res = request_mem_region(res->start, res->end - res->start + 1,
810 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
816 host = mmc_priv(mmc);
824 host->mapbase = res->start;
825 host->base = ioremap(host->mapbase, SZ_4K);
826 mmc->ops = &mmc_omap_ops;
828 mmc->f_max = 52000000;
830 sema_init(&host->sem, 1);
832 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
833 if (IS_ERR(host->iclk)) {
834 ret = PTR_ERR(host->iclk);
838 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
839 if (IS_ERR(host->fclk)) {
840 ret = PTR_ERR(host->fclk);
846 if (clk_enable(host->fclk) != 0) {
852 if (clk_enable(host->iclk) != 0) {
853 clk_disable(host->fclk);
859 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
861 * MMC can still work without debounce clock.
863 if (IS_ERR(host->dbclk))
864 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
866 if (clk_enable(host->dbclk) != 0)
867 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
870 host->dbclk_enabled = 1;
872 #ifdef CONFIG_MMC_BLOCK_BOUNCE
873 mmc->max_phys_segs = 1;
874 mmc->max_hw_segs = 1;
876 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
877 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
878 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
879 mmc->max_seg_size = mmc->max_req_size;
881 mmc->ocr_avail = mmc_slot(host).ocr_mask;
882 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
884 if (pdata->slots[host->slot_id].wire4)
885 mmc->caps |= MMC_CAP_4_BIT_DATA;
887 /* Only MMC1 supports 3.0V */
888 if (host->id == OMAP_MMC1_DEVID) {
896 OMAP_HSMMC_WRITE(host->base, HCTL,
897 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
899 OMAP_HSMMC_WRITE(host->base, CAPA,
900 OMAP_HSMMC_READ(host->base, CAPA) | capa);
902 /* Set the controller to AUTO IDLE mode */
903 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
904 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
906 /* Set SD bus power bit */
907 OMAP_HSMMC_WRITE(host->base, HCTL,
908 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
910 /* Request IRQ for MMC operations */
911 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name,
914 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
918 /* Request IRQ for card detect */
919 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
920 ret = request_irq(mmc_slot(host).card_detect_irq,
921 omap_mmc_cd_handler, IRQF_DISABLED, "MMC CD",
924 dev_dbg(mmc_dev(host->mmc),
925 "Unable to grab MMC CD IRQ\n");
930 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
931 if (pdata->init != NULL) {
932 if (pdata->init(&pdev->dev) != 0) {
933 dev_dbg(mmc_dev(host->mmc),
934 "Unable to configure MMC IRQs\n");
935 goto err_irq_cd_init;
939 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
940 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
942 platform_set_drvdata(pdev, host);
945 if (host->pdata->slots[host->slot_id].name != NULL) {
946 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
950 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
951 host->pdata->slots[host->slot_id].get_cover_state) {
952 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
954 goto err_cover_switch;
960 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
962 mmc_remove_host(mmc);
964 free_irq(mmc_slot(host).card_detect_irq, host);
966 free_irq(host->irq, host);
968 clk_disable(host->fclk);
969 clk_disable(host->iclk);
972 if (host->dbclk_enabled) {
973 clk_disable(host->dbclk);
974 clk_put(host->dbclk);
980 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
981 release_mem_region(res->start, res->end - res->start + 1);
987 static int omap_mmc_remove(struct platform_device *pdev)
989 struct mmc_omap_host *host = platform_get_drvdata(pdev);
990 struct resource *res;
993 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
995 * Set the vdd back to 3V,
996 * applicable for dual volt support.
998 vdd = fls(host->mmc->ocr_avail) - 1;
999 if (omap_mmc_switch_opcond(host, vdd) != 0)
1000 host->mmc->ios.vdd = vdd;
1003 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1005 release_mem_region(res->start, res->end - res->start + 1);
1007 platform_set_drvdata(pdev, NULL);
1009 mmc_remove_host(host->mmc);
1010 if (host->pdata->cleanup)
1011 host->pdata->cleanup(&pdev->dev);
1012 free_irq(host->irq, host);
1013 if (mmc_slot(host).card_detect_irq)
1014 free_irq(mmc_slot(host).card_detect_irq, host);
1015 flush_scheduled_work();
1017 clk_disable(host->fclk);
1018 clk_disable(host->iclk);
1019 clk_put(host->fclk);
1020 clk_put(host->iclk);
1021 if (host->dbclk_enabled) {
1022 clk_disable(host->dbclk);
1023 clk_put(host->dbclk);
1026 mmc_free_host(host->mmc);
1027 iounmap(host->base);
1034 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1037 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1039 if (host && host->suspended)
1043 ret = mmc_suspend_host(host->mmc, state);
1045 host->suspended = 1;
1047 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1048 OMAP_HSMMC_WRITE(host->base, IE, 0);
1050 if (host->pdata->suspend) {
1051 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1053 dev_dbg(mmc_dev(host->mmc),
1054 "Unable to handle MMC board"
1055 " level suspend\n");
1058 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1059 OMAP_HSMMC_WRITE(host->base, HCTL,
1060 OMAP_HSMMC_READ(host->base, HCTL)
1062 OMAP_HSMMC_WRITE(host->base, HCTL,
1063 OMAP_HSMMC_READ(host->base, HCTL)
1065 OMAP_HSMMC_WRITE(host->base, HCTL,
1066 OMAP_HSMMC_READ(host->base, HCTL)
1070 clk_disable(host->fclk);
1071 clk_disable(host->iclk);
1072 clk_disable(host->dbclk);
1079 /* Routine to resume the MMC device */
1080 static int omap_mmc_resume(struct platform_device *pdev)
1083 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1085 if (host && !host->suspended)
1090 ret = clk_enable(host->fclk);
1094 ret = clk_enable(host->iclk);
1096 clk_disable(host->fclk);
1097 clk_put(host->fclk);
1101 if (clk_enable(host->dbclk) != 0)
1102 dev_dbg(mmc_dev(host->mmc),
1103 "Enabling debounce clk failed\n");
1105 if (host->pdata->resume) {
1106 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1108 dev_dbg(mmc_dev(host->mmc),
1109 "Unmask interrupt failed\n");
1112 /* Notify the core to resume the host */
1113 ret = mmc_resume_host(host->mmc);
1115 host->suspended = 0;
1121 dev_dbg(mmc_dev(host->mmc),
1122 "Failed to enable MMC clocks during resume\n");
1127 #define omap_mmc_suspend NULL
1128 #define omap_mmc_resume NULL
1131 static struct platform_driver omap_mmc_driver = {
1132 .probe = omap_mmc_probe,
1133 .remove = omap_mmc_remove,
1134 .suspend = omap_mmc_suspend,
1135 .resume = omap_mmc_resume,
1137 .name = DRIVER_NAME,
1138 .owner = THIS_MODULE,
1142 static int __init omap_mmc_init(void)
1144 /* Register the MMC driver */
1145 return platform_driver_register(&omap_mmc_driver);
1148 static void __exit omap_mmc_cleanup(void)
1150 /* Unregister MMC driver */
1151 platform_driver_unregister(&omap_mmc_driver);
1154 module_init(omap_mmc_init);
1155 module_exit(omap_mmc_cleanup);
1157 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1158 MODULE_LICENSE("GPL");
1159 MODULE_ALIAS("platform:" DRIVER_NAME);
1160 MODULE_AUTHOR("Texas Instruments Inc");