drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1<<26)
  55 #define VS30                    (1<<25)
  56 #define SDVS18                  (0x5<<9)
  57 #define SDVS30                  (0x6<<9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1<<8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1<<2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define INT_EN_MASK             0x307F0033
  68 #define INIT_STREAM             (1<<1)
  69 #define DP_SELECT               (1<<21)
  70 #define DDIR                    (1<<4)
  71 #define DMA_EN                  0x1
  72 #define MSBS                    1<<5
  73 #define BCE                     1<<1
  74 #define FOUR_BIT                1 << 1
  75 #define CC                      0x1
  76 #define TC                      0x02
  77 #define OD                      0x1
  78 #define ERR                     (1 << 15)
  79 #define CMD_TIMEOUT             (1 << 16)
  80 #define DATA_TIMEOUT            (1 << 20)
  81 #define CMD_CRC                 (1 << 17)
  82 #define DATA_CRC                (1 << 21)
  83 #define CARD_ERR                (1 << 28)
  84 #define STAT_CLEAR              0xFFFFFFFF
  85 #define INIT_STREAM_CMD         0x00000000
  86 #define DUAL_VOLT_OCR_BIT       7
  87 #define SRC                     (1 << 25)
  88 #define SRD                     (1 << 26)
  89
  90 #define OMAP_MMC1_DEVID         1
  91 #define OMAP_MMC2_DEVID         2
  92 #define OMAP_MMC_DATADIR_NONE   0
  93 #define OMAP_MMC_DATADIR_READ   1
  94 #define OMAP_MMC_DATADIR_WRITE  2
  95 #define MMC_TIMEOUT_MS          20
  96 #define OMAP_MMC_MASTER_CLOCK   96000000
  97 #define DRIVER_NAME             "mmci-omap"
  98 /*
  99  * slot_id is device id - 1, device id is a static value
 100  * of 1 to represent device 1 etc..
 101  */
 102 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 103
 104 /*
 105  * MMC Host controller read/write API's
 106  */
 107 #define OMAP_HSMMC_READ(base, reg)      \
 108         __raw_readl((base) + OMAP_HSMMC_##reg)
 109
 110 #define OMAP_HSMMC_WRITE(base, reg, val) \
 111         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 112
 113 struct mmc_omap_host {
 114         struct  device          *dev;
 115         struct  mmc_host        *mmc;
 116         struct  mmc_request     *mrq;
 117         struct  mmc_command     *cmd;
 118         struct  mmc_data        *data;
 119         struct  clk             *fclk;
 120         struct  clk             *iclk;
 121         struct  clk             *dbclk;
 122         struct  semaphore       sem;
 123         struct  work_struct     mmc_carddetect_work;
 124         void    __iomem         *base;
 125         resource_size_t         mapbase;
 126         unsigned int            id;
 127         unsigned int            dma_len;
 128         unsigned int            dma_dir;
 129         unsigned char           bus_mode;
 130         unsigned char           datadir;
 131         u32                     *buffer;
 132         u32                     bytesleft;
 133         int                     suspended;
 134         int                     irq;
 135         int                     carddetect;
 136         int                     use_dma, dma_ch;
 137         int                     initstr;
 138         int                     slot_id;
 139         int                     dbclk_enabled;
 140         struct  omap_mmc_platform_data  *pdata;
 141 };
 142
 143 /*
 144  * Stop clock to the card
 145  */
 146 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 147 {
 148         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 149                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 150         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 151                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 152 }
 153
 154 /*
 155  * Send init stream sequence to card
 156  * before sending IDLE command
 157  */
 158 static void send_init_stream(struct mmc_omap_host *host)
 159 {
 160         int reg = 0;
 161         unsigned long timeout;
 162
 163         disable_irq(host->irq);
 164         OMAP_HSMMC_WRITE(host->base, CON,
 165                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 166         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 167
 168         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 169         while ((reg != CC) && time_before(jiffies, timeout))
 170                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 171
 172         OMAP_HSMMC_WRITE(host->base, CON,
 173                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 174         enable_irq(host->irq);
 175 }
 176
 177 static ssize_t
 178 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 179                         char *buf)
 180 {
 181         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 182         struct mmc_omap_host *host = mmc_priv(mmc);
 183         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 184
 185         return sprintf(buf, "slot:%s\n", slot.name);
 186 }
 187
 188 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 189
 190 /*
 191  * Configure the response type and send the cmd.
 192  */
 193 static void
 194 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 195         struct mmc_data *data)
 196 {
 197         int cmdreg = 0, resptype = 0, cmdtype = 0;
 198
 199         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 200                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 201         host->cmd = cmd;
 202
 203         /*
 204          * Clear status bits and enable interrupts
 205          */
 206         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 207         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 208         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 209
 210         if (cmd->flags & MMC_RSP_PRESENT) {
 211                 if (cmd->flags & MMC_RSP_136)
 212                         resptype = 1;
 213                 else
 214                         resptype = 2;
 215         }
 216
 217         /*
 218          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 219          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 220          */
 221         if (cmd->opcode == 12)
 222                 cmdtype = 0x3;
 223
 224         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 225
 226         if (data) {
 227                 cmdreg |= DP_SELECT | MSBS | BCE;
 228                 if (data->flags & MMC_DATA_READ)
 229                         cmdreg |= DDIR;
 230                 else
 231                         cmdreg &= ~(DDIR);
 232         }
 233
 234         if (host->use_dma)
 235                 cmdreg |= DMA_EN;
 236
 237         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 238         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 239 }
 240
 241 /*
 242  * Notify the transfer complete to MMC core
 243  */
 244 static void
 245 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 246 {
 247         host->data = NULL;
 248
 249         if (host->use_dma && host->dma_ch != -1)
 250                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 251                         host->dma_dir);
 252
 253         host->datadir = OMAP_MMC_DATADIR_NONE;
 254
 255         if (!data->error)
 256                 data->bytes_xfered += data->blocks * (data->blksz);
 257         else
 258                 data->bytes_xfered = 0;
 259
 260         if (!data->stop) {
 261                 host->mrq = NULL;
 262                 mmc_request_done(host->mmc, data->mrq);
 263                 return;
 264         }
 265         mmc_omap_start_command(host, data->stop, NULL);
 266 }
 267
 268 /*
 269  * Notify the core about command completion
 270  */
 271 static void
 272 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 273 {
 274         host->cmd = NULL;
 275
 276         if (cmd->flags & MMC_RSP_PRESENT) {
 277                 if (cmd->flags & MMC_RSP_136) {
 278                         /* response type 2 */
 279                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 280                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 281                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 282                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 283                 } else {
 284                         /* response types 1, 1b, 3, 4, 5, 6 */
 285                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 286                 }
 287         }
 288         if (host->data == NULL || cmd->error) {
 289                 host->mrq = NULL;
 290                 mmc_request_done(host->mmc, cmd->mrq);
 291         }
 292 }
 293
 294 /*
 295  * DMA clean up for command errors
 296  */
 297 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 298 {
 299         host->data->error = -ETIMEDOUT;
 300
 301         if (host->use_dma && host->dma_ch != -1) {
 302                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 303                         host->dma_dir);
 304                 omap_free_dma(host->dma_ch);
 305                 host->dma_ch = -1;
 306                 up(&host->sem);
 307         }
 308         host->data = NULL;
 309         host->datadir = OMAP_MMC_DATADIR_NONE;
 310 }
 311
 312 /*
 313  * Readable error output
 314  */
 315 #ifdef CONFIG_MMC_DEBUG
 316 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 317 {
 318         /* --- means reserved bit without definition at documentation */
 319         static const char *mmc_omap_status_bits[] = {
 320                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 321                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 322                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 323                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 324         };
 325         int i;
 326
 327         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 328
 329         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 330                 if (status & (1 << i))
 331                         /*
 332                          * KERN_* facility is not used here because this should
 333                          * print a single line.
 334                          */
 335                         printk(" %s", mmc_omap_status_bits[i]);
 336
 337         printk("\n");
 338
 339 }
 340 #endif  /* CONFIG_MMC_DEBUG */
 341
 342
 343 /*
 344  * MMC controller IRQ handler
 345  */
 346 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 347 {
 348         struct mmc_omap_host *host = dev_id;
 349         struct mmc_data *data;
 350         int end_cmd = 0, end_trans = 0, status;
 351
 352         if (host->cmd == NULL && host->data == NULL) {
 353                 OMAP_HSMMC_WRITE(host->base, STAT,
 354                         OMAP_HSMMC_READ(host->base, STAT));
 355                 return IRQ_HANDLED;
 356         }
 357
 358         data = host->data;
 359         status = OMAP_HSMMC_READ(host->base, STAT);
 360         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 361
 362         if (status & ERR) {
 363 #ifdef CONFIG_MMC_DEBUG
 364                 mmc_omap_report_irq(host, status);
 365 #endif
 366                 if ((status & CMD_TIMEOUT) ||
 367                         (status & CMD_CRC)) {
 368                         if (host->cmd) {
 369                                 if (status & CMD_TIMEOUT) {
 370                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 371                                                 OMAP_HSMMC_READ(host->base,
 372                                                                 SYSCTL) | SRC);
 373                                         while (OMAP_HSMMC_READ(host->base,
 374                                                                 SYSCTL) & SRC) ;
 375                                         host->cmd->error = -ETIMEDOUT;
 376                                 } else {
 377                                         host->cmd->error = -EILSEQ;
 378                                 }
 379                                 end_cmd = 1;
 380                         }
 381                         if (host->data)
 382                                 mmc_dma_cleanup(host);
 383                 }
 384                 if ((status & DATA_TIMEOUT) ||
 385                         (status & DATA_CRC)) {
 386                         if (host->data) {
 387                                 if (status & DATA_TIMEOUT)
 388                                         mmc_dma_cleanup(host);
 389                                 else
 390                                         host->data->error = -EILSEQ;
 391                                 end_trans = 1;
 392                         }
 393                 }
 394                 if (status & CARD_ERR) {
 395                         dev_dbg(mmc_dev(host->mmc),
 396                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 397                         if (host->cmd)
 398                                 end_cmd = 1;
 399                         if (host->data)
 400                                 end_trans = 1;
 401                 }
 402         }
 403
 404         OMAP_HSMMC_WRITE(host->base, STAT, status);
 405
 406         if (end_cmd || (status & CC))
 407                 mmc_omap_cmd_done(host, host->cmd);
 408         if (end_trans || (status & TC))
 409                 mmc_omap_xfer_done(host, data);
 410
 411         return IRQ_HANDLED;
 412 }
 413
 414 /*
 415  * Switch MMC operating voltage
 416  */
 417 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 418 {
 419         u32 reg_val = 0;
 420         int ret;
 421
 422         /* Disable the clocks */
 423         clk_disable(host->fclk);
 424         clk_disable(host->iclk);
 425         clk_disable(host->dbclk);
 426
 427         /* Turn the power off */
 428         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 429         if (ret != 0)
 430                 goto err;
 431
 432         /* Turn the power ON with given VDD 1.8 or 3.0v */
 433         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 434         if (ret != 0)
 435                 goto err;
 436
 437         clk_enable(host->fclk);
 438         clk_enable(host->iclk);
 439         clk_enable(host->dbclk);
 440
 441         OMAP_HSMMC_WRITE(host->base, HCTL,
 442                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 443         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 444         /*
 445          * If a MMC dual voltage card is detected, the set_ios fn calls
 446          * this fn with VDD bit set for 1.8V. Upon card removal from the
 447          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 448          *
 449          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 450          * set in HCTL.
 451          */
 452         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 453                                 ((1 << vdd) == MMC_VDD_33_34)))
 454                 reg_val |= SDVS30;
 455         if ((1 << vdd) == MMC_VDD_165_195)
 456                 reg_val |= SDVS18;
 457
 458         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 459
 460         OMAP_HSMMC_WRITE(host->base, HCTL,
 461                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 462
 463         return 0;
 464 err:
 465         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 466         return ret;
 467 }
 468
 469 /*
 470  * Work Item to notify the core about card insertion/removal
 471  */
 472 static void mmc_omap_detect(struct work_struct *work)
 473 {
 474         u16 vdd = 0;
 475         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 476                                                 mmc_carddetect_work);
 477
 478         if (host->carddetect) {
 479                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 480                         /*
 481                          * Set the VDD back to 3V when the card is removed
 482                          * before the set_ios fn turns off the power.
 483                          */
 484                         vdd = fls(host->mmc->ocr_avail) - 1;
 485                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 486                                 host->mmc->ios.vdd = vdd;
 487                 }
 488                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 489         } else {
 490                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 491                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 492                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 493                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 494         }
 495 }
 496
 497 /*
 498  * ISR for handling card insertion and removal
 499  */
 500 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 501 {
 502         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 503
 504         host->carddetect = mmc_slot(host).card_detect(irq);
 505         schedule_work(&host->mmc_carddetect_work);
 506
 507         return IRQ_HANDLED;
 508 }
 509
 510 /*
 511  * DMA call back function
 512  */
 513 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 514 {
 515         struct mmc_omap_host *host = data;
 516
 517         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 518                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 519
 520         if (host->dma_ch < 0)
 521                 return;
 522
 523         omap_free_dma(host->dma_ch);
 524         host->dma_ch = -1;
 525         /*
 526          * DMA Callback: run in interrupt context.
 527          * mutex_unlock will through a kernel warning if used.
 528          */
 529         up(&host->sem);
 530 }
 531
 532 /*
 533  * Configure dma src and destination parameters
 534  */
 535 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 536                                 struct mmc_data *data)
 537 {
 538         if (sync_dir == 0) {
 539                 omap_set_dma_dest_params(host->dma_ch, 0,
 540                         OMAP_DMA_AMODE_CONSTANT,
 541                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 542                 omap_set_dma_src_params(host->dma_ch, 0,
 543                         OMAP_DMA_AMODE_POST_INC,
 544                         sg_dma_address(&data->sg[0]), 0, 0);
 545         } else {
 546                 omap_set_dma_src_params(host->dma_ch, 0,
 547                         OMAP_DMA_AMODE_CONSTANT,
 548                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 549                 omap_set_dma_dest_params(host->dma_ch, 0,
 550                         OMAP_DMA_AMODE_POST_INC,
 551                         sg_dma_address(&data->sg[0]), 0, 0);
 552         }
 553         return 0;
 554 }
 555 /*
 556  * Routine to configure and start DMA for the MMC card
 557  */
 558 static int
 559 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 560 {
 561         int sync_dev, sync_dir = 0;
 562         int dma_ch = 0, ret = 0, err = 1;
 563         struct mmc_data *data = req->data;
 564
 565         /*
 566          * If for some reason the DMA transfer is still active,
 567          * we wait for timeout period and free the dma
 568          */
 569         if (host->dma_ch != -1) {
 570                 set_current_state(TASK_UNINTERRUPTIBLE);
 571                 schedule_timeout(100);
 572                 if (down_trylock(&host->sem)) {
 573                         omap_free_dma(host->dma_ch);
 574                         host->dma_ch = -1;
 575                         up(&host->sem);
 576                         return err;
 577                 }
 578         } else {
 579                 if (down_trylock(&host->sem))
 580                         return err;
 581         }
 582
 583         if (!(data->flags & MMC_DATA_WRITE)) {
 584                 host->dma_dir = DMA_FROM_DEVICE;
 585                 if (host->id == OMAP_MMC1_DEVID)
 586                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 587                 else
 588                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 589         } else {
 590                 host->dma_dir = DMA_TO_DEVICE;
 591                 if (host->id == OMAP_MMC1_DEVID)
 592                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 593                 else
 594                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 595         }
 596
 597         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 598                         host, &dma_ch);
 599         if (ret != 0) {
 600                 dev_dbg(mmc_dev(host->mmc),
 601                         "%s: omap_request_dma() failed with %d\n",
 602                         mmc_hostname(host->mmc), ret);
 603                 return ret;
 604         }
 605
 606         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 607                         data->sg_len, host->dma_dir);
 608         host->dma_ch = dma_ch;
 609
 610         if (!(data->flags & MMC_DATA_WRITE))
 611                 mmc_omap_config_dma_param(1, host, data);
 612         else
 613                 mmc_omap_config_dma_param(0, host, data);
 614
 615         if ((data->blksz % 4) == 0)
 616                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 617                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 618                         sync_dev, sync_dir);
 619         else
 620                 /* REVISIT: The MMC buffer increments only when MSB is written.
 621                  * Return error for blksz which is non multiple of four.
 622                  */
 623                 return -EINVAL;
 624
 625         omap_start_dma(dma_ch);
 626         return 0;
 627 }
 628
 629 /*
 630  * Configure block length for MMC/SD cards and initiate the transfer.
 631  */
 632 static int
 633 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 634 {
 635         int ret;
 636         host->data = req->data;
 637
 638         if (req->data == NULL) {
 639                 host->datadir = OMAP_MMC_DATADIR_NONE;
 640                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 641                 return 0;
 642         }
 643
 644         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 645                                         | (req->data->blocks << 16));
 646
 647         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 648                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 649
 650         if (host->use_dma) {
 651                 ret = mmc_omap_start_dma_transfer(host, req);
 652                 if (ret != 0) {
 653                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 654                         return ret;
 655                 }
 656         }
 657         return 0;
 658 }
 659
 660 /*
 661  * Request function. for read/write operation
 662  */
 663 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 664 {
 665         struct mmc_omap_host *host = mmc_priv(mmc);
 666
 667         WARN_ON(host->mrq != NULL);
 668         host->mrq = req;
 669         mmc_omap_prepare_data(host, req);
 670         mmc_omap_start_command(host, req->cmd, req->data);
 671 }
 672
 673
 674 /* Routine to configure clock values. Exposed API to core */
 675 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 676 {
 677         struct mmc_omap_host *host = mmc_priv(mmc);
 678         u16 dsor = 0;
 679         unsigned long regval;
 680         unsigned long timeout;
 681
 682         switch (ios->power_mode) {
 683         case MMC_POWER_OFF:
 684                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 685                 break;
 686         case MMC_POWER_UP:
 687                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 688                 break;
 689         }
 690
 691         switch (mmc->ios.bus_width) {
 692         case MMC_BUS_WIDTH_4:
 693                 OMAP_HSMMC_WRITE(host->base, HCTL,
 694                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 695                 break;
 696         case MMC_BUS_WIDTH_1:
 697                 OMAP_HSMMC_WRITE(host->base, HCTL,
 698                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 699                 break;
 700         }
 701
 702         if (host->id == OMAP_MMC1_DEVID) {
 703                 /* Only MMC1 can operate at 3V/1.8V */
 704                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 705                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 706                                 /*
 707                                  * The mmc_select_voltage fn of the core does
 708                                  * not seem to set the power_mode to
 709                                  * MMC_POWER_UP upon recalculating the voltage.
 710                                  * vdd 1.8v.
 711                                  */
 712                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 713                                         dev_dbg(mmc_dev(host->mmc),
 714                                                 "Switch operation failed\n");
 715                 }
 716         }
 717
 718         if (ios->clock) {
 719                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 720                 if (dsor < 1)
 721                         dsor = 1;
 722
 723                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 724                         dsor++;
 725
 726                 if (dsor > 250)
 727                         dsor = 250;
 728         }
 729         omap_mmc_stop_clock(host);
 730         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 731         regval = regval & ~(CLKD_MASK);
 732         regval = regval | (dsor << 6) | (DTO << 16);
 733         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 734         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 735                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 736
 737         /* Wait till the ICS bit is set */
 738         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 739         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 740                 && time_before(jiffies, timeout))
 741                 msleep(1);
 742
 743         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 744                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 745
 746         if (ios->power_mode == MMC_POWER_ON)
 747                 send_init_stream(host);
 748
 749         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 750                 OMAP_HSMMC_WRITE(host->base, CON,
 751                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 752 }
 753 /* NOTE: Read only switch not supported yet */
 754 static struct mmc_host_ops mmc_omap_ops = {
 755         .request = omap_mmc_request,
 756         .set_ios = omap_mmc_set_ios,
 757 };
 758
 759 static int __init omap_mmc_probe(struct platform_device *pdev)
 760 {
 761         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 762         struct mmc_host *mmc;
 763         struct mmc_omap_host *host = NULL;
 764         struct resource *res;
 765         int ret = 0, irq;
 766         u32 hctl, capa;
 767
 768         if (pdata == NULL) {
 769                 dev_err(&pdev->dev, "Platform Data is missing\n");
 770                 return -ENXIO;
 771         }
 772
 773         if (pdata->nr_slots == 0) {
 774                 dev_err(&pdev->dev, "No Slots\n");
 775                 return -ENXIO;
 776         }
 777
 778         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 779         irq = platform_get_irq(pdev, 0);
 780         if (res == NULL || irq < 0)
 781                 return -ENXIO;
 782
 783         res = request_mem_region(res->start, res->end - res->start + 1,
 784                                                         pdev->name);
 785         if (res == NULL)
 786                 return -EBUSY;
 787
 788         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 789         if (!mmc) {
 790                 ret = -ENOMEM;
 791                 goto err;
 792         }
 793
 794         host            = mmc_priv(mmc);
 795         host->mmc       = mmc;
 796         host->pdata     = pdata;
 797         host->use_dma   = 1;
 798         host->dma_ch    = -1;
 799         host->irq       = irq;
 800         host->id        = pdev->id;
 801         host->slot_id   = 0;
 802         host->mapbase   = res->start;
 803         host->base      = ioremap(host->mapbase, SZ_4K);
 804         mmc->ops        = &mmc_omap_ops;
 805         mmc->f_min      = 400000;
 806         mmc->f_max      = 52000000;
 807
 808         sema_init(&host->sem, 1);
 809
 810         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 811         if (IS_ERR(host->iclk)) {
 812                 ret = PTR_ERR(host->iclk);
 813                 host->iclk = NULL;
 814                 goto err1;
 815         }
 816         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 817         if (IS_ERR(host->fclk)) {
 818                 ret = PTR_ERR(host->fclk);
 819                 host->fclk = NULL;
 820                 clk_put(host->iclk);
 821                 goto err1;
 822         }
 823
 824         if (clk_enable(host->fclk) != 0) {
 825                 clk_put(host->iclk);
 826                 clk_put(host->fclk);
 827                 goto err1;
 828         }
 829
 830         if (clk_enable(host->iclk) != 0) {
 831                 clk_disable(host->fclk);
 832                 clk_put(host->iclk);
 833                 clk_put(host->fclk);
 834                 goto err1;
 835         }
 836
 837         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 838         /*
 839          * MMC can still work without debounce clock.
 840          */
 841         if (IS_ERR(host->dbclk))
 842                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 843         else
 844                 if (clk_enable(host->dbclk) != 0)
 845                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 846                                                         " clk failed\n");
 847                 else
 848                         host->dbclk_enabled = 1;
 849
 850 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 851         mmc->max_phys_segs = 1;
 852         mmc->max_hw_segs = 1;
 853 #endif
 854         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 855         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 856         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 857         mmc->max_seg_size = mmc->max_req_size;
 858
 859         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 860         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
 861
 862         if (pdata->conf.wire4)
 863                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 864
 865         /* Only MMC1 supports 3.0V */
 866         if (host->id == OMAP_MMC1_DEVID) {
 867                 hctl = SDVS30;
 868                 capa = VS30 | VS18;
 869         } else {
 870                 hctl = SDVS18;
 871                 capa = VS18;
 872         }
 873
 874         OMAP_HSMMC_WRITE(host->base, HCTL,
 875                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 876
 877         OMAP_HSMMC_WRITE(host->base, CAPA,
 878                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 879
 880         /* Set the controller to AUTO IDLE mode */
 881         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 882                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 883
 884         /* Set SD bus power bit */
 885         OMAP_HSMMC_WRITE(host->base, HCTL,
 886                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 887
 888         /* Request IRQ for MMC operations */
 889         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name,
 890                          host);
 891         if (ret) {
 892                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
 893                 goto err_irq;
 894         }
 895
 896         /* Request IRQ for card detect */
 897         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
 898                 ret = request_irq(mmc_slot(host).card_detect_irq,
 899                                   omap_mmc_cd_handler, IRQF_DISABLED, "MMC CD",
 900                                   host);
 901                 if (ret) {
 902                         dev_dbg(mmc_dev(host->mmc),
 903                                 "Unable to grab MMC CD IRQ\n");
 904                         goto err_irq_cd;
 905                 }
 906         }
 907
 908         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 909         if (pdata->init != NULL) {
 910                 if (pdata->init(&pdev->dev) != 0) {
 911                         dev_dbg(mmc_dev(host->mmc),
 912                                 "Unable to configure MMC IRQs\n");
 913                         goto err_irq_cd_init;
 914                 }
 915         }
 916
 917         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 918         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 919
 920         platform_set_drvdata(pdev, host);
 921         mmc_add_host(mmc);
 922
 923         if (host->pdata->slots[host->slot_id].name != NULL) {
 924                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
 925                 if (ret < 0)
 926                         goto err_slot_name;
 927         }
 928
 929         return 0;
 930
 931 err_slot_name:
 932         mmc_remove_host(mmc);
 933 err_irq_cd_init:
 934         free_irq(mmc_slot(host).card_detect_irq, host);
 935 err_irq_cd:
 936         free_irq(host->irq, host);
 937 err_irq:
 938         clk_disable(host->fclk);
 939         clk_disable(host->iclk);
 940         clk_put(host->fclk);
 941         clk_put(host->iclk);
 942         if (host->dbclk_enabled) {
 943                 clk_disable(host->dbclk);
 944                 clk_put(host->dbclk);
 945         }
 946
 947 err1:
 948         iounmap(host->base);
 949 err:
 950         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
 951         release_mem_region(res->start, res->end - res->start + 1);
 952         if (host)
 953                 mmc_free_host(mmc);
 954         return ret;
 955 }
 956
 957 static int omap_mmc_remove(struct platform_device *pdev)
 958 {
 959         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 960         struct resource *res;
 961         u16 vdd = 0;
 962
 963         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 964         /*
 965          * Set the vdd back to 3V,
 966          * applicable for dual volt support.
 967          */
 968                 vdd = fls(host->mmc->ocr_avail) - 1;
 969                 if (omap_mmc_switch_opcond(host, vdd) != 0)
 970                         host->mmc->ios.vdd = vdd;
 971         }
 972
 973         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 974         if (res)
 975                 release_mem_region(res->start, res->end - res->start + 1);
 976
 977         platform_set_drvdata(pdev, NULL);
 978         if (host) {
 979                 mmc_remove_host(host->mmc);
 980                 if (host->pdata->cleanup)
 981                         host->pdata->cleanup(&pdev->dev);
 982                 free_irq(host->irq, host);
 983                 if (mmc_slot(host).card_detect_irq)
 984                         free_irq(mmc_slot(host).card_detect_irq, host);
 985                 flush_scheduled_work();
 986
 987                 clk_disable(host->fclk);
 988                 clk_disable(host->iclk);
 989                 clk_put(host->fclk);
 990                 clk_put(host->iclk);
 991                 if (host->dbclk_enabled) {
 992                         clk_disable(host->dbclk);
 993                         clk_put(host->dbclk);
 994                 }
 995
 996                 mmc_free_host(host->mmc);
 997                 iounmap(host->base);
 998         }
 999
1000         return 0;
1001 }
1002
1003 #ifdef CONFIG_PM
1004 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1005 {
1006         int ret = 0;
1007         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1008
1009         if (host && host->suspended)
1010                 return 0;
1011
1012         if (host) {
1013                 ret = mmc_suspend_host(host->mmc, state);
1014                 if (ret == 0) {
1015                         host->suspended = 1;
1016
1017                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1018                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1019
1020                         if (host->pdata->suspend) {
1021                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1022                                 if (ret)
1023                                         dev_dbg(mmc_dev(host->mmc),
1024                                                 "Unable to handle MMC board"
1025                                                 " level suspend\n");
1026                         }
1027
1028                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1029                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1030                                         OMAP_HSMMC_READ(host->base, HCTL)
1031                                         & SDVSCLR);
1032                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1033                                         OMAP_HSMMC_READ(host->base, HCTL)
1034                                         | SDVS30);
1035                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1036                                         OMAP_HSMMC_READ(host->base, HCTL)
1037                                         | SDBP);
1038                         }
1039
1040                         clk_disable(host->fclk);
1041                         clk_disable(host->iclk);
1042                         clk_disable(host->dbclk);
1043                 }
1044
1045         }
1046         return ret;
1047 }
1048
1049 /* Routine to resume the MMC device */
1050 static int omap_mmc_resume(struct platform_device *pdev)
1051 {
1052         int ret = 0;
1053         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1054
1055         if (host && !host->suspended)
1056                 return 0;
1057
1058         if (host) {
1059
1060                 ret = clk_enable(host->fclk);
1061                 if (ret)
1062                         goto clk_en_err;
1063
1064                 ret = clk_enable(host->iclk);
1065                 if (ret) {
1066                         clk_disable(host->fclk);
1067                         clk_put(host->fclk);
1068                         goto clk_en_err;
1069                 }
1070
1071                 if (clk_enable(host->dbclk) != 0)
1072                         dev_dbg(mmc_dev(host->mmc),
1073                                         "Enabling debounce clk failed\n");
1074
1075                 if (host->pdata->resume) {
1076                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1077                         if (ret)
1078                                 dev_dbg(mmc_dev(host->mmc),
1079                                         "Unmask interrupt failed\n");
1080                 }
1081
1082                 /* Notify the core to resume the host */
1083                 ret = mmc_resume_host(host->mmc);
1084                 if (ret == 0)
1085                         host->suspended = 0;
1086         }
1087
1088         return ret;
1089
1090 clk_en_err:
1091         dev_dbg(mmc_dev(host->mmc),
1092                 "Failed to enable MMC clocks during resume\n");
1093         return ret;
1094 }
1095
1096 #else
1097 #define omap_mmc_suspend        NULL
1098 #define omap_mmc_resume         NULL
1099 #endif
1100
1101 static struct platform_driver omap_mmc_driver = {
1102         .probe          = omap_mmc_probe,
1103         .remove         = omap_mmc_remove,
1104         .suspend        = omap_mmc_suspend,
1105         .resume         = omap_mmc_resume,
1106         .driver         = {
1107                 .name = DRIVER_NAME,
1108                 .owner = THIS_MODULE,
1109         },
1110 };
1111
1112 static int __init omap_mmc_init(void)
1113 {
1114         /* Register the MMC driver */
1115         return platform_driver_register(&omap_mmc_driver);
1116 }
1117
1118 static void __exit omap_mmc_cleanup(void)
1119 {
1120         /* Unregister MMC driver */
1121         platform_driver_unregister(&omap_mmc_driver);
1122 }
1123
1124 module_init(omap_mmc_init);
1125 module_exit(omap_mmc_cleanup);
1126
1127 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1128 MODULE_LICENSE("GPL");
1129 MODULE_ALIAS("platform:" DRIVER_NAME);
1130 MODULE_AUTHOR("Texas Instruments Inc");