drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <asm/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <asm/hardware.h>
  32 #include <asm/arch/board.h>
  33 #include <asm/arch/mmc.h>
  34 #include <asm/arch/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1<<26)
  55 #define VS30                    (1<<25)
  56 #define SDVS18                  (0x5<<9)
  57 #define SDVS30                  (0x6<<9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1<<8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1<<2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define INT_EN_MASK             0x307F0033
  68 #define INIT_STREAM             (1<<1)
  69 #define DP_SELECT               (1<<21)
  70 #define DDIR                    (1<<4)
  71 #define DMA_EN                  0x1
  72 #define MSBS                    1<<5
  73 #define BCE                     1<<1
  74 #define FOUR_BIT                1 << 1
  75 #define CC                      0x1
  76 #define TC                      0x02
  77 #define OD                      0x1
  78 #define ERR                     (1 << 15)
  79 #define CMD_TIMEOUT             (1 << 16)
  80 #define DATA_TIMEOUT            (1 << 20)
  81 #define CMD_CRC                 (1 << 17)
  82 #define DATA_CRC                (1 << 21)
  83 #define CARD_ERR                (1 << 28)
  84 #define STAT_CLEAR              0xFFFFFFFF
  85 #define INIT_STREAM_CMD         0x00000000
  86 #define DUAL_VOLT_OCR_BIT       7
  87
  88 #define OMAP_MMC1_DEVID         1
  89 #define OMAP_MMC2_DEVID         2
  90 #define OMAP_MMC_DATADIR_NONE   0
  91 #define OMAP_MMC_DATADIR_READ   1
  92 #define OMAP_MMC_DATADIR_WRITE  2
  93 #define MMC_TIMEOUT_MS          20
  94 #define OMAP_MMC_MASTER_CLOCK   96000000
  95 #define DRIVER_NAME             "mmci-omap"
  96 /*
  97  * slot_id is device id - 1, device id is a static value
  98  * of 1 to represent device 1 etc..
  99  */
 100 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 101
 102 /*
 103  * MMC Host controller read/write API's
 104  */
 105 #define OMAP_HSMMC_READ(base, reg)      \
 106         __raw_readl((base) + OMAP_HSMMC_##reg)
 107
 108 #define OMAP_HSMMC_WRITE(base, reg, val) \
 109         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 110
 111 struct mmc_omap_host {
 112         struct  device          *dev;
 113         struct  mmc_host        *mmc;
 114         struct  mmc_request     *mrq;
 115         struct  mmc_command     *cmd;
 116         struct  mmc_data        *data;
 117         struct  clk             *fclk;
 118         struct  clk             *iclk;
 119         struct  clk             *dbclk;
 120         struct  semaphore       sem;
 121         struct  work_struct     mmc_carddetect_work;
 122         void    __iomem         *base;
 123         resource_size_t         mapbase;
 124         unsigned int            id;
 125         unsigned int            dma_len;
 126         unsigned int            dma_dir;
 127         unsigned char           bus_mode;
 128         unsigned char           datadir;
 129         u32                     *buffer;
 130         u32                     bytesleft;
 131         int                     suspended;
 132         int                     irq;
 133         int                     carddetect;
 134         int                     use_dma, dma_ch;
 135         int                     initstr;
 136         int                     slot_id;
 137         int                     dbclk_enabled;
 138         struct  omap_mmc_platform_data  *pdata;
 139 };
 140
 141 /*
 142  * Stop clock to the card
 143  */
 144 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 145 {
 146         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 147                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 148         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 149                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 150 }
 151
 152 /*
 153  * Send init stream sequence to card
 154  * before sending IDLE command
 155  */
 156 static void send_init_stream(struct mmc_omap_host *host)
 157 {
 158         int reg = 0;
 159         unsigned long timeout;
 160
 161         disable_irq(host->irq);
 162         OMAP_HSMMC_WRITE(host->base, CON,
 163                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 164         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 165
 166         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 167         while ((reg != CC) && time_before(jiffies, timeout))
 168                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 169
 170         OMAP_HSMMC_WRITE(host->base, CON,
 171                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 172         enable_irq(host->irq);
 173 }
 174
 175 /*
 176  * Configure the response type and send the cmd.
 177  */
 178 static void
 179 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 180         struct mmc_data *data)
 181 {
 182         int cmdreg = 0, resptype = 0, cmdtype = 0;
 183
 184         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 185                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 186         host->cmd = cmd;
 187
 188         /*
 189          * Clear status bits and enable interrupts
 190          */
 191         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 192         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 193         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 194
 195         if (cmd->flags & MMC_RSP_PRESENT) {
 196                 if (cmd->flags & MMC_RSP_136)
 197                         resptype = 1;
 198                 else
 199                         resptype = 2;
 200         }
 201
 202         /*
 203          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 204          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 205          */
 206         if (cmd->opcode == 12)
 207                 cmdtype = 0x3;
 208
 209         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 210
 211         if (data) {
 212                 cmdreg |= DP_SELECT | MSBS | BCE;
 213                 if (data->flags & MMC_DATA_READ)
 214                         cmdreg |= DDIR;
 215                 else
 216                         cmdreg &= ~(DDIR);
 217         }
 218
 219         if (host->use_dma)
 220                 cmdreg |= DMA_EN;
 221
 222         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 223         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 224 }
 225
 226 /*
 227  * Notify the transfer complete to MMC core
 228  */
 229 static void
 230 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 231 {
 232         host->data = NULL;
 233
 234         if (host->use_dma && host->dma_ch != -1)
 235                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 236                         host->dma_dir);
 237
 238         host->datadir = OMAP_MMC_DATADIR_NONE;
 239
 240         if (!data->error)
 241                 data->bytes_xfered += data->blocks * (data->blksz);
 242         else
 243                 data->bytes_xfered = 0;
 244
 245         if (!data->stop) {
 246                 host->mrq = NULL;
 247                 mmc_request_done(host->mmc, data->mrq);
 248                 return;
 249         }
 250         mmc_omap_start_command(host, data->stop, NULL);
 251 }
 252
 253 /*
 254  * Notify the core about command completion
 255  */
 256 static void
 257 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 258 {
 259         host->cmd = NULL;
 260
 261         if (cmd->flags & MMC_RSP_PRESENT) {
 262                 if (cmd->flags & MMC_RSP_136) {
 263                         /* response type 2 */
 264                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 265                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 266                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 267                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 268                 } else {
 269                         /* response types 1, 1b, 3, 4, 5, 6 */
 270                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 271                 }
 272         }
 273         if (host->data == NULL || cmd->error) {
 274                 host->mrq = NULL;
 275                 mmc_request_done(host->mmc, cmd->mrq);
 276         }
 277 }
 278
 279 /*
 280  * DMA clean up for command errors
 281  */
 282 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 283 {
 284         host->data->error = -ETIMEDOUT;
 285
 286         if (host->use_dma && host->dma_ch != -1) {
 287                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 288                         host->dma_dir);
 289                 omap_free_dma(host->dma_ch);
 290                 host->dma_ch = -1;
 291                 up(&host->sem);
 292         }
 293         host->data = NULL;
 294         host->datadir = OMAP_MMC_DATADIR_NONE;
 295 }
 296
 297 /*
 298  * MMC controller IRQ handler
 299  */
 300 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 301 {
 302         struct mmc_omap_host *host = dev_id;
 303         int end_cmd = 0, end_trans = 0, status;
 304
 305         if (host->cmd == NULL && host->data == NULL) {
 306                 OMAP_HSMMC_WRITE(host->base, STAT,
 307                         OMAP_HSMMC_READ(host->base, STAT));
 308                 return IRQ_HANDLED;
 309         }
 310
 311         status = OMAP_HSMMC_READ(host->base, STAT);
 312         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 313
 314         if (status & ERR) {
 315                 if ((status & CMD_TIMEOUT) ||
 316                         (status & CMD_CRC)) {
 317                         if (host->cmd) {
 318                                 if (status & CMD_TIMEOUT)
 319                                         host->cmd->error = -ETIMEDOUT;
 320                                 else
 321                                         host->cmd->error = -EILSEQ;
 322                                 end_cmd = 1;
 323                         }
 324                         if (host->data)
 325                                 mmc_dma_cleanup(host);
 326                 }
 327                 if ((status & DATA_TIMEOUT) ||
 328                         (status & DATA_CRC)) {
 329                         if (host->data) {
 330                                 if (status & DATA_TIMEOUT)
 331                                         mmc_dma_cleanup(host);
 332                                 else
 333                                         host->data->error = -EILSEQ;
 334                                 end_trans = 1;
 335                         }
 336                 }
 337                 if (status & CARD_ERR) {
 338                         dev_dbg(mmc_dev(host->mmc),
 339                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 340                         if (host->cmd)
 341                                 end_cmd = 1;
 342                         if (host->data)
 343                                 end_trans = 1;
 344                 }
 345         }
 346
 347         OMAP_HSMMC_WRITE(host->base, STAT, status);
 348
 349         if (end_cmd || (status & CC))
 350                 mmc_omap_cmd_done(host, host->cmd);
 351         if (end_trans || (status & TC))
 352                 mmc_omap_xfer_done(host, host->data);
 353
 354         return IRQ_HANDLED;
 355 }
 356
 357 /*
 358  * Switch MMC operating voltage
 359  */
 360 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 361 {
 362         u32 reg_val = 0;
 363         int ret;
 364
 365         /* Disable the clocks */
 366         clk_disable(host->fclk);
 367         clk_disable(host->iclk);
 368         clk_disable(host->dbclk);
 369
 370         /* Turn the power off */
 371         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 372         if (ret != 0)
 373                 goto err;
 374
 375         /* Turn the power ON with given VDD 1.8 or 3.0v */
 376         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 377         if (ret != 0)
 378                 goto err;
 379
 380         clk_enable(host->fclk);
 381         clk_enable(host->iclk);
 382         clk_enable(host->dbclk);
 383
 384         OMAP_HSMMC_WRITE(host->base, HCTL,
 385                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 386         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 387         /*
 388          * If a MMC dual voltage card is detected, the set_ios fn calls
 389          * this fn with VDD bit set for 1.8V. Upon card removal from the
 390          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 391          *
 392          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 393          * set in HCTL.
 394          */
 395         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 396                                 ((1 << vdd) == MMC_VDD_33_34)))
 397                 reg_val |= SDVS30;
 398         if ((1 << vdd) == MMC_VDD_165_195)
 399                 reg_val |= SDVS18;
 400
 401         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 402
 403         OMAP_HSMMC_WRITE(host->base, HCTL,
 404                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 405
 406         return 0;
 407 err:
 408         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 409         return ret;
 410 }
 411
 412 /*
 413  * Work Item to notify the core about card insertion/removal
 414  */
 415 static void mmc_omap_detect(struct work_struct *work)
 416 {
 417         u16 vdd = 0;
 418         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 419                                                 mmc_carddetect_work);
 420
 421         if (host->carddetect) {
 422                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 423                         /*
 424                          * Set the VDD back to 3V when the card is removed
 425                          * before the set_ios fn turns off the power.
 426                          */
 427                         vdd = fls(host->mmc->ocr_avail) - 1;
 428                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 429                                 host->mmc->ios.vdd = vdd;
 430                 }
 431                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 432         } else
 433                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 434 }
 435
 436 /*
 437  * ISR for handling card insertion and removal
 438  */
 439 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 440 {
 441         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 442
 443         host->carddetect = mmc_slot(host).card_detect(irq);
 444         schedule_work(&host->mmc_carddetect_work);
 445
 446         return IRQ_HANDLED;
 447 }
 448
 449 /*
 450  * DMA call back function
 451  */
 452 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 453 {
 454         struct mmc_omap_host *host = data;
 455
 456         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 457                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 458
 459         if (host->dma_ch < 0)
 460                 return;
 461
 462         omap_free_dma(host->dma_ch);
 463         host->dma_ch = -1;
 464         /*
 465          * DMA Callback: run in interrupt context.
 466          * mutex_unlock will through a kernel warning if used.
 467          */
 468         up(&host->sem);
 469 }
 470
 471 /*
 472  * Configure dma src and destination parameters
 473  */
 474 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 475                                 struct mmc_data *data)
 476 {
 477         if (sync_dir == 0) {
 478                 omap_set_dma_dest_params(host->dma_ch, 0,
 479                         OMAP_DMA_AMODE_CONSTANT,
 480                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 481                 omap_set_dma_src_params(host->dma_ch, 0,
 482                         OMAP_DMA_AMODE_POST_INC,
 483                         sg_dma_address(&data->sg[0]), 0, 0);
 484         } else {
 485                 omap_set_dma_src_params(host->dma_ch, 0,
 486                         OMAP_DMA_AMODE_CONSTANT,
 487                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 488                 omap_set_dma_dest_params(host->dma_ch, 0,
 489                         OMAP_DMA_AMODE_POST_INC,
 490                         sg_dma_address(&data->sg[0]), 0, 0);
 491         }
 492         return 0;
 493 }
 494 /*
 495  * Routine to configure and start DMA for the MMC card
 496  */
 497 static int
 498 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 499 {
 500         int sync_dev, sync_dir = 0;
 501         int dma_ch = 0, ret = 0, err = 1;
 502         struct mmc_data *data = req->data;
 503
 504         /*
 505          * If for some reason the DMA transfer is still active,
 506          * we wait for timeout period and free the dma
 507          */
 508         if (host->dma_ch != -1) {
 509                 set_current_state(TASK_UNINTERRUPTIBLE);
 510                 schedule_timeout(100);
 511                 if (down_trylock(&host->sem)) {
 512                         omap_free_dma(host->dma_ch);
 513                         host->dma_ch = -1;
 514                         up(&host->sem);
 515                         return err;
 516                 }
 517         } else {
 518                 if (down_trylock(&host->sem))
 519                         return err;
 520         }
 521
 522         if (!(data->flags & MMC_DATA_WRITE)) {
 523                 host->dma_dir = DMA_FROM_DEVICE;
 524                 if (host->id == OMAP_MMC1_DEVID)
 525                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 526                 else
 527                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 528         } else {
 529                 host->dma_dir = DMA_TO_DEVICE;
 530                 if (host->id == OMAP_MMC1_DEVID)
 531                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 532                 else
 533                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 534         }
 535
 536         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 537                         host, &dma_ch);
 538         if (ret != 0) {
 539                 dev_dbg(mmc_dev(host->mmc),
 540                         "%s: omap_request_dma() failed with %d\n",
 541                         mmc_hostname(host->mmc), ret);
 542                 return ret;
 543         }
 544
 545         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 546                         data->sg_len, host->dma_dir);
 547         host->dma_ch = dma_ch;
 548
 549         if (!(data->flags & MMC_DATA_WRITE))
 550                 mmc_omap_config_dma_param(1, host, data);
 551         else
 552                 mmc_omap_config_dma_param(0, host, data);
 553
 554         if ((data->blksz % 4) == 0)
 555                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 556                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 557                         sync_dev, sync_dir);
 558         else
 559                 /* REVISIT: The MMC buffer increments only when MSB is written.
 560                  * Return error for blksz which is non multiple of four.
 561                  */
 562                 return -EINVAL;
 563
 564         omap_start_dma(dma_ch);
 565         return 0;
 566 }
 567
 568 /*
 569  * Configure block length for MMC/SD cards and initiate the transfer.
 570  */
 571 static int
 572 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 573 {
 574         int ret;
 575         host->data = req->data;
 576
 577         if (req->data == NULL) {
 578                 host->datadir = OMAP_MMC_DATADIR_NONE;
 579                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 580                 return 0;
 581         }
 582
 583         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 584                                         | (req->data->blocks << 16));
 585
 586         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 587                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 588
 589         if (host->use_dma) {
 590                 ret = mmc_omap_start_dma_transfer(host, req);
 591                 if (ret != 0) {
 592                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 593                         return ret;
 594                 }
 595         }
 596         return 0;
 597 }
 598
 599 /*
 600  * Request function. for read/write operation
 601  */
 602 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 603 {
 604         struct mmc_omap_host *host = mmc_priv(mmc);
 605
 606         WARN_ON(host->mrq != NULL);
 607         host->mrq = req;
 608         mmc_omap_prepare_data(host, req);
 609         mmc_omap_start_command(host, req->cmd, req->data);
 610 }
 611
 612
 613 /* Routine to configure clock values. Exposed API to core */
 614 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 615 {
 616         struct mmc_omap_host *host = mmc_priv(mmc);
 617         u16 dsor = 0;
 618         unsigned long regval;
 619         unsigned long timeout;
 620
 621         switch (ios->power_mode) {
 622         case MMC_POWER_OFF:
 623                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 624                 break;
 625         case MMC_POWER_UP:
 626                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 627                 break;
 628         }
 629
 630         switch (mmc->ios.bus_width) {
 631         case MMC_BUS_WIDTH_4:
 632                 OMAP_HSMMC_WRITE(host->base, HCTL,
 633                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 634                 break;
 635         case MMC_BUS_WIDTH_1:
 636                 OMAP_HSMMC_WRITE(host->base, HCTL,
 637                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 638                 break;
 639         }
 640
 641         if (host->id == OMAP_MMC1_DEVID) {
 642                 /* Only MMC1 can operate at 3V/1.8V */
 643                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 644                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 645                                 /*
 646                                  * The mmc_select_voltage fn of the core does
 647                                  * not seem to set the power_mode to
 648                                  * MMC_POWER_UP upon recalculating the voltage.
 649                                  * vdd 1.8v.
 650                                  */
 651                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 652                                         dev_dbg(mmc_dev(host->mmc),
 653                                                 "Switch operation failed\n");
 654                 }
 655         }
 656
 657         if (ios->clock) {
 658                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 659                 if (dsor < 1)
 660                         dsor = 1;
 661
 662                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 663                         dsor++;
 664
 665                 if (dsor > 250)
 666                         dsor = 250;
 667         }
 668         omap_mmc_stop_clock(host);
 669         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 670         regval = regval & ~(CLKD_MASK);
 671         regval = regval | (dsor << 6) | (DTO << 16);
 672         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 673         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 674                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 675
 676         /* Wait till the ICS bit is set */
 677         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 678         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 679                 && time_before(jiffies, timeout))
 680                 msleep(1);
 681
 682         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 683                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 684
 685         if (ios->power_mode == MMC_POWER_ON)
 686                 send_init_stream(host);
 687
 688         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 689                 OMAP_HSMMC_WRITE(host->base, CON,
 690                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 691 }
 692 /* NOTE: Read only switch not supported yet */
 693 static struct mmc_host_ops mmc_omap_ops = {
 694         .request = omap_mmc_request,
 695         .set_ios = omap_mmc_set_ios,
 696 };
 697
 698 static int __init omap_mmc_probe(struct platform_device *pdev)
 699 {
 700         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 701         struct mmc_host *mmc;
 702         struct mmc_omap_host *host = NULL;
 703         struct resource *res;
 704         int ret = 0, irq;
 705         u32 hctl, capa;
 706
 707         if (pdata == NULL) {
 708                 dev_err(&pdev->dev, "Platform Data is missing\n");
 709                 return -ENXIO;
 710         }
 711
 712         if (pdata->nr_slots == 0) {
 713                 dev_err(&pdev->dev, "No Slots\n");
 714                 return -ENXIO;
 715         }
 716
 717         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 718         irq = platform_get_irq(pdev, 0);
 719         if (res == NULL || irq < 0)
 720                 return -ENXIO;
 721
 722         res = request_mem_region(res->start, res->end - res->start + 1,
 723                                                         pdev->name);
 724         if (res == NULL)
 725                 return -EBUSY;
 726
 727         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 728         if (!mmc) {
 729                 ret = -ENOMEM;
 730                 goto err;
 731         }
 732
 733         host            = mmc_priv(mmc);
 734         host->mmc       = mmc;
 735         host->pdata     = pdata;
 736         host->use_dma   = 1;
 737         host->dma_ch    = -1;
 738         host->irq       = irq;
 739         host->id        = pdev->id;
 740         host->slot_id   = 0;
 741         host->mapbase   = res->start;
 742         host->base      = ioremap(host->mapbase, SZ_4K);
 743         mmc->ops        = &mmc_omap_ops;
 744         mmc->f_min      = 400000;
 745         mmc->f_max      = 52000000;
 746
 747         sema_init(&host->sem, 1);
 748
 749         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 750         if (IS_ERR(host->iclk)) {
 751                 ret = PTR_ERR(host->iclk);
 752                 host->iclk = NULL;
 753                 goto err;
 754         }
 755         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 756         if (IS_ERR(host->fclk)) {
 757                 ret = PTR_ERR(host->fclk);
 758                 host->fclk = NULL;
 759                 clk_put(host->iclk);
 760                 goto err;
 761         }
 762
 763         if (clk_enable(host->fclk) != 0)
 764                 goto err;
 765
 766         if (clk_enable(host->iclk) != 0) {
 767                 clk_disable(host->fclk);
 768                 clk_put(host->fclk);
 769                 goto err;
 770         }
 771
 772         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 773         /*
 774          * MMC can still work without debounce clock.
 775          */
 776         if (IS_ERR(host->dbclk))
 777                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 778         else
 779                 if (clk_enable(host->dbclk) != 0)
 780                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 781                                                         " clk failed\n");
 782                 else
 783                         host->dbclk_enabled = 1;
 784
 785         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 786         mmc->caps |= MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
 787                                 MMC_CAP_SD_HIGHSPEED;
 788
 789         if (pdata->conf.wire4)
 790                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 791
 792         /* Only MMC1 supports 3.0V */
 793         if (host->id == OMAP_MMC1_DEVID) {
 794                 hctl = SDVS30;
 795                 capa = VS30 | VS18;
 796         } else {
 797                 hctl = SDVS18;
 798                 capa = VS18;
 799         }
 800
 801         OMAP_HSMMC_WRITE(host->base, HCTL,
 802                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 803
 804         OMAP_HSMMC_WRITE(host->base, CAPA,
 805                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 806
 807         /* Set the controller to AUTO IDLE mode */
 808         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 809                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 810
 811         /* Set SD bus power bit */
 812         OMAP_HSMMC_WRITE(host->base, HCTL,
 813                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 814
 815         /* Request IRQ for MMC operations */
 816         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name,
 817                          host);
 818         if (ret) {
 819                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
 820                 goto irq_err;
 821         }
 822
 823         /* Request IRQ for card detect */
 824         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
 825                 ret = request_irq(mmc_slot(host).card_detect_irq,
 826                                   omap_mmc_cd_handler, IRQF_DISABLED, "MMC CD",
 827                                   host);
 828                 if (ret) {
 829                         dev_dbg(mmc_dev(host->mmc),
 830                                 "Unable to grab MMC CD IRQ");
 831                         free_irq(host->irq, host);
 832                         goto irq_err;
 833                 }
 834         }
 835
 836         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 837         if (pdata->init != NULL) {
 838                 if (pdata->init(&pdev->dev) != 0) {
 839                         free_irq(mmc_slot(host).card_detect_irq, host);
 840                         free_irq(host->irq, host);
 841                         goto irq_err;
 842                 }
 843         }
 844
 845         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 846         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 847
 848         platform_set_drvdata(pdev, host);
 849         mmc_add_host(mmc);
 850
 851         return 0;
 852
 853 err:
 854         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
 855         if (host)
 856                 mmc_free_host(mmc);
 857         return ret;
 858
 859 irq_err:
 860         dev_dbg(mmc_dev(host->mmc), "Unable to configure MMC IRQs\n");
 861         clk_disable(host->fclk);
 862         clk_disable(host->iclk);
 863         clk_put(host->fclk);
 864         clk_put(host->iclk);
 865         if (host->dbclk_enabled) {
 866                 clk_disable(host->dbclk);
 867                 clk_put(host->dbclk);
 868         }
 869
 870         if (host)
 871                 mmc_free_host(mmc);
 872         return ret;
 873 }
 874
 875 static int omap_mmc_remove(struct platform_device *pdev)
 876 {
 877         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 878
 879         platform_set_drvdata(pdev, NULL);
 880         if (host) {
 881                 host->pdata->cleanup(&pdev->dev);
 882                 free_irq(host->irq, host);
 883                 if (mmc_slot(host).card_detect_irq)
 884                         free_irq(mmc_slot(host).card_detect_irq, host);
 885                 flush_scheduled_work();
 886
 887                 clk_disable(host->fclk);
 888                 clk_disable(host->iclk);
 889                 clk_put(host->fclk);
 890                 clk_put(host->iclk);
 891                 if (host->dbclk_enabled) {
 892                         clk_disable(host->dbclk);
 893                         clk_put(host->dbclk);
 894                 }
 895
 896                 mmc_free_host(host->mmc);
 897         }
 898
 899         return 0;
 900 }
 901
 902 #ifdef CONFIG_PM
 903 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
 904 {
 905         int ret = 0;
 906         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 907
 908         if (host && host->suspended)
 909                 return 0;
 910
 911         if (host) {
 912                 ret = mmc_suspend_host(host->mmc, state);
 913                 if (ret == 0) {
 914                         host->suspended = 1;
 915
 916                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 917                         OMAP_HSMMC_WRITE(host->base, IE, 0);
 918
 919                         ret = host->pdata->suspend(&pdev->dev, host->slot_id);
 920                         if (ret)
 921                                 dev_dbg(mmc_dev(host->mmc),
 922                                         "Unable to handle MMC board"
 923                                         " level suspend\n");
 924
 925                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 926                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 927                                         OMAP_HSMMC_READ(host->base, HCTL)
 928                                         & SDVSCLR);
 929                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 930                                         OMAP_HSMMC_READ(host->base, HCTL)
 931                                         | SDVS30);
 932                                 OMAP_HSMMC_WRITE(host->base, HCTL,
 933                                         OMAP_HSMMC_READ(host->base, HCTL)
 934                                         | SDBP);
 935                         }
 936
 937                         clk_disable(host->fclk);
 938                         clk_disable(host->iclk);
 939                         clk_disable(host->dbclk);
 940                 }
 941
 942         }
 943         return ret;
 944 }
 945
 946 /* Routine to resume the MMC device */
 947 static int omap_mmc_resume(struct platform_device *pdev)
 948 {
 949         int ret = 0;
 950         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 951
 952         if (host && !host->suspended)
 953                 return 0;
 954
 955         if (host) {
 956
 957                 ret = clk_enable(host->fclk);
 958                 if (ret)
 959                         goto clk_en_err;
 960
 961                 ret = clk_enable(host->iclk);
 962                 if (ret) {
 963                         clk_disable(host->fclk);
 964                         clk_put(host->fclk);
 965                         goto clk_en_err;
 966                 }
 967
 968                 if (clk_enable(host->dbclk) != 0)
 969                         dev_dbg(mmc_dev(host->mmc),
 970                                         "Enabling debounce clk failed\n");
 971
 972                 ret = host->pdata->resume(&pdev->dev, host->slot_id);
 973                 if (ret)
 974                         dev_dbg(mmc_dev(host->mmc),
 975                                         "Unmask interrupt failed\n");
 976
 977                 /* Notify the core to resume the host */
 978                 ret = mmc_resume_host(host->mmc);
 979                 if (ret == 0)
 980                         host->suspended = 0;
 981         }
 982
 983         return ret;
 984
 985 clk_en_err:
 986         dev_dbg(mmc_dev(host->mmc),
 987                 "Failed to enable MMC clocks during resume\n");
 988         return ret;
 989 }
 990
 991 #else
 992 #define omap_mmc_suspend        NULL
 993 #define omap_mmc_resume         NULL
 994 #endif
 995
 996 static struct platform_driver omap_mmc_driver = {
 997         .probe          = omap_mmc_probe,
 998         .remove         = omap_mmc_remove,
 999         .suspend        = omap_mmc_suspend,
1000         .resume         = omap_mmc_resume,
1001         .driver         = {
1002                 .name = DRIVER_NAME,
1003         },
1004 };
1005
1006 static int __init omap_mmc_init(void)
1007 {
1008         /* Register the MMC driver */
1009         return platform_driver_register(&omap_mmc_driver);
1010 }
1011
1012 static void __exit omap_mmc_cleanup(void)
1013 {
1014         /* Unregister MMC driver */
1015         platform_driver_unregister(&omap_mmc_driver);
1016 }
1017
1018 module_init(omap_mmc_init);
1019 module_exit(omap_mmc_cleanup);
1020
1021 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1022 MODULE_LICENSE("GPL");
1023 MODULE_ALIAS(DRIVER_NAME);
1024 MODULE_AUTHOR("Texas Instruments Inc");