drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define OMAP_MMC_DATADIR_NONE   0
 102 #define OMAP_MMC_DATADIR_READ   1
 103 #define OMAP_MMC_DATADIR_WRITE  2
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 enum {OFF = 0, ON};
 125 #define IDLE_TIMEOUT (jiffies_to_msecs(10))
 126
 127 struct mmc_omap_host {
 128         struct  device          *dev;
 129         struct  mmc_host        *mmc;
 130         struct  mmc_request     *mrq;
 131         struct  mmc_command     *cmd;
 132         struct  mmc_data        *data;
 133         struct  clk             *fclk;
 134         struct  clk             *iclk;
 135         struct  clk             *dbclk;
 136         struct  semaphore       sem;
 137         struct  work_struct     mmc_carddetect_work;
 138         void    __iomem         *base;
 139         resource_size_t         mapbase;
 140         unsigned int            id;
 141         unsigned int            dma_len;
 142         unsigned int            dma_dir;
 143         unsigned char           bus_mode;
 144         unsigned char           datadir;
 145         u32                     *buffer;
 146         u32                     bytesleft;
 147         int                     suspended;
 148         int                     irq;
 149         int                     carddetect;
 150         int                     use_dma, dma_ch;
 151         int                     initstr;
 152         int                     slot_id;
 153         int                     dbclk_enabled;
 154
 155         struct timer_list       idle_timer;
 156         spinlock_t              clk_lock;     /* for changing enabled state */
 157         unsigned int            fclk_enabled:1;
 158
 159         struct  omap_mmc_platform_data  *pdata;
 160 };
 161
 162 static int mmc_omap_fclk_state(struct mmc_omap_host *host, unsigned int state)
 163 {
 164         unsigned long flags;
 165         int ret = 0;
 166
 167         spin_lock_irqsave(&host->clk_lock, flags);
 168         del_timer(&host->idle_timer);
 169         if (host->fclk_enabled != state) {
 170                 if (state == ON) {
 171                         ret = clk_enable(host->fclk);
 172                         if (ret != 0)
 173                                 goto err_out;
 174
 175                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
 176                 } else {
 177                         clk_disable(host->fclk);
 178                         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
 179                 }
 180                 host->fclk_enabled = state;
 181         }
 182
 183 err_out:
 184         spin_unlock_irqrestore(&host->clk_lock, flags);
 185         return ret;
 186 }
 187
 188 static void mmc_omap_idle_timer(unsigned long data)
 189 {
 190         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 191
 192         mmc_omap_fclk_state(host, OFF);
 193 }
 194
 195 /*
 196  * Stop clock to the card
 197  */
 198 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 199 {
 200         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 201                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 202         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 203                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 204 }
 205
 206 /*
 207  * Send init stream sequence to card
 208  * before sending IDLE command
 209  */
 210 static void send_init_stream(struct mmc_omap_host *host)
 211 {
 212         int reg = 0;
 213         unsigned long timeout;
 214
 215         disable_irq(host->irq);
 216         OMAP_HSMMC_WRITE(host->base, CON,
 217                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 218         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 219
 220         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 221         while ((reg != CC) && time_before(jiffies, timeout))
 222                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 223
 224         OMAP_HSMMC_WRITE(host->base, CON,
 225                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 226         enable_irq(host->irq);
 227 }
 228
 229 static inline
 230 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 231 {
 232         if (host->pdata->slots[host->slot_id].get_cover_state)
 233                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 234         return 1;
 235 }
 236
 237 static ssize_t
 238 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 239                            char *buf)
 240 {
 241         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 242         struct mmc_omap_host *host = mmc_priv(mmc);
 243
 244         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 245                        "open");
 246 }
 247
 248 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 249
 250 static ssize_t
 251 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 252                         char *buf)
 253 {
 254         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 255         struct mmc_omap_host *host = mmc_priv(mmc);
 256         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 257
 258         return sprintf(buf, "slot:%s\n", slot.name);
 259 }
 260
 261 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 262
 263 /*
 264  * Configure the response type and send the cmd.
 265  */
 266 static void
 267 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 268         struct mmc_data *data)
 269 {
 270         int cmdreg = 0, resptype = 0, cmdtype = 0;
 271
 272         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 273                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 274         host->cmd = cmd;
 275
 276         /*
 277          * Clear status bits and enable interrupts
 278          */
 279         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 280         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 281         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 282
 283         if (cmd->flags & MMC_RSP_PRESENT) {
 284                 if (cmd->flags & MMC_RSP_136)
 285                         resptype = 1;
 286                 else
 287                         resptype = 2;
 288         }
 289
 290         /*
 291          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 292          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 293          */
 294         if (cmd->opcode == 12)
 295                 cmdtype = 0x3;
 296
 297         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 298
 299         if (data) {
 300                 cmdreg |= DP_SELECT | MSBS | BCE;
 301                 if (data->flags & MMC_DATA_READ)
 302                         cmdreg |= DDIR;
 303                 else
 304                         cmdreg &= ~(DDIR);
 305         }
 306
 307         if (host->use_dma)
 308                 cmdreg |= DMA_EN;
 309
 310         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 311         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 312 }
 313
 314 /*
 315  * Notify the transfer complete to MMC core
 316  */
 317 static void
 318 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 319 {
 320         host->data = NULL;
 321
 322         if (host->use_dma && host->dma_ch != -1)
 323                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 324                         host->dma_dir);
 325
 326         host->datadir = OMAP_MMC_DATADIR_NONE;
 327
 328         if (!data->error)
 329                 data->bytes_xfered += data->blocks * (data->blksz);
 330         else
 331                 data->bytes_xfered = 0;
 332
 333         if (!data->stop) {
 334                 host->mrq = NULL;
 335                 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 336                 mmc_request_done(host->mmc, data->mrq);
 337                 return;
 338         }
 339         mmc_omap_start_command(host, data->stop, NULL);
 340 }
 341
 342 /*
 343  * Notify the core about command completion
 344  */
 345 static void
 346 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 347 {
 348         host->cmd = NULL;
 349
 350         if (cmd->flags & MMC_RSP_PRESENT) {
 351                 if (cmd->flags & MMC_RSP_136) {
 352                         /* response type 2 */
 353                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 354                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 355                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 356                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 357                 } else {
 358                         /* response types 1, 1b, 3, 4, 5, 6 */
 359                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 360                 }
 361         }
 362         if (host->data == NULL || cmd->error) {
 363                 host->mrq = NULL;
 364                 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 365                 mmc_request_done(host->mmc, cmd->mrq);
 366         }
 367 }
 368
 369 /*
 370  * DMA clean up for command errors
 371  */
 372 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 373 {
 374         host->data->error = -ETIMEDOUT;
 375
 376         if (host->use_dma && host->dma_ch != -1) {
 377                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 378                         host->dma_dir);
 379                 omap_free_dma(host->dma_ch);
 380                 host->dma_ch = -1;
 381                 up(&host->sem);
 382         }
 383         host->data = NULL;
 384         host->datadir = OMAP_MMC_DATADIR_NONE;
 385 }
 386
 387 /*
 388  * Readable error output
 389  */
 390 #ifdef CONFIG_MMC_DEBUG
 391 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 392 {
 393         /* --- means reserved bit without definition at documentation */
 394         static const char *mmc_omap_status_bits[] = {
 395                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 396                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 397                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 398                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 399         };
 400         int i;
 401
 402         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 403
 404         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 405                 if (status & (1 << i))
 406                         /*
 407                          * KERN_* facility is not used here because this should
 408                          * print a single line.
 409                          */
 410                         printk(" %s", mmc_omap_status_bits[i]);
 411
 412         printk("\n");
 413
 414 }
 415 #endif  /* CONFIG_MMC_DEBUG */
 416
 417
 418 /*
 419  * MMC controller IRQ handler
 420  */
 421 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 422 {
 423         struct mmc_omap_host *host = dev_id;
 424         struct mmc_data *data;
 425         int end_cmd = 0, end_trans = 0, status;
 426
 427         if (host->cmd == NULL && host->data == NULL) {
 428                 OMAP_HSMMC_WRITE(host->base, STAT,
 429                         OMAP_HSMMC_READ(host->base, STAT));
 430                 return IRQ_HANDLED;
 431         }
 432
 433         data = host->data;
 434         status = OMAP_HSMMC_READ(host->base, STAT);
 435         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 436
 437         if (status & ERR) {
 438 #ifdef CONFIG_MMC_DEBUG
 439                 mmc_omap_report_irq(host, status);
 440 #endif
 441                 if ((status & CMD_TIMEOUT) ||
 442                         (status & CMD_CRC)) {
 443                         if (host->cmd) {
 444                                 if (status & CMD_TIMEOUT) {
 445                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 446                                                 OMAP_HSMMC_READ(host->base,
 447                                                                 SYSCTL) | SRC);
 448                                         while (OMAP_HSMMC_READ(host->base,
 449                                                                 SYSCTL) & SRC) ;
 450                                         host->cmd->error = -ETIMEDOUT;
 451                                 } else {
 452                                         host->cmd->error = -EILSEQ;
 453                                 }
 454                                 end_cmd = 1;
 455                         }
 456                         if (host->data)
 457                                 mmc_dma_cleanup(host);
 458                 }
 459                 if ((status & DATA_TIMEOUT) ||
 460                         (status & DATA_CRC)) {
 461                         if (host->data) {
 462                                 if (status & DATA_TIMEOUT)
 463                                         mmc_dma_cleanup(host);
 464                                 else
 465                                         host->data->error = -EILSEQ;
 466                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 467                                         OMAP_HSMMC_READ(host->base,
 468                                                         SYSCTL) | SRD);
 469                                 while (OMAP_HSMMC_READ(host->base,
 470                                                         SYSCTL) & SRD) ;
 471                                 end_trans = 1;
 472                         }
 473                 }
 474                 if (status & CARD_ERR) {
 475                         dev_dbg(mmc_dev(host->mmc),
 476                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 477                         if (host->cmd)
 478                                 end_cmd = 1;
 479                         if (host->data)
 480                                 end_trans = 1;
 481                 }
 482         }
 483
 484         OMAP_HSMMC_WRITE(host->base, STAT, status);
 485
 486         if (end_cmd || (status & CC))
 487                 mmc_omap_cmd_done(host, host->cmd);
 488         if (end_trans || (status & TC))
 489                 mmc_omap_xfer_done(host, data);
 490
 491         return IRQ_HANDLED;
 492 }
 493
 494 /*
 495  * Switch MMC operating voltage
 496  */
 497 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 498 {
 499         u32 reg_val = 0;
 500         int ret;
 501
 502         /* Disable the clocks */
 503         mmc_omap_fclk_state(host, OFF);
 504         clk_disable(host->iclk);
 505         clk_disable(host->dbclk);
 506
 507         /* Turn the power off */
 508         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 509         if (ret != 0)
 510                 goto err;
 511
 512         /* Turn the power ON with given VDD 1.8 or 3.0v */
 513         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 514         if (ret != 0)
 515                 goto err;
 516
 517         mmc_omap_fclk_state(host, ON);
 518         clk_enable(host->iclk);
 519         clk_enable(host->dbclk);
 520
 521         OMAP_HSMMC_WRITE(host->base, HCTL,
 522                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 523         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 524         /*
 525          * If a MMC dual voltage card is detected, the set_ios fn calls
 526          * this fn with VDD bit set for 1.8V. Upon card removal from the
 527          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 528          *
 529          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 530          * set in HCTL.
 531          */
 532         if (host->id == OMAP_MMC1_DEVID) {
 533                 if (((1 << vdd) == MMC_VDD_32_33) ||
 534                     ((1 << vdd) == MMC_VDD_33_34))
 535                         reg_val |= SDVS30;
 536                 else if ((1 << vdd) == MMC_VDD_165_195)
 537                         reg_val |= SDVS18;
 538         } else
 539                 reg_val |= SDVS18;
 540
 541         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 542
 543         OMAP_HSMMC_WRITE(host->base, HCTL,
 544                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 545
 546         return 0;
 547 err:
 548         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 549         return ret;
 550 }
 551
 552 /*
 553  * Work Item to notify the core about card insertion/removal
 554  */
 555 static void mmc_omap_detect(struct work_struct *work)
 556 {
 557         u16 vdd = 0;
 558         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 559                                                 mmc_carddetect_work);
 560
 561         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 562         mmc_omap_fclk_state(host, ON);
 563         if (host->carddetect) {
 564                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 565                         /*
 566                          * Set the VDD back to 3V when the card is removed
 567                          * before the set_ios fn turns off the power.
 568                          */
 569                         vdd = fls(host->mmc->ocr_avail) - 1;
 570                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 571                                 host->mmc->ios.vdd = vdd;
 572                 }
 573                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 574         } else {
 575                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 576                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 577                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 578                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 579         }
 580         mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 581 }
 582
 583 /*
 584  * ISR for handling card insertion and removal
 585  */
 586 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 587 {
 588         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 589
 590         host->carddetect = mmc_slot(host).card_detect(irq);
 591         schedule_work(&host->mmc_carddetect_work);
 592
 593         return IRQ_HANDLED;
 594 }
 595
 596 /*
 597  * DMA call back function
 598  */
 599 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 600 {
 601         struct mmc_omap_host *host = data;
 602
 603         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 604                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 605
 606         if (host->dma_ch < 0)
 607                 return;
 608
 609         omap_free_dma(host->dma_ch);
 610         host->dma_ch = -1;
 611         /*
 612          * DMA Callback: run in interrupt context.
 613          * mutex_unlock will through a kernel warning if used.
 614          */
 615         up(&host->sem);
 616 }
 617
 618 /*
 619  * Configure dma src and destination parameters
 620  */
 621 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 622                                 struct mmc_data *data)
 623 {
 624         if (sync_dir == 0) {
 625                 omap_set_dma_dest_params(host->dma_ch, 0,
 626                         OMAP_DMA_AMODE_CONSTANT,
 627                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 628                 omap_set_dma_src_params(host->dma_ch, 0,
 629                         OMAP_DMA_AMODE_POST_INC,
 630                         sg_dma_address(&data->sg[0]), 0, 0);
 631         } else {
 632                 omap_set_dma_src_params(host->dma_ch, 0,
 633                         OMAP_DMA_AMODE_CONSTANT,
 634                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 635                 omap_set_dma_dest_params(host->dma_ch, 0,
 636                         OMAP_DMA_AMODE_POST_INC,
 637                         sg_dma_address(&data->sg[0]), 0, 0);
 638         }
 639         return 0;
 640 }
 641 /*
 642  * Routine to configure and start DMA for the MMC card
 643  */
 644 static int
 645 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 646 {
 647         int sync_dev, sync_dir = 0;
 648         int dma_ch = 0, ret = 0, err = 1;
 649         struct mmc_data *data = req->data;
 650
 651         /*
 652          * If for some reason the DMA transfer is still active,
 653          * we wait for timeout period and free the dma
 654          */
 655         if (host->dma_ch != -1) {
 656                 set_current_state(TASK_UNINTERRUPTIBLE);
 657                 schedule_timeout(100);
 658                 if (down_trylock(&host->sem)) {
 659                         omap_free_dma(host->dma_ch);
 660                         host->dma_ch = -1;
 661                         up(&host->sem);
 662                         return err;
 663                 }
 664         } else {
 665                 if (down_trylock(&host->sem))
 666                         return err;
 667         }
 668
 669         if (!(data->flags & MMC_DATA_WRITE)) {
 670                 host->dma_dir = DMA_FROM_DEVICE;
 671                 if (host->id == OMAP_MMC1_DEVID)
 672                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 673                 else
 674                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 675         } else {
 676                 host->dma_dir = DMA_TO_DEVICE;
 677                 if (host->id == OMAP_MMC1_DEVID)
 678                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 679                 else
 680                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 681         }
 682
 683         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 684                         host, &dma_ch);
 685         if (ret != 0) {
 686                 dev_dbg(mmc_dev(host->mmc),
 687                         "%s: omap_request_dma() failed with %d\n",
 688                         mmc_hostname(host->mmc), ret);
 689                 return ret;
 690         }
 691
 692         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 693                         data->sg_len, host->dma_dir);
 694         host->dma_ch = dma_ch;
 695
 696         if (!(data->flags & MMC_DATA_WRITE))
 697                 mmc_omap_config_dma_param(1, host, data);
 698         else
 699                 mmc_omap_config_dma_param(0, host, data);
 700
 701         if ((data->blksz % 4) == 0)
 702                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 703                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 704                         sync_dev, sync_dir);
 705         else
 706                 /* REVISIT: The MMC buffer increments only when MSB is written.
 707                  * Return error for blksz which is non multiple of four.
 708                  */
 709                 return -EINVAL;
 710
 711         omap_start_dma(dma_ch);
 712         return 0;
 713 }
 714
 715 static void set_data_timeout(struct mmc_omap_host *host,
 716                              struct mmc_request *req)
 717 {
 718         unsigned int timeout, cycle_ns;
 719         uint32_t reg, clkd, dto = 0;
 720
 721         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 722         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 723         if (clkd == 0)
 724                 clkd = 1;
 725
 726         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 727         timeout = req->data->timeout_ns / cycle_ns;
 728         timeout += req->data->timeout_clks;
 729         if (timeout) {
 730                 while ((timeout & 0x80000000) == 0) {
 731                         dto += 1;
 732                         timeout <<= 1;
 733                 }
 734                 dto = 31 - dto;
 735                 timeout <<= 1;
 736                 if (timeout && dto)
 737                         dto += 1;
 738                 if (dto >= 13)
 739                         dto -= 13;
 740                 else
 741                         dto = 0;
 742                 if (dto > 14)
 743                         dto = 14;
 744         }
 745
 746         reg &= ~DTO_MASK;
 747         reg |= dto << DTO_SHIFT;
 748         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 749 }
 750
 751 /*
 752  * Configure block length for MMC/SD cards and initiate the transfer.
 753  */
 754 static int
 755 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 756 {
 757         int ret;
 758         host->data = req->data;
 759
 760         if (req->data == NULL) {
 761                 host->datadir = OMAP_MMC_DATADIR_NONE;
 762                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 763                 return 0;
 764         }
 765
 766         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 767                                         | (req->data->blocks << 16));
 768         set_data_timeout(host, req);
 769
 770         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 771                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 772
 773         if (host->use_dma) {
 774                 ret = mmc_omap_start_dma_transfer(host, req);
 775                 if (ret != 0) {
 776                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 777                         return ret;
 778                 }
 779         }
 780         return 0;
 781 }
 782
 783 /*
 784  * Request function. for read/write operation
 785  */
 786 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 787 {
 788         struct mmc_omap_host *host = mmc_priv(mmc);
 789
 790         WARN_ON(host->mrq != NULL);
 791         host->mrq = req;
 792         mmc_omap_fclk_state(host, ON);
 793         mmc_omap_prepare_data(host, req);
 794         mmc_omap_start_command(host, req->cmd, req->data);
 795 }
 796
 797 /* Routine to configure clock values. Exposed API to core */
 798 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 799 {
 800         struct mmc_omap_host *host = mmc_priv(mmc);
 801         u16 dsor = 0;
 802         unsigned long regval;
 803         unsigned long timeout;
 804
 805         mmc_omap_fclk_state(host, ON);
 806
 807         switch (ios->power_mode) {
 808         case MMC_POWER_OFF:
 809                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 810                 break;
 811         case MMC_POWER_UP:
 812                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 813                 break;
 814         }
 815
 816         switch (mmc->ios.bus_width) {
 817         case MMC_BUS_WIDTH_4:
 818                 OMAP_HSMMC_WRITE(host->base, HCTL,
 819                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 820                 break;
 821         case MMC_BUS_WIDTH_1:
 822                 OMAP_HSMMC_WRITE(host->base, HCTL,
 823                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 824                 break;
 825         }
 826
 827         if (host->id == OMAP_MMC1_DEVID) {
 828                 /* Only MMC1 can operate at 3V/1.8V */
 829                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 830                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 831                                 /*
 832                                  * The mmc_select_voltage fn of the core does
 833                                  * not seem to set the power_mode to
 834                                  * MMC_POWER_UP upon recalculating the voltage.
 835                                  * vdd 1.8v.
 836                                  */
 837                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 838                                         dev_dbg(mmc_dev(host->mmc),
 839                                                 "Switch operation failed\n");
 840                 }
 841         }
 842
 843         if (ios->clock) {
 844                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 845                 if (dsor < 1)
 846                         dsor = 1;
 847
 848                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 849                         dsor++;
 850
 851                 if (dsor > 250)
 852                         dsor = 250;
 853         }
 854         omap_mmc_stop_clock(host);
 855         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 856         regval = regval & ~(CLKD_MASK);
 857         regval = regval | (dsor << 6) | (DTO << 16);
 858         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 859         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 860                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 861
 862         /* Wait till the ICS bit is set */
 863         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 864         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 865                 && time_before(jiffies, timeout))
 866                 msleep(1);
 867
 868         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 869                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 870
 871         if (ios->power_mode == MMC_POWER_ON)
 872                 send_init_stream(host);
 873
 874         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 875                 OMAP_HSMMC_WRITE(host->base, CON,
 876                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 877
 878         if (ios->power_mode == MMC_POWER_OFF)
 879                 mmc_omap_fclk_state(host, OFF);
 880         else
 881                 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
 882 }
 883
 884 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 885 {
 886         struct mmc_omap_host *host = mmc_priv(mmc);
 887         struct omap_mmc_platform_data *pdata = host->pdata;
 888
 889         if (!pdata->slots[0].card_detect)
 890                 return -ENOSYS;
 891         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 892 }
 893
 894 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 895 {
 896         struct mmc_omap_host *host = mmc_priv(mmc);
 897         struct omap_mmc_platform_data *pdata = host->pdata;
 898
 899         if (!pdata->slots[0].get_ro)
 900                 return -ENOSYS;
 901         return pdata->slots[0].get_ro(host->dev, 0);
 902 }
 903
 904 static struct mmc_host_ops mmc_omap_ops = {
 905         .request = omap_mmc_request,
 906         .set_ios = omap_mmc_set_ios,
 907         .get_cd = omap_hsmmc_get_cd,
 908         .get_ro = omap_hsmmc_get_ro,
 909         /* NYET -- enable_sdio_irq */
 910 };
 911
 912 static int __init omap_mmc_probe(struct platform_device *pdev)
 913 {
 914         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 915         struct mmc_host *mmc;
 916         struct mmc_omap_host *host = NULL;
 917         struct resource *res;
 918         int ret = 0, irq, reg;
 919         u32 hctl, capa;
 920
 921         if (pdata == NULL) {
 922                 dev_err(&pdev->dev, "Platform Data is missing\n");
 923                 return -ENXIO;
 924         }
 925
 926         if (pdata->nr_slots == 0) {
 927                 dev_err(&pdev->dev, "No Slots\n");
 928                 return -ENXIO;
 929         }
 930
 931         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 932         irq = platform_get_irq(pdev, 0);
 933         if (res == NULL || irq < 0)
 934                 return -ENXIO;
 935
 936         res = request_mem_region(res->start, res->end - res->start + 1,
 937                                                         pdev->name);
 938         if (res == NULL)
 939                 return -EBUSY;
 940
 941         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 942         if (!mmc) {
 943                 ret = -ENOMEM;
 944                 goto err;
 945         }
 946
 947         host            = mmc_priv(mmc);
 948         host->mmc       = mmc;
 949         host->pdata     = pdata;
 950         host->dev       = &pdev->dev;
 951         host->use_dma   = 1;
 952         host->dev->dma_mask = &pdata->dma_mask;
 953         host->dma_ch    = -1;
 954         host->irq       = irq;
 955         host->id        = pdev->id;
 956         host->slot_id   = 0;
 957         host->mapbase   = res->start;
 958         host->base      = ioremap(host->mapbase, SZ_4K);
 959
 960         platform_set_drvdata(pdev, host);
 961         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 962
 963         mmc->ops        = &mmc_omap_ops;
 964         mmc->f_min      = 400000;
 965         mmc->f_max      = 52000000;
 966
 967         sema_init(&host->sem, 1);
 968
 969         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 970         if (IS_ERR(host->iclk)) {
 971                 ret = PTR_ERR(host->iclk);
 972                 host->iclk = NULL;
 973                 goto err1;
 974         }
 975         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 976         if (IS_ERR(host->fclk)) {
 977                 ret = PTR_ERR(host->fclk);
 978                 host->fclk = NULL;
 979                 clk_put(host->iclk);
 980                 goto err1;
 981         }
 982
 983         spin_lock_init(&host->clk_lock);
 984         setup_timer(&host->idle_timer, mmc_omap_idle_timer,
 985                     (unsigned long) host);
 986
 987         if (mmc_omap_fclk_state(host, ON) != 0) {
 988                 clk_put(host->iclk);
 989                 clk_put(host->fclk);
 990                 goto err1;
 991         }
 992         if (clk_enable(host->iclk) != 0) {
 993                 mmc_omap_fclk_state(host, OFF);
 994                 clk_put(host->iclk);
 995                 clk_put(host->fclk);
 996                 goto err1;
 997         }
 998
 999         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1000         /*
1001          * MMC can still work without debounce clock.
1002          */
1003         if (IS_ERR(host->dbclk))
1004                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1005         else
1006                 if (clk_enable(host->dbclk) != 0)
1007                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1008                                                         " clk failed\n");
1009                 else
1010                         host->dbclk_enabled = 1;
1011
1012 #ifdef CONFIG_MMC_BLOCK_BOUNCE
1013         mmc->max_phys_segs = 1;
1014         mmc->max_hw_segs = 1;
1015 #endif
1016         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1017         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1018         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1019         mmc->max_seg_size = mmc->max_req_size;
1020
1021         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1022         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1023
1024         if (pdata->slots[host->slot_id].wires >= 4)
1025                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1026
1027         /* Only MMC1 supports 3.0V */
1028         if (host->id == OMAP_MMC1_DEVID) {
1029                 hctl = SDVS30;
1030                 capa = VS30 | VS18;
1031         } else {
1032                 hctl = SDVS18;
1033                 capa = VS18;
1034         }
1035
1036         OMAP_HSMMC_WRITE(host->base, HCTL,
1037                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1038
1039         OMAP_HSMMC_WRITE(host->base, CAPA,
1040                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1041
1042         /* Set the controller to AUTO IDLE mode */
1043         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1044                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1045
1046         /* Set SD bus power bit */
1047         OMAP_HSMMC_WRITE(host->base, HCTL,
1048                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1049
1050         /* Request IRQ for MMC operations */
1051         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1052                         mmc_hostname(mmc), host);
1053         if (ret) {
1054                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1055                 goto err_irq;
1056         }
1057
1058         if (pdata->init != NULL) {
1059                 if (pdata->init(&pdev->dev) != 0) {
1060                         dev_dbg(mmc_dev(host->mmc),
1061                                 "Unable to configure MMC IRQs\n");
1062                         goto err_irq_cd_init;
1063                 }
1064         }
1065
1066         /* Request IRQ for card detect */
1067         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1068                 ret = request_irq(mmc_slot(host).card_detect_irq,
1069                                   omap_mmc_cd_handler,
1070                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1071                                           | IRQF_DISABLED,
1072                                   mmc_hostname(mmc), host);
1073                 if (ret) {
1074                         dev_dbg(mmc_dev(host->mmc),
1075                                 "Unable to grab MMC CD IRQ\n");
1076                         goto err_irq_cd;
1077                 }
1078         }
1079
1080         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1081         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1082
1083         mmc_add_host(mmc);
1084
1085         if (host->pdata->slots[host->slot_id].name != NULL) {
1086                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1087                 if (ret < 0)
1088                         goto err_slot_name;
1089         }
1090         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1091                         host->pdata->slots[host->slot_id].get_cover_state) {
1092                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1093                 if (ret < 0)
1094                         goto err_cover_switch;
1095         }
1096         mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
1097
1098         return 0;
1099
1100 err_cover_switch:
1101         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1102 err_slot_name:
1103         mmc_remove_host(mmc);
1104 err_irq_cd:
1105         free_irq(mmc_slot(host).card_detect_irq, host);
1106 err_irq_cd_init:
1107         free_irq(host->irq, host);
1108 err_irq:
1109         mmc_omap_fclk_state(host, OFF);
1110         clk_disable(host->iclk);
1111         clk_put(host->fclk);
1112         clk_put(host->iclk);
1113         if (host->dbclk_enabled) {
1114                 clk_disable(host->dbclk);
1115                 clk_put(host->dbclk);
1116         }
1117
1118 err1:
1119         iounmap(host->base);
1120 err:
1121         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1122         release_mem_region(res->start, res->end - res->start + 1);
1123         if (host)
1124                 mmc_free_host(mmc);
1125         return ret;
1126 }
1127
1128 static int omap_mmc_remove(struct platform_device *pdev)
1129 {
1130         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1131         struct resource *res;
1132         u16 vdd = 0;
1133
1134         if (host) {
1135                 mmc_omap_fclk_state(host, ON);
1136                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1137                         /*
1138                          * Set the vdd back to 3V,
1139                          * applicable for dual volt support.
1140                          */
1141                         vdd = fls(host->mmc->ocr_avail) - 1;
1142                         if (omap_mmc_switch_opcond(host, vdd) != 0)
1143                                 host->mmc->ios.vdd = vdd;
1144                 }
1145         }
1146
1147         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1148         if (res)
1149                 release_mem_region(res->start, res->end - res->start + 1);
1150
1151         platform_set_drvdata(pdev, NULL);
1152         if (host) {
1153                 mmc_remove_host(host->mmc);
1154                 if (host->pdata->cleanup)
1155                         host->pdata->cleanup(&pdev->dev);
1156                 free_irq(host->irq, host);
1157                 if (mmc_slot(host).card_detect_irq)
1158                         free_irq(mmc_slot(host).card_detect_irq, host);
1159                 flush_scheduled_work();
1160
1161                 mmc_omap_fclk_state(host, OFF);
1162                 clk_disable(host->iclk);
1163                 clk_put(host->fclk);
1164                 clk_put(host->iclk);
1165                 if (host->dbclk_enabled) {
1166                         clk_disable(host->dbclk);
1167                         clk_put(host->dbclk);
1168                 }
1169
1170                 mmc_free_host(host->mmc);
1171                 iounmap(host->base);
1172         }
1173
1174         return 0;
1175 }
1176
1177 #ifdef CONFIG_PM
1178 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1179 {
1180         int ret = 0;
1181         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1182
1183         if (host && host->suspended)
1184                 return 0;
1185
1186         if (host) {
1187                 mmc_omap_fclk_state(host, ON);
1188
1189                 ret = mmc_suspend_host(host->mmc, state);
1190                 if (ret == 0) {
1191                         host->suspended = 1;
1192
1193                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1194                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1195
1196                         if (host->pdata->suspend) {
1197                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1198                                 if (ret)
1199                                         dev_dbg(mmc_dev(host->mmc),
1200                                                 "Unable to handle MMC board"
1201                                                 " level suspend\n");
1202                         }
1203
1204                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1205                                 u32 hctl = OMAP_HSMMC_READ(host->base, HCTL) &
1206                                         SDVSCLR;
1207
1208                                 if (host->id == OMAP_MMC1_DEVID)
1209                                         hctl |= SDVS30;
1210                                 else
1211                                         hctl |= SDVS18;
1212
1213                                 OMAP_HSMMC_WRITE(host->base, HCTL, hctl);
1214                                 OMAP_HSMMC_WRITE(host->base, HCTL, hctl | SDBP);
1215                         }
1216
1217                         mmc_omap_fclk_state(host, OFF);
1218                         clk_disable(host->iclk);
1219                         clk_disable(host->dbclk);
1220                 }
1221
1222         }
1223         return ret;
1224 }
1225
1226 /* Routine to resume the MMC device */
1227 static int omap_mmc_resume(struct platform_device *pdev)
1228 {
1229         int ret = 0;
1230         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1231
1232         if (host && !host->suspended)
1233                 return 0;
1234
1235         if (host) {
1236
1237                 if (mmc_omap_fclk_state(host, ON) != 0)
1238                         goto clk_en_err;
1239
1240                 ret = clk_enable(host->iclk);
1241                 if (ret) {
1242                         mmc_omap_fclk_state(host, OFF);
1243                         clk_put(host->fclk);
1244                         goto clk_en_err;
1245                 }
1246
1247                 if (clk_enable(host->dbclk) != 0)
1248                         dev_dbg(mmc_dev(host->mmc),
1249                                         "Enabling debounce clk failed\n");
1250
1251                 if (host->pdata->resume) {
1252                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1253                         if (ret)
1254                                 dev_dbg(mmc_dev(host->mmc),
1255                                         "Unmask interrupt failed\n");
1256                 }
1257
1258                 /* Notify the core to resume the host */
1259                 ret = mmc_resume_host(host->mmc);
1260                 if (ret == 0)
1261                         host->suspended = 0;
1262
1263                 mod_timer(&host->idle_timer, jiffies + IDLE_TIMEOUT);
1264         }
1265
1266         return ret;
1267
1268 clk_en_err:
1269         dev_dbg(mmc_dev(host->mmc),
1270                 "Failed to enable MMC clocks during resume\n");
1271         return ret;
1272 }
1273
1274 #else
1275 #define omap_mmc_suspend        NULL
1276 #define omap_mmc_resume         NULL
1277 #endif
1278
1279 static struct platform_driver omap_mmc_driver = {
1280         .probe          = omap_mmc_probe,
1281         .remove         = omap_mmc_remove,
1282         .suspend        = omap_mmc_suspend,
1283         .resume         = omap_mmc_resume,
1284         .driver         = {
1285                 .name = DRIVER_NAME,
1286                 .owner = THIS_MODULE,
1287         },
1288 };
1289
1290 static int __init omap_mmc_init(void)
1291 {
1292         /* Register the MMC driver */
1293         return platform_driver_register(&omap_mmc_driver);
1294 }
1295
1296 static void __exit omap_mmc_cleanup(void)
1297 {
1298         /* Unregister MMC driver */
1299         platform_driver_unregister(&omap_mmc_driver);
1300 }
1301
1302 module_init(omap_mmc_init);
1303 module_exit(omap_mmc_cleanup);
1304
1305 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1306 MODULE_LICENSE("GPL");
1307 MODULE_ALIAS("platform:" DRIVER_NAME);
1308 MODULE_AUTHOR("Texas Instruments Inc");