drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <asm/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1<<26)
  55 #define VS30                    (1<<25)
  56 #define SDVS18                  (0x5<<9)
  57 #define SDVS30                  (0x6<<9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1<<8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1<<2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define INT_EN_MASK             0x307F0033
  68 #define INIT_STREAM             (1<<1)
  69 #define DP_SELECT               (1<<21)
  70 #define DDIR                    (1<<4)
  71 #define DMA_EN                  0x1
  72 #define MSBS                    1<<5
  73 #define BCE                     1<<1
  74 #define FOUR_BIT                1 << 1
  75 #define CC                      0x1
  76 #define TC                      0x02
  77 #define OD                      0x1
  78 #define ERR                     (1 << 15)
  79 #define CMD_TIMEOUT             (1 << 16)
  80 #define DATA_TIMEOUT            (1 << 20)
  81 #define CMD_CRC                 (1 << 17)
  82 #define DATA_CRC                (1 << 21)
  83 #define CARD_ERR                (1 << 28)
  84 #define STAT_CLEAR              0xFFFFFFFF
  85 #define INIT_STREAM_CMD         0x00000000
  86 #define DUAL_VOLT_OCR_BIT       7
  87 #define SRC                     (1 << 25)
  88 #define SRD                     (1 << 26)
  89
  90 #define OMAP_MMC1_DEVID         1
  91 #define OMAP_MMC2_DEVID         2
  92 #define OMAP_MMC_DATADIR_NONE   0
  93 #define OMAP_MMC_DATADIR_READ   1
  94 #define OMAP_MMC_DATADIR_WRITE  2
  95 #define MMC_TIMEOUT_MS          20
  96 #define OMAP_MMC_MASTER_CLOCK   96000000
  97 #define DRIVER_NAME             "mmci-omap"
  98 /*
  99  * slot_id is device id - 1, device id is a static value
 100  * of 1 to represent device 1 etc..
 101  */
 102 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 103
 104 /*
 105  * MMC Host controller read/write API's
 106  */
 107 #define OMAP_HSMMC_READ(base, reg)      \
 108         __raw_readl((base) + OMAP_HSMMC_##reg)
 109
 110 #define OMAP_HSMMC_WRITE(base, reg, val) \
 111         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 112
 113 struct mmc_omap_host {
 114         struct  device          *dev;
 115         struct  mmc_host        *mmc;
 116         struct  mmc_request     *mrq;
 117         struct  mmc_command     *cmd;
 118         struct  mmc_data        *data;
 119         struct  clk             *fclk;
 120         struct  clk             *iclk;
 121         struct  clk             *dbclk;
 122         struct  semaphore       sem;
 123         struct  work_struct     mmc_carddetect_work;
 124         void    __iomem         *base;
 125         resource_size_t         mapbase;
 126         unsigned int            id;
 127         unsigned int            dma_len;
 128         unsigned int            dma_dir;
 129         unsigned char           bus_mode;
 130         unsigned char           datadir;
 131         u32                     *buffer;
 132         u32                     bytesleft;
 133         int                     suspended;
 134         int                     irq;
 135         int                     carddetect;
 136         int                     use_dma, dma_ch;
 137         int                     initstr;
 138         int                     slot_id;
 139         int                     dbclk_enabled;
 140         struct  omap_mmc_platform_data  *pdata;
 141 };
 142
 143 /*
 144  * Stop clock to the card
 145  */
 146 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 147 {
 148         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 149                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 150         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 151                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 152 }
 153
 154 /*
 155  * Send init stream sequence to card
 156  * before sending IDLE command
 157  */
 158 static void send_init_stream(struct mmc_omap_host *host)
 159 {
 160         int reg = 0;
 161         unsigned long timeout;
 162
 163         disable_irq(host->irq);
 164         OMAP_HSMMC_WRITE(host->base, CON,
 165                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 166         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 167
 168         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 169         while ((reg != CC) && time_before(jiffies, timeout))
 170                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 171
 172         OMAP_HSMMC_WRITE(host->base, CON,
 173                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 174         enable_irq(host->irq);
 175 }
 176
 177 static inline
 178 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 179 {
 180         if (host->pdata->slots[host->slot_id].get_cover_state)
 181                 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
 182         return 1;
 183 }
 184
 185 static ssize_t
 186 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 187                            char *buf)
 188 {
 189         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 190         struct mmc_omap_host *host = mmc_priv(mmc);
 191
 192         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 193                        "open");
 194 }
 195
 196 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 197
 198 static ssize_t
 199 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 200                         char *buf)
 201 {
 202         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 203         struct mmc_omap_host *host = mmc_priv(mmc);
 204         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 205
 206         return sprintf(buf, "slot:%s\n", slot.name);
 207 }
 208
 209 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 210
 211 /*
 212  * Configure the response type and send the cmd.
 213  */
 214 static void
 215 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 216         struct mmc_data *data)
 217 {
 218         int cmdreg = 0, resptype = 0, cmdtype = 0;
 219
 220         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 221                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 222         host->cmd = cmd;
 223
 224         /*
 225          * Clear status bits and enable interrupts
 226          */
 227         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 228         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 229         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 230
 231         if (cmd->flags & MMC_RSP_PRESENT) {
 232                 if (cmd->flags & MMC_RSP_136)
 233                         resptype = 1;
 234                 else
 235                         resptype = 2;
 236         }
 237
 238         /*
 239          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 240          * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
 241          */
 242         if (cmd->opcode == 12)
 243                 cmdtype = 0x3;
 244
 245         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 246
 247         if (data) {
 248                 cmdreg |= DP_SELECT | MSBS | BCE;
 249                 if (data->flags & MMC_DATA_READ)
 250                         cmdreg |= DDIR;
 251                 else
 252                         cmdreg &= ~(DDIR);
 253         }
 254
 255         if (host->use_dma)
 256                 cmdreg |= DMA_EN;
 257
 258         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 259         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 260 }
 261
 262 /*
 263  * Notify the transfer complete to MMC core
 264  */
 265 static void
 266 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 267 {
 268         host->data = NULL;
 269
 270         if (host->use_dma && host->dma_ch != -1)
 271                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 272                         host->dma_dir);
 273
 274         host->datadir = OMAP_MMC_DATADIR_NONE;
 275
 276         if (!data->error)
 277                 data->bytes_xfered += data->blocks * (data->blksz);
 278         else
 279                 data->bytes_xfered = 0;
 280
 281         if (!data->stop) {
 282                 host->mrq = NULL;
 283                 mmc_request_done(host->mmc, data->mrq);
 284                 return;
 285         }
 286         mmc_omap_start_command(host, data->stop, NULL);
 287 }
 288
 289 /*
 290  * Notify the core about command completion
 291  */
 292 static void
 293 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 294 {
 295         host->cmd = NULL;
 296
 297         if (cmd->flags & MMC_RSP_PRESENT) {
 298                 if (cmd->flags & MMC_RSP_136) {
 299                         /* response type 2 */
 300                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 301                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 302                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 303                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 304                 } else {
 305                         /* response types 1, 1b, 3, 4, 5, 6 */
 306                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 307                 }
 308         }
 309         if (host->data == NULL || cmd->error) {
 310                 host->mrq = NULL;
 311                 mmc_request_done(host->mmc, cmd->mrq);
 312         }
 313 }
 314
 315 /*
 316  * DMA clean up for command errors
 317  */
 318 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 319 {
 320         host->data->error = -ETIMEDOUT;
 321
 322         if (host->use_dma && host->dma_ch != -1) {
 323                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 324                         host->dma_dir);
 325                 omap_free_dma(host->dma_ch);
 326                 host->dma_ch = -1;
 327                 up(&host->sem);
 328         }
 329         host->data = NULL;
 330         host->datadir = OMAP_MMC_DATADIR_NONE;
 331 }
 332
 333 /*
 334  * Readable error output
 335  */
 336 #ifdef CONFIG_MMC_DEBUG
 337 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 338 {
 339         /* --- means reserved bit without definition at documentation */
 340         static const char *mmc_omap_status_bits[] = {
 341                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 342                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 343                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 344                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 345         };
 346         int i;
 347
 348         dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
 349
 350         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 351                 if (status & (1 << i))
 352                         /*
 353                          * KERN_* facility is not used here because this should
 354                          * print a single line.
 355                          */
 356                         printk(" %s", mmc_omap_status_bits[i]);
 357
 358         printk("\n");
 359
 360 }
 361 #endif  /* CONFIG_MMC_DEBUG */
 362
 363
 364 /*
 365  * MMC controller IRQ handler
 366  */
 367 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 368 {
 369         struct mmc_omap_host *host = dev_id;
 370         struct mmc_data *data;
 371         int end_cmd = 0, end_trans = 0, status;
 372
 373         if (host->cmd == NULL && host->data == NULL) {
 374                 OMAP_HSMMC_WRITE(host->base, STAT,
 375                         OMAP_HSMMC_READ(host->base, STAT));
 376                 return IRQ_HANDLED;
 377         }
 378
 379         data = host->data;
 380         status = OMAP_HSMMC_READ(host->base, STAT);
 381         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 382
 383         if (status & ERR) {
 384 #ifdef CONFIG_MMC_DEBUG
 385                 mmc_omap_report_irq(host, status);
 386 #endif
 387                 if ((status & CMD_TIMEOUT) ||
 388                         (status & CMD_CRC)) {
 389                         if (host->cmd) {
 390                                 if (status & CMD_TIMEOUT) {
 391                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 392                                                 OMAP_HSMMC_READ(host->base,
 393                                                                 SYSCTL) | SRC);
 394                                         while (OMAP_HSMMC_READ(host->base,
 395                                                                 SYSCTL) & SRC) ;
 396                                         host->cmd->error = -ETIMEDOUT;
 397                                 } else {
 398                                         host->cmd->error = -EILSEQ;
 399                                 }
 400                                 end_cmd = 1;
 401                         }
 402                         if (host->data)
 403                                 mmc_dma_cleanup(host);
 404                 }
 405                 if ((status & DATA_TIMEOUT) ||
 406                         (status & DATA_CRC)) {
 407                         if (host->data) {
 408                                 if (status & DATA_TIMEOUT)
 409                                         mmc_dma_cleanup(host);
 410                                 else
 411                                         host->data->error = -EILSEQ;
 412                                 end_trans = 1;
 413                         }
 414                 }
 415                 if (status & CARD_ERR) {
 416                         dev_dbg(mmc_dev(host->mmc),
 417                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 418                         if (host->cmd)
 419                                 end_cmd = 1;
 420                         if (host->data)
 421                                 end_trans = 1;
 422                 }
 423         }
 424
 425         OMAP_HSMMC_WRITE(host->base, STAT, status);
 426
 427         if (end_cmd || (status & CC))
 428                 mmc_omap_cmd_done(host, host->cmd);
 429         if (end_trans || (status & TC))
 430                 mmc_omap_xfer_done(host, data);
 431
 432         return IRQ_HANDLED;
 433 }
 434
 435 /*
 436  * Switch MMC operating voltage
 437  */
 438 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 439 {
 440         u32 reg_val = 0;
 441         int ret;
 442
 443         /* Disable the clocks */
 444         clk_disable(host->fclk);
 445         clk_disable(host->iclk);
 446         clk_disable(host->dbclk);
 447
 448         /* Turn the power off */
 449         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 450         if (ret != 0)
 451                 goto err;
 452
 453         /* Turn the power ON with given VDD 1.8 or 3.0v */
 454         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 455         if (ret != 0)
 456                 goto err;
 457
 458         clk_enable(host->fclk);
 459         clk_enable(host->iclk);
 460         clk_enable(host->dbclk);
 461
 462         OMAP_HSMMC_WRITE(host->base, HCTL,
 463                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 464         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 465         /*
 466          * If a MMC dual voltage card is detected, the set_ios fn calls
 467          * this fn with VDD bit set for 1.8V. Upon card removal from the
 468          * slot, mmc_omap_detect fn sets the VDD back to 3V.
 469          *
 470          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 471          * set in HCTL.
 472          */
 473         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 474                                 ((1 << vdd) == MMC_VDD_33_34)))
 475                 reg_val |= SDVS30;
 476         if ((1 << vdd) == MMC_VDD_165_195)
 477                 reg_val |= SDVS18;
 478
 479         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 480
 481         OMAP_HSMMC_WRITE(host->base, HCTL,
 482                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 483
 484         return 0;
 485 err:
 486         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 487         return ret;
 488 }
 489
 490 /*
 491  * Work Item to notify the core about card insertion/removal
 492  */
 493 static void mmc_omap_detect(struct work_struct *work)
 494 {
 495         u16 vdd = 0;
 496         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 497                                                 mmc_carddetect_work);
 498
 499         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 500         if (host->carddetect) {
 501                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 502                         /*
 503                          * Set the VDD back to 3V when the card is removed
 504                          * before the set_ios fn turns off the power.
 505                          */
 506                         vdd = fls(host->mmc->ocr_avail) - 1;
 507                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 508                                 host->mmc->ios.vdd = vdd;
 509                 }
 510                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 511         } else {
 512                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 513                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 514                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
 515                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 516         }
 517 }
 518
 519 /*
 520  * ISR for handling card insertion and removal
 521  */
 522 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 523 {
 524         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 525
 526         host->carddetect = mmc_slot(host).card_detect(irq);
 527         schedule_work(&host->mmc_carddetect_work);
 528
 529         return IRQ_HANDLED;
 530 }
 531
 532 /*
 533  * DMA call back function
 534  */
 535 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 536 {
 537         struct mmc_omap_host *host = data;
 538
 539         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 540                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 541
 542         if (host->dma_ch < 0)
 543                 return;
 544
 545         omap_free_dma(host->dma_ch);
 546         host->dma_ch = -1;
 547         /*
 548          * DMA Callback: run in interrupt context.
 549          * mutex_unlock will through a kernel warning if used.
 550          */
 551         up(&host->sem);
 552 }
 553
 554 /*
 555  * Configure dma src and destination parameters
 556  */
 557 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 558                                 struct mmc_data *data)
 559 {
 560         if (sync_dir == 0) {
 561                 omap_set_dma_dest_params(host->dma_ch, 0,
 562                         OMAP_DMA_AMODE_CONSTANT,
 563                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 564                 omap_set_dma_src_params(host->dma_ch, 0,
 565                         OMAP_DMA_AMODE_POST_INC,
 566                         sg_dma_address(&data->sg[0]), 0, 0);
 567         } else {
 568                 omap_set_dma_src_params(host->dma_ch, 0,
 569                         OMAP_DMA_AMODE_CONSTANT,
 570                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 571                 omap_set_dma_dest_params(host->dma_ch, 0,
 572                         OMAP_DMA_AMODE_POST_INC,
 573                         sg_dma_address(&data->sg[0]), 0, 0);
 574         }
 575         return 0;
 576 }
 577 /*
 578  * Routine to configure and start DMA for the MMC card
 579  */
 580 static int
 581 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 582 {
 583         int sync_dev, sync_dir = 0;
 584         int dma_ch = 0, ret = 0, err = 1;
 585         struct mmc_data *data = req->data;
 586
 587         /*
 588          * If for some reason the DMA transfer is still active,
 589          * we wait for timeout period and free the dma
 590          */
 591         if (host->dma_ch != -1) {
 592                 set_current_state(TASK_UNINTERRUPTIBLE);
 593                 schedule_timeout(100);
 594                 if (down_trylock(&host->sem)) {
 595                         omap_free_dma(host->dma_ch);
 596                         host->dma_ch = -1;
 597                         up(&host->sem);
 598                         return err;
 599                 }
 600         } else {
 601                 if (down_trylock(&host->sem))
 602                         return err;
 603         }
 604
 605         if (!(data->flags & MMC_DATA_WRITE)) {
 606                 host->dma_dir = DMA_FROM_DEVICE;
 607                 if (host->id == OMAP_MMC1_DEVID)
 608                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 609                 else
 610                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 611         } else {
 612                 host->dma_dir = DMA_TO_DEVICE;
 613                 if (host->id == OMAP_MMC1_DEVID)
 614                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 615                 else
 616                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 617         }
 618
 619         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 620                         host, &dma_ch);
 621         if (ret != 0) {
 622                 dev_dbg(mmc_dev(host->mmc),
 623                         "%s: omap_request_dma() failed with %d\n",
 624                         mmc_hostname(host->mmc), ret);
 625                 return ret;
 626         }
 627
 628         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 629                         data->sg_len, host->dma_dir);
 630         host->dma_ch = dma_ch;
 631
 632         if (!(data->flags & MMC_DATA_WRITE))
 633                 mmc_omap_config_dma_param(1, host, data);
 634         else
 635                 mmc_omap_config_dma_param(0, host, data);
 636
 637         if ((data->blksz % 4) == 0)
 638                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 639                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 640                         sync_dev, sync_dir);
 641         else
 642                 /* REVISIT: The MMC buffer increments only when MSB is written.
 643                  * Return error for blksz which is non multiple of four.
 644                  */
 645                 return -EINVAL;
 646
 647         omap_start_dma(dma_ch);
 648         return 0;
 649 }
 650
 651 /*
 652  * Configure block length for MMC/SD cards and initiate the transfer.
 653  */
 654 static int
 655 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 656 {
 657         int ret;
 658         host->data = req->data;
 659
 660         if (req->data == NULL) {
 661                 host->datadir = OMAP_MMC_DATADIR_NONE;
 662                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 663                 return 0;
 664         }
 665
 666         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 667                                         | (req->data->blocks << 16));
 668
 669         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 670                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 671
 672         if (host->use_dma) {
 673                 ret = mmc_omap_start_dma_transfer(host, req);
 674                 if (ret != 0) {
 675                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 676                         return ret;
 677                 }
 678         }
 679         return 0;
 680 }
 681
 682 /*
 683  * Request function. for read/write operation
 684  */
 685 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 686 {
 687         struct mmc_omap_host *host = mmc_priv(mmc);
 688
 689         WARN_ON(host->mrq != NULL);
 690         host->mrq = req;
 691         mmc_omap_prepare_data(host, req);
 692         mmc_omap_start_command(host, req->cmd, req->data);
 693 }
 694
 695
 696 /* Routine to configure clock values. Exposed API to core */
 697 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 698 {
 699         struct mmc_omap_host *host = mmc_priv(mmc);
 700         u16 dsor = 0;
 701         unsigned long regval;
 702         unsigned long timeout;
 703
 704         switch (ios->power_mode) {
 705         case MMC_POWER_OFF:
 706                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 707                 break;
 708         case MMC_POWER_UP:
 709                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 710                 break;
 711         }
 712
 713         switch (mmc->ios.bus_width) {
 714         case MMC_BUS_WIDTH_4:
 715                 OMAP_HSMMC_WRITE(host->base, HCTL,
 716                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 717                 break;
 718         case MMC_BUS_WIDTH_1:
 719                 OMAP_HSMMC_WRITE(host->base, HCTL,
 720                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 721                 break;
 722         }
 723
 724         if (host->id == OMAP_MMC1_DEVID) {
 725                 /* Only MMC1 can operate at 3V/1.8V */
 726                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 727                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 728                                 /*
 729                                  * The mmc_select_voltage fn of the core does
 730                                  * not seem to set the power_mode to
 731                                  * MMC_POWER_UP upon recalculating the voltage.
 732                                  * vdd 1.8v.
 733                                  */
 734                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 735                                         dev_dbg(mmc_dev(host->mmc),
 736                                                 "Switch operation failed\n");
 737                 }
 738         }
 739
 740         if (ios->clock) {
 741                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 742                 if (dsor < 1)
 743                         dsor = 1;
 744
 745                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 746                         dsor++;
 747
 748                 if (dsor > 250)
 749                         dsor = 250;
 750         }
 751         omap_mmc_stop_clock(host);
 752         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 753         regval = regval & ~(CLKD_MASK);
 754         regval = regval | (dsor << 6) | (DTO << 16);
 755         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 756         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 757                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 758
 759         /* Wait till the ICS bit is set */
 760         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 761         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 762                 && time_before(jiffies, timeout))
 763                 msleep(1);
 764
 765         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 766                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 767
 768         if (ios->power_mode == MMC_POWER_ON)
 769                 send_init_stream(host);
 770
 771         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 772                 OMAP_HSMMC_WRITE(host->base, CON,
 773                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 774 }
 775 /* NOTE: Read only switch not supported yet */
 776 static struct mmc_host_ops mmc_omap_ops = {
 777         .request = omap_mmc_request,
 778         .set_ios = omap_mmc_set_ios,
 779 };
 780
 781 static int __init omap_mmc_probe(struct platform_device *pdev)
 782 {
 783         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 784         struct mmc_host *mmc;
 785         struct mmc_omap_host *host = NULL;
 786         struct resource *res;
 787         int ret = 0, irq;
 788         u32 hctl, capa;
 789
 790         if (pdata == NULL) {
 791                 dev_err(&pdev->dev, "Platform Data is missing\n");
 792                 return -ENXIO;
 793         }
 794
 795         if (pdata->nr_slots == 0) {
 796                 dev_err(&pdev->dev, "No Slots\n");
 797                 return -ENXIO;
 798         }
 799
 800         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 801         irq = platform_get_irq(pdev, 0);
 802         if (res == NULL || irq < 0)
 803                 return -ENXIO;
 804
 805         res = request_mem_region(res->start, res->end - res->start + 1,
 806                                                         pdev->name);
 807         if (res == NULL)
 808                 return -EBUSY;
 809
 810         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 811         if (!mmc) {
 812                 ret = -ENOMEM;
 813                 goto err;
 814         }
 815
 816         host            = mmc_priv(mmc);
 817         host->mmc       = mmc;
 818         host->pdata     = pdata;
 819         host->use_dma   = 1;
 820         host->dma_ch    = -1;
 821         host->irq       = irq;
 822         host->id        = pdev->id;
 823         host->slot_id   = 0;
 824         host->mapbase   = res->start;
 825         host->base      = ioremap(host->mapbase, SZ_4K);
 826         mmc->ops        = &mmc_omap_ops;
 827         mmc->f_min      = 400000;
 828         mmc->f_max      = 52000000;
 829
 830         sema_init(&host->sem, 1);
 831
 832         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 833         if (IS_ERR(host->iclk)) {
 834                 ret = PTR_ERR(host->iclk);
 835                 host->iclk = NULL;
 836                 goto err1;
 837         }
 838         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 839         if (IS_ERR(host->fclk)) {
 840                 ret = PTR_ERR(host->fclk);
 841                 host->fclk = NULL;
 842                 clk_put(host->iclk);
 843                 goto err1;
 844         }
 845
 846         if (clk_enable(host->fclk) != 0) {
 847                 clk_put(host->iclk);
 848                 clk_put(host->fclk);
 849                 goto err1;
 850         }
 851
 852         if (clk_enable(host->iclk) != 0) {
 853                 clk_disable(host->fclk);
 854                 clk_put(host->iclk);
 855                 clk_put(host->fclk);
 856                 goto err1;
 857         }
 858
 859         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 860         /*
 861          * MMC can still work without debounce clock.
 862          */
 863         if (IS_ERR(host->dbclk))
 864                 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 865         else
 866                 if (clk_enable(host->dbclk) != 0)
 867                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 868                                                         " clk failed\n");
 869                 else
 870                         host->dbclk_enabled = 1;
 871
 872 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 873         mmc->max_phys_segs = 1;
 874         mmc->max_hw_segs = 1;
 875 #endif
 876         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 877         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 878         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 879         mmc->max_seg_size = mmc->max_req_size;
 880
 881         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 882         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
 883
 884         if (pdata->slots[host->slot_id].wire4)
 885                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 886
 887         /* Only MMC1 supports 3.0V */
 888         if (host->id == OMAP_MMC1_DEVID) {
 889                 hctl = SDVS30;
 890                 capa = VS30 | VS18;
 891         } else {
 892                 hctl = SDVS18;
 893                 capa = VS18;
 894         }
 895
 896         OMAP_HSMMC_WRITE(host->base, HCTL,
 897                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 898
 899         OMAP_HSMMC_WRITE(host->base, CAPA,
 900                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 901
 902         /* Set the controller to AUTO IDLE mode */
 903         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 904                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 905
 906         /* Set SD bus power bit */
 907         OMAP_HSMMC_WRITE(host->base, HCTL,
 908                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 909
 910         /* Request IRQ for MMC operations */
 911         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, pdev->name,
 912                          host);
 913         if (ret) {
 914                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
 915                 goto err_irq;
 916         }
 917
 918         /* Request IRQ for card detect */
 919         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
 920                 ret = request_irq(mmc_slot(host).card_detect_irq,
 921                                   omap_mmc_cd_handler, IRQF_DISABLED, "MMC CD",
 922                                   host);
 923                 if (ret) {
 924                         dev_dbg(mmc_dev(host->mmc),
 925                                 "Unable to grab MMC CD IRQ\n");
 926                         goto err_irq_cd;
 927                 }
 928         }
 929
 930         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 931         if (pdata->init != NULL) {
 932                 if (pdata->init(&pdev->dev) != 0) {
 933                         dev_dbg(mmc_dev(host->mmc),
 934                                 "Unable to configure MMC IRQs\n");
 935                         goto err_irq_cd_init;
 936                 }
 937         }
 938
 939         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 940         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 941
 942         platform_set_drvdata(pdev, host);
 943         mmc_add_host(mmc);
 944
 945         if (host->pdata->slots[host->slot_id].name != NULL) {
 946                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
 947                 if (ret < 0)
 948                         goto err_slot_name;
 949         }
 950         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
 951                         host->pdata->slots[host->slot_id].get_cover_state) {
 952                 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
 953                 if (ret < 0)
 954                         goto err_cover_switch;
 955         }
 956
 957         return 0;
 958
 959 err_cover_switch:
 960         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
 961 err_slot_name:
 962         mmc_remove_host(mmc);
 963 err_irq_cd_init:
 964         free_irq(mmc_slot(host).card_detect_irq, host);
 965 err_irq_cd:
 966         free_irq(host->irq, host);
 967 err_irq:
 968         clk_disable(host->fclk);
 969         clk_disable(host->iclk);
 970         clk_put(host->fclk);
 971         clk_put(host->iclk);
 972         if (host->dbclk_enabled) {
 973                 clk_disable(host->dbclk);
 974                 clk_put(host->dbclk);
 975         }
 976
 977 err1:
 978         iounmap(host->base);
 979 err:
 980         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
 981         release_mem_region(res->start, res->end - res->start + 1);
 982         if (host)
 983                 mmc_free_host(mmc);
 984         return ret;
 985 }
 986
 987 static int omap_mmc_remove(struct platform_device *pdev)
 988 {
 989         struct mmc_omap_host *host = platform_get_drvdata(pdev);
 990         struct resource *res;
 991         u16 vdd = 0;
 992
 993         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 994         /*
 995          * Set the vdd back to 3V,
 996          * applicable for dual volt support.
 997          */
 998                 vdd = fls(host->mmc->ocr_avail) - 1;
 999                 if (omap_mmc_switch_opcond(host, vdd) != 0)
1000                         host->mmc->ios.vdd = vdd;
1001         }
1002
1003         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004         if (res)
1005                 release_mem_region(res->start, res->end - res->start + 1);
1006
1007         platform_set_drvdata(pdev, NULL);
1008         if (host) {
1009                 mmc_remove_host(host->mmc);
1010                 if (host->pdata->cleanup)
1011                         host->pdata->cleanup(&pdev->dev);
1012                 free_irq(host->irq, host);
1013                 if (mmc_slot(host).card_detect_irq)
1014                         free_irq(mmc_slot(host).card_detect_irq, host);
1015                 flush_scheduled_work();
1016
1017                 clk_disable(host->fclk);
1018                 clk_disable(host->iclk);
1019                 clk_put(host->fclk);
1020                 clk_put(host->iclk);
1021                 if (host->dbclk_enabled) {
1022                         clk_disable(host->dbclk);
1023                         clk_put(host->dbclk);
1024                 }
1025
1026                 mmc_free_host(host->mmc);
1027                 iounmap(host->base);
1028         }
1029
1030         return 0;
1031 }
1032
1033 #ifdef CONFIG_PM
1034 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1035 {
1036         int ret = 0;
1037         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1038
1039         if (host && host->suspended)
1040                 return 0;
1041
1042         if (host) {
1043                 ret = mmc_suspend_host(host->mmc, state);
1044                 if (ret == 0) {
1045                         host->suspended = 1;
1046
1047                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1048                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1049
1050                         if (host->pdata->suspend) {
1051                                 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1052                                 if (ret)
1053                                         dev_dbg(mmc_dev(host->mmc),
1054                                                 "Unable to handle MMC board"
1055                                                 " level suspend\n");
1056                         }
1057
1058                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1059                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1060                                         OMAP_HSMMC_READ(host->base, HCTL)
1061                                         & SDVSCLR);
1062                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1063                                         OMAP_HSMMC_READ(host->base, HCTL)
1064                                         | SDVS30);
1065                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1066                                         OMAP_HSMMC_READ(host->base, HCTL)
1067                                         | SDBP);
1068                         }
1069
1070                         clk_disable(host->fclk);
1071                         clk_disable(host->iclk);
1072                         clk_disable(host->dbclk);
1073                 }
1074
1075         }
1076         return ret;
1077 }
1078
1079 /* Routine to resume the MMC device */
1080 static int omap_mmc_resume(struct platform_device *pdev)
1081 {
1082         int ret = 0;
1083         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1084
1085         if (host && !host->suspended)
1086                 return 0;
1087
1088         if (host) {
1089
1090                 ret = clk_enable(host->fclk);
1091                 if (ret)
1092                         goto clk_en_err;
1093
1094                 ret = clk_enable(host->iclk);
1095                 if (ret) {
1096                         clk_disable(host->fclk);
1097                         clk_put(host->fclk);
1098                         goto clk_en_err;
1099                 }
1100
1101                 if (clk_enable(host->dbclk) != 0)
1102                         dev_dbg(mmc_dev(host->mmc),
1103                                         "Enabling debounce clk failed\n");
1104
1105                 if (host->pdata->resume) {
1106                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1107                         if (ret)
1108                                 dev_dbg(mmc_dev(host->mmc),
1109                                         "Unmask interrupt failed\n");
1110                 }
1111
1112                 /* Notify the core to resume the host */
1113                 ret = mmc_resume_host(host->mmc);
1114                 if (ret == 0)
1115                         host->suspended = 0;
1116         }
1117
1118         return ret;
1119
1120 clk_en_err:
1121         dev_dbg(mmc_dev(host->mmc),
1122                 "Failed to enable MMC clocks during resume\n");
1123         return ret;
1124 }
1125
1126 #else
1127 #define omap_mmc_suspend        NULL
1128 #define omap_mmc_resume         NULL
1129 #endif
1130
1131 static struct platform_driver omap_mmc_driver = {
1132         .probe          = omap_mmc_probe,
1133         .remove         = omap_mmc_remove,
1134         .suspend        = omap_mmc_suspend,
1135         .resume         = omap_mmc_resume,
1136         .driver         = {
1137                 .name = DRIVER_NAME,
1138                 .owner = THIS_MODULE,
1139         },
1140 };
1141
1142 static int __init omap_mmc_init(void)
1143 {
1144         /* Register the MMC driver */
1145         return platform_driver_register(&omap_mmc_driver);
1146 }
1147
1148 static void __exit omap_mmc_cleanup(void)
1149 {
1150         /* Unregister MMC driver */
1151         platform_driver_unregister(&omap_mmc_driver);
1152 }
1153
1154 module_init(omap_mmc_init);
1155 module_exit(omap_mmc_cleanup);
1156
1157 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1158 MODULE_LICENSE("GPL");
1159 MODULE_ALIAS("platform:" DRIVER_NAME);
1160 MODULE_AUTHOR("Texas Instruments Inc");