2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_device.h>
24 #include <linux/workqueue.h>
25 #include <linux/timer.h>
26 #include <linux/clk.h>
27 #include <linux/mmc/host.h>
29 #include <linux/semaphore.h>
31 #include <mach/hardware.h>
32 #include <mach/board.h>
36 /* OMAP HSMMC Host Controller Registers */
37 #define OMAP_HSMMC_SYSCONFIG 0x0010
38 #define OMAP_HSMMC_CON 0x002C
39 #define OMAP_HSMMC_BLK 0x0104
40 #define OMAP_HSMMC_ARG 0x0108
41 #define OMAP_HSMMC_CMD 0x010C
42 #define OMAP_HSMMC_RSP10 0x0110
43 #define OMAP_HSMMC_RSP32 0x0114
44 #define OMAP_HSMMC_RSP54 0x0118
45 #define OMAP_HSMMC_RSP76 0x011C
46 #define OMAP_HSMMC_DATA 0x0120
47 #define OMAP_HSMMC_HCTL 0x0128
48 #define OMAP_HSMMC_SYSCTL 0x012C
49 #define OMAP_HSMMC_STAT 0x0130
50 #define OMAP_HSMMC_IE 0x0134
51 #define OMAP_HSMMC_ISE 0x0138
52 #define OMAP_HSMMC_CAPA 0x0140
56 #define SDVS18 (0x5<<9)
57 #define SDVS30 (0x6<<9)
58 #define SDVSCLR 0xFFFFF1FF
59 #define SDVSDET 0x00000400
66 #define CLKD_MASK 0x0000FFC0
68 #define DTO_MASK 0x000F0000
70 #define INT_EN_MASK 0x307F0033
71 #define INIT_STREAM (1<<1)
72 #define DP_SELECT (1<<21)
77 #define FOUR_BIT 1 << 1
82 #define CMD_TIMEOUT (1 << 16)
83 #define DATA_TIMEOUT (1 << 20)
84 #define CMD_CRC (1 << 17)
85 #define DATA_CRC (1 << 21)
86 #define CARD_ERR (1 << 28)
87 #define STAT_CLEAR 0xFFFFFFFF
88 #define INIT_STREAM_CMD 0x00000000
89 #define DUAL_VOLT_OCR_BIT 7
94 * FIXME: Most likely all the data using these _DEVID defines should come
95 * from the platform_data, or implemented in controller and slot specific
98 #define OMAP_MMC1_DEVID 0
99 #define OMAP_MMC2_DEVID 1
101 #define OMAP_MMC_DATADIR_NONE 0
102 #define OMAP_MMC_DATADIR_READ 1
103 #define OMAP_MMC_DATADIR_WRITE 2
104 #define MMC_TIMEOUT_MS 20
105 #define OMAP_MMC_MASTER_CLOCK 96000000
106 #define DRIVER_NAME "mmci-omap"
109 * One controller can have multiple slots, like on some omap boards using
110 * omap.c controller driver. Luckily this is not currently done on any known
111 * omap_hsmmc.c device.
113 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
116 * MMC Host controller read/write API's
118 #define OMAP_HSMMC_READ(base, reg) \
119 __raw_readl((base) + OMAP_HSMMC_##reg)
121 #define OMAP_HSMMC_WRITE(base, reg, val) \
122 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
124 struct mmc_omap_host {
126 struct mmc_host *mmc;
127 struct mmc_request *mrq;
128 struct mmc_command *cmd;
129 struct mmc_data *data;
133 struct semaphore sem;
134 struct work_struct mmc_carddetect_work;
136 resource_size_t mapbase;
138 unsigned int dma_len;
139 unsigned int dma_dir;
140 unsigned char bus_mode;
141 unsigned char datadir;
151 struct omap_mmc_platform_data *pdata;
155 * Stop clock to the card
157 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
159 OMAP_HSMMC_WRITE(host->base, SYSCTL,
160 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
161 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
162 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
166 * Send init stream sequence to card
167 * before sending IDLE command
169 static void send_init_stream(struct mmc_omap_host *host)
172 unsigned long timeout;
174 disable_irq(host->irq);
175 OMAP_HSMMC_WRITE(host->base, CON,
176 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
177 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
179 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
180 while ((reg != CC) && time_before(jiffies, timeout))
181 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
183 OMAP_HSMMC_WRITE(host->base, CON,
184 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
185 enable_irq(host->irq);
189 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
191 if (host->pdata->slots[host->slot_id].get_cover_state)
192 return host->pdata->slots[host->slot_id].get_cover_state(host->dev, host->slot_id);
197 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
200 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
201 struct mmc_omap_host *host = mmc_priv(mmc);
203 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
207 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
210 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
213 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
214 struct mmc_omap_host *host = mmc_priv(mmc);
215 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
217 return sprintf(buf, "slot:%s\n", slot.name);
220 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
223 * Configure the response type and send the cmd.
226 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
227 struct mmc_data *data)
229 int cmdreg = 0, resptype = 0, cmdtype = 0;
231 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
232 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
236 * Clear status bits and enable interrupts
238 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
239 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
240 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
242 if (cmd->flags & MMC_RSP_PRESENT) {
243 if (cmd->flags & MMC_RSP_136)
250 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
251 * ac, bc, adtc, bcr. Only CMD12 needs a val of 0x3, rest 0x0.
253 if (cmd->opcode == 12)
256 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
259 cmdreg |= DP_SELECT | MSBS | BCE;
260 if (data->flags & MMC_DATA_READ)
269 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
270 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
274 * Notify the transfer complete to MMC core
277 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
281 if (host->use_dma && host->dma_ch != -1)
282 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
285 host->datadir = OMAP_MMC_DATADIR_NONE;
288 data->bytes_xfered += data->blocks * (data->blksz);
290 data->bytes_xfered = 0;
294 mmc_request_done(host->mmc, data->mrq);
297 mmc_omap_start_command(host, data->stop, NULL);
301 * Notify the core about command completion
304 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
308 if (cmd->flags & MMC_RSP_PRESENT) {
309 if (cmd->flags & MMC_RSP_136) {
310 /* response type 2 */
311 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
312 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
313 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
314 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
316 /* response types 1, 1b, 3, 4, 5, 6 */
317 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
320 if (host->data == NULL || cmd->error) {
322 mmc_request_done(host->mmc, cmd->mrq);
327 * DMA clean up for command errors
329 static void mmc_dma_cleanup(struct mmc_omap_host *host)
331 host->data->error = -ETIMEDOUT;
333 if (host->use_dma && host->dma_ch != -1) {
334 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
336 omap_free_dma(host->dma_ch);
341 host->datadir = OMAP_MMC_DATADIR_NONE;
345 * Readable error output
347 #ifdef CONFIG_MMC_DEBUG
348 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
350 /* --- means reserved bit without definition at documentation */
351 static const char *mmc_omap_status_bits[] = {
352 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
353 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
354 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
355 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
359 dev_dbg(mmc_dev(host->mmc), "MMC IRQ 0x%x :", status);
361 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
362 if (status & (1 << i))
364 * KERN_* facility is not used here because this should
365 * print a single line.
367 printk(" %s", mmc_omap_status_bits[i]);
372 #endif /* CONFIG_MMC_DEBUG */
376 * MMC controller IRQ handler
378 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
380 struct mmc_omap_host *host = dev_id;
381 struct mmc_data *data;
382 int end_cmd = 0, end_trans = 0, status;
384 if (host->cmd == NULL && host->data == NULL) {
385 OMAP_HSMMC_WRITE(host->base, STAT,
386 OMAP_HSMMC_READ(host->base, STAT));
391 status = OMAP_HSMMC_READ(host->base, STAT);
392 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
395 #ifdef CONFIG_MMC_DEBUG
396 mmc_omap_report_irq(host, status);
398 if ((status & CMD_TIMEOUT) ||
399 (status & CMD_CRC)) {
401 if (status & CMD_TIMEOUT) {
402 OMAP_HSMMC_WRITE(host->base, SYSCTL,
403 OMAP_HSMMC_READ(host->base,
405 while (OMAP_HSMMC_READ(host->base,
407 host->cmd->error = -ETIMEDOUT;
409 host->cmd->error = -EILSEQ;
414 mmc_dma_cleanup(host);
416 if ((status & DATA_TIMEOUT) ||
417 (status & DATA_CRC)) {
419 if (status & DATA_TIMEOUT)
420 mmc_dma_cleanup(host);
422 host->data->error = -EILSEQ;
423 OMAP_HSMMC_WRITE(host->base, SYSCTL,
424 OMAP_HSMMC_READ(host->base,
426 while (OMAP_HSMMC_READ(host->base,
431 if (status & CARD_ERR) {
432 dev_dbg(mmc_dev(host->mmc),
433 "Ignoring card err CMD%d\n", host->cmd->opcode);
441 OMAP_HSMMC_WRITE(host->base, STAT, status);
443 if (end_cmd || (status & CC))
444 mmc_omap_cmd_done(host, host->cmd);
445 if (end_trans || (status & TC))
446 mmc_omap_xfer_done(host, data);
452 * Switch MMC operating voltage
454 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
459 /* Disable the clocks */
460 clk_disable(host->fclk);
461 clk_disable(host->iclk);
462 clk_disable(host->dbclk);
464 /* Turn the power off */
465 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
469 /* Turn the power ON with given VDD 1.8 or 3.0v */
470 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
474 clk_enable(host->fclk);
475 clk_enable(host->iclk);
476 clk_enable(host->dbclk);
478 OMAP_HSMMC_WRITE(host->base, HCTL,
479 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
480 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
482 * If a MMC dual voltage card is detected, the set_ios fn calls
483 * this fn with VDD bit set for 1.8V. Upon card removal from the
484 * slot, mmc_omap_detect fn sets the VDD back to 3V.
486 * Only MMC1 supports 3.0V. MMC2 will not function if SDVS30 is
489 if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
490 ((1 << vdd) == MMC_VDD_33_34)))
492 if ((1 << vdd) == MMC_VDD_165_195)
495 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
497 OMAP_HSMMC_WRITE(host->base, HCTL,
498 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
502 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
507 * Work Item to notify the core about card insertion/removal
509 static void mmc_omap_detect(struct work_struct *work)
512 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
513 mmc_carddetect_work);
515 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
516 if (host->carddetect) {
517 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
519 * Set the VDD back to 3V when the card is removed
520 * before the set_ios fn turns off the power.
522 vdd = fls(host->mmc->ocr_avail) - 1;
523 if (omap_mmc_switch_opcond(host, vdd) != 0)
524 host->mmc->ios.vdd = vdd;
526 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
528 OMAP_HSMMC_WRITE(host->base, SYSCTL,
529 OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
530 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD) ;
531 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
536 * ISR for handling card insertion and removal
538 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
540 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
542 host->carddetect = mmc_slot(host).card_detect(irq);
543 schedule_work(&host->mmc_carddetect_work);
549 * DMA call back function
551 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
553 struct mmc_omap_host *host = data;
555 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
556 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
558 if (host->dma_ch < 0)
561 omap_free_dma(host->dma_ch);
564 * DMA Callback: run in interrupt context.
565 * mutex_unlock will through a kernel warning if used.
571 * Configure dma src and destination parameters
573 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
574 struct mmc_data *data)
577 omap_set_dma_dest_params(host->dma_ch, 0,
578 OMAP_DMA_AMODE_CONSTANT,
579 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
580 omap_set_dma_src_params(host->dma_ch, 0,
581 OMAP_DMA_AMODE_POST_INC,
582 sg_dma_address(&data->sg[0]), 0, 0);
584 omap_set_dma_src_params(host->dma_ch, 0,
585 OMAP_DMA_AMODE_CONSTANT,
586 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
587 omap_set_dma_dest_params(host->dma_ch, 0,
588 OMAP_DMA_AMODE_POST_INC,
589 sg_dma_address(&data->sg[0]), 0, 0);
594 * Routine to configure and start DMA for the MMC card
597 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
599 int sync_dev, sync_dir = 0;
600 int dma_ch = 0, ret = 0, err = 1;
601 struct mmc_data *data = req->data;
604 * If for some reason the DMA transfer is still active,
605 * we wait for timeout period and free the dma
607 if (host->dma_ch != -1) {
608 set_current_state(TASK_UNINTERRUPTIBLE);
609 schedule_timeout(100);
610 if (down_trylock(&host->sem)) {
611 omap_free_dma(host->dma_ch);
617 if (down_trylock(&host->sem))
621 if (!(data->flags & MMC_DATA_WRITE)) {
622 host->dma_dir = DMA_FROM_DEVICE;
623 if (host->id == OMAP_MMC1_DEVID)
624 sync_dev = OMAP24XX_DMA_MMC1_RX;
626 sync_dev = OMAP24XX_DMA_MMC2_RX;
628 host->dma_dir = DMA_TO_DEVICE;
629 if (host->id == OMAP_MMC1_DEVID)
630 sync_dev = OMAP24XX_DMA_MMC1_TX;
632 sync_dev = OMAP24XX_DMA_MMC2_TX;
635 ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
638 dev_dbg(mmc_dev(host->mmc),
639 "%s: omap_request_dma() failed with %d\n",
640 mmc_hostname(host->mmc), ret);
644 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
645 data->sg_len, host->dma_dir);
646 host->dma_ch = dma_ch;
648 if (!(data->flags & MMC_DATA_WRITE))
649 mmc_omap_config_dma_param(1, host, data);
651 mmc_omap_config_dma_param(0, host, data);
653 if ((data->blksz % 4) == 0)
654 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
655 (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
658 /* REVISIT: The MMC buffer increments only when MSB is written.
659 * Return error for blksz which is non multiple of four.
663 omap_start_dma(dma_ch);
667 static void set_data_timeout(struct mmc_omap_host *host,
668 struct mmc_request *req)
670 unsigned int timeout, cycle_ns;
671 uint32_t reg, clkd, dto = 0;
673 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
674 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
678 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
679 timeout = req->data->timeout_ns / cycle_ns;
680 timeout += req->data->timeout_clks;
682 while ((timeout & 0x80000000) == 0) {
699 reg |= dto << DTO_SHIFT;
700 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
704 * Configure block length for MMC/SD cards and initiate the transfer.
707 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
710 host->data = req->data;
712 if (req->data == NULL) {
713 host->datadir = OMAP_MMC_DATADIR_NONE;
714 OMAP_HSMMC_WRITE(host->base, BLK, 0);
718 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
719 | (req->data->blocks << 16));
720 set_data_timeout(host, req);
722 host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
723 OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
726 ret = mmc_omap_start_dma_transfer(host, req);
728 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
736 * Request function. for read/write operation
738 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
740 struct mmc_omap_host *host = mmc_priv(mmc);
742 WARN_ON(host->mrq != NULL);
744 mmc_omap_prepare_data(host, req);
745 mmc_omap_start_command(host, req->cmd, req->data);
749 /* Routine to configure clock values. Exposed API to core */
750 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
752 struct mmc_omap_host *host = mmc_priv(mmc);
754 unsigned long regval;
755 unsigned long timeout;
757 switch (ios->power_mode) {
759 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
762 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
766 switch (mmc->ios.bus_width) {
767 case MMC_BUS_WIDTH_4:
768 OMAP_HSMMC_WRITE(host->base, HCTL,
769 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
771 case MMC_BUS_WIDTH_1:
772 OMAP_HSMMC_WRITE(host->base, HCTL,
773 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
777 if (host->id == OMAP_MMC1_DEVID) {
778 /* Only MMC1 can operate at 3V/1.8V */
779 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
780 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
782 * The mmc_select_voltage fn of the core does
783 * not seem to set the power_mode to
784 * MMC_POWER_UP upon recalculating the voltage.
787 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
788 dev_dbg(mmc_dev(host->mmc),
789 "Switch operation failed\n");
794 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
798 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
804 omap_mmc_stop_clock(host);
805 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
806 regval = regval & ~(CLKD_MASK);
807 regval = regval | (dsor << 6) | (DTO << 16);
808 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
809 OMAP_HSMMC_WRITE(host->base, SYSCTL,
810 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
812 /* Wait till the ICS bit is set */
813 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
814 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
815 && time_before(jiffies, timeout))
818 OMAP_HSMMC_WRITE(host->base, SYSCTL,
819 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
821 if (ios->power_mode == MMC_POWER_ON)
822 send_init_stream(host);
824 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
825 OMAP_HSMMC_WRITE(host->base, CON,
826 OMAP_HSMMC_READ(host->base, CON) | OD);
828 /* NOTE: Read only switch not supported yet */
829 static struct mmc_host_ops mmc_omap_ops = {
830 .request = omap_mmc_request,
831 .set_ios = omap_mmc_set_ios,
834 static int __init omap_mmc_probe(struct platform_device *pdev)
836 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
837 struct mmc_host *mmc;
838 struct mmc_omap_host *host = NULL;
839 struct resource *res;
844 dev_err(&pdev->dev, "Platform Data is missing\n");
848 if (pdata->nr_slots == 0) {
849 dev_err(&pdev->dev, "No Slots\n");
853 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
854 irq = platform_get_irq(pdev, 0);
855 if (res == NULL || irq < 0)
858 res = request_mem_region(res->start, res->end - res->start + 1,
863 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
869 host = mmc_priv(mmc);
872 host->dev = &pdev->dev;
874 host->dev->dma_mask = &pdata->dma_mask;
879 host->mapbase = res->start;
880 host->base = ioremap(host->mapbase, SZ_4K);
881 mmc->ops = &mmc_omap_ops;
883 mmc->f_max = 52000000;
885 sema_init(&host->sem, 1);
887 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
888 if (IS_ERR(host->iclk)) {
889 ret = PTR_ERR(host->iclk);
893 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
894 if (IS_ERR(host->fclk)) {
895 ret = PTR_ERR(host->fclk);
901 if (clk_enable(host->fclk) != 0) {
907 if (clk_enable(host->iclk) != 0) {
908 clk_disable(host->fclk);
914 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
916 * MMC can still work without debounce clock.
918 if (IS_ERR(host->dbclk))
919 dev_dbg(mmc_dev(host->mmc), "Failed to get debounce clock\n");
921 if (clk_enable(host->dbclk) != 0)
922 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
925 host->dbclk_enabled = 1;
927 #ifdef CONFIG_MMC_BLOCK_BOUNCE
928 mmc->max_phys_segs = 1;
929 mmc->max_hw_segs = 1;
931 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
932 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
933 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
934 mmc->max_seg_size = mmc->max_req_size;
936 mmc->ocr_avail = mmc_slot(host).ocr_mask;
937 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
939 if (pdata->slots[host->slot_id].wire4)
940 mmc->caps |= MMC_CAP_4_BIT_DATA;
942 /* Only MMC1 supports 3.0V */
943 if (host->id == OMAP_MMC1_DEVID) {
951 OMAP_HSMMC_WRITE(host->base, HCTL,
952 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
954 OMAP_HSMMC_WRITE(host->base, CAPA,
955 OMAP_HSMMC_READ(host->base, CAPA) | capa);
957 /* Set the controller to AUTO IDLE mode */
958 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
959 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
961 /* Set SD bus power bit */
962 OMAP_HSMMC_WRITE(host->base, HCTL,
963 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
965 /* Request IRQ for MMC operations */
966 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
967 mmc_hostname(mmc), host);
969 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
973 /* Request IRQ for card detect */
974 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
975 ret = request_irq(mmc_slot(host).card_detect_irq,
977 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
979 mmc_hostname(mmc), host);
981 dev_dbg(mmc_dev(host->mmc),
982 "Unable to grab MMC CD IRQ\n");
987 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
988 if (pdata->init != NULL) {
989 if (pdata->init(&pdev->dev) != 0) {
990 dev_dbg(mmc_dev(host->mmc),
991 "Unable to configure MMC IRQs\n");
992 goto err_irq_cd_init;
996 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
997 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
999 platform_set_drvdata(pdev, host);
1002 if (host->pdata->slots[host->slot_id].name != NULL) {
1003 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1007 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1008 host->pdata->slots[host->slot_id].get_cover_state) {
1009 ret = device_create_file(&mmc->class_dev, &dev_attr_cover_switch);
1011 goto err_cover_switch;
1017 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1019 mmc_remove_host(mmc);
1021 free_irq(mmc_slot(host).card_detect_irq, host);
1023 free_irq(host->irq, host);
1025 clk_disable(host->fclk);
1026 clk_disable(host->iclk);
1027 clk_put(host->fclk);
1028 clk_put(host->iclk);
1029 if (host->dbclk_enabled) {
1030 clk_disable(host->dbclk);
1031 clk_put(host->dbclk);
1035 iounmap(host->base);
1037 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1038 release_mem_region(res->start, res->end - res->start + 1);
1044 static int omap_mmc_remove(struct platform_device *pdev)
1046 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1047 struct resource *res;
1050 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1052 * Set the vdd back to 3V,
1053 * applicable for dual volt support.
1055 vdd = fls(host->mmc->ocr_avail) - 1;
1056 if (omap_mmc_switch_opcond(host, vdd) != 0)
1057 host->mmc->ios.vdd = vdd;
1060 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1062 release_mem_region(res->start, res->end - res->start + 1);
1064 platform_set_drvdata(pdev, NULL);
1066 mmc_remove_host(host->mmc);
1067 if (host->pdata->cleanup)
1068 host->pdata->cleanup(&pdev->dev);
1069 free_irq(host->irq, host);
1070 if (mmc_slot(host).card_detect_irq)
1071 free_irq(mmc_slot(host).card_detect_irq, host);
1072 flush_scheduled_work();
1074 clk_disable(host->fclk);
1075 clk_disable(host->iclk);
1076 clk_put(host->fclk);
1077 clk_put(host->iclk);
1078 if (host->dbclk_enabled) {
1079 clk_disable(host->dbclk);
1080 clk_put(host->dbclk);
1083 mmc_free_host(host->mmc);
1084 iounmap(host->base);
1091 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1094 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1096 if (host && host->suspended)
1100 ret = mmc_suspend_host(host->mmc, state);
1102 host->suspended = 1;
1104 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1105 OMAP_HSMMC_WRITE(host->base, IE, 0);
1107 if (host->pdata->suspend) {
1108 ret = host->pdata->suspend(&pdev->dev, host->slot_id);
1110 dev_dbg(mmc_dev(host->mmc),
1111 "Unable to handle MMC board"
1112 " level suspend\n");
1115 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1116 OMAP_HSMMC_WRITE(host->base, HCTL,
1117 OMAP_HSMMC_READ(host->base, HCTL)
1119 OMAP_HSMMC_WRITE(host->base, HCTL,
1120 OMAP_HSMMC_READ(host->base, HCTL)
1122 OMAP_HSMMC_WRITE(host->base, HCTL,
1123 OMAP_HSMMC_READ(host->base, HCTL)
1127 clk_disable(host->fclk);
1128 clk_disable(host->iclk);
1129 clk_disable(host->dbclk);
1136 /* Routine to resume the MMC device */
1137 static int omap_mmc_resume(struct platform_device *pdev)
1140 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1142 if (host && !host->suspended)
1147 ret = clk_enable(host->fclk);
1151 ret = clk_enable(host->iclk);
1153 clk_disable(host->fclk);
1154 clk_put(host->fclk);
1158 if (clk_enable(host->dbclk) != 0)
1159 dev_dbg(mmc_dev(host->mmc),
1160 "Enabling debounce clk failed\n");
1162 if (host->pdata->resume) {
1163 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1165 dev_dbg(mmc_dev(host->mmc),
1166 "Unmask interrupt failed\n");
1169 /* Notify the core to resume the host */
1170 ret = mmc_resume_host(host->mmc);
1172 host->suspended = 0;
1178 dev_dbg(mmc_dev(host->mmc),
1179 "Failed to enable MMC clocks during resume\n");
1184 #define omap_mmc_suspend NULL
1185 #define omap_mmc_resume NULL
1188 static struct platform_driver omap_mmc_driver = {
1189 .probe = omap_mmc_probe,
1190 .remove = omap_mmc_remove,
1191 .suspend = omap_mmc_suspend,
1192 .resume = omap_mmc_resume,
1194 .name = DRIVER_NAME,
1195 .owner = THIS_MODULE,
1199 static int __init omap_mmc_init(void)
1201 /* Register the MMC driver */
1202 return platform_driver_register(&omap_mmc_driver);
1205 static void __exit omap_mmc_cleanup(void)
1207 /* Unregister MMC driver */
1208 platform_driver_unregister(&omap_mmc_driver);
1211 module_init(omap_mmc_init);
1212 module_exit(omap_mmc_cleanup);
1214 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1215 MODULE_LICENSE("GPL");
1216 MODULE_ALIAS("platform:" DRIVER_NAME);
1217 MODULE_AUTHOR("Texas Instruments Inc");