drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/media/mmc/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/scatterlist.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39 #include <asm/arch/tps65010.h>
  40 #include <asm/arch/board-sx1.h>
  41
  42 #define OMAP_MMC_REG_CMD        0x00
  43 #define OMAP_MMC_REG_ARGL       0x04
  44 #define OMAP_MMC_REG_ARGH       0x08
  45 #define OMAP_MMC_REG_CON        0x0c
  46 #define OMAP_MMC_REG_STAT       0x10
  47 #define OMAP_MMC_REG_IE         0x14
  48 #define OMAP_MMC_REG_CTO        0x18
  49 #define OMAP_MMC_REG_DTO        0x1c
  50 #define OMAP_MMC_REG_DATA       0x20
  51 #define OMAP_MMC_REG_BLEN       0x24
  52 #define OMAP_MMC_REG_NBLK       0x28
  53 #define OMAP_MMC_REG_BUF        0x2c
  54 #define OMAP_MMC_REG_SDIO       0x34
  55 #define OMAP_MMC_REG_REV        0x3c
  56 #define OMAP_MMC_REG_RSP0       0x40
  57 #define OMAP_MMC_REG_RSP1       0x44
  58 #define OMAP_MMC_REG_RSP2       0x48
  59 #define OMAP_MMC_REG_RSP3       0x4c
  60 #define OMAP_MMC_REG_RSP4       0x50
  61 #define OMAP_MMC_REG_RSP5       0x54
  62 #define OMAP_MMC_REG_RSP6       0x58
  63 #define OMAP_MMC_REG_RSP7       0x5c
  64 #define OMAP_MMC_REG_IOSR       0x60
  65 #define OMAP_MMC_REG_SYSC       0x64
  66 #define OMAP_MMC_REG_SYSS       0x68
  67
  68 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  69 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  70 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  71 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  72 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  73 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  74 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  75 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  76 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  77 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  78 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  79 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  80 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  81
  82 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  83 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  84
  85 /*
  86  * Command types
  87  */
  88 #define OMAP_MMC_CMDTYPE_BC     0
  89 #define OMAP_MMC_CMDTYPE_BCR    1
  90 #define OMAP_MMC_CMDTYPE_AC     2
  91 #define OMAP_MMC_CMDTYPE_ADTC   3
  92
  93
  94 #define DRIVER_NAME "mmci-omap"
  95
  96 /* Specifies how often in millisecs to poll for card status changes
  97  * when the cover switch is open */
  98 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  99
 100 static int mmc_omap_enable_poll = 1;
 101
 102 struct mmc_omap_host {
 103         int                     initialized;
 104         int                     suspended;
 105         struct mmc_request *    mrq;
 106         struct mmc_command *    cmd;
 107         struct mmc_data *       data;
 108         struct mmc_host *       mmc;
 109         struct device *         dev;
 110         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 111         struct clk *            iclk;
 112         struct clk *            fclk;
 113         struct resource         *mem_res;
 114         void __iomem            *virt_base;
 115         unsigned int            phys_base;
 116         int                     irq;
 117         unsigned char           bus_mode;
 118         unsigned char           hw_bus_mode;
 119
 120         unsigned int            sg_len;
 121         int                     sg_idx;
 122         u16 *                   buffer;
 123         u32                     buffer_bytes_left;
 124         u32                     total_bytes_left;
 125
 126         unsigned                use_dma:1;
 127         unsigned                brs_received:1, dma_done:1;
 128         unsigned                dma_is_read:1;
 129         unsigned                dma_in_use:1;
 130         int                     dma_ch;
 131         spinlock_t              dma_lock;
 132         struct timer_list       dma_timer;
 133         unsigned                dma_len;
 134
 135         short                   power_pin;
 136         short                   wp_pin;
 137
 138         int                     switch_pin;
 139         struct work_struct      switch_work;
 140         struct timer_list       switch_timer;
 141         int                     switch_last_state;
 142 };
 143
 144 static inline int
 145 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 146 {
 147         if (host->switch_pin < 0)
 148                 return 0;
 149         return omap_get_gpio_datain(host->switch_pin);
 150 }
 151
 152 static ssize_t
 153 mmc_omap_show_cover_switch(struct device *dev,
 154         struct device_attribute *attr, char *buf)
 155 {
 156         struct mmc_omap_host *host = dev_get_drvdata(dev);
 157
 158         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
 159                         "closed");
 160 }
 161
 162 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 163
 164 static ssize_t
 165 mmc_omap_show_enable_poll(struct device *dev,
 166         struct device_attribute *attr, char *buf)
 167 {
 168         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 169 }
 170
 171 static ssize_t
 172 mmc_omap_store_enable_poll(struct device *dev,
 173         struct device_attribute *attr, const char *buf,
 174         size_t size)
 175 {
 176         int enable_poll;
 177
 178         if (sscanf(buf, "%10d", &enable_poll) != 1)
 179                 return -EINVAL;
 180
 181         if (enable_poll != mmc_omap_enable_poll) {
 182                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 183
 184                 mmc_omap_enable_poll = enable_poll;
 185                 if (enable_poll && host->switch_pin >= 0)
 186                         schedule_work(&host->switch_work);
 187         }
 188         return size;
 189 }
 190
 191 static DEVICE_ATTR(enable_poll, 0664,
 192                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 193
 194 static void
 195 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 196 {
 197         u32 cmdreg;
 198         u32 resptype;
 199         u32 cmdtype;
 200
 201         host->cmd = cmd;
 202
 203         resptype = 0;
 204         cmdtype = 0;
 205
 206         /* Our hardware needs to know exact type */
 207         switch (mmc_resp_type(cmd)) {
 208         case MMC_RSP_NONE:
 209                 break;
 210         case MMC_RSP_R1:
 211         case MMC_RSP_R1B:
 212                 /* resp 1, 1b, 6, 7 */
 213                 resptype = 1;
 214                 break;
 215         case MMC_RSP_R2:
 216                 resptype = 2;
 217                 break;
 218         case MMC_RSP_R3:
 219                 resptype = 3;
 220                 break;
 221         default:
 222                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 223                 break;
 224         }
 225
 226         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 227                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 228         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 229                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 230         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 231                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 232         } else {
 233                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 234         }
 235
 236         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 237
 238         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 239                 cmdreg |= 1 << 6;
 240
 241         if (cmd->flags & MMC_RSP_BUSY)
 242                 cmdreg |= 1 << 11;
 243
 244         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 245                 cmdreg |= 1 << 15;
 246
 247         clk_enable(host->fclk);
 248
 249         OMAP_MMC_WRITE(host, CTO, 200);
 250         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 251         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 252         OMAP_MMC_WRITE(host, IE,
 253                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 254                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 255                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 256                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 257                        OMAP_MMC_STAT_END_OF_DATA);
 258         OMAP_MMC_WRITE(host, CMD, cmdreg);
 259 }
 260
 261 static void
 262 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 263 {
 264         if (host->dma_in_use) {
 265                 enum dma_data_direction dma_data_dir;
 266
 267                 BUG_ON(host->dma_ch < 0);
 268                 if (data->error != MMC_ERR_NONE)
 269                         omap_stop_dma(host->dma_ch);
 270                 /* Release DMA channel lazily */
 271                 mod_timer(&host->dma_timer, jiffies + HZ);
 272                 if (data->flags & MMC_DATA_WRITE)
 273                         dma_data_dir = DMA_TO_DEVICE;
 274                 else
 275                         dma_data_dir = DMA_FROM_DEVICE;
 276                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 277                              dma_data_dir);
 278         }
 279         host->data = NULL;
 280         host->sg_len = 0;
 281         clk_disable(host->fclk);
 282
 283         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 284          * dozens of requests until the card finishes writing data.
 285          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 286          */
 287
 288         if (!data->stop) {
 289                 host->mrq = NULL;
 290                 mmc_request_done(host->mmc, data->mrq);
 291                 return;
 292         }
 293
 294         mmc_omap_start_command(host, data->stop);
 295 }
 296
 297 static void
 298 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 299 {
 300         unsigned long flags;
 301         int done;
 302
 303         if (!host->dma_in_use) {
 304                 mmc_omap_xfer_done(host, data);
 305                 return;
 306         }
 307         done = 0;
 308         spin_lock_irqsave(&host->dma_lock, flags);
 309         if (host->dma_done)
 310                 done = 1;
 311         else
 312                 host->brs_received = 1;
 313         spin_unlock_irqrestore(&host->dma_lock, flags);
 314         if (done)
 315                 mmc_omap_xfer_done(host, data);
 316 }
 317
 318 static void
 319 mmc_omap_dma_timer(unsigned long data)
 320 {
 321         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 322
 323         BUG_ON(host->dma_ch < 0);
 324         omap_free_dma(host->dma_ch);
 325         host->dma_ch = -1;
 326 }
 327
 328 static void
 329 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 330 {
 331         unsigned long flags;
 332         int done;
 333
 334         done = 0;
 335         spin_lock_irqsave(&host->dma_lock, flags);
 336         if (host->brs_received)
 337                 done = 1;
 338         else
 339                 host->dma_done = 1;
 340         spin_unlock_irqrestore(&host->dma_lock, flags);
 341         if (done)
 342                 mmc_omap_xfer_done(host, data);
 343 }
 344
 345 static void
 346 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 347 {
 348         host->cmd = NULL;
 349
 350         if (cmd->flags & MMC_RSP_PRESENT) {
 351                 if (cmd->flags & MMC_RSP_136) {
 352                         /* response type 2 */
 353                         cmd->resp[3] =
 354                                 OMAP_MMC_READ(host, RSP0) |
 355                                 (OMAP_MMC_READ(host, RSP1) << 16);
 356                         cmd->resp[2] =
 357                                 OMAP_MMC_READ(host, RSP2) |
 358                                 (OMAP_MMC_READ(host, RSP3) << 16);
 359                         cmd->resp[1] =
 360                                 OMAP_MMC_READ(host, RSP4) |
 361                                 (OMAP_MMC_READ(host, RSP5) << 16);
 362                         cmd->resp[0] =
 363                                 OMAP_MMC_READ(host, RSP6) |
 364                                 (OMAP_MMC_READ(host, RSP7) << 16);
 365                 } else {
 366                         /* response types 1, 1b, 3, 4, 5, 6 */
 367                         cmd->resp[0] =
 368                                 OMAP_MMC_READ(host, RSP6) |
 369                                 (OMAP_MMC_READ(host, RSP7) << 16);
 370                 }
 371         }
 372
 373         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
 374                 host->mrq = NULL;
 375                 clk_disable(host->fclk);
 376                 mmc_request_done(host->mmc, cmd->mrq);
 377         }
 378 }
 379
 380 /* PIO only */
 381 static void
 382 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 383 {
 384         struct scatterlist *sg;
 385
 386         sg = host->data->sg + host->sg_idx;
 387         host->buffer_bytes_left = sg->length;
 388         host->buffer = page_address(sg->page) + sg->offset;
 389         if (host->buffer_bytes_left > host->total_bytes_left)
 390                 host->buffer_bytes_left = host->total_bytes_left;
 391 }
 392
 393 /* PIO only */
 394 static void
 395 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 396 {
 397         int n;
 398
 399         if (host->buffer_bytes_left == 0) {
 400                 host->sg_idx++;
 401                 BUG_ON(host->sg_idx == host->sg_len);
 402                 mmc_omap_sg_to_buf(host);
 403         }
 404         n = 64;
 405         if (n > host->buffer_bytes_left)
 406                 n = host->buffer_bytes_left;
 407         host->buffer_bytes_left -= n;
 408         host->total_bytes_left -= n;
 409         host->data->bytes_xfered += n;
 410
 411         if (write) {
 412                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 413         } else {
 414                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 415         }
 416 }
 417
 418 static inline void mmc_omap_report_irq(u16 status)
 419 {
 420         static const char *mmc_omap_status_bits[] = {
 421                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 422                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 423         };
 424         int i, c = 0;
 425
 426         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 427                 if (status & (1 << i)) {
 428                         if (c)
 429                                 printk(" ");
 430                         printk("%s", mmc_omap_status_bits[i]);
 431                         c++;
 432                 }
 433 }
 434
 435 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 436 {
 437         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 438         u16 status;
 439         int end_command;
 440         int end_transfer;
 441         int transfer_error;
 442
 443         if (host->cmd == NULL && host->data == NULL) {
 444                 status = OMAP_MMC_READ(host, STAT);
 445                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 446                 if (status != 0) {
 447                         OMAP_MMC_WRITE(host, STAT, status);
 448                         OMAP_MMC_WRITE(host, IE, 0);
 449                 }
 450                 return IRQ_HANDLED;
 451         }
 452
 453         end_command = 0;
 454         end_transfer = 0;
 455         transfer_error = 0;
 456
 457         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 458                 OMAP_MMC_WRITE(host, STAT, status);
 459 #ifdef CONFIG_MMC_DEBUG
 460                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 461                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 462                 mmc_omap_report_irq(status);
 463                 printk("\n");
 464 #endif
 465                 if (host->total_bytes_left) {
 466                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 467                             (status & OMAP_MMC_STAT_END_OF_DATA))
 468                                 mmc_omap_xfer_data(host, 0);
 469                         if (status & OMAP_MMC_STAT_A_EMPTY)
 470                                 mmc_omap_xfer_data(host, 1);
 471                 }
 472
 473                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 474                         end_transfer = 1;
 475                 }
 476
 477                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 478                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 479                         if (host->data) {
 480                                 host->data->error |= MMC_ERR_TIMEOUT;
 481                                 transfer_error = 1;
 482                         }
 483                 }
 484
 485                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 486                         if (host->data) {
 487                                 host->data->error |= MMC_ERR_BADCRC;
 488                                 dev_dbg(mmc_dev(host->mmc),
 489                                          "data CRC error, bytes left %d\n",
 490                                         host->total_bytes_left);
 491                                 transfer_error = 1;
 492                         } else {
 493                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 494                         }
 495                 }
 496
 497                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 498                         /* Timeouts are routine with some commands */
 499                         if (host->cmd) {
 500                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 501                                                 host->cmd->opcode !=
 502                                                 MMC_SEND_OP_COND &&
 503                                                 host->cmd->opcode !=
 504                                                 MMC_APP_CMD &&
 505                                                 !mmc_omap_cover_is_open(host))
 506                                         dev_err(mmc_dev(host->mmc),
 507                                                 "command timeout, CMD %d\n",
 508                                                 host->cmd->opcode);
 509                                 host->cmd->error = MMC_ERR_TIMEOUT;
 510                                 end_command = 1;
 511                         }
 512                 }
 513
 514                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 515                         if (host->cmd) {
 516                                 dev_err(mmc_dev(host->mmc),
 517                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 518                                         host->cmd->opcode, host->cmd->arg);
 519                                 host->cmd->error = MMC_ERR_BADCRC;
 520                                 end_command = 1;
 521                         } else
 522                                 dev_err(mmc_dev(host->mmc),
 523                                         "command CRC error without cmd?\n");
 524                 }
 525
 526                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 527                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
 528                                 u32 response = OMAP_MMC_READ(host, RSP6)
 529                                         | (OMAP_MMC_READ(host, RSP7) << 16);
 530                                 /* STOP sometimes sets must-ignore bits */
 531                                 if (!(response & (R1_CC_ERROR
 532                                                                 | R1_ILLEGAL_COMMAND
 533                                                                 | R1_COM_CRC_ERROR))) {
 534                                         end_command = 1;
 535                                         continue;
 536                                 }
 537                         }
 538
 539                         dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
 540                                 host->cmd->opcode);
 541                         if (host->cmd) {
 542                                 host->cmd->error = MMC_ERR_FAILED;
 543                                 end_command = 1;
 544                         }
 545                         if (host->data) {
 546                                 host->data->error = MMC_ERR_FAILED;
 547                                 transfer_error = 1;
 548                         }
 549                 }
 550
 551                 /*
 552                  * NOTE: On 1610 the END_OF_CMD may come too early when
 553                  * starting a write
 554                  */
 555                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 556                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 557                         end_command = 1;
 558                 }
 559         }
 560
 561         if (end_command) {
 562                 mmc_omap_cmd_done(host, host->cmd);
 563         }
 564         if (transfer_error)
 565                 mmc_omap_xfer_done(host, host->data);
 566         else if (end_transfer)
 567                 mmc_omap_end_of_data(host, host->data);
 568
 569         return IRQ_HANDLED;
 570 }
 571
 572 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
 573 {
 574         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 575
 576         schedule_work(&host->switch_work);
 577
 578         return IRQ_HANDLED;
 579 }
 580
 581 static void mmc_omap_switch_timer(unsigned long arg)
 582 {
 583         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 584
 585         schedule_work(&host->switch_work);
 586 }
 587
 588 static void mmc_omap_switch_handler(struct work_struct *work)
 589 {
 590         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
 591         static int complained = 0;
 592         int cover_open;
 593
 594         if (host->switch_pin == -1)
 595                 return;
 596         cover_open = mmc_omap_cover_is_open(host);
 597         if (cover_open != host->switch_last_state) {
 598                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 599                 host->switch_last_state = cover_open;
 600         }
 601         mmc_detect_change(host->mmc, 0);
 602         if (mmc_omap_cover_is_open(host)) {
 603                 if (!complained) {
 604                         dev_info(mmc_dev(host->mmc), "cover is open\n");
 605                         complained = 1;
 606                 }
 607                 if (mmc_omap_enable_poll)
 608                         mod_timer(&host->switch_timer, jiffies +
 609                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 610         } else {
 611                 complained = 0;
 612         }
 613 }
 614
 615 /* Prepare to transfer the next segment of a scatterlist */
 616 static void
 617 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 618 {
 619         int dma_ch = host->dma_ch;
 620         unsigned long data_addr;
 621         u16 buf, frame;
 622         u32 count;
 623         struct scatterlist *sg = &data->sg[host->sg_idx];
 624         int src_port = 0;
 625         int dst_port = 0;
 626         int sync_dev = 0;
 627
 628         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 629         frame = data->blksz;
 630         count = sg_dma_len(sg);
 631
 632         if ((data->blocks == 1) && (count > data->blksz))
 633                 count = frame;
 634
 635         host->dma_len = count;
 636
 637         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 638          * Use 16 or 32 word frames when the blocksize is at least that large.
 639          * Blocksize is usually 512 bytes; but not for some SD reads.
 640          */
 641         if (cpu_is_omap15xx() && frame > 32)
 642                 frame = 32;
 643         else if (frame > 64)
 644                 frame = 64;
 645         count /= frame;
 646         frame >>= 1;
 647
 648         if (!(data->flags & MMC_DATA_WRITE)) {
 649                 buf = 0x800f | ((frame - 1) << 8);
 650
 651                 if (cpu_class_is_omap1()) {
 652                         src_port = OMAP_DMA_PORT_TIPB;
 653                         dst_port = OMAP_DMA_PORT_EMIFF;
 654                 }
 655                 if (cpu_is_omap24xx())
 656                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 657
 658                 omap_set_dma_src_params(dma_ch, src_port,
 659                                         OMAP_DMA_AMODE_CONSTANT,
 660                                         data_addr, 0, 0);
 661                 omap_set_dma_dest_params(dma_ch, dst_port,
 662                                          OMAP_DMA_AMODE_POST_INC,
 663                                          sg_dma_address(sg), 0, 0);
 664                 omap_set_dma_dest_data_pack(dma_ch, 1);
 665                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 666         } else {
 667                 buf = 0x0f80 | ((frame - 1) << 0);
 668
 669                 if (cpu_class_is_omap1()) {
 670                         src_port = OMAP_DMA_PORT_EMIFF;
 671                         dst_port = OMAP_DMA_PORT_TIPB;
 672                 }
 673                 if (cpu_is_omap24xx())
 674                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 675
 676                 omap_set_dma_dest_params(dma_ch, dst_port,
 677                                          OMAP_DMA_AMODE_CONSTANT,
 678                                          data_addr, 0, 0);
 679                 omap_set_dma_src_params(dma_ch, src_port,
 680                                         OMAP_DMA_AMODE_POST_INC,
 681                                         sg_dma_address(sg), 0, 0);
 682                 omap_set_dma_src_data_pack(dma_ch, 1);
 683                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 684         }
 685
 686         /* Max limit for DMA frame count is 0xffff */
 687         BUG_ON(count > 0xffff);
 688
 689         OMAP_MMC_WRITE(host, BUF, buf);
 690         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 691                                      frame, count, OMAP_DMA_SYNC_FRAME,
 692                                      sync_dev, 0);
 693 }
 694
 695 /* A scatterlist segment completed */
 696 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 697 {
 698         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 699         struct mmc_data *mmcdat = host->data;
 700
 701         if (unlikely(host->dma_ch < 0)) {
 702                 dev_err(mmc_dev(host->mmc),
 703                         "DMA callback while DMA not enabled\n");
 704                 return;
 705         }
 706         /* FIXME: We really should do something to _handle_ the errors */
 707         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 708                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 709                 return;
 710         }
 711         if (ch_status & OMAP_DMA_DROP_IRQ) {
 712                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 713                 return;
 714         }
 715         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 716                 return;
 717         }
 718         mmcdat->bytes_xfered += host->dma_len;
 719         host->sg_idx++;
 720         if (host->sg_idx < host->sg_len) {
 721                 mmc_omap_prepare_dma(host, host->data);
 722                 omap_start_dma(host->dma_ch);
 723         } else
 724                 mmc_omap_dma_done(host, host->data);
 725 }
 726
 727 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 728 {
 729         const char *dev_name;
 730         int sync_dev, dma_ch, is_read, r;
 731
 732         is_read = !(data->flags & MMC_DATA_WRITE);
 733         del_timer_sync(&host->dma_timer);
 734         if (host->dma_ch >= 0) {
 735                 if (is_read == host->dma_is_read)
 736                         return 0;
 737                 omap_free_dma(host->dma_ch);
 738                 host->dma_ch = -1;
 739         }
 740
 741         if (is_read) {
 742                 if (host->id == 1) {
 743                         sync_dev = OMAP_DMA_MMC_RX;
 744                         dev_name = "MMC1 read";
 745                 } else {
 746                         sync_dev = OMAP_DMA_MMC2_RX;
 747                         dev_name = "MMC2 read";
 748                 }
 749         } else {
 750                 if (host->id == 1) {
 751                         sync_dev = OMAP_DMA_MMC_TX;
 752                         dev_name = "MMC1 write";
 753                 } else {
 754                         sync_dev = OMAP_DMA_MMC2_TX;
 755                         dev_name = "MMC2 write";
 756                 }
 757         }
 758         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 759                              host, &dma_ch);
 760         if (r != 0) {
 761                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 762                 return r;
 763         }
 764         host->dma_ch = dma_ch;
 765         host->dma_is_read = is_read;
 766
 767         return 0;
 768 }
 769
 770 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 771 {
 772         u16 reg;
 773
 774         reg = OMAP_MMC_READ(host, SDIO);
 775         reg &= ~(1 << 5);
 776         OMAP_MMC_WRITE(host, SDIO, reg);
 777         /* Set maximum timeout */
 778         OMAP_MMC_WRITE(host, CTO, 0xff);
 779 }
 780
 781 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 782 {
 783         int timeout;
 784         u16 reg;
 785
 786         /* Convert ns to clock cycles by assuming 20MHz frequency
 787          * 1 cycle at 20MHz = 500 ns
 788          */
 789         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 790
 791         /* Check if we need to use timeout multiplier register */
 792         reg = OMAP_MMC_READ(host, SDIO);
 793         if (timeout > 0xffff) {
 794                 reg |= (1 << 5);
 795                 timeout /= 1024;
 796         } else
 797                 reg &= ~(1 << 5);
 798         OMAP_MMC_WRITE(host, SDIO, reg);
 799         OMAP_MMC_WRITE(host, DTO, timeout);
 800 }
 801
 802 static void
 803 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 804 {
 805         struct mmc_data *data = req->data;
 806         int i, use_dma, block_size;
 807         unsigned sg_len;
 808
 809         host->data = data;
 810         if (data == NULL) {
 811                 OMAP_MMC_WRITE(host, BLEN, 0);
 812                 OMAP_MMC_WRITE(host, NBLK, 0);
 813                 OMAP_MMC_WRITE(host, BUF, 0);
 814                 host->dma_in_use = 0;
 815                 set_cmd_timeout(host, req);
 816                 return;
 817         }
 818
 819         block_size = data->blksz;
 820
 821         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 822         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 823         set_data_timeout(host, req);
 824
 825         /* cope with calling layer confusion; it issues "single
 826          * block" writes using multi-block scatterlists.
 827          */
 828         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 829
 830         /* Only do DMA for entire blocks */
 831         use_dma = host->use_dma;
 832         if (use_dma) {
 833                 for (i = 0; i < sg_len; i++) {
 834                         if ((data->sg[i].length % block_size) != 0) {
 835                                 use_dma = 0;
 836                                 break;
 837                         }
 838                 }
 839         }
 840
 841         host->sg_idx = 0;
 842         if (use_dma) {
 843                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 844                         enum dma_data_direction dma_data_dir;
 845
 846                         if (data->flags & MMC_DATA_WRITE)
 847                                 dma_data_dir = DMA_TO_DEVICE;
 848                         else
 849                                 dma_data_dir = DMA_FROM_DEVICE;
 850
 851                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 852                                                 sg_len, dma_data_dir);
 853                         host->total_bytes_left = 0;
 854                         mmc_omap_prepare_dma(host, req->data);
 855                         host->brs_received = 0;
 856                         host->dma_done = 0;
 857                         host->dma_in_use = 1;
 858                 } else
 859                         use_dma = 0;
 860         }
 861
 862         /* Revert to PIO? */
 863         if (!use_dma) {
 864                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 865                 host->total_bytes_left = data->blocks * block_size;
 866                 host->sg_len = sg_len;
 867                 mmc_omap_sg_to_buf(host);
 868                 host->dma_in_use = 0;
 869         }
 870 }
 871
 872 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 873 {
 874         struct mmc_omap_host *host = mmc_priv(mmc);
 875
 876         WARN_ON(host->mrq != NULL);
 877
 878         host->mrq = req;
 879
 880         /* only touch fifo AFTER the controller readies it */
 881         mmc_omap_prepare_data(host, req);
 882         mmc_omap_start_command(host, req->cmd);
 883         if (host->dma_in_use)
 884                 omap_start_dma(host->dma_ch);
 885 }
 886
 887 static void innovator_fpga_socket_power(int on)
 888 {
 889 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 890         if (on) {
 891                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 892                      OMAP1510_FPGA_POWER);
 893         } else {
 894                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 895                      OMAP1510_FPGA_POWER);
 896         }
 897 #endif
 898 }
 899
 900 /*
 901  * Turn the socket power on/off. Innovator uses FPGA, most boards
 902  * probably use GPIO.
 903  */
 904 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 905 {
 906         if (machine_is_sx1())
 907                 sx1_setmmcpower(on);
 908         else if (on) {
 909                 if (machine_is_omap_innovator())
 910                         innovator_fpga_socket_power(1);
 911                 else if (machine_is_omap_h2())
 912                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 913                 else if (machine_is_omap_h3())
 914                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 915                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 916                 else if (cpu_is_omap24xx()) {
 917                         u16 reg = OMAP_MMC_READ(host, CON);
 918                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 919                 } else
 920                         if (host->power_pin >= 0)
 921                                 omap_set_gpio_dataout(host->power_pin, 1);
 922         } else {
 923                 if (machine_is_omap_innovator())
 924                         innovator_fpga_socket_power(0);
 925                 else if (machine_is_omap_h2())
 926                         tps65010_set_gpio_out_value(GPIO3, LOW);
 927                 else if (machine_is_omap_h3())
 928                         tps65010_set_gpio_out_value(GPIO4, LOW);
 929                 else if (cpu_is_omap24xx()) {
 930                         u16 reg = OMAP_MMC_READ(host, CON);
 931                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 932                 } else
 933                         if (host->power_pin >= 0)
 934                                 omap_set_gpio_dataout(host->power_pin, 0);
 935         }
 936 }
 937
 938 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 939 {
 940         struct mmc_omap_host *host = mmc_priv(mmc);
 941         int func_clk_rate = clk_get_rate(host->fclk);
 942         int dsor;
 943
 944         if (ios->clock == 0)
 945                 return 0;
 946
 947         dsor = func_clk_rate / ios->clock;
 948         if (dsor < 1)
 949                 dsor = 1;
 950
 951         if (func_clk_rate / dsor > ios->clock)
 952                 dsor++;
 953
 954         if (dsor > 250)
 955                 dsor = 250;
 956         dsor++;
 957
 958         if (ios->bus_width == MMC_BUS_WIDTH_4)
 959                 dsor |= 1 << 15;
 960
 961         return dsor;
 962 }
 963
 964 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 965 {
 966         struct mmc_omap_host *host = mmc_priv(mmc);
 967         int dsor;
 968         int i;
 969
 970         dsor = mmc_omap_calc_divisor(mmc, ios);
 971         host->bus_mode = ios->bus_mode;
 972         host->hw_bus_mode = host->bus_mode;
 973
 974         switch (ios->power_mode) {
 975         case MMC_POWER_OFF:
 976                 mmc_omap_power(host, 0);
 977                 break;
 978         case MMC_POWER_UP:
 979                 /* Cannot touch dsor yet, just power up MMC */
 980                 mmc_omap_power(host, 1);
 981                 return;
 982         case MMC_POWER_ON:
 983                 dsor |= 1 << 11;
 984                 break;
 985         }
 986
 987         clk_enable(host->fclk);
 988
 989         /* On insanely high arm_per frequencies something sometimes
 990          * goes somehow out of sync, and the POW bit is not being set,
 991          * which results in the while loop below getting stuck.
 992          * Writing to the CON register twice seems to do the trick. */
 993         for (i = 0; i < 2; i++)
 994                 OMAP_MMC_WRITE(host, CON, dsor);
 995         if (ios->power_mode == MMC_POWER_ON) {
 996                 /* Send clock cycles, poll completion */
 997                 OMAP_MMC_WRITE(host, IE, 0);
 998                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 999                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1000                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1001                 OMAP_MMC_WRITE(host, STAT, 1);
1002         }
1003         clk_disable(host->fclk);
1004 }
1005
1006 static int mmc_omap_get_ro(struct mmc_host *mmc)
1007 {
1008         struct mmc_omap_host *host = mmc_priv(mmc);
1009
1010         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1011 }
1012
1013 static const struct mmc_host_ops mmc_omap_ops = {
1014         .request        = mmc_omap_request,
1015         .set_ios        = mmc_omap_set_ios,
1016         .get_ro         = mmc_omap_get_ro,
1017 };
1018
1019 static int __init mmc_omap_probe(struct platform_device *pdev)
1020 {
1021         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1022         struct mmc_host *mmc;
1023         struct mmc_omap_host *host = NULL;
1024         struct resource *res;
1025         int ret = 0;
1026         int irq;
1027
1028         if (minfo == NULL) {
1029                 dev_err(&pdev->dev, "platform data missing\n");
1030                 return -ENXIO;
1031         }
1032
1033         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1034         irq = platform_get_irq(pdev, 0);
1035         if (res == NULL || irq < 0)
1036                 return -ENXIO;
1037
1038         res = request_mem_region(res->start, res->end - res->start + 1,
1039                                  pdev->name);
1040         if (res == NULL)
1041                 return -EBUSY;
1042
1043         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1044         if (mmc == NULL) {
1045                 ret = -ENOMEM;
1046                 goto err_free_mem_region;
1047         }
1048
1049         host = mmc_priv(mmc);
1050         host->mmc = mmc;
1051
1052         spin_lock_init(&host->dma_lock);
1053         init_timer(&host->dma_timer);
1054         host->dma_timer.function = mmc_omap_dma_timer;
1055         host->dma_timer.data = (unsigned long) host;
1056
1057         host->id = pdev->id;
1058         host->mem_res = res;
1059         host->irq = irq;
1060
1061         if (cpu_is_omap24xx()) {
1062                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1063                 if (IS_ERR(host->iclk))
1064                         goto err_free_mmc_host;
1065                 clk_enable(host->iclk);
1066         }
1067
1068         if (!cpu_is_omap24xx())
1069                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1070         else
1071                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1072
1073         if (IS_ERR(host->fclk)) {
1074                 ret = PTR_ERR(host->fclk);
1075                 goto err_free_iclk;
1076         }
1077
1078         /* REVISIT:
1079          * Also, use minfo->cover to decide how to manage
1080          * the card detect sensing.
1081          */
1082         host->power_pin = minfo->power_pin;
1083         host->switch_pin = minfo->switch_pin;
1084         host->wp_pin = minfo->wp_pin;
1085         host->use_dma = 1;
1086         host->dma_ch = -1;
1087
1088         host->irq = irq;
1089         host->phys_base = host->mem_res->start;
1090         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1091
1092         mmc->ops = &mmc_omap_ops;
1093         mmc->f_min = 400000;
1094         mmc->f_max = 24000000;
1095         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1096         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1097
1098         if (minfo->wire4)
1099                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1100
1101         /* Use scatterlist DMA to reduce per-transfer costs.
1102          * NOTE max_seg_size assumption that small blocks aren't
1103          * normally used (except e.g. for reading SD registers).
1104          */
1105         mmc->max_phys_segs = 32;
1106         mmc->max_hw_segs = 32;
1107         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1108         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1109         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1110         mmc->max_seg_size = mmc->max_req_size;
1111
1112         if (host->power_pin >= 0) {
1113                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1114                         dev_err(mmc_dev(host->mmc),
1115                                 "Unable to get GPIO pin for MMC power\n");
1116                         goto err_free_fclk;
1117                 }
1118                 omap_set_gpio_direction(host->power_pin, 0);
1119         }
1120
1121         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1122         if (ret)
1123                 goto err_free_power_gpio;
1124
1125         host->dev = &pdev->dev;
1126         platform_set_drvdata(pdev, host);
1127
1128         if (host->switch_pin >= 0) {
1129                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1130                 init_timer(&host->switch_timer);
1131                 host->switch_timer.function = mmc_omap_switch_timer;
1132                 host->switch_timer.data = (unsigned long) host;
1133                 if (omap_request_gpio(host->switch_pin) != 0) {
1134                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1135                         host->switch_pin = -1;
1136                         goto no_switch;
1137                 }
1138
1139                 omap_set_gpio_direction(host->switch_pin, 1);
1140                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1141                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1142                 if (ret) {
1143                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1144                         omap_free_gpio(host->switch_pin);
1145                         host->switch_pin = -1;
1146                         goto no_switch;
1147                 }
1148                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1149                 if (ret == 0) {
1150                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1151                         if (ret != 0)
1152                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1153                 }
1154                 if (ret) {
1155                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1156                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1157                         omap_free_gpio(host->switch_pin);
1158                         host->switch_pin = -1;
1159                         goto no_switch;
1160                 }
1161                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1162                         schedule_work(&host->switch_work);
1163         }
1164
1165         mmc_add_host(mmc);
1166
1167         return 0;
1168
1169 no_switch:
1170         /* FIXME: Free other resources too. */
1171         if (host) {
1172                 if (host->iclk && !IS_ERR(host->iclk))
1173                         clk_put(host->iclk);
1174                 if (host->fclk && !IS_ERR(host->fclk))
1175                         clk_put(host->fclk);
1176                 mmc_free_host(host->mmc);
1177         }
1178 err_free_power_gpio:
1179         if (host->power_pin >= 0)
1180                 omap_free_gpio(host->power_pin);
1181 err_free_fclk:
1182         clk_put(host->fclk);
1183 err_free_iclk:
1184         if (host->iclk != NULL) {
1185                 clk_disable(host->iclk);
1186                 clk_put(host->iclk);
1187         }
1188 err_free_mmc_host:
1189         mmc_free_host(host->mmc);
1190 err_free_mem_region:
1191         release_mem_region(res->start, res->end - res->start + 1);
1192         return ret;
1193 }
1194
1195 static int mmc_omap_remove(struct platform_device *pdev)
1196 {
1197         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1198
1199         platform_set_drvdata(pdev, NULL);
1200
1201         BUG_ON(host == NULL);
1202
1203         mmc_remove_host(host->mmc);
1204         free_irq(host->irq, host);
1205
1206         if (host->power_pin >= 0)
1207                 omap_free_gpio(host->power_pin);
1208         if (host->switch_pin >= 0) {
1209                 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1210                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1211                 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1212                 omap_free_gpio(host->switch_pin);
1213                 host->switch_pin = -1;
1214                 del_timer_sync(&host->switch_timer);
1215                 flush_scheduled_work();
1216         }
1217         if (host->iclk && !IS_ERR(host->iclk))
1218                 clk_put(host->iclk);
1219         if (host->fclk && !IS_ERR(host->fclk))
1220                 clk_put(host->fclk);
1221
1222         release_mem_region(pdev->resource[0].start,
1223                            pdev->resource[0].end - pdev->resource[0].start + 1);
1224
1225         mmc_free_host(host->mmc);
1226
1227         return 0;
1228 }
1229
1230 #ifdef CONFIG_PM
1231 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1232 {
1233         int ret = 0;
1234         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1235
1236         if (host && host->suspended)
1237                 return 0;
1238
1239         if (host) {
1240                 ret = mmc_suspend_host(host->mmc, mesg);
1241                 if (ret == 0)
1242                         host->suspended = 1;
1243         }
1244         return ret;
1245 }
1246
1247 static int mmc_omap_resume(struct platform_device *pdev)
1248 {
1249         int ret = 0;
1250         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1251
1252         if (host && !host->suspended)
1253                 return 0;
1254
1255         if (host) {
1256                 ret = mmc_resume_host(host->mmc);
1257                 if (ret == 0)
1258                         host->suspended = 0;
1259         }
1260
1261         return ret;
1262 }
1263 #else
1264 #define mmc_omap_suspend        NULL
1265 #define mmc_omap_resume         NULL
1266 #endif
1267
1268 static struct platform_driver mmc_omap_driver = {
1269         .probe          = mmc_omap_probe,
1270         .remove         = mmc_omap_remove,
1271         .suspend        = mmc_omap_suspend,
1272         .resume         = mmc_omap_resume,
1273         .driver         = {
1274                 .name   = DRIVER_NAME,
1275         },
1276 };
1277
1278 static int __init mmc_omap_init(void)
1279 {
1280         return platform_driver_register(&mmc_omap_driver);
1281 }
1282
1283 static void __exit mmc_omap_exit(void)
1284 {
1285         platform_driver_unregister(&mmc_omap_driver);
1286 }
1287
1288 module_init(mmc_omap_init);
1289 module_exit(mmc_omap_exit);
1290
1291 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1292 MODULE_LICENSE("GPL");
1293 MODULE_ALIAS(DRIVER_NAME);
1294 MODULE_AUTHOR("Juha Yrjölä");