drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39
  40 #define OMAP_MMC_REG_CMD        0x00
  41 #define OMAP_MMC_REG_ARGL       0x04
  42 #define OMAP_MMC_REG_ARGH       0x08
  43 #define OMAP_MMC_REG_CON        0x0c
  44 #define OMAP_MMC_REG_STAT       0x10
  45 #define OMAP_MMC_REG_IE         0x14
  46 #define OMAP_MMC_REG_CTO        0x18
  47 #define OMAP_MMC_REG_DTO        0x1c
  48 #define OMAP_MMC_REG_DATA       0x20
  49 #define OMAP_MMC_REG_BLEN       0x24
  50 #define OMAP_MMC_REG_NBLK       0x28
  51 #define OMAP_MMC_REG_BUF        0x2c
  52 #define OMAP_MMC_REG_SDIO       0x34
  53 #define OMAP_MMC_REG_REV        0x3c
  54 #define OMAP_MMC_REG_RSP0       0x40
  55 #define OMAP_MMC_REG_RSP1       0x44
  56 #define OMAP_MMC_REG_RSP2       0x48
  57 #define OMAP_MMC_REG_RSP3       0x4c
  58 #define OMAP_MMC_REG_RSP4       0x50
  59 #define OMAP_MMC_REG_RSP5       0x54
  60 #define OMAP_MMC_REG_RSP6       0x58
  61 #define OMAP_MMC_REG_RSP7       0x5c
  62 #define OMAP_MMC_REG_IOSR       0x60
  63 #define OMAP_MMC_REG_SYSC       0x64
  64 #define OMAP_MMC_REG_SYSS       0x68
  65
  66 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  67 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  68 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  69 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  70 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  71 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  72 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  73 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  74 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  75 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  76 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  77 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  78 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  79
  80 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  81 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  82
  83 /*
  84  * Command types
  85  */
  86 #define OMAP_MMC_CMDTYPE_BC     0
  87 #define OMAP_MMC_CMDTYPE_BCR    1
  88 #define OMAP_MMC_CMDTYPE_AC     2
  89 #define OMAP_MMC_CMDTYPE_ADTC   3
  90
  91
  92 #define DRIVER_NAME "mmci-omap"
  93
  94 /* Specifies how often in millisecs to poll for card status changes
  95  * when the cover switch is open */
  96 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  97
  98 static int mmc_omap_enable_poll = 1;
  99
 100 struct mmc_omap_host {
 101         int                     initialized;
 102         int                     suspended;
 103         struct mmc_request *    mrq;
 104         struct mmc_command *    cmd;
 105         struct mmc_data *       data;
 106         struct mmc_host *       mmc;
 107         struct device *         dev;
 108         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 109         struct clk *            iclk;
 110         struct clk *            fclk;
 111         struct resource         *mem_res;
 112         void __iomem            *virt_base;
 113         unsigned int            phys_base;
 114         int                     irq;
 115         unsigned char           bus_mode;
 116         unsigned char           hw_bus_mode;
 117
 118         unsigned int            sg_len;
 119         int                     sg_idx;
 120         u16 *                   buffer;
 121         u32                     buffer_bytes_left;
 122         u32                     total_bytes_left;
 123
 124         unsigned                use_dma:1;
 125         unsigned                brs_received:1, dma_done:1;
 126         unsigned                dma_is_read:1;
 127         unsigned                dma_in_use:1;
 128         int                     dma_ch;
 129         spinlock_t              dma_lock;
 130         struct timer_list       dma_timer;
 131         unsigned                dma_len;
 132
 133         short                   power_pin;
 134         short                   wp_pin;
 135
 136         int                     switch_pin;
 137         struct work_struct      switch_work;
 138         struct timer_list       switch_timer;
 139         int                     switch_last_state;
 140 };
 141
 142 static inline int
 143 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 144 {
 145         if (host->switch_pin < 0)
 146                 return 0;
 147         return omap_get_gpio_datain(host->switch_pin);
 148 }
 149
 150 static ssize_t
 151 mmc_omap_show_cover_switch(struct device *dev,
 152         struct device_attribute *attr, char *buf)
 153 {
 154         struct mmc_omap_host *host = dev_get_drvdata(dev);
 155
 156         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
 157                         "closed");
 158 }
 159
 160 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 161
 162 static ssize_t
 163 mmc_omap_show_enable_poll(struct device *dev,
 164         struct device_attribute *attr, char *buf)
 165 {
 166         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 167 }
 168
 169 static ssize_t
 170 mmc_omap_store_enable_poll(struct device *dev,
 171         struct device_attribute *attr, const char *buf,
 172         size_t size)
 173 {
 174         int enable_poll;
 175
 176         if (sscanf(buf, "%10d", &enable_poll) != 1)
 177                 return -EINVAL;
 178
 179         if (enable_poll != mmc_omap_enable_poll) {
 180                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 181
 182                 mmc_omap_enable_poll = enable_poll;
 183                 if (enable_poll && host->switch_pin >= 0)
 184                         schedule_work(&host->switch_work);
 185         }
 186         return size;
 187 }
 188
 189 static DEVICE_ATTR(enable_poll, 0664,
 190                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 191
 192 static void
 193 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 194 {
 195         u32 cmdreg;
 196         u32 resptype;
 197         u32 cmdtype;
 198
 199         host->cmd = cmd;
 200
 201         resptype = 0;
 202         cmdtype = 0;
 203
 204         /* Our hardware needs to know exact type */
 205         switch (mmc_resp_type(cmd)) {
 206         case MMC_RSP_NONE:
 207                 break;
 208         case MMC_RSP_R1:
 209         case MMC_RSP_R1B:
 210                 /* resp 1, 1b, 6, 7 */
 211                 resptype = 1;
 212                 break;
 213         case MMC_RSP_R2:
 214                 resptype = 2;
 215                 break;
 216         case MMC_RSP_R3:
 217                 resptype = 3;
 218                 break;
 219         default:
 220                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 221                 break;
 222         }
 223
 224         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 225                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 226         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 227                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 228         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 229                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 230         } else {
 231                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 232         }
 233
 234         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 235
 236         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 237                 cmdreg |= 1 << 6;
 238
 239         if (cmd->flags & MMC_RSP_BUSY)
 240                 cmdreg |= 1 << 11;
 241
 242         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 243                 cmdreg |= 1 << 15;
 244
 245         clk_enable(host->fclk);
 246
 247         OMAP_MMC_WRITE(host, CTO, 200);
 248         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 249         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 250         OMAP_MMC_WRITE(host, IE,
 251                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 252                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 253                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 254                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 255                        OMAP_MMC_STAT_END_OF_DATA);
 256         OMAP_MMC_WRITE(host, CMD, cmdreg);
 257 }
 258
 259 static void
 260 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 261 {
 262         if (host->dma_in_use) {
 263                 enum dma_data_direction dma_data_dir;
 264
 265                 BUG_ON(host->dma_ch < 0);
 266                 if (data->error)
 267                         omap_stop_dma(host->dma_ch);
 268                 /* Release DMA channel lazily */
 269                 mod_timer(&host->dma_timer, jiffies + HZ);
 270                 if (data->flags & MMC_DATA_WRITE)
 271                         dma_data_dir = DMA_TO_DEVICE;
 272                 else
 273                         dma_data_dir = DMA_FROM_DEVICE;
 274                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 275                              dma_data_dir);
 276         }
 277         host->data = NULL;
 278         host->sg_len = 0;
 279         clk_disable(host->fclk);
 280
 281         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 282          * dozens of requests until the card finishes writing data.
 283          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 284          */
 285
 286         if (!data->stop) {
 287                 host->mrq = NULL;
 288                 mmc_request_done(host->mmc, data->mrq);
 289                 return;
 290         }
 291
 292         mmc_omap_start_command(host, data->stop);
 293 }
 294
 295 static void
 296 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 297 {
 298         unsigned long flags;
 299         int done;
 300
 301         if (!host->dma_in_use) {
 302                 mmc_omap_xfer_done(host, data);
 303                 return;
 304         }
 305         done = 0;
 306         spin_lock_irqsave(&host->dma_lock, flags);
 307         if (host->dma_done)
 308                 done = 1;
 309         else
 310                 host->brs_received = 1;
 311         spin_unlock_irqrestore(&host->dma_lock, flags);
 312         if (done)
 313                 mmc_omap_xfer_done(host, data);
 314 }
 315
 316 static void
 317 mmc_omap_dma_timer(unsigned long data)
 318 {
 319         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 320
 321         BUG_ON(host->dma_ch < 0);
 322         omap_free_dma(host->dma_ch);
 323         host->dma_ch = -1;
 324 }
 325
 326 static void
 327 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 328 {
 329         unsigned long flags;
 330         int done;
 331
 332         done = 0;
 333         spin_lock_irqsave(&host->dma_lock, flags);
 334         if (host->brs_received)
 335                 done = 1;
 336         else
 337                 host->dma_done = 1;
 338         spin_unlock_irqrestore(&host->dma_lock, flags);
 339         if (done)
 340                 mmc_omap_xfer_done(host, data);
 341 }
 342
 343 static void
 344 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 345 {
 346         host->cmd = NULL;
 347
 348         if (cmd->flags & MMC_RSP_PRESENT) {
 349                 if (cmd->flags & MMC_RSP_136) {
 350                         /* response type 2 */
 351                         cmd->resp[3] =
 352                                 OMAP_MMC_READ(host, RSP0) |
 353                                 (OMAP_MMC_READ(host, RSP1) << 16);
 354                         cmd->resp[2] =
 355                                 OMAP_MMC_READ(host, RSP2) |
 356                                 (OMAP_MMC_READ(host, RSP3) << 16);
 357                         cmd->resp[1] =
 358                                 OMAP_MMC_READ(host, RSP4) |
 359                                 (OMAP_MMC_READ(host, RSP5) << 16);
 360                         cmd->resp[0] =
 361                                 OMAP_MMC_READ(host, RSP6) |
 362                                 (OMAP_MMC_READ(host, RSP7) << 16);
 363                 } else {
 364                         /* response types 1, 1b, 3, 4, 5, 6 */
 365                         cmd->resp[0] =
 366                                 OMAP_MMC_READ(host, RSP6) |
 367                                 (OMAP_MMC_READ(host, RSP7) << 16);
 368                 }
 369         }
 370
 371         if (host->data == NULL || cmd->error) {
 372                 host->mrq = NULL;
 373                 clk_disable(host->fclk);
 374                 mmc_request_done(host->mmc, cmd->mrq);
 375         }
 376 }
 377
 378 /* PIO only */
 379 static void
 380 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 381 {
 382         struct scatterlist *sg;
 383
 384         sg = host->data->sg + host->sg_idx;
 385         host->buffer_bytes_left = sg->length;
 386         host->buffer = sg_virt(sg);
 387         if (host->buffer_bytes_left > host->total_bytes_left)
 388                 host->buffer_bytes_left = host->total_bytes_left;
 389 }
 390
 391 /* PIO only */
 392 static void
 393 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 394 {
 395         int n;
 396
 397         if (host->buffer_bytes_left == 0) {
 398                 host->sg_idx++;
 399                 BUG_ON(host->sg_idx == host->sg_len);
 400                 mmc_omap_sg_to_buf(host);
 401         }
 402         n = 64;
 403         if (n > host->buffer_bytes_left)
 404                 n = host->buffer_bytes_left;
 405         host->buffer_bytes_left -= n;
 406         host->total_bytes_left -= n;
 407         host->data->bytes_xfered += n;
 408
 409         if (write) {
 410                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 411         } else {
 412                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 413         }
 414 }
 415
 416 static inline void mmc_omap_report_irq(u16 status)
 417 {
 418         static const char *mmc_omap_status_bits[] = {
 419                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 420                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 421         };
 422         int i, c = 0;
 423
 424         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 425                 if (status & (1 << i)) {
 426                         if (c)
 427                                 printk(" ");
 428                         printk("%s", mmc_omap_status_bits[i]);
 429                         c++;
 430                 }
 431 }
 432
 433 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 434 {
 435         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 436         u16 status;
 437         int end_command;
 438         int end_transfer;
 439         int transfer_error;
 440
 441         if (host->cmd == NULL && host->data == NULL) {
 442                 status = OMAP_MMC_READ(host, STAT);
 443                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 444                 if (status != 0) {
 445                         OMAP_MMC_WRITE(host, STAT, status);
 446                         OMAP_MMC_WRITE(host, IE, 0);
 447                 }
 448                 return IRQ_HANDLED;
 449         }
 450
 451         end_command = 0;
 452         end_transfer = 0;
 453         transfer_error = 0;
 454
 455         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 456                 OMAP_MMC_WRITE(host, STAT, status);
 457 #ifdef CONFIG_MMC_DEBUG
 458                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 459                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 460                 mmc_omap_report_irq(status);
 461                 printk("\n");
 462 #endif
 463                 if (host->total_bytes_left) {
 464                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 465                             (status & OMAP_MMC_STAT_END_OF_DATA))
 466                                 mmc_omap_xfer_data(host, 0);
 467                         if (status & OMAP_MMC_STAT_A_EMPTY)
 468                                 mmc_omap_xfer_data(host, 1);
 469                 }
 470
 471                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 472                         end_transfer = 1;
 473                 }
 474
 475                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 476                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 477                         if (host->data) {
 478                                 host->data->error = -ETIMEDOUT;
 479                                 transfer_error = 1;
 480                         }
 481                 }
 482
 483                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 484                         if (host->data) {
 485                                 host->data->error = -EILSEQ;
 486                                 dev_dbg(mmc_dev(host->mmc),
 487                                          "data CRC error, bytes left %d\n",
 488                                         host->total_bytes_left);
 489                                 transfer_error = 1;
 490                         } else {
 491                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 492                         }
 493                 }
 494
 495                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 496                         /* Timeouts are routine with some commands */
 497                         if (host->cmd) {
 498                                 if (!mmc_omap_cover_is_open(host))
 499                                         dev_err(mmc_dev(host->mmc),
 500                                         "command timeout, CMD %d\n",
 501                                         host->cmd->opcode);
 502                                 host->cmd->error = -ETIMEDOUT;
 503                                 end_command = 1;
 504                         }
 505                 }
 506
 507                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 508                         if (host->cmd) {
 509                                 dev_err(mmc_dev(host->mmc),
 510                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 511                                         host->cmd->opcode, host->cmd->arg);
 512                                 host->cmd->error = -EILSEQ;
 513                                 end_command = 1;
 514                         } else
 515                                 dev_err(mmc_dev(host->mmc),
 516                                         "command CRC error without cmd?\n");
 517                 }
 518
 519                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 520                         dev_dbg(mmc_dev(host->mmc),
 521                                 "ignoring card status error (CMD%d)\n",
 522                                 host->cmd->opcode);
 523                         end_command = 1;
 524                 }
 525
 526                 /*
 527                  * NOTE: On 1610 the END_OF_CMD may come too early when
 528                  * starting a write
 529                  */
 530                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 531                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 532                         end_command = 1;
 533                 }
 534         }
 535
 536         if (end_command) {
 537                 mmc_omap_cmd_done(host, host->cmd);
 538         }
 539         if (transfer_error)
 540                 mmc_omap_xfer_done(host, host->data);
 541         else if (end_transfer)
 542                 mmc_omap_end_of_data(host, host->data);
 543
 544         return IRQ_HANDLED;
 545 }
 546
 547 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
 548 {
 549         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 550
 551         schedule_work(&host->switch_work);
 552
 553         return IRQ_HANDLED;
 554 }
 555
 556 static void mmc_omap_switch_timer(unsigned long arg)
 557 {
 558         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 559
 560         schedule_work(&host->switch_work);
 561 }
 562
 563 static void mmc_omap_switch_handler(struct work_struct *work)
 564 {
 565         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
 566         struct mmc_card *card;
 567         static int complained = 0;
 568         int cards = 0, cover_open;
 569
 570         if (host->switch_pin == -1)
 571                 return;
 572         cover_open = mmc_omap_cover_is_open(host);
 573         if (cover_open != host->switch_last_state) {
 574                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 575                 host->switch_last_state = cover_open;
 576         }
 577         mmc_detect_change(host->mmc, 0);
 578         list_for_each_entry(card, &host->mmc->cards, node) {
 579                 if (mmc_card_present(card))
 580                         cards++;
 581         }
 582         if (mmc_omap_cover_is_open(host)) {
 583                 if (!complained) {
 584                         dev_info(mmc_dev(host->mmc), "cover is open\n");
 585                         complained = 1;
 586                 }
 587                 if (mmc_omap_enable_poll)
 588                         mod_timer(&host->switch_timer, jiffies +
 589                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 590         } else {
 591                 complained = 0;
 592         }
 593 }
 594
 595 /* Prepare to transfer the next segment of a scatterlist */
 596 static void
 597 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 598 {
 599         int dma_ch = host->dma_ch;
 600         unsigned long data_addr;
 601         u16 buf, frame;
 602         u32 count;
 603         struct scatterlist *sg = &data->sg[host->sg_idx];
 604         int src_port = 0;
 605         int dst_port = 0;
 606         int sync_dev = 0;
 607
 608         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 609         frame = data->blksz;
 610         count = sg_dma_len(sg);
 611
 612         if ((data->blocks == 1) && (count > data->blksz))
 613                 count = frame;
 614
 615         host->dma_len = count;
 616
 617         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 618          * Use 16 or 32 word frames when the blocksize is at least that large.
 619          * Blocksize is usually 512 bytes; but not for some SD reads.
 620          */
 621         if (cpu_is_omap15xx() && frame > 32)
 622                 frame = 32;
 623         else if (frame > 64)
 624                 frame = 64;
 625         count /= frame;
 626         frame >>= 1;
 627
 628         if (!(data->flags & MMC_DATA_WRITE)) {
 629                 buf = 0x800f | ((frame - 1) << 8);
 630
 631                 if (cpu_class_is_omap1()) {
 632                         src_port = OMAP_DMA_PORT_TIPB;
 633                         dst_port = OMAP_DMA_PORT_EMIFF;
 634                 }
 635                 if (cpu_is_omap24xx())
 636                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 637
 638                 omap_set_dma_src_params(dma_ch, src_port,
 639                                         OMAP_DMA_AMODE_CONSTANT,
 640                                         data_addr, 0, 0);
 641                 omap_set_dma_dest_params(dma_ch, dst_port,
 642                                          OMAP_DMA_AMODE_POST_INC,
 643                                          sg_dma_address(sg), 0, 0);
 644                 omap_set_dma_dest_data_pack(dma_ch, 1);
 645                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 646         } else {
 647                 buf = 0x0f80 | ((frame - 1) << 0);
 648
 649                 if (cpu_class_is_omap1()) {
 650                         src_port = OMAP_DMA_PORT_EMIFF;
 651                         dst_port = OMAP_DMA_PORT_TIPB;
 652                 }
 653                 if (cpu_is_omap24xx())
 654                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 655
 656                 omap_set_dma_dest_params(dma_ch, dst_port,
 657                                          OMAP_DMA_AMODE_CONSTANT,
 658                                          data_addr, 0, 0);
 659                 omap_set_dma_src_params(dma_ch, src_port,
 660                                         OMAP_DMA_AMODE_POST_INC,
 661                                         sg_dma_address(sg), 0, 0);
 662                 omap_set_dma_src_data_pack(dma_ch, 1);
 663                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 664         }
 665
 666         /* Max limit for DMA frame count is 0xffff */
 667         BUG_ON(count > 0xffff);
 668
 669         OMAP_MMC_WRITE(host, BUF, buf);
 670         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 671                                      frame, count, OMAP_DMA_SYNC_FRAME,
 672                                      sync_dev, 0);
 673 }
 674
 675 /* A scatterlist segment completed */
 676 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 677 {
 678         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 679         struct mmc_data *mmcdat = host->data;
 680
 681         if (unlikely(host->dma_ch < 0)) {
 682                 dev_err(mmc_dev(host->mmc),
 683                         "DMA callback while DMA not enabled\n");
 684                 return;
 685         }
 686         /* FIXME: We really should do something to _handle_ the errors */
 687         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 688                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 689                 return;
 690         }
 691         if (ch_status & OMAP_DMA_DROP_IRQ) {
 692                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 693                 return;
 694         }
 695         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 696                 return;
 697         }
 698         mmcdat->bytes_xfered += host->dma_len;
 699         host->sg_idx++;
 700         if (host->sg_idx < host->sg_len) {
 701                 mmc_omap_prepare_dma(host, host->data);
 702                 omap_start_dma(host->dma_ch);
 703         } else
 704                 mmc_omap_dma_done(host, host->data);
 705 }
 706
 707 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 708 {
 709         const char *dev_name;
 710         int sync_dev, dma_ch, is_read, r;
 711
 712         is_read = !(data->flags & MMC_DATA_WRITE);
 713         del_timer_sync(&host->dma_timer);
 714         if (host->dma_ch >= 0) {
 715                 if (is_read == host->dma_is_read)
 716                         return 0;
 717                 omap_free_dma(host->dma_ch);
 718                 host->dma_ch = -1;
 719         }
 720
 721         if (is_read) {
 722                 if (host->id == 1) {
 723                         sync_dev = OMAP_DMA_MMC_RX;
 724                         dev_name = "MMC1 read";
 725                 } else {
 726                         sync_dev = OMAP_DMA_MMC2_RX;
 727                         dev_name = "MMC2 read";
 728                 }
 729         } else {
 730                 if (host->id == 1) {
 731                         sync_dev = OMAP_DMA_MMC_TX;
 732                         dev_name = "MMC1 write";
 733                 } else {
 734                         sync_dev = OMAP_DMA_MMC2_TX;
 735                         dev_name = "MMC2 write";
 736                 }
 737         }
 738         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 739                              host, &dma_ch);
 740         if (r != 0) {
 741                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 742                 return r;
 743         }
 744         host->dma_ch = dma_ch;
 745         host->dma_is_read = is_read;
 746
 747         return 0;
 748 }
 749
 750 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 751 {
 752         u16 reg;
 753
 754         reg = OMAP_MMC_READ(host, SDIO);
 755         reg &= ~(1 << 5);
 756         OMAP_MMC_WRITE(host, SDIO, reg);
 757         /* Set maximum timeout */
 758         OMAP_MMC_WRITE(host, CTO, 0xff);
 759 }
 760
 761 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 762 {
 763         int timeout;
 764         u16 reg;
 765
 766         /* Convert ns to clock cycles by assuming 20MHz frequency
 767          * 1 cycle at 20MHz = 500 ns
 768          */
 769         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 770
 771         /* Check if we need to use timeout multiplier register */
 772         reg = OMAP_MMC_READ(host, SDIO);
 773         if (timeout > 0xffff) {
 774                 reg |= (1 << 5);
 775                 timeout /= 1024;
 776         } else
 777                 reg &= ~(1 << 5);
 778         OMAP_MMC_WRITE(host, SDIO, reg);
 779         OMAP_MMC_WRITE(host, DTO, timeout);
 780 }
 781
 782 static void
 783 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 784 {
 785         struct mmc_data *data = req->data;
 786         int i, use_dma, block_size;
 787         unsigned sg_len;
 788
 789         host->data = data;
 790         if (data == NULL) {
 791                 OMAP_MMC_WRITE(host, BLEN, 0);
 792                 OMAP_MMC_WRITE(host, NBLK, 0);
 793                 OMAP_MMC_WRITE(host, BUF, 0);
 794                 host->dma_in_use = 0;
 795                 set_cmd_timeout(host, req);
 796                 return;
 797         }
 798
 799         block_size = data->blksz;
 800
 801         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 802         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 803         set_data_timeout(host, req);
 804
 805         /* cope with calling layer confusion; it issues "single
 806          * block" writes using multi-block scatterlists.
 807          */
 808         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 809
 810         /* Only do DMA for entire blocks */
 811         use_dma = host->use_dma;
 812         if (use_dma) {
 813                 for (i = 0; i < sg_len; i++) {
 814                         if ((data->sg[i].length % block_size) != 0) {
 815                                 use_dma = 0;
 816                                 break;
 817                         }
 818                 }
 819         }
 820
 821         host->sg_idx = 0;
 822         if (use_dma) {
 823                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 824                         enum dma_data_direction dma_data_dir;
 825
 826                         if (data->flags & MMC_DATA_WRITE)
 827                                 dma_data_dir = DMA_TO_DEVICE;
 828                         else
 829                                 dma_data_dir = DMA_FROM_DEVICE;
 830
 831                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 832                                                 sg_len, dma_data_dir);
 833                         host->total_bytes_left = 0;
 834                         mmc_omap_prepare_dma(host, req->data);
 835                         host->brs_received = 0;
 836                         host->dma_done = 0;
 837                         host->dma_in_use = 1;
 838                 } else
 839                         use_dma = 0;
 840         }
 841
 842         /* Revert to PIO? */
 843         if (!use_dma) {
 844                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 845                 host->total_bytes_left = data->blocks * block_size;
 846                 host->sg_len = sg_len;
 847                 mmc_omap_sg_to_buf(host);
 848                 host->dma_in_use = 0;
 849         }
 850 }
 851
 852 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 853 {
 854         struct mmc_omap_host *host = mmc_priv(mmc);
 855
 856         WARN_ON(host->mrq != NULL);
 857
 858         host->mrq = req;
 859
 860         /* only touch fifo AFTER the controller readies it */
 861         mmc_omap_prepare_data(host, req);
 862         mmc_omap_start_command(host, req->cmd);
 863         if (host->dma_in_use)
 864                 omap_start_dma(host->dma_ch);
 865 }
 866
 867 static void innovator_fpga_socket_power(int on)
 868 {
 869 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 870         if (on) {
 871                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 872                      OMAP1510_FPGA_POWER);
 873         } else {
 874                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 875                      OMAP1510_FPGA_POWER);
 876         }
 877 #endif
 878 }
 879
 880 /*
 881  * Turn the socket power on/off. Innovator uses FPGA, most boards
 882  * probably use GPIO.
 883  */
 884 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 885 {
 886         if (on) {
 887                 if (machine_is_omap_innovator())
 888                         innovator_fpga_socket_power(1);
 889                 else if (machine_is_omap_h2())
 890                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 891                 else if (machine_is_omap_h3())
 892                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 893                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 894                 else if (cpu_is_omap24xx()) {
 895                         u16 reg = OMAP_MMC_READ(host, CON);
 896                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 897                 } else
 898                         if (host->power_pin >= 0)
 899                                 omap_set_gpio_dataout(host->power_pin, 1);
 900         } else {
 901                 if (machine_is_omap_innovator())
 902                         innovator_fpga_socket_power(0);
 903                 else if (machine_is_omap_h2())
 904                         tps65010_set_gpio_out_value(GPIO3, LOW);
 905                 else if (machine_is_omap_h3())
 906                         tps65010_set_gpio_out_value(GPIO4, LOW);
 907                 else if (cpu_is_omap24xx()) {
 908                         u16 reg = OMAP_MMC_READ(host, CON);
 909                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 910                 } else
 911                         if (host->power_pin >= 0)
 912                                 omap_set_gpio_dataout(host->power_pin, 0);
 913         }
 914 }
 915
 916 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 917 {
 918         struct mmc_omap_host *host = mmc_priv(mmc);
 919         int func_clk_rate = clk_get_rate(host->fclk);
 920         int dsor;
 921
 922         if (ios->clock == 0)
 923                 return 0;
 924
 925         dsor = func_clk_rate / ios->clock;
 926         if (dsor < 1)
 927                 dsor = 1;
 928
 929         if (func_clk_rate / dsor > ios->clock)
 930                 dsor++;
 931
 932         if (dsor > 250)
 933                 dsor = 250;
 934         dsor++;
 935
 936         if (ios->bus_width == MMC_BUS_WIDTH_4)
 937                 dsor |= 1 << 15;
 938
 939         return dsor;
 940 }
 941
 942 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 943 {
 944         struct mmc_omap_host *host = mmc_priv(mmc);
 945         int dsor;
 946         int i;
 947
 948         dsor = mmc_omap_calc_divisor(mmc, ios);
 949         host->bus_mode = ios->bus_mode;
 950         host->hw_bus_mode = host->bus_mode;
 951
 952         switch (ios->power_mode) {
 953         case MMC_POWER_OFF:
 954                 mmc_omap_power(host, 0);
 955                 break;
 956         case MMC_POWER_UP:
 957                 /* Cannot touch dsor yet, just power up MMC */
 958                 mmc_omap_power(host, 1);
 959                 return;
 960         case MMC_POWER_ON:
 961                 dsor |= 1 << 11;
 962                 break;
 963         }
 964
 965         clk_enable(host->fclk);
 966
 967         /* On insanely high arm_per frequencies something sometimes
 968          * goes somehow out of sync, and the POW bit is not being set,
 969          * which results in the while loop below getting stuck.
 970          * Writing to the CON register twice seems to do the trick. */
 971         for (i = 0; i < 2; i++)
 972                 OMAP_MMC_WRITE(host, CON, dsor);
 973         if (ios->power_mode == MMC_POWER_ON) {
 974                 /* Send clock cycles, poll completion */
 975                 OMAP_MMC_WRITE(host, IE, 0);
 976                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 977                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
 978                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
 979                 OMAP_MMC_WRITE(host, STAT, 1);
 980         }
 981         clk_disable(host->fclk);
 982 }
 983
 984 static int mmc_omap_get_ro(struct mmc_host *mmc)
 985 {
 986         struct mmc_omap_host *host = mmc_priv(mmc);
 987
 988         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
 989 }
 990
 991 static const struct mmc_host_ops mmc_omap_ops = {
 992         .request        = mmc_omap_request,
 993         .set_ios        = mmc_omap_set_ios,
 994         .get_ro         = mmc_omap_get_ro,
 995 };
 996
 997 static int __init mmc_omap_probe(struct platform_device *pdev)
 998 {
 999         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1000         struct mmc_host *mmc;
1001         struct mmc_omap_host *host = NULL;
1002         struct resource *res;
1003         int ret = 0;
1004         int irq;
1005
1006         if (minfo == NULL) {
1007                 dev_err(&pdev->dev, "platform data missing\n");
1008                 return -ENXIO;
1009         }
1010
1011         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1012         irq = platform_get_irq(pdev, 0);
1013         if (res == NULL || irq < 0)
1014                 return -ENXIO;
1015
1016         res = request_mem_region(res->start, res->end - res->start + 1,
1017                                  pdev->name);
1018         if (res == NULL)
1019                 return -EBUSY;
1020
1021         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1022         if (mmc == NULL) {
1023                 ret = -ENOMEM;
1024                 goto err_free_mem_region;
1025         }
1026
1027         host = mmc_priv(mmc);
1028         host->mmc = mmc;
1029
1030         spin_lock_init(&host->dma_lock);
1031         init_timer(&host->dma_timer);
1032         host->dma_timer.function = mmc_omap_dma_timer;
1033         host->dma_timer.data = (unsigned long) host;
1034
1035         host->id = pdev->id;
1036         host->mem_res = res;
1037         host->irq = irq;
1038
1039         if (cpu_is_omap24xx()) {
1040                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1041                 if (IS_ERR(host->iclk))
1042                         goto err_free_mmc_host;
1043                 clk_enable(host->iclk);
1044         }
1045
1046         if (!cpu_is_omap24xx())
1047                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1048         else
1049                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1050
1051         if (IS_ERR(host->fclk)) {
1052                 ret = PTR_ERR(host->fclk);
1053                 goto err_free_iclk;
1054         }
1055
1056         /* REVISIT:
1057          * Also, use minfo->cover to decide how to manage
1058          * the card detect sensing.
1059          */
1060         host->power_pin = minfo->power_pin;
1061         host->switch_pin = minfo->switch_pin;
1062         host->wp_pin = minfo->wp_pin;
1063         host->use_dma = 1;
1064         host->dma_ch = -1;
1065
1066         host->irq = irq;
1067         host->phys_base = host->mem_res->start;
1068         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1069
1070         mmc->ops = &mmc_omap_ops;
1071         mmc->f_min = 400000;
1072         mmc->f_max = 24000000;
1073         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1074         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1075
1076         if (minfo->wire4)
1077                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1078
1079         /* Use scatterlist DMA to reduce per-transfer costs.
1080          * NOTE max_seg_size assumption that small blocks aren't
1081          * normally used (except e.g. for reading SD registers).
1082          */
1083         mmc->max_phys_segs = 32;
1084         mmc->max_hw_segs = 32;
1085         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1086         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1087         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1088         mmc->max_seg_size = mmc->max_req_size;
1089
1090         if (host->power_pin >= 0) {
1091                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1092                         dev_err(mmc_dev(host->mmc),
1093                                 "Unable to get GPIO pin for MMC power\n");
1094                         goto err_free_fclk;
1095                 }
1096                 omap_set_gpio_direction(host->power_pin, 0);
1097         }
1098
1099         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1100         if (ret)
1101                 goto err_free_power_gpio;
1102
1103         host->dev = &pdev->dev;
1104         platform_set_drvdata(pdev, host);
1105
1106         if (host->switch_pin >= 0) {
1107                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1108                 init_timer(&host->switch_timer);
1109                 host->switch_timer.function = mmc_omap_switch_timer;
1110                 host->switch_timer.data = (unsigned long) host;
1111                 if (omap_request_gpio(host->switch_pin) != 0) {
1112                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1113                         host->switch_pin = -1;
1114                         goto no_switch;
1115                 }
1116
1117                 omap_set_gpio_direction(host->switch_pin, 1);
1118                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1119                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1120                 if (ret) {
1121                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1122                         omap_free_gpio(host->switch_pin);
1123                         host->switch_pin = -1;
1124                         goto no_switch;
1125                 }
1126                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1127                 if (ret == 0) {
1128                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1129                         if (ret != 0)
1130                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1131                 }
1132                 if (ret) {
1133                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1134                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1135                         omap_free_gpio(host->switch_pin);
1136                         host->switch_pin = -1;
1137                         goto no_switch;
1138                 }
1139                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1140                         schedule_work(&host->switch_work);
1141         }
1142
1143         mmc_add_host(mmc);
1144
1145         return 0;
1146
1147 no_switch:
1148         /* FIXME: Free other resources too. */
1149         if (host) {
1150                 if (host->iclk && !IS_ERR(host->iclk))
1151                         clk_put(host->iclk);
1152                 if (host->fclk && !IS_ERR(host->fclk))
1153                         clk_put(host->fclk);
1154                 mmc_free_host(host->mmc);
1155         }
1156 err_free_power_gpio:
1157         if (host->power_pin >= 0)
1158                 omap_free_gpio(host->power_pin);
1159 err_free_fclk:
1160         clk_put(host->fclk);
1161 err_free_iclk:
1162         if (host->iclk != NULL) {
1163                 clk_disable(host->iclk);
1164                 clk_put(host->iclk);
1165         }
1166 err_free_mmc_host:
1167         mmc_free_host(host->mmc);
1168 err_free_mem_region:
1169         release_mem_region(res->start, res->end - res->start + 1);
1170         return ret;
1171 }
1172
1173 static int mmc_omap_remove(struct platform_device *pdev)
1174 {
1175         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1176
1177         platform_set_drvdata(pdev, NULL);
1178
1179         BUG_ON(host == NULL);
1180
1181         mmc_remove_host(host->mmc);
1182         free_irq(host->irq, host);
1183
1184         if (host->power_pin >= 0)
1185                 omap_free_gpio(host->power_pin);
1186         if (host->switch_pin >= 0) {
1187                 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1188                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1189                 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1190                 omap_free_gpio(host->switch_pin);
1191                 host->switch_pin = -1;
1192                 del_timer_sync(&host->switch_timer);
1193                 flush_scheduled_work();
1194         }
1195         if (host->iclk && !IS_ERR(host->iclk))
1196                 clk_put(host->iclk);
1197         if (host->fclk && !IS_ERR(host->fclk))
1198                 clk_put(host->fclk);
1199
1200         release_mem_region(pdev->resource[0].start,
1201                            pdev->resource[0].end - pdev->resource[0].start + 1);
1202
1203         mmc_free_host(host->mmc);
1204
1205         return 0;
1206 }
1207
1208 #ifdef CONFIG_PM
1209 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1210 {
1211         int ret = 0;
1212         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1213
1214         if (host && host->suspended)
1215                 return 0;
1216
1217         if (host) {
1218                 ret = mmc_suspend_host(host->mmc, mesg);
1219                 if (ret == 0)
1220                         host->suspended = 1;
1221         }
1222         return ret;
1223 }
1224
1225 static int mmc_omap_resume(struct platform_device *pdev)
1226 {
1227         int ret = 0;
1228         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1229
1230         if (host && !host->suspended)
1231                 return 0;
1232
1233         if (host) {
1234                 ret = mmc_resume_host(host->mmc);
1235                 if (ret == 0)
1236                         host->suspended = 0;
1237         }
1238
1239         return ret;
1240 }
1241 #else
1242 #define mmc_omap_suspend        NULL
1243 #define mmc_omap_resume         NULL
1244 #endif
1245
1246 static struct platform_driver mmc_omap_driver = {
1247         .probe          = mmc_omap_probe,
1248         .remove         = mmc_omap_remove,
1249         .suspend        = mmc_omap_suspend,
1250         .resume         = mmc_omap_resume,
1251         .driver         = {
1252                 .name   = DRIVER_NAME,
1253                 .owner  = THIS_MODULE,
1254         },
1255 };
1256
1257 static int __init mmc_omap_init(void)
1258 {
1259         return platform_driver_register(&mmc_omap_driver);
1260 }
1261
1262 static void __exit mmc_omap_exit(void)
1263 {
1264         platform_driver_unregister(&mmc_omap_driver);
1265 }
1266
1267 module_init(mmc_omap_init);
1268 module_exit(mmc_omap_exit);
1269
1270 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1271 MODULE_LICENSE("GPL");
1272 MODULE_ALIAS("platform:" DRIVER_NAME);
1273 MODULE_AUTHOR("Juha Yrjölä");