2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrj�l�<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
29 #include <linux/i2c/tps65010.h>
33 #include <asm/mach-types.h>
35 #include <asm/arch/board.h>
36 #include <asm/arch/mmc.h>
37 #include <asm/arch/gpio.h>
38 #include <asm/arch/dma.h>
39 #include <asm/arch/mux.h>
40 #include <asm/arch/fpga.h>
41 #include <asm/arch/board-sx1.h>
43 #define OMAP_MMC_REG_CMD 0x00
44 #define OMAP_MMC_REG_ARGL 0x04
45 #define OMAP_MMC_REG_ARGH 0x08
46 #define OMAP_MMC_REG_CON 0x0c
47 #define OMAP_MMC_REG_STAT 0x10
48 #define OMAP_MMC_REG_IE 0x14
49 #define OMAP_MMC_REG_CTO 0x18
50 #define OMAP_MMC_REG_DTO 0x1c
51 #define OMAP_MMC_REG_DATA 0x20
52 #define OMAP_MMC_REG_BLEN 0x24
53 #define OMAP_MMC_REG_NBLK 0x28
54 #define OMAP_MMC_REG_BUF 0x2c
55 #define OMAP_MMC_REG_SDIO 0x34
56 #define OMAP_MMC_REG_REV 0x3c
57 #define OMAP_MMC_REG_RSP0 0x40
58 #define OMAP_MMC_REG_RSP1 0x44
59 #define OMAP_MMC_REG_RSP2 0x48
60 #define OMAP_MMC_REG_RSP3 0x4c
61 #define OMAP_MMC_REG_RSP4 0x50
62 #define OMAP_MMC_REG_RSP5 0x54
63 #define OMAP_MMC_REG_RSP6 0x58
64 #define OMAP_MMC_REG_RSP7 0x5c
65 #define OMAP_MMC_REG_IOSR 0x60
66 #define OMAP_MMC_REG_SYSC 0x64
67 #define OMAP_MMC_REG_SYSS 0x68
69 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
70 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
71 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
72 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
73 #define OMAP_MMC_STAT_A_FULL (1 << 10)
74 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
75 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
76 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
77 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
78 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
79 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
80 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
81 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
83 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
84 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
89 #define OMAP_MMC_CMDTYPE_BC 0
90 #define OMAP_MMC_CMDTYPE_BCR 1
91 #define OMAP_MMC_CMDTYPE_AC 2
92 #define OMAP_MMC_CMDTYPE_ADTC 3
95 #define DRIVER_NAME "mmci-omap"
97 /* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
99 #define OMAP_MMC_COVER_POLL_DELAY 500
101 struct mmc_omap_host;
103 struct mmc_omap_slot {
108 unsigned int fclk_freq;
111 struct tasklet_struct cover_tasklet;
112 struct timer_list cover_timer;
115 struct mmc_request *mrq;
116 struct mmc_omap_host *host;
117 struct mmc_host *mmc;
118 struct omap_mmc_slot_data *pdata;
121 struct mmc_omap_host {
124 struct mmc_request * mrq;
125 struct mmc_command * cmd;
126 struct mmc_data * data;
127 struct mmc_host * mmc;
129 unsigned char id; /* 16xx chips have 2 MMC blocks */
132 struct resource *mem_res;
133 void __iomem *virt_base;
134 unsigned int phys_base;
136 unsigned char bus_mode;
137 unsigned char hw_bus_mode;
139 struct work_struct cmd_abort_work;
141 struct timer_list cmd_abort_timer;
143 struct work_struct slot_release_work;
144 struct mmc_omap_slot *next_slot;
145 struct work_struct send_stop_work;
146 struct mmc_data *stop_data;
151 u32 buffer_bytes_left;
152 u32 total_bytes_left;
155 unsigned brs_received:1, dma_done:1;
156 unsigned dma_is_read:1;
157 unsigned dma_in_use:1;
160 struct timer_list dma_timer;
165 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
166 struct mmc_omap_slot *current_slot;
167 spinlock_t slot_lock;
168 wait_queue_head_t slot_wq;
171 struct timer_list clk_timer;
172 spinlock_t clk_lock; /* for changing enabled state */
173 unsigned int fclk_enabled:1;
175 struct omap_mmc_platform_data *pdata;
178 void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
180 unsigned long tick_ns;
182 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
183 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
188 void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
192 spin_lock_irqsave(&host->clk_lock, flags);
193 if (host->fclk_enabled != enable) {
194 host->fclk_enabled = enable;
196 clk_enable(host->fclk);
198 clk_disable(host->fclk);
200 spin_unlock_irqrestore(&host->clk_lock, flags);
203 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
205 struct mmc_omap_host *host = slot->host;
210 spin_lock_irqsave(&host->slot_lock, flags);
211 while (host->mmc != NULL) {
212 spin_unlock_irqrestore(&host->slot_lock, flags);
213 wait_event(host->slot_wq, host->mmc == NULL);
214 spin_lock_irqsave(&host->slot_lock, flags);
216 host->mmc = slot->mmc;
217 spin_unlock_irqrestore(&host->slot_lock, flags);
219 del_timer(&host->clk_timer);
220 if (host->current_slot != slot || !claimed)
221 mmc_omap_fclk_offdelay(host->current_slot);
223 if (host->current_slot != slot) {
224 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
225 if (host->pdata->switch_slot != NULL)
226 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
227 host->current_slot = slot;
231 mmc_omap_fclk_enable(host, 1);
233 /* Doing the dummy read here seems to work around some bug
234 * at least in OMAP24xx silicon where the command would not
235 * start after writing the CMD register. Sigh. */
236 OMAP_MMC_READ(host, CON);
238 OMAP_MMC_WRITE(host, CON, slot->saved_con);
240 mmc_omap_fclk_enable(host, 0);
243 static void mmc_omap_start_request(struct mmc_omap_host *host,
244 struct mmc_request *req);
246 static void mmc_omap_slot_release_work(struct work_struct *work)
248 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
250 struct mmc_omap_slot *next_slot = host->next_slot;
251 struct mmc_request *rq;
253 host->next_slot = NULL;
254 mmc_omap_select_slot(next_slot, 1);
257 next_slot->mrq = NULL;
258 mmc_omap_start_request(host, rq);
261 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
263 struct mmc_omap_host *host = slot->host;
267 BUG_ON(slot == NULL || host->mmc == NULL);
270 /* Keeps clock running for at least 8 cycles on valid freq */
271 mod_timer(&host->clk_timer, jiffies + HZ/10);
273 del_timer(&host->clk_timer);
274 mmc_omap_fclk_offdelay(slot);
275 mmc_omap_fclk_enable(host, 0);
278 spin_lock_irqsave(&host->slot_lock, flags);
279 /* Check for any pending requests */
280 for (i = 0; i < host->nr_slots; i++) {
281 struct mmc_omap_slot *new_slot;
283 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
286 BUG_ON(host->next_slot != NULL);
287 new_slot = host->slots[i];
288 /* The current slot should not have a request in queue */
289 BUG_ON(new_slot == host->current_slot);
291 host->next_slot = new_slot;
292 host->mmc = new_slot->mmc;
293 spin_unlock_irqrestore(&host->slot_lock, flags);
294 schedule_work(&host->slot_release_work);
299 wake_up(&host->slot_wq);
300 spin_unlock_irqrestore(&host->slot_lock, flags);
304 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
306 if (slot->pdata->get_cover_state)
307 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
312 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
315 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
316 struct mmc_omap_slot *slot = mmc_priv(mmc);
318 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
322 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
324 /* Access to the R/O switch is required for production testing
327 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
329 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
330 struct mmc_omap_slot *slot = mmc_priv(mmc);
332 return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
336 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
339 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
342 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
343 struct mmc_omap_slot *slot = mmc_priv(mmc);
345 return sprintf(buf, "%s\n", slot->pdata->name);
348 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
351 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
362 /* Our hardware needs to know exact type */
363 switch (mmc_resp_type(cmd)) {
368 /* resp 1, 1b, 6, 7 */
378 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
382 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
383 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
384 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
385 cmdtype = OMAP_MMC_CMDTYPE_BC;
386 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
387 cmdtype = OMAP_MMC_CMDTYPE_BCR;
389 cmdtype = OMAP_MMC_CMDTYPE_AC;
392 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
394 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
397 if (cmd->flags & MMC_RSP_BUSY)
400 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
403 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
405 OMAP_MMC_WRITE(host, CTO, 200);
406 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
407 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
408 OMAP_MMC_WRITE(host, IE,
409 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
410 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
411 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
412 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
413 OMAP_MMC_STAT_END_OF_DATA);
414 OMAP_MMC_WRITE(host, CMD, cmdreg);
418 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
421 enum dma_data_direction dma_data_dir;
423 BUG_ON(host->dma_ch < 0);
425 omap_stop_dma(host->dma_ch);
426 /* Release DMA channel lazily */
427 mod_timer(&host->dma_timer, jiffies + HZ);
428 if (data->flags & MMC_DATA_WRITE)
429 dma_data_dir = DMA_TO_DEVICE;
431 dma_data_dir = DMA_FROM_DEVICE;
432 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
436 static void mmc_omap_send_stop_work(struct work_struct *work)
438 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
440 struct mmc_omap_slot *slot = host->current_slot;
441 struct mmc_data *data = host->stop_data;
442 unsigned long tick_ns;
444 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
447 mmc_omap_start_command(host, data->stop);
451 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
453 if (host->dma_in_use)
454 mmc_omap_release_dma(host, data, data->error);
459 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
460 * dozens of requests until the card finishes writing data.
461 * It'd be cheaper to just wait till an EOFB interrupt arrives...
465 struct mmc_host *mmc;
469 mmc_omap_release_slot(host->current_slot, 1);
470 mmc_request_done(mmc, data->mrq);
474 host->stop_data = data;
475 schedule_work(&host->send_stop_work);
479 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
481 struct mmc_omap_slot *slot = host->current_slot;
482 unsigned int restarts, passes, timeout;
485 /* Sending abort takes 80 clocks. Have some extra and round up */
486 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
488 while (restarts < maxloops) {
489 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
490 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
493 while (passes < timeout) {
494 stat = OMAP_MMC_READ(host, STAT);
495 if (stat & OMAP_MMC_STAT_END_OF_CMD)
504 OMAP_MMC_WRITE(host, STAT, stat);
508 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
510 if (host->dma_in_use)
511 mmc_omap_release_dma(host, data, 1);
516 mmc_omap_send_abort(host, 10000);
520 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
525 if (!host->dma_in_use) {
526 mmc_omap_xfer_done(host, data);
530 spin_lock_irqsave(&host->dma_lock, flags);
534 host->brs_received = 1;
535 spin_unlock_irqrestore(&host->dma_lock, flags);
537 mmc_omap_xfer_done(host, data);
541 mmc_omap_dma_timer(unsigned long data)
543 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
545 BUG_ON(host->dma_ch < 0);
546 omap_free_dma(host->dma_ch);
551 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
557 spin_lock_irqsave(&host->dma_lock, flags);
558 if (host->brs_received)
562 spin_unlock_irqrestore(&host->dma_lock, flags);
564 mmc_omap_xfer_done(host, data);
568 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
572 del_timer(&host->cmd_abort_timer);
574 if (cmd->flags & MMC_RSP_PRESENT) {
575 if (cmd->flags & MMC_RSP_136) {
576 /* response type 2 */
578 OMAP_MMC_READ(host, RSP0) |
579 (OMAP_MMC_READ(host, RSP1) << 16);
581 OMAP_MMC_READ(host, RSP2) |
582 (OMAP_MMC_READ(host, RSP3) << 16);
584 OMAP_MMC_READ(host, RSP4) |
585 (OMAP_MMC_READ(host, RSP5) << 16);
587 OMAP_MMC_READ(host, RSP6) |
588 (OMAP_MMC_READ(host, RSP7) << 16);
590 /* response types 1, 1b, 3, 4, 5, 6 */
592 OMAP_MMC_READ(host, RSP6) |
593 (OMAP_MMC_READ(host, RSP7) << 16);
597 if (host->data == NULL || cmd->error) {
598 struct mmc_host *mmc;
600 if (host->data != NULL)
601 mmc_omap_abort_xfer(host, host->data);
604 mmc_omap_release_slot(host->current_slot, 1);
605 mmc_request_done(mmc, cmd->mrq);
610 * Abort stuck command. Can occur when card is removed while it is being
613 static void mmc_omap_abort_command(struct work_struct *work)
615 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
619 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
622 if (host->cmd->error == 0)
623 host->cmd->error = -ETIMEDOUT;
625 if (host->data == NULL) {
626 struct mmc_command *cmd;
627 struct mmc_host *mmc;
631 mmc_omap_send_abort(host, 10000);
635 mmc_omap_release_slot(host->current_slot, 1);
636 mmc_request_done(mmc, cmd->mrq);
638 mmc_omap_cmd_done(host, host->cmd);
641 enable_irq(host->irq);
645 mmc_omap_cmd_timer(unsigned long data)
647 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
650 spin_lock_irqsave(&host->slot_lock, flags);
651 if (host->cmd != NULL && !host->abort) {
652 OMAP_MMC_WRITE(host, IE, 0);
653 disable_irq(host->irq);
655 schedule_work(&host->cmd_abort_work);
657 spin_unlock_irqrestore(&host->slot_lock, flags);
662 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
664 struct scatterlist *sg;
666 sg = host->data->sg + host->sg_idx;
667 host->buffer_bytes_left = sg->length;
668 host->buffer = sg_virt(sg);
669 if (host->buffer_bytes_left > host->total_bytes_left)
670 host->buffer_bytes_left = host->total_bytes_left;
674 mmc_omap_clk_timer(unsigned long data)
676 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
678 mmc_omap_fclk_enable(host, 0);
683 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
687 if (host->buffer_bytes_left == 0) {
689 BUG_ON(host->sg_idx == host->sg_len);
690 mmc_omap_sg_to_buf(host);
693 if (n > host->buffer_bytes_left)
694 n = host->buffer_bytes_left;
695 host->buffer_bytes_left -= n;
696 host->total_bytes_left -= n;
697 host->data->bytes_xfered += n;
700 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
702 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
706 static inline void mmc_omap_report_irq(u16 status)
708 static const char *mmc_omap_status_bits[] = {
709 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
710 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
714 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
715 if (status & (1 << i)) {
718 printk("%s", mmc_omap_status_bits[i]);
723 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
725 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
729 int transfer_error, cmd_error;
731 if (host->cmd == NULL && host->data == NULL) {
732 status = OMAP_MMC_READ(host, STAT);
733 dev_info(mmc_dev(host->slots[0]->mmc),
734 "Spurious IRQ 0x%04x\n", status);
736 OMAP_MMC_WRITE(host, STAT, status);
737 OMAP_MMC_WRITE(host, IE, 0);
747 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
750 OMAP_MMC_WRITE(host, STAT, status);
751 if (host->cmd != NULL)
752 cmd = host->cmd->opcode;
755 #ifdef CONFIG_MMC_DEBUG
756 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
758 mmc_omap_report_irq(status);
761 if (host->total_bytes_left) {
762 if ((status & OMAP_MMC_STAT_A_FULL) ||
763 (status & OMAP_MMC_STAT_END_OF_DATA))
764 mmc_omap_xfer_data(host, 0);
765 if (status & OMAP_MMC_STAT_A_EMPTY)
766 mmc_omap_xfer_data(host, 1);
769 if (status & OMAP_MMC_STAT_END_OF_DATA)
772 if (status & OMAP_MMC_STAT_DATA_TOUT) {
773 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
776 host->data->error = -ETIMEDOUT;
781 if (status & OMAP_MMC_STAT_DATA_CRC) {
783 host->data->error = -EILSEQ;
784 dev_dbg(mmc_dev(host->mmc),
785 "data CRC error, bytes left %d\n",
786 host->total_bytes_left);
789 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
793 if (status & OMAP_MMC_STAT_CMD_TOUT) {
794 /* Timeouts are routine with some commands */
796 struct mmc_omap_slot *slot =
798 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
799 host->cmd->opcode != MMC_SEND_OP_COND &&
800 host->cmd->opcode != MMC_APP_CMD &&
802 !mmc_omap_cover_is_open(slot)))
803 dev_err(mmc_dev(host->mmc),
804 "command timeout (CMD%d)\n",
806 host->cmd->error = -ETIMEDOUT;
812 if (status & OMAP_MMC_STAT_CMD_CRC) {
814 dev_err(mmc_dev(host->mmc),
815 "command CRC error (CMD%d, arg 0x%08x)\n",
816 cmd, host->cmd->arg);
817 host->cmd->error = -EILSEQ;
821 dev_err(mmc_dev(host->mmc),
822 "command CRC error without cmd?\n");
825 if (status & OMAP_MMC_STAT_CARD_ERR) {
826 dev_dbg(mmc_dev(host->mmc),
827 "ignoring card status error (CMD%d)\n",
833 * NOTE: On 1610 the END_OF_CMD may come too early when
836 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
837 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
842 if (cmd_error && host->data) {
843 del_timer(&host->cmd_abort_timer);
845 OMAP_MMC_WRITE(host, IE, 0);
846 disable_irq(host->irq);
847 schedule_work(&host->cmd_abort_work);
852 mmc_omap_cmd_done(host, host->cmd);
853 if (host->data != NULL) {
855 mmc_omap_xfer_done(host, host->data);
856 else if (end_transfer)
857 mmc_omap_end_of_data(host, host->data);
863 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
866 struct mmc_omap_host *host = dev_get_drvdata(dev);
867 struct mmc_omap_slot *slot = host->slots[num];
869 BUG_ON(num >= host->nr_slots);
871 /* Other subsystems can call in here before we're initialised. */
872 if (host->nr_slots == 0 || !host->slots[num])
875 cover_open = mmc_omap_cover_is_open(slot);
876 if (cover_open != slot->cover_open) {
877 slot->cover_open = cover_open;
878 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
881 tasklet_hi_schedule(&slot->cover_tasklet);
884 static void mmc_omap_cover_timer(unsigned long arg)
886 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
887 tasklet_schedule(&slot->cover_tasklet);
890 static void mmc_omap_cover_handler(unsigned long param)
892 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
893 int cover_open = mmc_omap_cover_is_open(slot);
895 mmc_detect_change(slot->mmc, 0);
900 * If no card is inserted, we postpone polling until
901 * the cover has been closed.
903 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
906 mod_timer(&slot->cover_timer,
907 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
910 /* Prepare to transfer the next segment of a scatterlist */
912 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
914 int dma_ch = host->dma_ch;
915 unsigned long data_addr;
918 struct scatterlist *sg = &data->sg[host->sg_idx];
923 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
925 count = sg_dma_len(sg);
927 if ((data->blocks == 1) && (count > data->blksz))
930 host->dma_len = count;
932 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
933 * Use 16 or 32 word frames when the blocksize is at least that large.
934 * Blocksize is usually 512 bytes; but not for some SD reads.
936 if (cpu_is_omap15xx() && frame > 32)
943 if (!(data->flags & MMC_DATA_WRITE)) {
944 buf = 0x800f | ((frame - 1) << 8);
946 if (cpu_class_is_omap1()) {
947 src_port = OMAP_DMA_PORT_TIPB;
948 dst_port = OMAP_DMA_PORT_EMIFF;
950 if (cpu_is_omap24xx())
951 sync_dev = OMAP24XX_DMA_MMC1_RX;
953 omap_set_dma_src_params(dma_ch, src_port,
954 OMAP_DMA_AMODE_CONSTANT,
956 omap_set_dma_dest_params(dma_ch, dst_port,
957 OMAP_DMA_AMODE_POST_INC,
958 sg_dma_address(sg), 0, 0);
959 omap_set_dma_dest_data_pack(dma_ch, 1);
960 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
962 buf = 0x0f80 | ((frame - 1) << 0);
964 if (cpu_class_is_omap1()) {
965 src_port = OMAP_DMA_PORT_EMIFF;
966 dst_port = OMAP_DMA_PORT_TIPB;
968 if (cpu_is_omap24xx())
969 sync_dev = OMAP24XX_DMA_MMC1_TX;
971 omap_set_dma_dest_params(dma_ch, dst_port,
972 OMAP_DMA_AMODE_CONSTANT,
974 omap_set_dma_src_params(dma_ch, src_port,
975 OMAP_DMA_AMODE_POST_INC,
976 sg_dma_address(sg), 0, 0);
977 omap_set_dma_src_data_pack(dma_ch, 1);
978 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
981 /* Max limit for DMA frame count is 0xffff */
982 BUG_ON(count > 0xffff);
984 OMAP_MMC_WRITE(host, BUF, buf);
985 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
986 frame, count, OMAP_DMA_SYNC_FRAME,
990 /* A scatterlist segment completed */
991 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
993 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
994 struct mmc_data *mmcdat = host->data;
996 if (unlikely(host->dma_ch < 0)) {
997 dev_err(mmc_dev(host->mmc),
998 "DMA callback while DMA not enabled\n");
1001 /* FIXME: We really should do something to _handle_ the errors */
1002 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
1003 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
1006 if (ch_status & OMAP_DMA_DROP_IRQ) {
1007 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
1010 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1013 mmcdat->bytes_xfered += host->dma_len;
1015 if (host->sg_idx < host->sg_len) {
1016 mmc_omap_prepare_dma(host, host->data);
1017 omap_start_dma(host->dma_ch);
1019 mmc_omap_dma_done(host, host->data);
1022 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
1024 const char *dev_name;
1025 int sync_dev, dma_ch, is_read, r;
1027 is_read = !(data->flags & MMC_DATA_WRITE);
1028 del_timer_sync(&host->dma_timer);
1029 if (host->dma_ch >= 0) {
1030 if (is_read == host->dma_is_read)
1032 omap_free_dma(host->dma_ch);
1037 if (host->id == 1) {
1038 sync_dev = OMAP_DMA_MMC_RX;
1039 dev_name = "MMC1 read";
1041 sync_dev = OMAP_DMA_MMC2_RX;
1042 dev_name = "MMC2 read";
1045 if (host->id == 1) {
1046 sync_dev = OMAP_DMA_MMC_TX;
1047 dev_name = "MMC1 write";
1049 sync_dev = OMAP_DMA_MMC2_TX;
1050 dev_name = "MMC2 write";
1053 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
1056 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
1059 host->dma_ch = dma_ch;
1060 host->dma_is_read = is_read;
1065 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1069 reg = OMAP_MMC_READ(host, SDIO);
1071 OMAP_MMC_WRITE(host, SDIO, reg);
1072 /* Set maximum timeout */
1073 OMAP_MMC_WRITE(host, CTO, 0xff);
1076 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1078 unsigned int timeout, cycle_ns;
1081 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
1082 timeout = req->data->timeout_ns / cycle_ns;
1083 timeout += req->data->timeout_clks;
1085 /* Check if we need to use timeout multiplier register */
1086 reg = OMAP_MMC_READ(host, SDIO);
1087 if (timeout > 0xffff) {
1092 OMAP_MMC_WRITE(host, SDIO, reg);
1093 OMAP_MMC_WRITE(host, DTO, timeout);
1097 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
1099 struct mmc_data *data = req->data;
1100 int i, use_dma, block_size;
1105 OMAP_MMC_WRITE(host, BLEN, 0);
1106 OMAP_MMC_WRITE(host, NBLK, 0);
1107 OMAP_MMC_WRITE(host, BUF, 0);
1108 host->dma_in_use = 0;
1109 set_cmd_timeout(host, req);
1113 block_size = data->blksz;
1115 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1116 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1117 set_data_timeout(host, req);
1119 /* cope with calling layer confusion; it issues "single
1120 * block" writes using multi-block scatterlists.
1122 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1124 /* Only do DMA for entire blocks */
1125 use_dma = host->use_dma;
1127 for (i = 0; i < sg_len; i++) {
1128 if ((data->sg[i].length % block_size) != 0) {
1137 if (mmc_omap_get_dma_channel(host, data) == 0) {
1138 enum dma_data_direction dma_data_dir;
1140 if (data->flags & MMC_DATA_WRITE)
1141 dma_data_dir = DMA_TO_DEVICE;
1143 dma_data_dir = DMA_FROM_DEVICE;
1145 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1146 sg_len, dma_data_dir);
1147 host->total_bytes_left = 0;
1148 mmc_omap_prepare_dma(host, req->data);
1149 host->brs_received = 0;
1151 host->dma_in_use = 1;
1156 /* Revert to PIO? */
1158 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1159 host->total_bytes_left = data->blocks * block_size;
1160 host->sg_len = sg_len;
1161 mmc_omap_sg_to_buf(host);
1162 host->dma_in_use = 0;
1166 static void mmc_omap_start_request(struct mmc_omap_host *host,
1167 struct mmc_request *req)
1169 BUG_ON(host->mrq != NULL);
1173 /* only touch fifo AFTER the controller readies it */
1174 mmc_omap_prepare_data(host, req);
1175 mmc_omap_start_command(host, req->cmd);
1176 if (host->dma_in_use)
1177 omap_start_dma(host->dma_ch);
1178 BUG_ON(irqs_disabled());
1181 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1183 struct mmc_omap_slot *slot = mmc_priv(mmc);
1184 struct mmc_omap_host *host = slot->host;
1185 unsigned long flags;
1187 spin_lock_irqsave(&host->slot_lock, flags);
1188 if (host->mmc != NULL) {
1189 BUG_ON(slot->mrq != NULL);
1191 spin_unlock_irqrestore(&host->slot_lock, flags);
1195 spin_unlock_irqrestore(&host->slot_lock, flags);
1196 mmc_omap_select_slot(slot, 1);
1197 mmc_omap_start_request(host, req);
1200 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1203 struct mmc_omap_host *host;
1207 if (slot->pdata->set_power != NULL)
1208 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1211 if (cpu_is_omap24xx()) {
1215 w = OMAP_MMC_READ(host, CON);
1216 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1218 w = OMAP_MMC_READ(host, CON);
1219 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1224 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1226 struct mmc_omap_slot *slot = mmc_priv(mmc);
1227 struct mmc_omap_host *host = slot->host;
1228 int func_clk_rate = clk_get_rate(host->fclk);
1231 if (ios->clock == 0)
1234 dsor = func_clk_rate / ios->clock;
1238 if (func_clk_rate / dsor > ios->clock)
1244 slot->fclk_freq = func_clk_rate / dsor;
1246 if (ios->bus_width == MMC_BUS_WIDTH_4)
1252 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1254 struct mmc_omap_slot *slot = mmc_priv(mmc);
1255 struct mmc_omap_host *host = slot->host;
1259 mmc_omap_select_slot(slot, 0);
1261 dsor = mmc_omap_calc_divisor(mmc, ios);
1263 if (ios->vdd != slot->vdd)
1264 slot->vdd = ios->vdd;
1267 switch (ios->power_mode) {
1269 mmc_omap_set_power(slot, 0, ios->vdd);
1272 /* Cannot touch dsor yet, just power up MMC */
1273 mmc_omap_set_power(slot, 1, ios->vdd);
1276 mmc_omap_fclk_enable(host, 1);
1282 if (slot->bus_mode != ios->bus_mode) {
1283 if (slot->pdata->set_bus_mode != NULL)
1284 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1286 slot->bus_mode = ios->bus_mode;
1289 /* On insanely high arm_per frequencies something sometimes
1290 * goes somehow out of sync, and the POW bit is not being set,
1291 * which results in the while loop below getting stuck.
1292 * Writing to the CON register twice seems to do the trick. */
1293 for (i = 0; i < 2; i++)
1294 OMAP_MMC_WRITE(host, CON, dsor);
1295 slot->saved_con = dsor;
1296 if (ios->power_mode == MMC_POWER_ON) {
1297 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1300 /* Send clock cycles, poll completion */
1301 OMAP_MMC_WRITE(host, IE, 0);
1302 OMAP_MMC_WRITE(host, STAT, 0xffff);
1303 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1304 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1308 OMAP_MMC_WRITE(host, STAT, 1);
1312 mmc_omap_release_slot(slot, clk_enabled);
1315 static int mmc_omap_get_ro(struct mmc_host *mmc)
1317 struct mmc_omap_slot *slot = mmc_priv(mmc);
1319 if (slot->pdata->get_ro != NULL)
1320 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1324 static const struct mmc_host_ops mmc_omap_ops = {
1325 .request = mmc_omap_request,
1326 .set_ios = mmc_omap_set_ios,
1327 .get_ro = mmc_omap_get_ro,
1330 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1332 struct mmc_omap_slot *slot = NULL;
1333 struct mmc_host *mmc;
1336 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1340 slot = mmc_priv(mmc);
1344 slot->pdata = &host->pdata->slots[id];
1346 host->slots[id] = slot;
1348 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1349 MMC_CAP_SD_HIGHSPEED;
1350 if (host->pdata->conf.wire4)
1351 mmc->caps |= MMC_CAP_4_BIT_DATA;
1353 mmc->ops = &mmc_omap_ops;
1354 mmc->f_min = 400000;
1356 if (cpu_class_is_omap2())
1357 mmc->f_max = 48000000;
1359 mmc->f_max = 24000000;
1360 if (host->pdata->max_freq)
1361 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1362 mmc->ocr_avail = slot->pdata->ocr_mask;
1364 /* Use scatterlist DMA to reduce per-transfer costs.
1365 * NOTE max_seg_size assumption that small blocks aren't
1366 * normally used (except e.g. for reading SD registers).
1368 mmc->max_phys_segs = 32;
1369 mmc->max_hw_segs = 32;
1370 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1371 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1372 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1373 mmc->max_seg_size = mmc->max_req_size;
1375 r = mmc_add_host(mmc);
1379 if (slot->pdata->name != NULL) {
1380 r = device_create_file(&mmc->class_dev,
1381 &dev_attr_slot_name);
1383 goto err_remove_host;
1386 if (slot->pdata->get_cover_state != NULL) {
1387 r = device_create_file(&mmc->class_dev,
1388 &dev_attr_cover_switch);
1390 goto err_remove_slot_name;
1392 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1393 (unsigned long)slot);
1394 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1395 (unsigned long)slot);
1396 tasklet_schedule(&slot->cover_tasklet);
1399 if (slot->pdata->get_ro != NULL) {
1400 r = device_create_file(&mmc->class_dev,
1403 goto err_remove_cover_attr;
1408 err_remove_cover_attr:
1409 if (slot->pdata->get_cover_state != NULL)
1410 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1411 err_remove_slot_name:
1412 if (slot->pdata->name != NULL)
1413 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1415 mmc_remove_host(mmc);
1419 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1421 struct mmc_host *mmc = slot->mmc;
1423 if (slot->pdata->name != NULL)
1424 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1425 if (slot->pdata->get_cover_state != NULL)
1426 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1427 if (slot->pdata->get_ro != NULL)
1428 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1430 tasklet_kill(&slot->cover_tasklet);
1431 del_timer_sync(&slot->cover_timer);
1432 flush_scheduled_work();
1434 mmc_remove_host(mmc);
1438 static int __init mmc_omap_probe(struct platform_device *pdev)
1440 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1441 struct mmc_omap_host *host = NULL;
1442 struct resource *res;
1446 if (pdata == NULL) {
1447 dev_err(&pdev->dev, "platform data missing\n");
1450 if (pdata->nr_slots == 0) {
1451 dev_err(&pdev->dev, "no slots\n");
1455 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1456 irq = platform_get_irq(pdev, 0);
1457 if (res == NULL || irq < 0)
1460 res = request_mem_region(res->start, res->end - res->start + 1,
1465 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1468 goto err_free_mem_region;
1471 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1472 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1474 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1475 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1476 (unsigned long) host);
1478 spin_lock_init(&host->clk_lock);
1479 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1481 spin_lock_init(&host->dma_lock);
1482 setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1483 spin_lock_init(&host->slot_lock);
1484 init_waitqueue_head(&host->slot_wq);
1486 host->pdata = pdata;
1487 host->dev = &pdev->dev;
1488 platform_set_drvdata(pdev, host);
1490 host->id = pdev->id;
1491 host->mem_res = res;
1498 host->phys_base = host->mem_res->start;
1499 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1501 if (cpu_is_omap24xx()) {
1502 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1503 if (IS_ERR(host->iclk))
1504 goto err_free_mmc_host;
1505 clk_enable(host->iclk);
1508 if (!cpu_is_omap24xx())
1509 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1511 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1513 if (IS_ERR(host->fclk)) {
1514 ret = PTR_ERR(host->fclk);
1518 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1522 if (pdata->init != NULL) {
1523 ret = pdata->init(&pdev->dev);
1528 host->nr_slots = pdata->nr_slots;
1529 for (i = 0; i < pdata->nr_slots; i++) {
1530 ret = mmc_omap_new_slot(host, i);
1533 mmc_omap_remove_slot(host->slots[i]);
1535 goto err_plat_cleanup;
1543 pdata->cleanup(&pdev->dev);
1545 free_irq(host->irq, host);
1547 clk_put(host->fclk);
1549 if (host->iclk != NULL) {
1550 clk_disable(host->iclk);
1551 clk_put(host->iclk);
1555 err_free_mem_region:
1556 release_mem_region(res->start, res->end - res->start + 1);
1560 static int mmc_omap_remove(struct platform_device *pdev)
1562 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1565 platform_set_drvdata(pdev, NULL);
1567 BUG_ON(host == NULL);
1569 for (i = 0; i < host->nr_slots; i++)
1570 mmc_omap_remove_slot(host->slots[i]);
1572 if (host->pdata->cleanup)
1573 host->pdata->cleanup(&pdev->dev);
1575 if (host->iclk && !IS_ERR(host->iclk))
1576 clk_put(host->iclk);
1577 if (host->fclk && !IS_ERR(host->fclk))
1578 clk_put(host->fclk);
1580 release_mem_region(pdev->resource[0].start,
1581 pdev->resource[0].end - pdev->resource[0].start + 1);
1589 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1592 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1594 if (host == NULL || host->suspended)
1597 for (i = 0; i < host->nr_slots; i++) {
1598 struct mmc_omap_slot *slot;
1600 slot = host->slots[i];
1601 ret = mmc_suspend_host(slot->mmc, mesg);
1604 slot = host->slots[i];
1605 mmc_resume_host(slot->mmc);
1610 host->suspended = 1;
1614 static int mmc_omap_resume(struct platform_device *pdev)
1617 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1619 if (host == NULL || !host->suspended)
1622 for (i = 0; i < host->nr_slots; i++) {
1623 struct mmc_omap_slot *slot;
1624 slot = host->slots[i];
1625 ret = mmc_resume_host(slot->mmc);
1629 host->suspended = 0;
1634 #define mmc_omap_suspend NULL
1635 #define mmc_omap_resume NULL
1638 static struct platform_driver mmc_omap_driver = {
1639 .probe = mmc_omap_probe,
1640 .remove = mmc_omap_remove,
1641 .suspend = mmc_omap_suspend,
1642 .resume = mmc_omap_resume,
1644 .name = DRIVER_NAME,
1645 .owner = THIS_MODULE,
1649 static int __init mmc_omap_init(void)
1651 return platform_driver_register(&mmc_omap_driver);
1654 static void __exit mmc_omap_exit(void)
1656 platform_driver_unregister(&mmc_omap_driver);
1659 module_init(mmc_omap_init);
1660 module_exit(mmc_omap_exit);
1662 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1663 MODULE_LICENSE("GPL");
1664 MODULE_ALIAS("platform:" DRIVER_NAME);
1665 MODULE_AUTHOR("Juha Yrj�l�");