drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/dma.h>
  37 #include <asm/arch/mux.h>
  38 #include <asm/arch/fpga.h>
  39
  40 #define OMAP_MMC_REG_CMD        0x00
  41 #define OMAP_MMC_REG_ARGL       0x04
  42 #define OMAP_MMC_REG_ARGH       0x08
  43 #define OMAP_MMC_REG_CON        0x0c
  44 #define OMAP_MMC_REG_STAT       0x10
  45 #define OMAP_MMC_REG_IE         0x14
  46 #define OMAP_MMC_REG_CTO        0x18
  47 #define OMAP_MMC_REG_DTO        0x1c
  48 #define OMAP_MMC_REG_DATA       0x20
  49 #define OMAP_MMC_REG_BLEN       0x24
  50 #define OMAP_MMC_REG_NBLK       0x28
  51 #define OMAP_MMC_REG_BUF        0x2c
  52 #define OMAP_MMC_REG_SDIO       0x34
  53 #define OMAP_MMC_REG_REV        0x3c
  54 #define OMAP_MMC_REG_RSP0       0x40
  55 #define OMAP_MMC_REG_RSP1       0x44
  56 #define OMAP_MMC_REG_RSP2       0x48
  57 #define OMAP_MMC_REG_RSP3       0x4c
  58 #define OMAP_MMC_REG_RSP4       0x50
  59 #define OMAP_MMC_REG_RSP5       0x54
  60 #define OMAP_MMC_REG_RSP6       0x58
  61 #define OMAP_MMC_REG_RSP7       0x5c
  62 #define OMAP_MMC_REG_IOSR       0x60
  63 #define OMAP_MMC_REG_SYSC       0x64
  64 #define OMAP_MMC_REG_SYSS       0x68
  65
  66 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  67 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  68 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  69 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  70 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  71 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  72 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  73 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  74 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  75 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  76 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  77 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  78 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  79
  80 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  81 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  82
  83 /*
  84  * Command types
  85  */
  86 #define OMAP_MMC_CMDTYPE_BC     0
  87 #define OMAP_MMC_CMDTYPE_BCR    1
  88 #define OMAP_MMC_CMDTYPE_AC     2
  89 #define OMAP_MMC_CMDTYPE_ADTC   3
  90
  91
  92 #define DRIVER_NAME "mmci-omap"
  93
  94 /* Specifies how often in millisecs to poll for card status changes
  95  * when the cover switch is open */
  96 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  97
  98 static int mmc_omap_enable_poll = 1;
  99
 100 struct mmc_omap_host {
 101         int                     initialized;
 102         int                     suspended;
 103         struct mmc_request *    mrq;
 104         struct mmc_command *    cmd;
 105         struct mmc_data *       data;
 106         struct mmc_host *       mmc;
 107         struct device *         dev;
 108         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 109         struct clk *            iclk;
 110         struct clk *            fclk;
 111         struct resource         *mem_res;
 112         void __iomem            *virt_base;
 113         unsigned int            phys_base;
 114         int                     irq;
 115         unsigned char           bus_mode;
 116         unsigned char           hw_bus_mode;
 117
 118         unsigned int            sg_len;
 119         int                     sg_idx;
 120         u16 *                   buffer;
 121         u32                     buffer_bytes_left;
 122         u32                     total_bytes_left;
 123
 124         unsigned                use_dma:1;
 125         unsigned                brs_received:1, dma_done:1;
 126         unsigned                dma_is_read:1;
 127         unsigned                dma_in_use:1;
 128         int                     dma_ch;
 129         spinlock_t              dma_lock;
 130         struct timer_list       dma_timer;
 131         unsigned                dma_len;
 132
 133         short                   power_pin;
 134         short                   wp_pin;
 135
 136         int                     switch_pin;
 137         struct work_struct      switch_work;
 138         struct timer_list       switch_timer;
 139         int                     switch_last_state;
 140 };
 141
 142 static inline int
 143 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 144 {
 145         if (host->switch_pin < 0)
 146                 return 0;
 147         return omap_get_gpio_datain(host->switch_pin);
 148 }
 149
 150 static ssize_t
 151 mmc_omap_show_cover_switch(struct device *dev,
 152         struct device_attribute *attr, char *buf)
 153 {
 154         struct mmc_omap_host *host = dev_get_drvdata(dev);
 155
 156         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
 157                         "closed");
 158 }
 159
 160 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 161
 162 static ssize_t
 163 mmc_omap_show_enable_poll(struct device *dev,
 164         struct device_attribute *attr, char *buf)
 165 {
 166         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 167 }
 168
 169 static ssize_t
 170 mmc_omap_store_enable_poll(struct device *dev,
 171         struct device_attribute *attr, const char *buf,
 172         size_t size)
 173 {
 174         int enable_poll;
 175
 176         if (sscanf(buf, "%10d", &enable_poll) != 1)
 177                 return -EINVAL;
 178
 179         if (enable_poll != mmc_omap_enable_poll) {
 180                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 181
 182                 mmc_omap_enable_poll = enable_poll;
 183                 if (enable_poll && host->switch_pin >= 0)
 184                         schedule_work(&host->switch_work);
 185         }
 186         return size;
 187 }
 188
 189 static DEVICE_ATTR(enable_poll, 0664,
 190                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 191
 192 static void
 193 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 194 {
 195         u32 cmdreg;
 196         u32 resptype;
 197         u32 cmdtype;
 198
 199         host->cmd = cmd;
 200
 201         resptype = 0;
 202         cmdtype = 0;
 203
 204         /* Our hardware needs to know exact type */
 205         switch (mmc_resp_type(cmd)) {
 206         case MMC_RSP_NONE:
 207                 break;
 208         case MMC_RSP_R1:
 209         case MMC_RSP_R1B:
 210                 /* resp 1, 1b, 6, 7 */
 211                 resptype = 1;
 212                 break;
 213         case MMC_RSP_R2:
 214                 resptype = 2;
 215                 break;
 216         case MMC_RSP_R3:
 217                 resptype = 3;
 218                 break;
 219         default:
 220                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 221                 break;
 222         }
 223
 224         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 225                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 226         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 227                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 228         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 229                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 230         } else {
 231                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 232         }
 233
 234         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 235
 236         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 237                 cmdreg |= 1 << 6;
 238
 239         if (cmd->flags & MMC_RSP_BUSY)
 240                 cmdreg |= 1 << 11;
 241
 242         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 243                 cmdreg |= 1 << 15;
 244
 245         clk_enable(host->fclk);
 246
 247         OMAP_MMC_WRITE(host, CTO, 200);
 248         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 249         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 250         OMAP_MMC_WRITE(host, IE,
 251                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 252                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 253                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 254                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 255                        OMAP_MMC_STAT_END_OF_DATA);
 256         OMAP_MMC_WRITE(host, CMD, cmdreg);
 257 }
 258
 259 static void
 260 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 261 {
 262         if (host->dma_in_use) {
 263                 enum dma_data_direction dma_data_dir;
 264
 265                 BUG_ON(host->dma_ch < 0);
 266                 if (data->error)
 267                         omap_stop_dma(host->dma_ch);
 268                 /* Release DMA channel lazily */
 269                 mod_timer(&host->dma_timer, jiffies + HZ);
 270                 if (data->flags & MMC_DATA_WRITE)
 271                         dma_data_dir = DMA_TO_DEVICE;
 272                 else
 273                         dma_data_dir = DMA_FROM_DEVICE;
 274                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 275                              dma_data_dir);
 276         }
 277         host->data = NULL;
 278         host->sg_len = 0;
 279         clk_disable(host->fclk);
 280
 281         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 282          * dozens of requests until the card finishes writing data.
 283          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 284          */
 285
 286         if (!data->stop) {
 287                 host->mrq = NULL;
 288                 mmc_request_done(host->mmc, data->mrq);
 289                 return;
 290         }
 291
 292         mmc_omap_start_command(host, data->stop);
 293 }
 294
 295 static void
 296 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 297 {
 298         unsigned long flags;
 299         int done;
 300
 301         if (!host->dma_in_use) {
 302                 mmc_omap_xfer_done(host, data);
 303                 return;
 304         }
 305         done = 0;
 306         spin_lock_irqsave(&host->dma_lock, flags);
 307         if (host->dma_done)
 308                 done = 1;
 309         else
 310                 host->brs_received = 1;
 311         spin_unlock_irqrestore(&host->dma_lock, flags);
 312         if (done)
 313                 mmc_omap_xfer_done(host, data);
 314 }
 315
 316 static void
 317 mmc_omap_dma_timer(unsigned long data)
 318 {
 319         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 320
 321         BUG_ON(host->dma_ch < 0);
 322         omap_free_dma(host->dma_ch);
 323         host->dma_ch = -1;
 324 }
 325
 326 static void
 327 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 328 {
 329         unsigned long flags;
 330         int done;
 331
 332         done = 0;
 333         spin_lock_irqsave(&host->dma_lock, flags);
 334         if (host->brs_received)
 335                 done = 1;
 336         else
 337                 host->dma_done = 1;
 338         spin_unlock_irqrestore(&host->dma_lock, flags);
 339         if (done)
 340                 mmc_omap_xfer_done(host, data);
 341 }
 342
 343 static void
 344 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 345 {
 346         host->cmd = NULL;
 347
 348         if (cmd->flags & MMC_RSP_PRESENT) {
 349                 if (cmd->flags & MMC_RSP_136) {
 350                         /* response type 2 */
 351                         cmd->resp[3] =
 352                                 OMAP_MMC_READ(host, RSP0) |
 353                                 (OMAP_MMC_READ(host, RSP1) << 16);
 354                         cmd->resp[2] =
 355                                 OMAP_MMC_READ(host, RSP2) |
 356                                 (OMAP_MMC_READ(host, RSP3) << 16);
 357                         cmd->resp[1] =
 358                                 OMAP_MMC_READ(host, RSP4) |
 359                                 (OMAP_MMC_READ(host, RSP5) << 16);
 360                         cmd->resp[0] =
 361                                 OMAP_MMC_READ(host, RSP6) |
 362                                 (OMAP_MMC_READ(host, RSP7) << 16);
 363                 } else {
 364                         /* response types 1, 1b, 3, 4, 5, 6 */
 365                         cmd->resp[0] =
 366                                 OMAP_MMC_READ(host, RSP6) |
 367                                 (OMAP_MMC_READ(host, RSP7) << 16);
 368                 }
 369         }
 370
 371         if (host->data == NULL || cmd->error) {
 372                 host->mrq = NULL;
 373                 clk_disable(host->fclk);
 374                 mmc_request_done(host->mmc, cmd->mrq);
 375         }
 376 }
 377
 378 /* PIO only */
 379 static void
 380 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 381 {
 382         struct scatterlist *sg;
 383
 384         sg = host->data->sg + host->sg_idx;
 385         host->buffer_bytes_left = sg->length;
 386         host->buffer = sg_virt(sg);
 387         if (host->buffer_bytes_left > host->total_bytes_left)
 388                 host->buffer_bytes_left = host->total_bytes_left;
 389 }
 390
 391 /* PIO only */
 392 static void
 393 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 394 {
 395         int n;
 396
 397         if (host->buffer_bytes_left == 0) {
 398                 host->sg_idx++;
 399                 BUG_ON(host->sg_idx == host->sg_len);
 400                 mmc_omap_sg_to_buf(host);
 401         }
 402         n = 64;
 403         if (n > host->buffer_bytes_left)
 404                 n = host->buffer_bytes_left;
 405         host->buffer_bytes_left -= n;
 406         host->total_bytes_left -= n;
 407         host->data->bytes_xfered += n;
 408
 409         if (write) {
 410                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 411         } else {
 412                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 413         }
 414 }
 415
 416 static inline void mmc_omap_report_irq(u16 status)
 417 {
 418         static const char *mmc_omap_status_bits[] = {
 419                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 420                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 421         };
 422         int i, c = 0;
 423
 424         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 425                 if (status & (1 << i)) {
 426                         if (c)
 427                                 printk(" ");
 428                         printk("%s", mmc_omap_status_bits[i]);
 429                         c++;
 430                 }
 431 }
 432
 433 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 434 {
 435         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 436         u16 status;
 437         int end_command;
 438         int end_transfer;
 439         int transfer_error;
 440
 441         if (host->cmd == NULL && host->data == NULL) {
 442                 status = OMAP_MMC_READ(host, STAT);
 443                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 444                 if (status != 0) {
 445                         OMAP_MMC_WRITE(host, STAT, status);
 446                         OMAP_MMC_WRITE(host, IE, 0);
 447                 }
 448                 return IRQ_HANDLED;
 449         }
 450
 451         end_command = 0;
 452         end_transfer = 0;
 453         transfer_error = 0;
 454
 455         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 456                 OMAP_MMC_WRITE(host, STAT, status);
 457 #ifdef CONFIG_MMC_DEBUG
 458                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 459                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 460                 mmc_omap_report_irq(status);
 461                 printk("\n");
 462 #endif
 463                 if (host->total_bytes_left) {
 464                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 465                             (status & OMAP_MMC_STAT_END_OF_DATA))
 466                                 mmc_omap_xfer_data(host, 0);
 467                         if (status & OMAP_MMC_STAT_A_EMPTY)
 468                                 mmc_omap_xfer_data(host, 1);
 469                 }
 470
 471                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 472                         end_transfer = 1;
 473                 }
 474
 475                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 476                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 477                         if (host->data) {
 478                                 host->data->error = -ETIMEDOUT;
 479                                 transfer_error = 1;
 480                         }
 481                 }
 482
 483                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 484                         if (host->data) {
 485                                 host->data->error = -EILSEQ;
 486                                 dev_dbg(mmc_dev(host->mmc),
 487                                          "data CRC error, bytes left %d\n",
 488                                         host->total_bytes_left);
 489                                 transfer_error = 1;
 490                         } else {
 491                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 492                         }
 493                 }
 494
 495                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 496                         /* Timeouts are routine with some commands */
 497                         if (host->cmd) {
 498                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 499                                                 host->cmd->opcode !=
 500                                                 MMC_SEND_OP_COND &&
 501                                                 host->cmd->opcode !=
 502                                                 MMC_APP_CMD &&
 503                                                 !mmc_omap_cover_is_open(host))
 504                                         dev_err(mmc_dev(host->mmc),
 505                                                 "command timeout, CMD %d\n",
 506                                                 host->cmd->opcode);
 507                                 host->cmd->error = -ETIMEDOUT;
 508                                 end_command = 1;
 509                         }
 510                 }
 511
 512                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 513                         if (host->cmd) {
 514                                 dev_err(mmc_dev(host->mmc),
 515                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 516                                         host->cmd->opcode, host->cmd->arg);
 517                                 host->cmd->error = -EILSEQ;
 518                                 end_command = 1;
 519                         } else
 520                                 dev_err(mmc_dev(host->mmc),
 521                                         "command CRC error without cmd?\n");
 522                 }
 523
 524                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 525                         dev_dbg(mmc_dev(host->mmc),
 526                                 "ignoring card status error (CMD%d)\n",
 527                                 host->cmd->opcode);
 528                         end_command = 1;
 529                 }
 530
 531                 /*
 532                  * NOTE: On 1610 the END_OF_CMD may come too early when
 533                  * starting a write
 534                  */
 535                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 536                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 537                         end_command = 1;
 538                 }
 539         }
 540
 541         if (end_command) {
 542                 mmc_omap_cmd_done(host, host->cmd);
 543         }
 544         if (transfer_error)
 545                 mmc_omap_xfer_done(host, host->data);
 546         else if (end_transfer)
 547                 mmc_omap_end_of_data(host, host->data);
 548
 549         return IRQ_HANDLED;
 550 }
 551
 552 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
 553 {
 554         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 555
 556         schedule_work(&host->switch_work);
 557
 558         return IRQ_HANDLED;
 559 }
 560
 561 static void mmc_omap_switch_timer(unsigned long arg)
 562 {
 563         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 564
 565         schedule_work(&host->switch_work);
 566 }
 567
 568 static void mmc_omap_switch_handler(struct work_struct *work)
 569 {
 570         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
 571         struct mmc_card *card;
 572         static int complained = 0;
 573         int cards = 0, cover_open;
 574
 575         if (host->switch_pin == -1)
 576                 return;
 577         cover_open = mmc_omap_cover_is_open(host);
 578         if (cover_open != host->switch_last_state) {
 579                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 580                 host->switch_last_state = cover_open;
 581         }
 582         mmc_detect_change(host->mmc, 0);
 583         list_for_each_entry(card, &host->mmc->cards, node) {
 584                 if (mmc_card_present(card))
 585                         cards++;
 586         }
 587         if (mmc_omap_cover_is_open(host)) {
 588                 if (!complained) {
 589                         dev_info(mmc_dev(host->mmc), "cover is open\n");
 590                         complained = 1;
 591                 }
 592                 if (mmc_omap_enable_poll)
 593                         mod_timer(&host->switch_timer, jiffies +
 594                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 595         } else {
 596                 complained = 0;
 597         }
 598 }
 599
 600 /* Prepare to transfer the next segment of a scatterlist */
 601 static void
 602 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 603 {
 604         int dma_ch = host->dma_ch;
 605         unsigned long data_addr;
 606         u16 buf, frame;
 607         u32 count;
 608         struct scatterlist *sg = &data->sg[host->sg_idx];
 609         int src_port = 0;
 610         int dst_port = 0;
 611         int sync_dev = 0;
 612
 613         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 614         frame = data->blksz;
 615         count = sg_dma_len(sg);
 616
 617         if ((data->blocks == 1) && (count > data->blksz))
 618                 count = frame;
 619
 620         host->dma_len = count;
 621
 622         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 623          * Use 16 or 32 word frames when the blocksize is at least that large.
 624          * Blocksize is usually 512 bytes; but not for some SD reads.
 625          */
 626         if (cpu_is_omap15xx() && frame > 32)
 627                 frame = 32;
 628         else if (frame > 64)
 629                 frame = 64;
 630         count /= frame;
 631         frame >>= 1;
 632
 633         if (!(data->flags & MMC_DATA_WRITE)) {
 634                 buf = 0x800f | ((frame - 1) << 8);
 635
 636                 if (cpu_class_is_omap1()) {
 637                         src_port = OMAP_DMA_PORT_TIPB;
 638                         dst_port = OMAP_DMA_PORT_EMIFF;
 639                 }
 640                 if (cpu_is_omap24xx())
 641                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 642
 643                 omap_set_dma_src_params(dma_ch, src_port,
 644                                         OMAP_DMA_AMODE_CONSTANT,
 645                                         data_addr, 0, 0);
 646                 omap_set_dma_dest_params(dma_ch, dst_port,
 647                                          OMAP_DMA_AMODE_POST_INC,
 648                                          sg_dma_address(sg), 0, 0);
 649                 omap_set_dma_dest_data_pack(dma_ch, 1);
 650                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 651         } else {
 652                 buf = 0x0f80 | ((frame - 1) << 0);
 653
 654                 if (cpu_class_is_omap1()) {
 655                         src_port = OMAP_DMA_PORT_EMIFF;
 656                         dst_port = OMAP_DMA_PORT_TIPB;
 657                 }
 658                 if (cpu_is_omap24xx())
 659                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 660
 661                 omap_set_dma_dest_params(dma_ch, dst_port,
 662                                          OMAP_DMA_AMODE_CONSTANT,
 663                                          data_addr, 0, 0);
 664                 omap_set_dma_src_params(dma_ch, src_port,
 665                                         OMAP_DMA_AMODE_POST_INC,
 666                                         sg_dma_address(sg), 0, 0);
 667                 omap_set_dma_src_data_pack(dma_ch, 1);
 668                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 669         }
 670
 671         /* Max limit for DMA frame count is 0xffff */
 672         BUG_ON(count > 0xffff);
 673
 674         OMAP_MMC_WRITE(host, BUF, buf);
 675         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 676                                      frame, count, OMAP_DMA_SYNC_FRAME,
 677                                      sync_dev, 0);
 678 }
 679
 680 /* A scatterlist segment completed */
 681 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 682 {
 683         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 684         struct mmc_data *mmcdat = host->data;
 685
 686         if (unlikely(host->dma_ch < 0)) {
 687                 dev_err(mmc_dev(host->mmc),
 688                         "DMA callback while DMA not enabled\n");
 689                 return;
 690         }
 691         /* FIXME: We really should do something to _handle_ the errors */
 692         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 693                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 694                 return;
 695         }
 696         if (ch_status & OMAP_DMA_DROP_IRQ) {
 697                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 698                 return;
 699         }
 700         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 701                 return;
 702         }
 703         mmcdat->bytes_xfered += host->dma_len;
 704         host->sg_idx++;
 705         if (host->sg_idx < host->sg_len) {
 706                 mmc_omap_prepare_dma(host, host->data);
 707                 omap_start_dma(host->dma_ch);
 708         } else
 709                 mmc_omap_dma_done(host, host->data);
 710 }
 711
 712 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 713 {
 714         const char *dev_name;
 715         int sync_dev, dma_ch, is_read, r;
 716
 717         is_read = !(data->flags & MMC_DATA_WRITE);
 718         del_timer_sync(&host->dma_timer);
 719         if (host->dma_ch >= 0) {
 720                 if (is_read == host->dma_is_read)
 721                         return 0;
 722                 omap_free_dma(host->dma_ch);
 723                 host->dma_ch = -1;
 724         }
 725
 726         if (is_read) {
 727                 if (host->id == 1) {
 728                         sync_dev = OMAP_DMA_MMC_RX;
 729                         dev_name = "MMC1 read";
 730                 } else {
 731                         sync_dev = OMAP_DMA_MMC2_RX;
 732                         dev_name = "MMC2 read";
 733                 }
 734         } else {
 735                 if (host->id == 1) {
 736                         sync_dev = OMAP_DMA_MMC_TX;
 737                         dev_name = "MMC1 write";
 738                 } else {
 739                         sync_dev = OMAP_DMA_MMC2_TX;
 740                         dev_name = "MMC2 write";
 741                 }
 742         }
 743         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 744                              host, &dma_ch);
 745         if (r != 0) {
 746                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 747                 return r;
 748         }
 749         host->dma_ch = dma_ch;
 750         host->dma_is_read = is_read;
 751
 752         return 0;
 753 }
 754
 755 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 756 {
 757         u16 reg;
 758
 759         reg = OMAP_MMC_READ(host, SDIO);
 760         reg &= ~(1 << 5);
 761         OMAP_MMC_WRITE(host, SDIO, reg);
 762         /* Set maximum timeout */
 763         OMAP_MMC_WRITE(host, CTO, 0xff);
 764 }
 765
 766 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 767 {
 768         int timeout;
 769         u16 reg;
 770
 771         /* Convert ns to clock cycles by assuming 20MHz frequency
 772          * 1 cycle at 20MHz = 500 ns
 773          */
 774         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 775
 776         /* Check if we need to use timeout multiplier register */
 777         reg = OMAP_MMC_READ(host, SDIO);
 778         if (timeout > 0xffff) {
 779                 reg |= (1 << 5);
 780                 timeout /= 1024;
 781         } else
 782                 reg &= ~(1 << 5);
 783         OMAP_MMC_WRITE(host, SDIO, reg);
 784         OMAP_MMC_WRITE(host, DTO, timeout);
 785 }
 786
 787 static void
 788 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 789 {
 790         struct mmc_data *data = req->data;
 791         int i, use_dma, block_size;
 792         unsigned sg_len;
 793
 794         host->data = data;
 795         if (data == NULL) {
 796                 OMAP_MMC_WRITE(host, BLEN, 0);
 797                 OMAP_MMC_WRITE(host, NBLK, 0);
 798                 OMAP_MMC_WRITE(host, BUF, 0);
 799                 host->dma_in_use = 0;
 800                 set_cmd_timeout(host, req);
 801                 return;
 802         }
 803
 804         block_size = data->blksz;
 805
 806         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 807         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 808         set_data_timeout(host, req);
 809
 810         /* cope with calling layer confusion; it issues "single
 811          * block" writes using multi-block scatterlists.
 812          */
 813         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 814
 815         /* Only do DMA for entire blocks */
 816         use_dma = host->use_dma;
 817         if (use_dma) {
 818                 for (i = 0; i < sg_len; i++) {
 819                         if ((data->sg[i].length % block_size) != 0) {
 820                                 use_dma = 0;
 821                                 break;
 822                         }
 823                 }
 824         }
 825
 826         host->sg_idx = 0;
 827         if (use_dma) {
 828                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 829                         enum dma_data_direction dma_data_dir;
 830
 831                         if (data->flags & MMC_DATA_WRITE)
 832                                 dma_data_dir = DMA_TO_DEVICE;
 833                         else
 834                                 dma_data_dir = DMA_FROM_DEVICE;
 835
 836                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 837                                                 sg_len, dma_data_dir);
 838                         host->total_bytes_left = 0;
 839                         mmc_omap_prepare_dma(host, req->data);
 840                         host->brs_received = 0;
 841                         host->dma_done = 0;
 842                         host->dma_in_use = 1;
 843                 } else
 844                         use_dma = 0;
 845         }
 846
 847         /* Revert to PIO? */
 848         if (!use_dma) {
 849                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 850                 host->total_bytes_left = data->blocks * block_size;
 851                 host->sg_len = sg_len;
 852                 mmc_omap_sg_to_buf(host);
 853                 host->dma_in_use = 0;
 854         }
 855 }
 856
 857 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 858 {
 859         struct mmc_omap_host *host = mmc_priv(mmc);
 860
 861         WARN_ON(host->mrq != NULL);
 862
 863         host->mrq = req;
 864
 865         /* only touch fifo AFTER the controller readies it */
 866         mmc_omap_prepare_data(host, req);
 867         mmc_omap_start_command(host, req->cmd);
 868         if (host->dma_in_use)
 869                 omap_start_dma(host->dma_ch);
 870 }
 871
 872 static void innovator_fpga_socket_power(int on)
 873 {
 874 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 875         if (on) {
 876                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 877                      OMAP1510_FPGA_POWER);
 878         } else {
 879                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 880                      OMAP1510_FPGA_POWER);
 881         }
 882 #endif
 883 }
 884
 885 /*
 886  * Turn the socket power on/off. Innovator uses FPGA, most boards
 887  * probably use GPIO.
 888  */
 889 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 890 {
 891         if (on) {
 892                 if (machine_is_omap_innovator())
 893                         innovator_fpga_socket_power(1);
 894                 else if (machine_is_omap_h2())
 895                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 896                 else if (machine_is_omap_h3())
 897                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 898                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 899                 else if (cpu_is_omap24xx()) {
 900                         u16 reg = OMAP_MMC_READ(host, CON);
 901                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 902                 } else
 903                         if (host->power_pin >= 0)
 904                                 omap_set_gpio_dataout(host->power_pin, 1);
 905         } else {
 906                 if (machine_is_omap_innovator())
 907                         innovator_fpga_socket_power(0);
 908                 else if (machine_is_omap_h2())
 909                         tps65010_set_gpio_out_value(GPIO3, LOW);
 910                 else if (machine_is_omap_h3())
 911                         tps65010_set_gpio_out_value(GPIO4, LOW);
 912                 else if (cpu_is_omap24xx()) {
 913                         u16 reg = OMAP_MMC_READ(host, CON);
 914                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 915                 } else
 916                         if (host->power_pin >= 0)
 917                                 omap_set_gpio_dataout(host->power_pin, 0);
 918         }
 919 }
 920
 921 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 922 {
 923         struct mmc_omap_host *host = mmc_priv(mmc);
 924         int func_clk_rate = clk_get_rate(host->fclk);
 925         int dsor;
 926
 927         if (ios->clock == 0)
 928                 return 0;
 929
 930         dsor = func_clk_rate / ios->clock;
 931         if (dsor < 1)
 932                 dsor = 1;
 933
 934         if (func_clk_rate / dsor > ios->clock)
 935                 dsor++;
 936
 937         if (dsor > 250)
 938                 dsor = 250;
 939         dsor++;
 940
 941         if (ios->bus_width == MMC_BUS_WIDTH_4)
 942                 dsor |= 1 << 15;
 943
 944         return dsor;
 945 }
 946
 947 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 948 {
 949         struct mmc_omap_host *host = mmc_priv(mmc);
 950         int dsor;
 951         int i;
 952
 953         dsor = mmc_omap_calc_divisor(mmc, ios);
 954         host->bus_mode = ios->bus_mode;
 955         host->hw_bus_mode = host->bus_mode;
 956
 957         switch (ios->power_mode) {
 958         case MMC_POWER_OFF:
 959                 mmc_omap_power(host, 0);
 960                 break;
 961         case MMC_POWER_UP:
 962                 /* Cannot touch dsor yet, just power up MMC */
 963                 mmc_omap_power(host, 1);
 964                 return;
 965         case MMC_POWER_ON:
 966                 dsor |= 1 << 11;
 967                 break;
 968         }
 969
 970         clk_enable(host->fclk);
 971
 972         /* On insanely high arm_per frequencies something sometimes
 973          * goes somehow out of sync, and the POW bit is not being set,
 974          * which results in the while loop below getting stuck.
 975          * Writing to the CON register twice seems to do the trick. */
 976         for (i = 0; i < 2; i++)
 977                 OMAP_MMC_WRITE(host, CON, dsor);
 978         if (ios->power_mode == MMC_POWER_ON) {
 979                 /* Send clock cycles, poll completion */
 980                 OMAP_MMC_WRITE(host, IE, 0);
 981                 OMAP_MMC_WRITE(host, STAT, 0xffff);
 982                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
 983                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
 984                 OMAP_MMC_WRITE(host, STAT, 1);
 985         }
 986         clk_disable(host->fclk);
 987 }
 988
 989 static int mmc_omap_get_ro(struct mmc_host *mmc)
 990 {
 991         struct mmc_omap_host *host = mmc_priv(mmc);
 992
 993         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
 994 }
 995
 996 static const struct mmc_host_ops mmc_omap_ops = {
 997         .request        = mmc_omap_request,
 998         .set_ios        = mmc_omap_set_ios,
 999         .get_ro         = mmc_omap_get_ro,
1000 };
1001
1002 static int __init mmc_omap_probe(struct platform_device *pdev)
1003 {
1004         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1005         struct mmc_host *mmc;
1006         struct mmc_omap_host *host = NULL;
1007         struct resource *res;
1008         int ret = 0;
1009         int irq;
1010
1011         if (minfo == NULL) {
1012                 dev_err(&pdev->dev, "platform data missing\n");
1013                 return -ENXIO;
1014         }
1015
1016         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017         irq = platform_get_irq(pdev, 0);
1018         if (res == NULL || irq < 0)
1019                 return -ENXIO;
1020
1021         res = request_mem_region(res->start, res->end - res->start + 1,
1022                                  pdev->name);
1023         if (res == NULL)
1024                 return -EBUSY;
1025
1026         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1027         if (mmc == NULL) {
1028                 ret = -ENOMEM;
1029                 goto err_free_mem_region;
1030         }
1031
1032         host = mmc_priv(mmc);
1033         host->mmc = mmc;
1034
1035         spin_lock_init(&host->dma_lock);
1036         init_timer(&host->dma_timer);
1037         host->dma_timer.function = mmc_omap_dma_timer;
1038         host->dma_timer.data = (unsigned long) host;
1039
1040         host->id = pdev->id;
1041         host->mem_res = res;
1042         host->irq = irq;
1043
1044         if (cpu_is_omap24xx()) {
1045                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1046                 if (IS_ERR(host->iclk))
1047                         goto err_free_mmc_host;
1048                 clk_enable(host->iclk);
1049         }
1050
1051         if (!cpu_is_omap24xx())
1052                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1053         else
1054                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1055
1056         if (IS_ERR(host->fclk)) {
1057                 ret = PTR_ERR(host->fclk);
1058                 goto err_free_iclk;
1059         }
1060
1061         /* REVISIT:
1062          * Also, use minfo->cover to decide how to manage
1063          * the card detect sensing.
1064          */
1065         host->power_pin = minfo->power_pin;
1066         host->switch_pin = minfo->switch_pin;
1067         host->wp_pin = minfo->wp_pin;
1068         host->use_dma = 1;
1069         host->dma_ch = -1;
1070
1071         host->irq = irq;
1072         host->phys_base = host->mem_res->start;
1073         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1074
1075         mmc->ops = &mmc_omap_ops;
1076         mmc->f_min = 400000;
1077         mmc->f_max = 24000000;
1078         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1079         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1080
1081         if (minfo->wire4)
1082                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1083
1084         /* Use scatterlist DMA to reduce per-transfer costs.
1085          * NOTE max_seg_size assumption that small blocks aren't
1086          * normally used (except e.g. for reading SD registers).
1087          */
1088         mmc->max_phys_segs = 32;
1089         mmc->max_hw_segs = 32;
1090         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1091         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1092         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1093         mmc->max_seg_size = mmc->max_req_size;
1094
1095         if (host->power_pin >= 0) {
1096                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1097                         dev_err(mmc_dev(host->mmc),
1098                                 "Unable to get GPIO pin for MMC power\n");
1099                         goto err_free_fclk;
1100                 }
1101                 omap_set_gpio_direction(host->power_pin, 0);
1102         }
1103
1104         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1105         if (ret)
1106                 goto err_free_power_gpio;
1107
1108         host->dev = &pdev->dev;
1109         platform_set_drvdata(pdev, host);
1110
1111         if (host->switch_pin >= 0) {
1112                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1113                 init_timer(&host->switch_timer);
1114                 host->switch_timer.function = mmc_omap_switch_timer;
1115                 host->switch_timer.data = (unsigned long) host;
1116                 if (omap_request_gpio(host->switch_pin) != 0) {
1117                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1118                         host->switch_pin = -1;
1119                         goto no_switch;
1120                 }
1121
1122                 omap_set_gpio_direction(host->switch_pin, 1);
1123                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1124                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1125                 if (ret) {
1126                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1127                         omap_free_gpio(host->switch_pin);
1128                         host->switch_pin = -1;
1129                         goto no_switch;
1130                 }
1131                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1132                 if (ret == 0) {
1133                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1134                         if (ret != 0)
1135                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1136                 }
1137                 if (ret) {
1138                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1139                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1140                         omap_free_gpio(host->switch_pin);
1141                         host->switch_pin = -1;
1142                         goto no_switch;
1143                 }
1144                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1145                         schedule_work(&host->switch_work);
1146         }
1147
1148         mmc_add_host(mmc);
1149
1150         return 0;
1151
1152 no_switch:
1153         /* FIXME: Free other resources too. */
1154         if (host) {
1155                 if (host->iclk && !IS_ERR(host->iclk))
1156                         clk_put(host->iclk);
1157                 if (host->fclk && !IS_ERR(host->fclk))
1158                         clk_put(host->fclk);
1159                 mmc_free_host(host->mmc);
1160         }
1161 err_free_power_gpio:
1162         if (host->power_pin >= 0)
1163                 omap_free_gpio(host->power_pin);
1164 err_free_fclk:
1165         clk_put(host->fclk);
1166 err_free_iclk:
1167         if (host->iclk != NULL) {
1168                 clk_disable(host->iclk);
1169                 clk_put(host->iclk);
1170         }
1171 err_free_mmc_host:
1172         mmc_free_host(host->mmc);
1173 err_free_mem_region:
1174         release_mem_region(res->start, res->end - res->start + 1);
1175         return ret;
1176 }
1177
1178 static int mmc_omap_remove(struct platform_device *pdev)
1179 {
1180         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1181
1182         platform_set_drvdata(pdev, NULL);
1183
1184         BUG_ON(host == NULL);
1185
1186         mmc_remove_host(host->mmc);
1187         free_irq(host->irq, host);
1188
1189         if (host->power_pin >= 0)
1190                 omap_free_gpio(host->power_pin);
1191         if (host->switch_pin >= 0) {
1192                 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1193                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1194                 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1195                 omap_free_gpio(host->switch_pin);
1196                 host->switch_pin = -1;
1197                 del_timer_sync(&host->switch_timer);
1198                 flush_scheduled_work();
1199         }
1200         if (host->iclk && !IS_ERR(host->iclk))
1201                 clk_put(host->iclk);
1202         if (host->fclk && !IS_ERR(host->fclk))
1203                 clk_put(host->fclk);
1204
1205         release_mem_region(pdev->resource[0].start,
1206                            pdev->resource[0].end - pdev->resource[0].start + 1);
1207
1208         mmc_free_host(host->mmc);
1209
1210         return 0;
1211 }
1212
1213 #ifdef CONFIG_PM
1214 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1215 {
1216         int ret = 0;
1217         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1218
1219         if (host && host->suspended)
1220                 return 0;
1221
1222         if (host) {
1223                 ret = mmc_suspend_host(host->mmc, mesg);
1224                 if (ret == 0)
1225                         host->suspended = 1;
1226         }
1227         return ret;
1228 }
1229
1230 static int mmc_omap_resume(struct platform_device *pdev)
1231 {
1232         int ret = 0;
1233         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1234
1235         if (host && !host->suspended)
1236                 return 0;
1237
1238         if (host) {
1239                 ret = mmc_resume_host(host->mmc);
1240                 if (ret == 0)
1241                         host->suspended = 0;
1242         }
1243
1244         return ret;
1245 }
1246 #else
1247 #define mmc_omap_suspend        NULL
1248 #define mmc_omap_resume         NULL
1249 #endif
1250
1251 static struct platform_driver mmc_omap_driver = {
1252         .probe          = mmc_omap_probe,
1253         .remove         = mmc_omap_remove,
1254         .suspend        = mmc_omap_suspend,
1255         .resume         = mmc_omap_resume,
1256         .driver         = {
1257                 .name   = DRIVER_NAME,
1258                 .owner  = THIS_MODULE,
1259         },
1260 };
1261
1262 static int __init mmc_omap_init(void)
1263 {
1264         return platform_driver_register(&mmc_omap_driver);
1265 }
1266
1267 static void __exit mmc_omap_exit(void)
1268 {
1269         platform_driver_unregister(&mmc_omap_driver);
1270 }
1271
1272 module_init(mmc_omap_init);
1273 module_exit(mmc_omap_exit);
1274
1275 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1276 MODULE_LICENSE("GPL");
1277 MODULE_ALIAS("platform:" DRIVER_NAME);
1278 MODULE_AUTHOR("Juha Yrjölä");