2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
32 #include <asm/mach-types.h>
34 #include <asm/arch/board.h>
35 #include <asm/arch/gpio.h>
36 #include <asm/arch/dma.h>
37 #include <asm/arch/mux.h>
38 #include <asm/arch/fpga.h>
39 #include <asm/arch/tps65010.h>
40 #include <asm/arch/board-sx1.h>
42 #define OMAP_MMC_REG_CMD 0x00
43 #define OMAP_MMC_REG_ARGL 0x04
44 #define OMAP_MMC_REG_ARGH 0x08
45 #define OMAP_MMC_REG_CON 0x0c
46 #define OMAP_MMC_REG_STAT 0x10
47 #define OMAP_MMC_REG_IE 0x14
48 #define OMAP_MMC_REG_CTO 0x18
49 #define OMAP_MMC_REG_DTO 0x1c
50 #define OMAP_MMC_REG_DATA 0x20
51 #define OMAP_MMC_REG_BLEN 0x24
52 #define OMAP_MMC_REG_NBLK 0x28
53 #define OMAP_MMC_REG_BUF 0x2c
54 #define OMAP_MMC_REG_SDIO 0x34
55 #define OMAP_MMC_REG_REV 0x3c
56 #define OMAP_MMC_REG_RSP0 0x40
57 #define OMAP_MMC_REG_RSP1 0x44
58 #define OMAP_MMC_REG_RSP2 0x48
59 #define OMAP_MMC_REG_RSP3 0x4c
60 #define OMAP_MMC_REG_RSP4 0x50
61 #define OMAP_MMC_REG_RSP5 0x54
62 #define OMAP_MMC_REG_RSP6 0x58
63 #define OMAP_MMC_REG_RSP7 0x5c
64 #define OMAP_MMC_REG_IOSR 0x60
65 #define OMAP_MMC_REG_SYSC 0x64
66 #define OMAP_MMC_REG_SYSS 0x68
68 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
69 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
70 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
71 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
72 #define OMAP_MMC_STAT_A_FULL (1 << 10)
73 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
74 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
75 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
76 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
77 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
78 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
79 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
80 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
82 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
83 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
88 #define OMAP_MMC_CMDTYPE_BC 0
89 #define OMAP_MMC_CMDTYPE_BCR 1
90 #define OMAP_MMC_CMDTYPE_AC 2
91 #define OMAP_MMC_CMDTYPE_ADTC 3
94 #define DRIVER_NAME "mmci-omap"
96 /* Specifies how often in millisecs to poll for card status changes
97 * when the cover switch is open */
98 #define OMAP_MMC_SWITCH_POLL_DELAY 500
100 static int mmc_omap_enable_poll = 1;
102 struct mmc_omap_host {
105 struct mmc_request * mrq;
106 struct mmc_command * cmd;
107 struct mmc_data * data;
108 struct mmc_host * mmc;
110 unsigned char id; /* 16xx chips have 2 MMC blocks */
113 struct resource *mem_res;
114 void __iomem *virt_base;
115 unsigned int phys_base;
117 unsigned char bus_mode;
118 unsigned char hw_bus_mode;
123 u32 buffer_bytes_left;
124 u32 total_bytes_left;
127 unsigned brs_received:1, dma_done:1;
128 unsigned dma_is_read:1;
129 unsigned dma_in_use:1;
132 struct timer_list dma_timer;
139 struct work_struct switch_work;
140 struct timer_list switch_timer;
141 int switch_last_state;
145 mmc_omap_cover_is_open(struct mmc_omap_host *host)
147 if (host->switch_pin < 0)
149 return omap_get_gpio_datain(host->switch_pin);
153 mmc_omap_show_cover_switch(struct device *dev,
154 struct device_attribute *attr, char *buf)
156 struct mmc_omap_host *host = dev_get_drvdata(dev);
158 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
162 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
165 mmc_omap_show_enable_poll(struct device *dev,
166 struct device_attribute *attr, char *buf)
168 return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
172 mmc_omap_store_enable_poll(struct device *dev,
173 struct device_attribute *attr, const char *buf,
178 if (sscanf(buf, "%10d", &enable_poll) != 1)
181 if (enable_poll != mmc_omap_enable_poll) {
182 struct mmc_omap_host *host = dev_get_drvdata(dev);
184 mmc_omap_enable_poll = enable_poll;
185 if (enable_poll && host->switch_pin >= 0)
186 schedule_work(&host->switch_work);
191 static DEVICE_ATTR(enable_poll, 0664,
192 mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
195 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
206 /* Our hardware needs to know exact type */
207 switch (mmc_resp_type(cmd)) {
212 /* resp 1, 1b, 6, 7 */
222 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
226 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
227 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
228 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
229 cmdtype = OMAP_MMC_CMDTYPE_BC;
230 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
231 cmdtype = OMAP_MMC_CMDTYPE_BCR;
233 cmdtype = OMAP_MMC_CMDTYPE_AC;
236 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
238 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
241 if (cmd->flags & MMC_RSP_BUSY)
244 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
247 clk_enable(host->fclk);
249 OMAP_MMC_WRITE(host, CTO, 200);
250 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
251 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
252 OMAP_MMC_WRITE(host, IE,
253 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
254 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
255 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
256 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
257 OMAP_MMC_STAT_END_OF_DATA);
258 OMAP_MMC_WRITE(host, CMD, cmdreg);
262 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
264 if (host->dma_in_use) {
265 enum dma_data_direction dma_data_dir;
267 BUG_ON(host->dma_ch < 0);
269 omap_stop_dma(host->dma_ch);
270 /* Release DMA channel lazily */
271 mod_timer(&host->dma_timer, jiffies + HZ);
272 if (data->flags & MMC_DATA_WRITE)
273 dma_data_dir = DMA_TO_DEVICE;
275 dma_data_dir = DMA_FROM_DEVICE;
276 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
281 clk_disable(host->fclk);
283 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
284 * dozens of requests until the card finishes writing data.
285 * It'd be cheaper to just wait till an EOFB interrupt arrives...
290 mmc_request_done(host->mmc, data->mrq);
294 mmc_omap_start_command(host, data->stop);
298 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
303 if (!host->dma_in_use) {
304 mmc_omap_xfer_done(host, data);
308 spin_lock_irqsave(&host->dma_lock, flags);
312 host->brs_received = 1;
313 spin_unlock_irqrestore(&host->dma_lock, flags);
315 mmc_omap_xfer_done(host, data);
319 mmc_omap_dma_timer(unsigned long data)
321 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
323 BUG_ON(host->dma_ch < 0);
324 omap_free_dma(host->dma_ch);
329 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
335 spin_lock_irqsave(&host->dma_lock, flags);
336 if (host->brs_received)
340 spin_unlock_irqrestore(&host->dma_lock, flags);
342 mmc_omap_xfer_done(host, data);
346 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
350 if (cmd->flags & MMC_RSP_PRESENT) {
351 if (cmd->flags & MMC_RSP_136) {
352 /* response type 2 */
354 OMAP_MMC_READ(host, RSP0) |
355 (OMAP_MMC_READ(host, RSP1) << 16);
357 OMAP_MMC_READ(host, RSP2) |
358 (OMAP_MMC_READ(host, RSP3) << 16);
360 OMAP_MMC_READ(host, RSP4) |
361 (OMAP_MMC_READ(host, RSP5) << 16);
363 OMAP_MMC_READ(host, RSP6) |
364 (OMAP_MMC_READ(host, RSP7) << 16);
366 /* response types 1, 1b, 3, 4, 5, 6 */
368 OMAP_MMC_READ(host, RSP6) |
369 (OMAP_MMC_READ(host, RSP7) << 16);
373 if (host->data == NULL || cmd->error) {
375 clk_disable(host->fclk);
376 mmc_request_done(host->mmc, cmd->mrq);
382 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
384 struct scatterlist *sg;
386 sg = host->data->sg + host->sg_idx;
387 host->buffer_bytes_left = sg->length;
388 host->buffer = sg_virt(sg);
389 if (host->buffer_bytes_left > host->total_bytes_left)
390 host->buffer_bytes_left = host->total_bytes_left;
395 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
399 if (host->buffer_bytes_left == 0) {
401 BUG_ON(host->sg_idx == host->sg_len);
402 mmc_omap_sg_to_buf(host);
405 if (n > host->buffer_bytes_left)
406 n = host->buffer_bytes_left;
407 host->buffer_bytes_left -= n;
408 host->total_bytes_left -= n;
409 host->data->bytes_xfered += n;
412 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
414 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
418 static inline void mmc_omap_report_irq(u16 status)
420 static const char *mmc_omap_status_bits[] = {
421 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
422 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
426 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
427 if (status & (1 << i)) {
430 printk("%s", mmc_omap_status_bits[i]);
435 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
437 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
443 if (host->cmd == NULL && host->data == NULL) {
444 status = OMAP_MMC_READ(host, STAT);
445 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
447 OMAP_MMC_WRITE(host, STAT, status);
448 OMAP_MMC_WRITE(host, IE, 0);
457 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
458 OMAP_MMC_WRITE(host, STAT, status);
459 #ifdef CONFIG_MMC_DEBUG
460 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
461 status, host->cmd != NULL ? host->cmd->opcode : -1);
462 mmc_omap_report_irq(status);
465 if (host->total_bytes_left) {
466 if ((status & OMAP_MMC_STAT_A_FULL) ||
467 (status & OMAP_MMC_STAT_END_OF_DATA))
468 mmc_omap_xfer_data(host, 0);
469 if (status & OMAP_MMC_STAT_A_EMPTY)
470 mmc_omap_xfer_data(host, 1);
473 if (status & OMAP_MMC_STAT_END_OF_DATA) {
477 if (status & OMAP_MMC_STAT_DATA_TOUT) {
478 dev_dbg(mmc_dev(host->mmc), "data timeout\n");
480 host->data->error = -ETIMEDOUT;
485 if (status & OMAP_MMC_STAT_DATA_CRC) {
487 host->data->error = -EILSEQ;
488 dev_dbg(mmc_dev(host->mmc),
489 "data CRC error, bytes left %d\n",
490 host->total_bytes_left);
493 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
497 if (status & OMAP_MMC_STAT_CMD_TOUT) {
498 /* Timeouts are routine with some commands */
500 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
505 !mmc_omap_cover_is_open(host))
506 dev_err(mmc_dev(host->mmc),
507 "command timeout, CMD %d\n",
509 host->cmd->error = -ETIMEDOUT;
514 if (status & OMAP_MMC_STAT_CMD_CRC) {
516 dev_err(mmc_dev(host->mmc),
517 "command CRC error (CMD%d, arg 0x%08x)\n",
518 host->cmd->opcode, host->cmd->arg);
519 host->cmd->error = -EILSEQ;
522 dev_err(mmc_dev(host->mmc),
523 "command CRC error without cmd?\n");
526 if (status & OMAP_MMC_STAT_CARD_ERR) {
527 dev_dbg(mmc_dev(host->mmc),
528 "ignoring card status error (CMD%d)\n",
534 * NOTE: On 1610 the END_OF_CMD may come too early when
537 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
538 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
544 mmc_omap_cmd_done(host, host->cmd);
547 mmc_omap_xfer_done(host, host->data);
548 else if (end_transfer)
549 mmc_omap_end_of_data(host, host->data);
554 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
556 struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
558 schedule_work(&host->switch_work);
563 static void mmc_omap_switch_timer(unsigned long arg)
565 struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
567 schedule_work(&host->switch_work);
570 static void mmc_omap_switch_handler(struct work_struct *work)
572 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
573 static int complained = 0;
576 if (host->switch_pin == -1)
578 cover_open = mmc_omap_cover_is_open(host);
579 if (cover_open != host->switch_last_state) {
580 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
581 host->switch_last_state = cover_open;
583 mmc_detect_change(host->mmc, 0);
584 if (mmc_omap_cover_is_open(host)) {
586 dev_info(mmc_dev(host->mmc), "cover is open\n");
589 if (mmc_omap_enable_poll)
590 mod_timer(&host->switch_timer, jiffies +
591 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
597 /* Prepare to transfer the next segment of a scatterlist */
599 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
601 int dma_ch = host->dma_ch;
602 unsigned long data_addr;
605 struct scatterlist *sg = &data->sg[host->sg_idx];
610 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
612 count = sg_dma_len(sg);
614 if ((data->blocks == 1) && (count > data->blksz))
617 host->dma_len = count;
619 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
620 * Use 16 or 32 word frames when the blocksize is at least that large.
621 * Blocksize is usually 512 bytes; but not for some SD reads.
623 if (cpu_is_omap15xx() && frame > 32)
630 if (!(data->flags & MMC_DATA_WRITE)) {
631 buf = 0x800f | ((frame - 1) << 8);
633 if (cpu_class_is_omap1()) {
634 src_port = OMAP_DMA_PORT_TIPB;
635 dst_port = OMAP_DMA_PORT_EMIFF;
637 if (cpu_is_omap24xx())
638 sync_dev = OMAP24XX_DMA_MMC1_RX;
640 omap_set_dma_src_params(dma_ch, src_port,
641 OMAP_DMA_AMODE_CONSTANT,
643 omap_set_dma_dest_params(dma_ch, dst_port,
644 OMAP_DMA_AMODE_POST_INC,
645 sg_dma_address(sg), 0, 0);
646 omap_set_dma_dest_data_pack(dma_ch, 1);
647 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
649 buf = 0x0f80 | ((frame - 1) << 0);
651 if (cpu_class_is_omap1()) {
652 src_port = OMAP_DMA_PORT_EMIFF;
653 dst_port = OMAP_DMA_PORT_TIPB;
655 if (cpu_is_omap24xx())
656 sync_dev = OMAP24XX_DMA_MMC1_TX;
658 omap_set_dma_dest_params(dma_ch, dst_port,
659 OMAP_DMA_AMODE_CONSTANT,
661 omap_set_dma_src_params(dma_ch, src_port,
662 OMAP_DMA_AMODE_POST_INC,
663 sg_dma_address(sg), 0, 0);
664 omap_set_dma_src_data_pack(dma_ch, 1);
665 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
668 /* Max limit for DMA frame count is 0xffff */
669 BUG_ON(count > 0xffff);
671 OMAP_MMC_WRITE(host, BUF, buf);
672 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
673 frame, count, OMAP_DMA_SYNC_FRAME,
677 /* A scatterlist segment completed */
678 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
680 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
681 struct mmc_data *mmcdat = host->data;
683 if (unlikely(host->dma_ch < 0)) {
684 dev_err(mmc_dev(host->mmc),
685 "DMA callback while DMA not enabled\n");
688 /* FIXME: We really should do something to _handle_ the errors */
689 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
690 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
693 if (ch_status & OMAP_DMA_DROP_IRQ) {
694 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
697 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
700 mmcdat->bytes_xfered += host->dma_len;
702 if (host->sg_idx < host->sg_len) {
703 mmc_omap_prepare_dma(host, host->data);
704 omap_start_dma(host->dma_ch);
706 mmc_omap_dma_done(host, host->data);
709 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
711 const char *dev_name;
712 int sync_dev, dma_ch, is_read, r;
714 is_read = !(data->flags & MMC_DATA_WRITE);
715 del_timer_sync(&host->dma_timer);
716 if (host->dma_ch >= 0) {
717 if (is_read == host->dma_is_read)
719 omap_free_dma(host->dma_ch);
725 sync_dev = OMAP_DMA_MMC_RX;
726 dev_name = "MMC1 read";
728 sync_dev = OMAP_DMA_MMC2_RX;
729 dev_name = "MMC2 read";
733 sync_dev = OMAP_DMA_MMC_TX;
734 dev_name = "MMC1 write";
736 sync_dev = OMAP_DMA_MMC2_TX;
737 dev_name = "MMC2 write";
740 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
743 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
746 host->dma_ch = dma_ch;
747 host->dma_is_read = is_read;
752 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
756 reg = OMAP_MMC_READ(host, SDIO);
758 OMAP_MMC_WRITE(host, SDIO, reg);
759 /* Set maximum timeout */
760 OMAP_MMC_WRITE(host, CTO, 0xff);
763 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
768 /* Convert ns to clock cycles by assuming 20MHz frequency
769 * 1 cycle at 20MHz = 500 ns
771 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
773 /* Check if we need to use timeout multiplier register */
774 reg = OMAP_MMC_READ(host, SDIO);
775 if (timeout > 0xffff) {
780 OMAP_MMC_WRITE(host, SDIO, reg);
781 OMAP_MMC_WRITE(host, DTO, timeout);
785 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
787 struct mmc_data *data = req->data;
788 int i, use_dma, block_size;
793 OMAP_MMC_WRITE(host, BLEN, 0);
794 OMAP_MMC_WRITE(host, NBLK, 0);
795 OMAP_MMC_WRITE(host, BUF, 0);
796 host->dma_in_use = 0;
797 set_cmd_timeout(host, req);
801 block_size = data->blksz;
803 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
804 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
805 set_data_timeout(host, req);
807 /* cope with calling layer confusion; it issues "single
808 * block" writes using multi-block scatterlists.
810 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
812 /* Only do DMA for entire blocks */
813 use_dma = host->use_dma;
815 for (i = 0; i < sg_len; i++) {
816 if ((data->sg[i].length % block_size) != 0) {
825 if (mmc_omap_get_dma_channel(host, data) == 0) {
826 enum dma_data_direction dma_data_dir;
828 if (data->flags & MMC_DATA_WRITE)
829 dma_data_dir = DMA_TO_DEVICE;
831 dma_data_dir = DMA_FROM_DEVICE;
833 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
834 sg_len, dma_data_dir);
835 host->total_bytes_left = 0;
836 mmc_omap_prepare_dma(host, req->data);
837 host->brs_received = 0;
839 host->dma_in_use = 1;
846 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
847 host->total_bytes_left = data->blocks * block_size;
848 host->sg_len = sg_len;
849 mmc_omap_sg_to_buf(host);
850 host->dma_in_use = 0;
854 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
856 struct mmc_omap_host *host = mmc_priv(mmc);
858 WARN_ON(host->mrq != NULL);
862 /* only touch fifo AFTER the controller readies it */
863 mmc_omap_prepare_data(host, req);
864 mmc_omap_start_command(host, req->cmd);
865 if (host->dma_in_use)
866 omap_start_dma(host->dma_ch);
869 static void innovator_fpga_socket_power(int on)
871 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
873 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
874 OMAP1510_FPGA_POWER);
876 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
877 OMAP1510_FPGA_POWER);
883 * Turn the socket power on/off. Innovator uses FPGA, most boards
886 static void mmc_omap_power(struct mmc_omap_host *host, int on)
888 if (machine_is_sx1())
891 if (machine_is_omap_innovator())
892 innovator_fpga_socket_power(1);
893 else if (machine_is_omap_h2())
894 tps65010_set_gpio_out_value(GPIO3, HIGH);
895 else if (machine_is_omap_h3())
896 /* GPIO 4 of TPS65010 sends SD_EN signal */
897 tps65010_set_gpio_out_value(GPIO4, HIGH);
898 else if (cpu_is_omap24xx()) {
899 u16 reg = OMAP_MMC_READ(host, CON);
900 OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
902 if (host->power_pin >= 0)
903 omap_set_gpio_dataout(host->power_pin, 1);
905 if (machine_is_omap_innovator())
906 innovator_fpga_socket_power(0);
907 else if (machine_is_omap_h2())
908 tps65010_set_gpio_out_value(GPIO3, LOW);
909 else if (machine_is_omap_h3())
910 tps65010_set_gpio_out_value(GPIO4, LOW);
911 else if (cpu_is_omap24xx()) {
912 u16 reg = OMAP_MMC_READ(host, CON);
913 OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
915 if (host->power_pin >= 0)
916 omap_set_gpio_dataout(host->power_pin, 0);
920 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
922 struct mmc_omap_host *host = mmc_priv(mmc);
923 int func_clk_rate = clk_get_rate(host->fclk);
929 dsor = func_clk_rate / ios->clock;
933 if (func_clk_rate / dsor > ios->clock)
939 if (ios->bus_width == MMC_BUS_WIDTH_4)
945 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
947 struct mmc_omap_host *host = mmc_priv(mmc);
951 dsor = mmc_omap_calc_divisor(mmc, ios);
952 host->bus_mode = ios->bus_mode;
953 host->hw_bus_mode = host->bus_mode;
955 switch (ios->power_mode) {
957 mmc_omap_power(host, 0);
960 /* Cannot touch dsor yet, just power up MMC */
961 mmc_omap_power(host, 1);
968 clk_enable(host->fclk);
970 /* On insanely high arm_per frequencies something sometimes
971 * goes somehow out of sync, and the POW bit is not being set,
972 * which results in the while loop below getting stuck.
973 * Writing to the CON register twice seems to do the trick. */
974 for (i = 0; i < 2; i++)
975 OMAP_MMC_WRITE(host, CON, dsor);
976 if (ios->power_mode == MMC_POWER_ON) {
977 /* Send clock cycles, poll completion */
978 OMAP_MMC_WRITE(host, IE, 0);
979 OMAP_MMC_WRITE(host, STAT, 0xffff);
980 OMAP_MMC_WRITE(host, CMD, 1 << 7);
981 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
982 OMAP_MMC_WRITE(host, STAT, 1);
984 clk_disable(host->fclk);
987 static int mmc_omap_get_ro(struct mmc_host *mmc)
989 struct mmc_omap_host *host = mmc_priv(mmc);
991 return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
994 static const struct mmc_host_ops mmc_omap_ops = {
995 .request = mmc_omap_request,
996 .set_ios = mmc_omap_set_ios,
997 .get_ro = mmc_omap_get_ro,
1000 static int __init mmc_omap_probe(struct platform_device *pdev)
1002 struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1003 struct mmc_host *mmc;
1004 struct mmc_omap_host *host = NULL;
1005 struct resource *res;
1009 if (minfo == NULL) {
1010 dev_err(&pdev->dev, "platform data missing\n");
1014 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1015 irq = platform_get_irq(pdev, 0);
1016 if (res == NULL || irq < 0)
1019 res = request_mem_region(res->start, res->end - res->start + 1,
1024 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1027 goto err_free_mem_region;
1030 host = mmc_priv(mmc);
1033 spin_lock_init(&host->dma_lock);
1034 init_timer(&host->dma_timer);
1035 host->dma_timer.function = mmc_omap_dma_timer;
1036 host->dma_timer.data = (unsigned long) host;
1038 host->id = pdev->id;
1039 host->mem_res = res;
1042 if (cpu_is_omap24xx()) {
1043 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1044 if (IS_ERR(host->iclk))
1045 goto err_free_mmc_host;
1046 clk_enable(host->iclk);
1049 if (!cpu_is_omap24xx())
1050 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1052 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1054 if (IS_ERR(host->fclk)) {
1055 ret = PTR_ERR(host->fclk);
1060 * Also, use minfo->cover to decide how to manage
1061 * the card detect sensing.
1063 host->power_pin = minfo->power_pin;
1064 host->switch_pin = minfo->switch_pin;
1065 host->wp_pin = minfo->wp_pin;
1070 host->phys_base = host->mem_res->start;
1071 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1073 mmc->ops = &mmc_omap_ops;
1074 mmc->f_min = 400000;
1075 mmc->f_max = 24000000;
1076 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1077 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1080 mmc->caps |= MMC_CAP_4_BIT_DATA;
1082 /* Use scatterlist DMA to reduce per-transfer costs.
1083 * NOTE max_seg_size assumption that small blocks aren't
1084 * normally used (except e.g. for reading SD registers).
1086 mmc->max_phys_segs = 32;
1087 mmc->max_hw_segs = 32;
1088 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1089 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1090 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1091 mmc->max_seg_size = mmc->max_req_size;
1093 if (host->power_pin >= 0) {
1094 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1095 dev_err(mmc_dev(host->mmc),
1096 "Unable to get GPIO pin for MMC power\n");
1099 omap_set_gpio_direction(host->power_pin, 0);
1102 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1104 goto err_free_power_gpio;
1106 host->dev = &pdev->dev;
1107 platform_set_drvdata(pdev, host);
1109 if (host->switch_pin >= 0) {
1110 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1111 init_timer(&host->switch_timer);
1112 host->switch_timer.function = mmc_omap_switch_timer;
1113 host->switch_timer.data = (unsigned long) host;
1114 if (omap_request_gpio(host->switch_pin) != 0) {
1115 dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1116 host->switch_pin = -1;
1120 omap_set_gpio_direction(host->switch_pin, 1);
1121 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1122 mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1124 dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1125 omap_free_gpio(host->switch_pin);
1126 host->switch_pin = -1;
1129 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1131 ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1133 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1136 dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1137 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1138 omap_free_gpio(host->switch_pin);
1139 host->switch_pin = -1;
1142 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1143 schedule_work(&host->switch_work);
1151 /* FIXME: Free other resources too. */
1153 if (host->iclk && !IS_ERR(host->iclk))
1154 clk_put(host->iclk);
1155 if (host->fclk && !IS_ERR(host->fclk))
1156 clk_put(host->fclk);
1157 mmc_free_host(host->mmc);
1159 err_free_power_gpio:
1160 if (host->power_pin >= 0)
1161 omap_free_gpio(host->power_pin);
1163 clk_put(host->fclk);
1165 if (host->iclk != NULL) {
1166 clk_disable(host->iclk);
1167 clk_put(host->iclk);
1170 mmc_free_host(host->mmc);
1171 err_free_mem_region:
1172 release_mem_region(res->start, res->end - res->start + 1);
1176 static int mmc_omap_remove(struct platform_device *pdev)
1178 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1180 platform_set_drvdata(pdev, NULL);
1182 BUG_ON(host == NULL);
1184 mmc_remove_host(host->mmc);
1185 free_irq(host->irq, host);
1187 if (host->power_pin >= 0)
1188 omap_free_gpio(host->power_pin);
1189 if (host->switch_pin >= 0) {
1190 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1191 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1192 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1193 omap_free_gpio(host->switch_pin);
1194 host->switch_pin = -1;
1195 del_timer_sync(&host->switch_timer);
1196 flush_scheduled_work();
1198 if (host->iclk && !IS_ERR(host->iclk))
1199 clk_put(host->iclk);
1200 if (host->fclk && !IS_ERR(host->fclk))
1201 clk_put(host->fclk);
1203 release_mem_region(pdev->resource[0].start,
1204 pdev->resource[0].end - pdev->resource[0].start + 1);
1206 mmc_free_host(host->mmc);
1212 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1215 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1217 if (host && host->suspended)
1221 ret = mmc_suspend_host(host->mmc, mesg);
1223 host->suspended = 1;
1228 static int mmc_omap_resume(struct platform_device *pdev)
1231 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1233 if (host && !host->suspended)
1237 ret = mmc_resume_host(host->mmc);
1239 host->suspended = 0;
1245 #define mmc_omap_suspend NULL
1246 #define mmc_omap_resume NULL
1249 static struct platform_driver mmc_omap_driver = {
1250 .probe = mmc_omap_probe,
1251 .remove = mmc_omap_remove,
1252 .suspend = mmc_omap_suspend,
1253 .resume = mmc_omap_resume,
1255 .name = DRIVER_NAME,
1259 static int __init mmc_omap_init(void)
1261 return platform_driver_register(&mmc_omap_driver);
1264 static void __exit mmc_omap_exit(void)
1266 platform_driver_unregister(&mmc_omap_driver);
1269 module_init(mmc_omap_init);
1270 module_exit(mmc_omap_exit);
1272 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1273 MODULE_LICENSE("GPL");
1274 MODULE_ALIAS(DRIVER_NAME);
1275 MODULE_AUTHOR("Juha Yrjölä");