drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrj�l�<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29 #include <linux/i2c/tps65010.h>
  30
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33 #include <asm/mach-types.h>
  34
  35 #include <asm/arch/board.h>
  36 #include <asm/arch/mmc.h>
  37 #include <asm/arch/gpio.h>
  38 #include <asm/arch/dma.h>
  39 #include <asm/arch/mux.h>
  40 #include <asm/arch/fpga.h>
  41 #include <asm/arch/board-sx1.h>
  42
  43 #define OMAP_MMC_REG_CMD        0x00
  44 #define OMAP_MMC_REG_ARGL       0x04
  45 #define OMAP_MMC_REG_ARGH       0x08
  46 #define OMAP_MMC_REG_CON        0x0c
  47 #define OMAP_MMC_REG_STAT       0x10
  48 #define OMAP_MMC_REG_IE         0x14
  49 #define OMAP_MMC_REG_CTO        0x18
  50 #define OMAP_MMC_REG_DTO        0x1c
  51 #define OMAP_MMC_REG_DATA       0x20
  52 #define OMAP_MMC_REG_BLEN       0x24
  53 #define OMAP_MMC_REG_NBLK       0x28
  54 #define OMAP_MMC_REG_BUF        0x2c
  55 #define OMAP_MMC_REG_SDIO       0x34
  56 #define OMAP_MMC_REG_REV        0x3c
  57 #define OMAP_MMC_REG_RSP0       0x40
  58 #define OMAP_MMC_REG_RSP1       0x44
  59 #define OMAP_MMC_REG_RSP2       0x48
  60 #define OMAP_MMC_REG_RSP3       0x4c
  61 #define OMAP_MMC_REG_RSP4       0x50
  62 #define OMAP_MMC_REG_RSP5       0x54
  63 #define OMAP_MMC_REG_RSP6       0x58
  64 #define OMAP_MMC_REG_RSP7       0x5c
  65 #define OMAP_MMC_REG_IOSR       0x60
  66 #define OMAP_MMC_REG_SYSC       0x64
  67 #define OMAP_MMC_REG_SYSS       0x68
  68
  69 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  70 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  71 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  72 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  73 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  74 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  75 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  76 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  77 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  78 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  79 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  80 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  81 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  82
  83 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  84 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  85
  86 /*
  87  * Command types
  88  */
  89 #define OMAP_MMC_CMDTYPE_BC     0
  90 #define OMAP_MMC_CMDTYPE_BCR    1
  91 #define OMAP_MMC_CMDTYPE_AC     2
  92 #define OMAP_MMC_CMDTYPE_ADTC   3
  93
  94
  95 #define DRIVER_NAME "mmci-omap"
  96
  97 /* Specifies how often in millisecs to poll for card status changes
  98  * when the cover switch is open */
  99 #define OMAP_MMC_COVER_POLL_DELAY       500
 100
 101 struct mmc_omap_host;
 102
 103 struct mmc_omap_slot {
 104         int                     id;
 105         unsigned int            vdd;
 106         u16                     saved_con;
 107         u16                     bus_mode;
 108         unsigned int            fclk_freq;
 109         unsigned                powered:1;
 110
 111         struct tasklet_struct   cover_tasklet;
 112         struct timer_list       cover_timer;
 113         unsigned                cover_open;
 114
 115         struct mmc_request      *mrq;
 116         struct mmc_omap_host    *host;
 117         struct mmc_host         *mmc;
 118         struct omap_mmc_slot_data *pdata;
 119 };
 120
 121 struct mmc_omap_host {
 122         int                     initialized;
 123         int                     suspended;
 124         struct mmc_request *    mrq;
 125         struct mmc_command *    cmd;
 126         struct mmc_data *       data;
 127         struct mmc_host *       mmc;
 128         struct device *         dev;
 129         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 130         struct clk *            iclk;
 131         struct clk *            fclk;
 132         struct resource         *mem_res;
 133         void __iomem            *virt_base;
 134         unsigned int            phys_base;
 135         int                     irq;
 136         unsigned char           bus_mode;
 137         unsigned char           hw_bus_mode;
 138
 139         struct work_struct      cmd_abort_work;
 140         unsigned                abort:1;
 141         struct timer_list       cmd_abort_timer;
 142
 143         struct work_struct      slot_release_work;
 144         struct mmc_omap_slot    *next_slot;
 145         struct work_struct      send_stop_work;
 146         struct mmc_data         *stop_data;
 147
 148         unsigned int            sg_len;
 149         int                     sg_idx;
 150         u16 *                   buffer;
 151         u32                     buffer_bytes_left;
 152         u32                     total_bytes_left;
 153
 154         unsigned                use_dma:1;
 155         unsigned                brs_received:1, dma_done:1;
 156         unsigned                dma_is_read:1;
 157         unsigned                dma_in_use:1;
 158         int                     dma_ch;
 159         spinlock_t              dma_lock;
 160         struct timer_list       dma_timer;
 161         unsigned                dma_len;
 162
 163         short                   power_pin;
 164
 165         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 166         struct mmc_omap_slot    *current_slot;
 167         spinlock_t              slot_lock;
 168         wait_queue_head_t       slot_wq;
 169         int                     nr_slots;
 170
 171         struct timer_list       clk_timer;
 172         spinlock_t              clk_lock;     /* for changing enabled state */
 173         unsigned int            fclk_enabled:1;
 174
 175         struct omap_mmc_platform_data *pdata;
 176 };
 177
 178 void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
 179 {
 180         unsigned long tick_ns;
 181
 182         if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
 183                 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
 184                 ndelay(8 * tick_ns);
 185         }
 186 }
 187
 188 void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
 189 {
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&host->clk_lock, flags);
 193         if (host->fclk_enabled != enable) {
 194                 host->fclk_enabled = enable;
 195                 if (enable)
 196                         clk_enable(host->fclk);
 197                 else
 198                         clk_disable(host->fclk);
 199         }
 200         spin_unlock_irqrestore(&host->clk_lock, flags);
 201 }
 202
 203 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 204 {
 205         struct mmc_omap_host *host = slot->host;
 206         unsigned long flags;
 207
 208         if (claimed)
 209                 goto no_claim;
 210         spin_lock_irqsave(&host->slot_lock, flags);
 211         while (host->mmc != NULL) {
 212                 spin_unlock_irqrestore(&host->slot_lock, flags);
 213                 wait_event(host->slot_wq, host->mmc == NULL);
 214                 spin_lock_irqsave(&host->slot_lock, flags);
 215         }
 216         host->mmc = slot->mmc;
 217         spin_unlock_irqrestore(&host->slot_lock, flags);
 218 no_claim:
 219         del_timer(&host->clk_timer);
 220         if (host->current_slot != slot || !claimed)
 221                 mmc_omap_fclk_offdelay(host->current_slot);
 222
 223         if (host->current_slot != slot) {
 224                 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
 225                 if (host->pdata->switch_slot != NULL)
 226                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 227                 host->current_slot = slot;
 228         }
 229
 230         if (claimed) {
 231                 mmc_omap_fclk_enable(host, 1);
 232
 233                 /* Doing the dummy read here seems to work around some bug
 234                  * at least in OMAP24xx silicon where the command would not
 235                  * start after writing the CMD register. Sigh. */
 236                 OMAP_MMC_READ(host, CON);
 237
 238                 OMAP_MMC_WRITE(host, CON, slot->saved_con);
 239         } else
 240                 mmc_omap_fclk_enable(host, 0);
 241 }
 242
 243 static void mmc_omap_start_request(struct mmc_omap_host *host,
 244                                    struct mmc_request *req);
 245
 246 static void mmc_omap_slot_release_work(struct work_struct *work)
 247 {
 248         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 249                                                   slot_release_work);
 250         struct mmc_omap_slot *next_slot = host->next_slot;
 251         struct mmc_request *rq;
 252
 253         host->next_slot = NULL;
 254         mmc_omap_select_slot(next_slot, 1);
 255
 256         rq = next_slot->mrq;
 257         next_slot->mrq = NULL;
 258         mmc_omap_start_request(host, rq);
 259 }
 260
 261 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
 262 {
 263         struct mmc_omap_host *host = slot->host;
 264         unsigned long flags;
 265         int i;
 266
 267         BUG_ON(slot == NULL || host->mmc == NULL);
 268
 269         if (clk_enabled)
 270                 /* Keeps clock running for at least 8 cycles on valid freq */
 271                 mod_timer(&host->clk_timer, jiffies  + HZ/10);
 272         else {
 273                 del_timer(&host->clk_timer);
 274                 mmc_omap_fclk_offdelay(slot);
 275                 mmc_omap_fclk_enable(host, 0);
 276         }
 277
 278         spin_lock_irqsave(&host->slot_lock, flags);
 279         /* Check for any pending requests */
 280         for (i = 0; i < host->nr_slots; i++) {
 281                 struct mmc_omap_slot *new_slot;
 282
 283                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 284                         continue;
 285
 286                 BUG_ON(host->next_slot != NULL);
 287                 new_slot = host->slots[i];
 288                 /* The current slot should not have a request in queue */
 289                 BUG_ON(new_slot == host->current_slot);
 290
 291                 host->next_slot = new_slot;
 292                 host->mmc = new_slot->mmc;
 293                 spin_unlock_irqrestore(&host->slot_lock, flags);
 294                 schedule_work(&host->slot_release_work);
 295                 return;
 296         }
 297
 298         host->mmc = NULL;
 299         wake_up(&host->slot_wq);
 300         spin_unlock_irqrestore(&host->slot_lock, flags);
 301 }
 302
 303 static inline
 304 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 305 {
 306         if (slot->pdata->get_cover_state)
 307                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 308         return 0;
 309 }
 310
 311 static ssize_t
 312 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 313                            char *buf)
 314 {
 315         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 316         struct mmc_omap_slot *slot = mmc_priv(mmc);
 317
 318         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 319                        "closed");
 320 }
 321
 322 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 323
 324 /* Access to the R/O switch is required for production testing
 325  * purposes. */
 326 static ssize_t
 327 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
 328 {
 329         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 330         struct mmc_omap_slot *slot = mmc_priv(mmc);
 331
 332         return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
 333                                                         slot->id));
 334 }
 335
 336 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
 337
 338 static ssize_t
 339 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 340                         char *buf)
 341 {
 342         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 343         struct mmc_omap_slot *slot = mmc_priv(mmc);
 344
 345         return sprintf(buf, "%s\n", slot->pdata->name);
 346 }
 347
 348 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 349
 350 static void
 351 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 352 {
 353         u32 cmdreg;
 354         u32 resptype;
 355         u32 cmdtype;
 356
 357         host->cmd = cmd;
 358
 359         resptype = 0;
 360         cmdtype = 0;
 361
 362         /* Our hardware needs to know exact type */
 363         switch (mmc_resp_type(cmd)) {
 364         case MMC_RSP_NONE:
 365                 break;
 366         case MMC_RSP_R1:
 367         case MMC_RSP_R1B:
 368                 /* resp 1, 1b, 6, 7 */
 369                 resptype = 1;
 370                 break;
 371         case MMC_RSP_R2:
 372                 resptype = 2;
 373                 break;
 374         case MMC_RSP_R3:
 375                 resptype = 3;
 376                 break;
 377         default:
 378                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 379                 break;
 380         }
 381
 382         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 383                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 384         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 385                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 386         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 387                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 388         } else {
 389                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 390         }
 391
 392         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 393
 394         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 395                 cmdreg |= 1 << 6;
 396
 397         if (cmd->flags & MMC_RSP_BUSY)
 398                 cmdreg |= 1 << 11;
 399
 400         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 401                 cmdreg |= 1 << 15;
 402
 403         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 404
 405         OMAP_MMC_WRITE(host, CTO, 200);
 406         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 407         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 408         OMAP_MMC_WRITE(host, IE,
 409                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 410                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 411                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 412                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 413                        OMAP_MMC_STAT_END_OF_DATA);
 414         OMAP_MMC_WRITE(host, CMD, cmdreg);
 415 }
 416
 417 static void
 418 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 419                      int abort)
 420 {
 421         enum dma_data_direction dma_data_dir;
 422
 423         BUG_ON(host->dma_ch < 0);
 424         if (data->error)
 425                 omap_stop_dma(host->dma_ch);
 426         /* Release DMA channel lazily */
 427         mod_timer(&host->dma_timer, jiffies + HZ);
 428         if (data->flags & MMC_DATA_WRITE)
 429                 dma_data_dir = DMA_TO_DEVICE;
 430         else
 431                 dma_data_dir = DMA_FROM_DEVICE;
 432         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 433                      dma_data_dir);
 434 }
 435
 436 static void mmc_omap_send_stop_work(struct work_struct *work)
 437 {
 438         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 439                                                   send_stop_work);
 440         struct mmc_omap_slot *slot = host->current_slot;
 441         struct mmc_data *data = host->stop_data;
 442         unsigned long tick_ns;
 443
 444         tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 445         ndelay(8*tick_ns);
 446
 447         mmc_omap_start_command(host, data->stop);
 448 }
 449
 450 static void
 451 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 452 {
 453         if (host->dma_in_use)
 454                 mmc_omap_release_dma(host, data, data->error);
 455
 456         host->data = NULL;
 457         host->sg_len = 0;
 458
 459         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 460          * dozens of requests until the card finishes writing data.
 461          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 462          */
 463
 464         if (!data->stop) {
 465                 struct mmc_host *mmc;
 466
 467                 host->mrq = NULL;
 468                 mmc = host->mmc;
 469                 mmc_omap_release_slot(host->current_slot, 1);
 470                 mmc_request_done(mmc, data->mrq);
 471                 return;
 472         }
 473
 474         host->stop_data = data;
 475         schedule_work(&host->send_stop_work);
 476 }
 477
 478 static void
 479 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 480 {
 481         struct mmc_omap_slot *slot = host->current_slot;
 482         unsigned int restarts, passes, timeout;
 483         u16 stat = 0;
 484
 485         /* Sending abort takes 80 clocks. Have some extra and round up */
 486         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 487         restarts = 0;
 488         while (restarts < maxloops) {
 489                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 490                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 491
 492                 passes = 0;
 493                 while (passes < timeout) {
 494                         stat = OMAP_MMC_READ(host, STAT);
 495                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 496                                 goto out;
 497                         udelay(1);
 498                         passes++;
 499                 }
 500
 501                 restarts++;
 502         }
 503 out:
 504         OMAP_MMC_WRITE(host, STAT, stat);
 505 }
 506
 507 static void
 508 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 509 {
 510         if (host->dma_in_use)
 511                 mmc_omap_release_dma(host, data, 1);
 512
 513         host->data = NULL;
 514         host->sg_len = 0;
 515
 516         mmc_omap_send_abort(host, 10000);
 517 }
 518
 519 static void
 520 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 521 {
 522         unsigned long flags;
 523         int done;
 524
 525         if (!host->dma_in_use) {
 526                 mmc_omap_xfer_done(host, data);
 527                 return;
 528         }
 529         done = 0;
 530         spin_lock_irqsave(&host->dma_lock, flags);
 531         if (host->dma_done)
 532                 done = 1;
 533         else
 534                 host->brs_received = 1;
 535         spin_unlock_irqrestore(&host->dma_lock, flags);
 536         if (done)
 537                 mmc_omap_xfer_done(host, data);
 538 }
 539
 540 static void
 541 mmc_omap_dma_timer(unsigned long data)
 542 {
 543         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 544
 545         BUG_ON(host->dma_ch < 0);
 546         omap_free_dma(host->dma_ch);
 547         host->dma_ch = -1;
 548 }
 549
 550 static void
 551 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 552 {
 553         unsigned long flags;
 554         int done;
 555
 556         done = 0;
 557         spin_lock_irqsave(&host->dma_lock, flags);
 558         if (host->brs_received)
 559                 done = 1;
 560         else
 561                 host->dma_done = 1;
 562         spin_unlock_irqrestore(&host->dma_lock, flags);
 563         if (done)
 564                 mmc_omap_xfer_done(host, data);
 565 }
 566
 567 static void
 568 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 569 {
 570         host->cmd = NULL;
 571
 572         del_timer(&host->cmd_abort_timer);
 573
 574         if (cmd->flags & MMC_RSP_PRESENT) {
 575                 if (cmd->flags & MMC_RSP_136) {
 576                         /* response type 2 */
 577                         cmd->resp[3] =
 578                                 OMAP_MMC_READ(host, RSP0) |
 579                                 (OMAP_MMC_READ(host, RSP1) << 16);
 580                         cmd->resp[2] =
 581                                 OMAP_MMC_READ(host, RSP2) |
 582                                 (OMAP_MMC_READ(host, RSP3) << 16);
 583                         cmd->resp[1] =
 584                                 OMAP_MMC_READ(host, RSP4) |
 585                                 (OMAP_MMC_READ(host, RSP5) << 16);
 586                         cmd->resp[0] =
 587                                 OMAP_MMC_READ(host, RSP6) |
 588                                 (OMAP_MMC_READ(host, RSP7) << 16);
 589                 } else {
 590                         /* response types 1, 1b, 3, 4, 5, 6 */
 591                         cmd->resp[0] =
 592                                 OMAP_MMC_READ(host, RSP6) |
 593                                 (OMAP_MMC_READ(host, RSP7) << 16);
 594                 }
 595         }
 596
 597         if (host->data == NULL || cmd->error) {
 598                 struct mmc_host *mmc;
 599
 600                 if (host->data != NULL)
 601                         mmc_omap_abort_xfer(host, host->data);
 602                 host->mrq = NULL;
 603                 mmc = host->mmc;
 604                 mmc_omap_release_slot(host->current_slot, 1);
 605                 mmc_request_done(mmc, cmd->mrq);
 606         }
 607 }
 608
 609 /*
 610  * Abort stuck command. Can occur when card is removed while it is being
 611  * read.
 612  */
 613 static void mmc_omap_abort_command(struct work_struct *work)
 614 {
 615         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 616                                                   cmd_abort_work);
 617         BUG_ON(!host->cmd);
 618
 619         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 620                 host->cmd->opcode);
 621
 622         if (host->cmd->error == 0)
 623                 host->cmd->error = -ETIMEDOUT;
 624
 625         if (host->data == NULL) {
 626                 struct mmc_command *cmd;
 627                 struct mmc_host    *mmc;
 628
 629                 cmd = host->cmd;
 630                 host->cmd = NULL;
 631                 mmc_omap_send_abort(host, 10000);
 632
 633                 host->mrq = NULL;
 634                 mmc = host->mmc;
 635                 mmc_omap_release_slot(host->current_slot, 1);
 636                 mmc_request_done(mmc, cmd->mrq);
 637         } else
 638                 mmc_omap_cmd_done(host, host->cmd);
 639
 640         host->abort = 0;
 641         enable_irq(host->irq);
 642 }
 643
 644 static void
 645 mmc_omap_cmd_timer(unsigned long data)
 646 {
 647         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 648         unsigned long flags;
 649
 650         spin_lock_irqsave(&host->slot_lock, flags);
 651         if (host->cmd != NULL && !host->abort) {
 652                 OMAP_MMC_WRITE(host, IE, 0);
 653                 disable_irq(host->irq);
 654                 host->abort = 1;
 655                 schedule_work(&host->cmd_abort_work);
 656         }
 657         spin_unlock_irqrestore(&host->slot_lock, flags);
 658 }
 659
 660 /* PIO only */
 661 static void
 662 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 663 {
 664         struct scatterlist *sg;
 665
 666         sg = host->data->sg + host->sg_idx;
 667         host->buffer_bytes_left = sg->length;
 668         host->buffer = sg_virt(sg);
 669         if (host->buffer_bytes_left > host->total_bytes_left)
 670                 host->buffer_bytes_left = host->total_bytes_left;
 671 }
 672
 673 static void
 674 mmc_omap_clk_timer(unsigned long data)
 675 {
 676         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 677
 678         mmc_omap_fclk_enable(host, 0);
 679 }
 680
 681 /* PIO only */
 682 static void
 683 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 684 {
 685         int n;
 686
 687         if (host->buffer_bytes_left == 0) {
 688                 host->sg_idx++;
 689                 BUG_ON(host->sg_idx == host->sg_len);
 690                 mmc_omap_sg_to_buf(host);
 691         }
 692         n = 64;
 693         if (n > host->buffer_bytes_left)
 694                 n = host->buffer_bytes_left;
 695         host->buffer_bytes_left -= n;
 696         host->total_bytes_left -= n;
 697         host->data->bytes_xfered += n;
 698
 699         if (write) {
 700                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 701         } else {
 702                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 703         }
 704 }
 705
 706 static inline void mmc_omap_report_irq(u16 status)
 707 {
 708         static const char *mmc_omap_status_bits[] = {
 709                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 710                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 711         };
 712         int i, c = 0;
 713
 714         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 715                 if (status & (1 << i)) {
 716                         if (c)
 717                                 printk(" ");
 718                         printk("%s", mmc_omap_status_bits[i]);
 719                         c++;
 720                 }
 721 }
 722
 723 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 724 {
 725         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 726         u16 status;
 727         int end_command;
 728         int end_transfer;
 729         int transfer_error, cmd_error;
 730
 731         if (host->cmd == NULL && host->data == NULL) {
 732                 status = OMAP_MMC_READ(host, STAT);
 733                 dev_info(mmc_dev(host->slots[0]->mmc),
 734                          "Spurious IRQ 0x%04x\n", status);
 735                 if (status != 0) {
 736                         OMAP_MMC_WRITE(host, STAT, status);
 737                         OMAP_MMC_WRITE(host, IE, 0);
 738                 }
 739                 return IRQ_HANDLED;
 740         }
 741
 742         end_command = 0;
 743         end_transfer = 0;
 744         transfer_error = 0;
 745         cmd_error = 0;
 746
 747         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 748                 int cmd;
 749
 750                 OMAP_MMC_WRITE(host, STAT, status);
 751                 if (host->cmd != NULL)
 752                         cmd = host->cmd->opcode;
 753                 else
 754                         cmd = -1;
 755 #ifdef CONFIG_MMC_DEBUG
 756                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 757                         status, cmd);
 758                 mmc_omap_report_irq(status);
 759                 printk("\n");
 760 #endif
 761                 if (host->total_bytes_left) {
 762                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 763                             (status & OMAP_MMC_STAT_END_OF_DATA))
 764                                 mmc_omap_xfer_data(host, 0);
 765                         if (status & OMAP_MMC_STAT_A_EMPTY)
 766                                 mmc_omap_xfer_data(host, 1);
 767                 }
 768
 769                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 770                         end_transfer = 1;
 771
 772                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 773                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 774                                 cmd);
 775                         if (host->data) {
 776                                 host->data->error = -ETIMEDOUT;
 777                                 transfer_error = 1;
 778                         }
 779                 }
 780
 781                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 782                         if (host->data) {
 783                                 host->data->error = -EILSEQ;
 784                                 dev_dbg(mmc_dev(host->mmc),
 785                                          "data CRC error, bytes left %d\n",
 786                                         host->total_bytes_left);
 787                                 transfer_error = 1;
 788                         } else {
 789                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 790                         }
 791                 }
 792
 793                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 794                         /* Timeouts are routine with some commands */
 795                         if (host->cmd) {
 796                                 struct mmc_omap_slot *slot =
 797                                         host->current_slot;
 798                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 799                                     host->cmd->opcode != MMC_SEND_OP_COND &&
 800                                     host->cmd->opcode != MMC_APP_CMD &&
 801                                     (slot == NULL ||
 802                                      !mmc_omap_cover_is_open(slot)))
 803                                         dev_err(mmc_dev(host->mmc),
 804                                                 "command timeout (CMD%d)\n",
 805                                                 cmd);
 806                                 host->cmd->error = -ETIMEDOUT;
 807                                 end_command = 1;
 808                                 cmd_error = 1;
 809                         }
 810                 }
 811
 812                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 813                         if (host->cmd) {
 814                                 dev_err(mmc_dev(host->mmc),
 815                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 816                                         cmd, host->cmd->arg);
 817                                 host->cmd->error = -EILSEQ;
 818                                 end_command = 1;
 819                                 cmd_error = 1;
 820                         } else
 821                                 dev_err(mmc_dev(host->mmc),
 822                                         "command CRC error without cmd?\n");
 823                 }
 824
 825                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 826                         dev_dbg(mmc_dev(host->mmc),
 827                                 "ignoring card status error (CMD%d)\n",
 828                                 cmd);
 829                         end_command = 1;
 830                 }
 831
 832                 /*
 833                  * NOTE: On 1610 the END_OF_CMD may come too early when
 834                  * starting a write
 835                  */
 836                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 837                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 838                         end_command = 1;
 839                 }
 840         }
 841
 842         if (cmd_error && host->data) {
 843                 del_timer(&host->cmd_abort_timer);
 844                 host->abort = 1;
 845                 OMAP_MMC_WRITE(host, IE, 0);
 846                 disable_irq(host->irq);
 847                 schedule_work(&host->cmd_abort_work);
 848                 return IRQ_HANDLED;
 849         }
 850
 851         if (end_command)
 852                 mmc_omap_cmd_done(host, host->cmd);
 853         if (host->data != NULL) {
 854                 if (transfer_error)
 855                         mmc_omap_xfer_done(host, host->data);
 856                 else if (end_transfer)
 857                         mmc_omap_end_of_data(host, host->data);
 858         }
 859
 860         return IRQ_HANDLED;
 861 }
 862
 863 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 864 {
 865         int cover_open;
 866         struct mmc_omap_host *host = dev_get_drvdata(dev);
 867         struct mmc_omap_slot *slot = host->slots[num];
 868
 869         BUG_ON(num >= host->nr_slots);
 870
 871         /* Other subsystems can call in here before we're initialised. */
 872         if (host->nr_slots == 0 || !host->slots[num])
 873                 return;
 874
 875         cover_open = mmc_omap_cover_is_open(slot);
 876         if (cover_open != slot->cover_open) {
 877                 slot->cover_open = cover_open;
 878                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 879         }
 880
 881         tasklet_hi_schedule(&slot->cover_tasklet);
 882 }
 883
 884 static void mmc_omap_cover_timer(unsigned long arg)
 885 {
 886         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 887         tasklet_schedule(&slot->cover_tasklet);
 888 }
 889
 890 static void mmc_omap_cover_handler(unsigned long param)
 891 {
 892         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 893         int cover_open = mmc_omap_cover_is_open(slot);
 894
 895         mmc_detect_change(slot->mmc, 0);
 896         if (!cover_open)
 897                 return;
 898
 899         /*
 900          * If no card is inserted, we postpone polling until
 901          * the cover has been closed.
 902          */
 903         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 904                 return;
 905
 906         mod_timer(&slot->cover_timer,
 907                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 908 }
 909
 910 /* Prepare to transfer the next segment of a scatterlist */
 911 static void
 912 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 913 {
 914         int dma_ch = host->dma_ch;
 915         unsigned long data_addr;
 916         u16 buf, frame;
 917         u32 count;
 918         struct scatterlist *sg = &data->sg[host->sg_idx];
 919         int src_port = 0;
 920         int dst_port = 0;
 921         int sync_dev = 0;
 922
 923         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 924         frame = data->blksz;
 925         count = sg_dma_len(sg);
 926
 927         if ((data->blocks == 1) && (count > data->blksz))
 928                 count = frame;
 929
 930         host->dma_len = count;
 931
 932         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 933          * Use 16 or 32 word frames when the blocksize is at least that large.
 934          * Blocksize is usually 512 bytes; but not for some SD reads.
 935          */
 936         if (cpu_is_omap15xx() && frame > 32)
 937                 frame = 32;
 938         else if (frame > 64)
 939                 frame = 64;
 940         count /= frame;
 941         frame >>= 1;
 942
 943         if (!(data->flags & MMC_DATA_WRITE)) {
 944                 buf = 0x800f | ((frame - 1) << 8);
 945
 946                 if (cpu_class_is_omap1()) {
 947                         src_port = OMAP_DMA_PORT_TIPB;
 948                         dst_port = OMAP_DMA_PORT_EMIFF;
 949                 }
 950                 if (cpu_is_omap24xx())
 951                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 952
 953                 omap_set_dma_src_params(dma_ch, src_port,
 954                                         OMAP_DMA_AMODE_CONSTANT,
 955                                         data_addr, 0, 0);
 956                 omap_set_dma_dest_params(dma_ch, dst_port,
 957                                          OMAP_DMA_AMODE_POST_INC,
 958                                          sg_dma_address(sg), 0, 0);
 959                 omap_set_dma_dest_data_pack(dma_ch, 1);
 960                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 961         } else {
 962                 buf = 0x0f80 | ((frame - 1) << 0);
 963
 964                 if (cpu_class_is_omap1()) {
 965                         src_port = OMAP_DMA_PORT_EMIFF;
 966                         dst_port = OMAP_DMA_PORT_TIPB;
 967                 }
 968                 if (cpu_is_omap24xx())
 969                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 970
 971                 omap_set_dma_dest_params(dma_ch, dst_port,
 972                                          OMAP_DMA_AMODE_CONSTANT,
 973                                          data_addr, 0, 0);
 974                 omap_set_dma_src_params(dma_ch, src_port,
 975                                         OMAP_DMA_AMODE_POST_INC,
 976                                         sg_dma_address(sg), 0, 0);
 977                 omap_set_dma_src_data_pack(dma_ch, 1);
 978                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 979         }
 980
 981         /* Max limit for DMA frame count is 0xffff */
 982         BUG_ON(count > 0xffff);
 983
 984         OMAP_MMC_WRITE(host, BUF, buf);
 985         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 986                                      frame, count, OMAP_DMA_SYNC_FRAME,
 987                                      sync_dev, 0);
 988 }
 989
 990 /* A scatterlist segment completed */
 991 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 992 {
 993         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 994         struct mmc_data *mmcdat = host->data;
 995
 996         if (unlikely(host->dma_ch < 0)) {
 997                 dev_err(mmc_dev(host->mmc),
 998                         "DMA callback while DMA not enabled\n");
 999                 return;
1000         }
1001         /* FIXME: We really should do something to _handle_ the errors */
1002         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
1003                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
1004                 return;
1005         }
1006         if (ch_status & OMAP_DMA_DROP_IRQ) {
1007                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
1008                 return;
1009         }
1010         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1011                 return;
1012         }
1013         mmcdat->bytes_xfered += host->dma_len;
1014         host->sg_idx++;
1015         if (host->sg_idx < host->sg_len) {
1016                 mmc_omap_prepare_dma(host, host->data);
1017                 omap_start_dma(host->dma_ch);
1018         } else
1019                 mmc_omap_dma_done(host, host->data);
1020 }
1021
1022 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
1023 {
1024         const char *dev_name;
1025         int sync_dev, dma_ch, is_read, r;
1026
1027         is_read = !(data->flags & MMC_DATA_WRITE);
1028         del_timer_sync(&host->dma_timer);
1029         if (host->dma_ch >= 0) {
1030                 if (is_read == host->dma_is_read)
1031                         return 0;
1032                 omap_free_dma(host->dma_ch);
1033                 host->dma_ch = -1;
1034         }
1035
1036         if (is_read) {
1037                 if (host->id == 1) {
1038                         sync_dev = OMAP_DMA_MMC_RX;
1039                         dev_name = "MMC1 read";
1040                 } else {
1041                         sync_dev = OMAP_DMA_MMC2_RX;
1042                         dev_name = "MMC2 read";
1043                 }
1044         } else {
1045                 if (host->id == 1) {
1046                         sync_dev = OMAP_DMA_MMC_TX;
1047                         dev_name = "MMC1 write";
1048                 } else {
1049                         sync_dev = OMAP_DMA_MMC2_TX;
1050                         dev_name = "MMC2 write";
1051                 }
1052         }
1053         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
1054                              host, &dma_ch);
1055         if (r != 0) {
1056                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
1057                 return r;
1058         }
1059         host->dma_ch = dma_ch;
1060         host->dma_is_read = is_read;
1061
1062         return 0;
1063 }
1064
1065 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1066 {
1067         u16 reg;
1068
1069         reg = OMAP_MMC_READ(host, SDIO);
1070         reg &= ~(1 << 5);
1071         OMAP_MMC_WRITE(host, SDIO, reg);
1072         /* Set maximum timeout */
1073         OMAP_MMC_WRITE(host, CTO, 0xff);
1074 }
1075
1076 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1077 {
1078         unsigned int timeout, cycle_ns;
1079         u16 reg;
1080
1081         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
1082         timeout = req->data->timeout_ns / cycle_ns;
1083         timeout += req->data->timeout_clks;
1084
1085         /* Check if we need to use timeout multiplier register */
1086         reg = OMAP_MMC_READ(host, SDIO);
1087         if (timeout > 0xffff) {
1088                 reg |= (1 << 5);
1089                 timeout /= 1024;
1090         } else
1091                 reg &= ~(1 << 5);
1092         OMAP_MMC_WRITE(host, SDIO, reg);
1093         OMAP_MMC_WRITE(host, DTO, timeout);
1094 }
1095
1096 static void
1097 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
1098 {
1099         struct mmc_data *data = req->data;
1100         int i, use_dma, block_size;
1101         unsigned sg_len;
1102
1103         host->data = data;
1104         if (data == NULL) {
1105                 OMAP_MMC_WRITE(host, BLEN, 0);
1106                 OMAP_MMC_WRITE(host, NBLK, 0);
1107                 OMAP_MMC_WRITE(host, BUF, 0);
1108                 host->dma_in_use = 0;
1109                 set_cmd_timeout(host, req);
1110                 return;
1111         }
1112
1113         block_size = data->blksz;
1114
1115         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1116         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1117         set_data_timeout(host, req);
1118
1119         /* cope with calling layer confusion; it issues "single
1120          * block" writes using multi-block scatterlists.
1121          */
1122         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1123
1124         /* Only do DMA for entire blocks */
1125         use_dma = host->use_dma;
1126         if (use_dma) {
1127                 for (i = 0; i < sg_len; i++) {
1128                         if ((data->sg[i].length % block_size) != 0) {
1129                                 use_dma = 0;
1130                                 break;
1131                         }
1132                 }
1133         }
1134
1135         host->sg_idx = 0;
1136         if (use_dma) {
1137                 if (mmc_omap_get_dma_channel(host, data) == 0) {
1138                         enum dma_data_direction dma_data_dir;
1139
1140                         if (data->flags & MMC_DATA_WRITE)
1141                                 dma_data_dir = DMA_TO_DEVICE;
1142                         else
1143                                 dma_data_dir = DMA_FROM_DEVICE;
1144
1145                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1146                                                 sg_len, dma_data_dir);
1147                         host->total_bytes_left = 0;
1148                         mmc_omap_prepare_dma(host, req->data);
1149                         host->brs_received = 0;
1150                         host->dma_done = 0;
1151                         host->dma_in_use = 1;
1152                 } else
1153                         use_dma = 0;
1154         }
1155
1156         /* Revert to PIO? */
1157         if (!use_dma) {
1158                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1159                 host->total_bytes_left = data->blocks * block_size;
1160                 host->sg_len = sg_len;
1161                 mmc_omap_sg_to_buf(host);
1162                 host->dma_in_use = 0;
1163         }
1164 }
1165
1166 static void mmc_omap_start_request(struct mmc_omap_host *host,
1167                                    struct mmc_request *req)
1168 {
1169         BUG_ON(host->mrq != NULL);
1170
1171         host->mrq = req;
1172
1173         /* only touch fifo AFTER the controller readies it */
1174         mmc_omap_prepare_data(host, req);
1175         mmc_omap_start_command(host, req->cmd);
1176         if (host->dma_in_use)
1177                 omap_start_dma(host->dma_ch);
1178         BUG_ON(irqs_disabled());
1179 }
1180
1181 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1182 {
1183         struct mmc_omap_slot *slot = mmc_priv(mmc);
1184         struct mmc_omap_host *host = slot->host;
1185         unsigned long flags;
1186
1187         spin_lock_irqsave(&host->slot_lock, flags);
1188         if (host->mmc != NULL) {
1189                 BUG_ON(slot->mrq != NULL);
1190                 slot->mrq = req;
1191                 spin_unlock_irqrestore(&host->slot_lock, flags);
1192                 return;
1193         } else
1194                 host->mmc = mmc;
1195         spin_unlock_irqrestore(&host->slot_lock, flags);
1196         mmc_omap_select_slot(slot, 1);
1197         mmc_omap_start_request(host, req);
1198 }
1199
1200 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1201                                 int vdd)
1202 {
1203         struct mmc_omap_host *host;
1204
1205         host = slot->host;
1206
1207         if (slot->pdata->set_power != NULL)
1208                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1209                                         vdd);
1210
1211         if (cpu_is_omap24xx()) {
1212                 u16 w;
1213
1214                 if (power_on) {
1215                         w = OMAP_MMC_READ(host, CON);
1216                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1217                 } else {
1218                         w = OMAP_MMC_READ(host, CON);
1219                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1220                 }
1221         }
1222 }
1223
1224 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1225 {
1226         struct mmc_omap_slot *slot = mmc_priv(mmc);
1227         struct mmc_omap_host *host = slot->host;
1228         int func_clk_rate = clk_get_rate(host->fclk);
1229         int dsor;
1230
1231         if (ios->clock == 0)
1232                 return 0;
1233
1234         dsor = func_clk_rate / ios->clock;
1235         if (dsor < 1)
1236                 dsor = 1;
1237
1238         if (func_clk_rate / dsor > ios->clock)
1239                 dsor++;
1240
1241         if (dsor > 250)
1242                 dsor = 250;
1243
1244         slot->fclk_freq = func_clk_rate / dsor;
1245
1246         if (ios->bus_width == MMC_BUS_WIDTH_4)
1247                 dsor |= 1 << 15;
1248
1249         return dsor;
1250 }
1251
1252 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1253 {
1254         struct mmc_omap_slot *slot = mmc_priv(mmc);
1255         struct mmc_omap_host *host = slot->host;
1256         int i, dsor;
1257         int clk_enabled;
1258
1259         mmc_omap_select_slot(slot, 0);
1260
1261         dsor = mmc_omap_calc_divisor(mmc, ios);
1262
1263         if (ios->vdd != slot->vdd)
1264                 slot->vdd = ios->vdd;
1265
1266         clk_enabled = 0;
1267         switch (ios->power_mode) {
1268         case MMC_POWER_OFF:
1269                 mmc_omap_set_power(slot, 0, ios->vdd);
1270                 break;
1271         case MMC_POWER_UP:
1272                 /* Cannot touch dsor yet, just power up MMC */
1273                 mmc_omap_set_power(slot, 1, ios->vdd);
1274                 goto exit;
1275         case MMC_POWER_ON:
1276                 mmc_omap_fclk_enable(host, 1);
1277                 clk_enabled = 1;
1278                 dsor |= 1 << 11;
1279                 break;
1280         }
1281
1282         if (slot->bus_mode != ios->bus_mode) {
1283                 if (slot->pdata->set_bus_mode != NULL)
1284                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1285                                                   ios->bus_mode);
1286                 slot->bus_mode = ios->bus_mode;
1287         }
1288
1289         /* On insanely high arm_per frequencies something sometimes
1290          * goes somehow out of sync, and the POW bit is not being set,
1291          * which results in the while loop below getting stuck.
1292          * Writing to the CON register twice seems to do the trick. */
1293         for (i = 0; i < 2; i++)
1294                 OMAP_MMC_WRITE(host, CON, dsor);
1295         slot->saved_con = dsor;
1296         if (ios->power_mode == MMC_POWER_ON) {
1297                 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1298                 int usecs = 250;
1299
1300                 /* Send clock cycles, poll completion */
1301                 OMAP_MMC_WRITE(host, IE, 0);
1302                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1303                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1304                 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1305                         udelay(1);
1306                         usecs--;
1307                 }
1308                 OMAP_MMC_WRITE(host, STAT, 1);
1309         }
1310
1311 exit:
1312         mmc_omap_release_slot(slot, clk_enabled);
1313 }
1314
1315 static int mmc_omap_get_ro(struct mmc_host *mmc)
1316 {
1317         struct mmc_omap_slot *slot = mmc_priv(mmc);
1318
1319         if (slot->pdata->get_ro != NULL)
1320                 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1321         return 0;
1322 }
1323
1324 static const struct mmc_host_ops mmc_omap_ops = {
1325         .request        = mmc_omap_request,
1326         .set_ios        = mmc_omap_set_ios,
1327         .get_ro         = mmc_omap_get_ro,
1328 };
1329
1330 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1331 {
1332         struct mmc_omap_slot *slot = NULL;
1333         struct mmc_host *mmc;
1334         int r;
1335
1336         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1337         if (mmc == NULL)
1338                 return -ENOMEM;
1339
1340         slot = mmc_priv(mmc);
1341         slot->host = host;
1342         slot->mmc = mmc;
1343         slot->id = id;
1344         slot->pdata = &host->pdata->slots[id];
1345
1346         host->slots[id] = slot;
1347
1348         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1349                     MMC_CAP_SD_HIGHSPEED;
1350         if (host->pdata->conf.wire4)
1351                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1352
1353         mmc->ops = &mmc_omap_ops;
1354         mmc->f_min = 400000;
1355
1356         if (cpu_class_is_omap2())
1357                 mmc->f_max = 48000000;
1358         else
1359                 mmc->f_max = 24000000;
1360         if (host->pdata->max_freq)
1361                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1362         mmc->ocr_avail = slot->pdata->ocr_mask;
1363
1364         /* Use scatterlist DMA to reduce per-transfer costs.
1365          * NOTE max_seg_size assumption that small blocks aren't
1366          * normally used (except e.g. for reading SD registers).
1367          */
1368         mmc->max_phys_segs = 32;
1369         mmc->max_hw_segs = 32;
1370         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1371         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1372         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1373         mmc->max_seg_size = mmc->max_req_size;
1374
1375         r = mmc_add_host(mmc);
1376         if (r < 0)
1377                 return r;
1378
1379         if (slot->pdata->name != NULL) {
1380                 r = device_create_file(&mmc->class_dev,
1381                                         &dev_attr_slot_name);
1382                 if (r < 0)
1383                         goto err_remove_host;
1384         }
1385
1386         if (slot->pdata->get_cover_state != NULL) {
1387                 r = device_create_file(&mmc->class_dev,
1388                                         &dev_attr_cover_switch);
1389                 if (r < 0)
1390                         goto err_remove_slot_name;
1391
1392                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1393                             (unsigned long)slot);
1394                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1395                              (unsigned long)slot);
1396                 tasklet_schedule(&slot->cover_tasklet);
1397         }
1398
1399         if (slot->pdata->get_ro != NULL) {
1400                 r = device_create_file(&mmc->class_dev,
1401                                         &dev_attr_ro);
1402                 if (r < 0)
1403                         goto err_remove_cover_attr;
1404         }
1405
1406         return 0;
1407
1408 err_remove_cover_attr:
1409         if (slot->pdata->get_cover_state != NULL)
1410                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1411 err_remove_slot_name:
1412         if (slot->pdata->name != NULL)
1413                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1414 err_remove_host:
1415         mmc_remove_host(mmc);
1416         return r;
1417 }
1418
1419 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1420 {
1421         struct mmc_host *mmc = slot->mmc;
1422
1423         if (slot->pdata->name != NULL)
1424                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1425         if (slot->pdata->get_cover_state != NULL)
1426                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1427         if (slot->pdata->get_ro != NULL)
1428                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1429
1430         tasklet_kill(&slot->cover_tasklet);
1431         del_timer_sync(&slot->cover_timer);
1432         flush_scheduled_work();
1433
1434         mmc_remove_host(mmc);
1435         mmc_free_host(mmc);
1436 }
1437
1438 static int __init mmc_omap_probe(struct platform_device *pdev)
1439 {
1440         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1441         struct mmc_omap_host *host = NULL;
1442         struct resource *res;
1443         int i, ret = 0;
1444         int irq;
1445
1446         if (pdata == NULL) {
1447                 dev_err(&pdev->dev, "platform data missing\n");
1448                 return -ENXIO;
1449         }
1450         if (pdata->nr_slots == 0) {
1451                 dev_err(&pdev->dev, "no slots\n");
1452                 return -ENXIO;
1453         }
1454
1455         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1456         irq = platform_get_irq(pdev, 0);
1457         if (res == NULL || irq < 0)
1458                 return -ENXIO;
1459
1460         res = request_mem_region(res->start, res->end - res->start + 1,
1461                                  pdev->name);
1462         if (res == NULL)
1463                 return -EBUSY;
1464
1465         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1466         if (host == NULL) {
1467                 ret = -ENOMEM;
1468                 goto err_free_mem_region;
1469         }
1470
1471         INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1472         INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1473
1474         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1475         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1476                     (unsigned long) host);
1477
1478         spin_lock_init(&host->clk_lock);
1479         setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1480
1481         spin_lock_init(&host->dma_lock);
1482         setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1483         spin_lock_init(&host->slot_lock);
1484         init_waitqueue_head(&host->slot_wq);
1485
1486         host->pdata = pdata;
1487         host->dev = &pdev->dev;
1488         platform_set_drvdata(pdev, host);
1489
1490         host->id = pdev->id;
1491         host->mem_res = res;
1492         host->irq = irq;
1493
1494         host->use_dma = 1;
1495         host->dma_ch = -1;
1496
1497         host->irq = irq;
1498         host->phys_base = host->mem_res->start;
1499         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1500
1501         if (cpu_is_omap24xx()) {
1502                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1503                 if (IS_ERR(host->iclk))
1504                         goto err_free_mmc_host;
1505                 clk_enable(host->iclk);
1506         }
1507
1508         if (!cpu_is_omap24xx())
1509                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1510         else
1511                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1512
1513         if (IS_ERR(host->fclk)) {
1514                 ret = PTR_ERR(host->fclk);
1515                 goto err_free_iclk;
1516         }
1517
1518         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1519         if (ret)
1520                 goto err_free_fclk;
1521
1522         if (pdata->init != NULL) {
1523                 ret = pdata->init(&pdev->dev);
1524                 if (ret < 0)
1525                         goto err_free_irq;
1526         }
1527
1528         host->nr_slots = pdata->nr_slots;
1529         for (i = 0; i < pdata->nr_slots; i++) {
1530                 ret = mmc_omap_new_slot(host, i);
1531                 if (ret < 0) {
1532                         while (--i >= 0)
1533                                 mmc_omap_remove_slot(host->slots[i]);
1534
1535                         goto err_plat_cleanup;
1536                 }
1537         }
1538
1539         return 0;
1540
1541 err_plat_cleanup:
1542         if (pdata->cleanup)
1543                 pdata->cleanup(&pdev->dev);
1544 err_free_irq:
1545         free_irq(host->irq, host);
1546 err_free_fclk:
1547         clk_put(host->fclk);
1548 err_free_iclk:
1549         if (host->iclk != NULL) {
1550                 clk_disable(host->iclk);
1551                 clk_put(host->iclk);
1552         }
1553 err_free_mmc_host:
1554         kfree(host);
1555 err_free_mem_region:
1556         release_mem_region(res->start, res->end - res->start + 1);
1557         return ret;
1558 }
1559
1560 static int mmc_omap_remove(struct platform_device *pdev)
1561 {
1562         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1563         int i;
1564
1565         platform_set_drvdata(pdev, NULL);
1566
1567         BUG_ON(host == NULL);
1568
1569         for (i = 0; i < host->nr_slots; i++)
1570                 mmc_omap_remove_slot(host->slots[i]);
1571
1572         if (host->pdata->cleanup)
1573                 host->pdata->cleanup(&pdev->dev);
1574
1575         if (host->iclk && !IS_ERR(host->iclk))
1576                 clk_put(host->iclk);
1577         if (host->fclk && !IS_ERR(host->fclk))
1578                 clk_put(host->fclk);
1579
1580         release_mem_region(pdev->resource[0].start,
1581                            pdev->resource[0].end - pdev->resource[0].start + 1);
1582
1583         kfree(host);
1584
1585         return 0;
1586 }
1587
1588 #ifdef CONFIG_PM
1589 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1590 {
1591         int i, ret = 0;
1592         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1593
1594         if (host == NULL || host->suspended)
1595                 return 0;
1596
1597         for (i = 0; i < host->nr_slots; i++) {
1598                 struct mmc_omap_slot *slot;
1599
1600                 slot = host->slots[i];
1601                 ret = mmc_suspend_host(slot->mmc, mesg);
1602                 if (ret < 0) {
1603                         while (--i >= 0) {
1604                                 slot = host->slots[i];
1605                                 mmc_resume_host(slot->mmc);
1606                         }
1607                         return ret;
1608                 }
1609         }
1610         host->suspended = 1;
1611         return 0;
1612 }
1613
1614 static int mmc_omap_resume(struct platform_device *pdev)
1615 {
1616         int i, ret = 0;
1617         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1618
1619         if (host == NULL || !host->suspended)
1620                 return 0;
1621
1622         for (i = 0; i < host->nr_slots; i++) {
1623                 struct mmc_omap_slot *slot;
1624                 slot = host->slots[i];
1625                 ret = mmc_resume_host(slot->mmc);
1626                 if (ret < 0)
1627                         return ret;
1628
1629                 host->suspended = 0;
1630         }
1631         return 0;
1632 }
1633 #else
1634 #define mmc_omap_suspend        NULL
1635 #define mmc_omap_resume         NULL
1636 #endif
1637
1638 static struct platform_driver mmc_omap_driver = {
1639         .probe          = mmc_omap_probe,
1640         .remove         = mmc_omap_remove,
1641         .suspend        = mmc_omap_suspend,
1642         .resume         = mmc_omap_resume,
1643         .driver         = {
1644                 .name   = DRIVER_NAME,
1645         },
1646 };
1647
1648 static int __init mmc_omap_init(void)
1649 {
1650         return platform_driver_register(&mmc_omap_driver);
1651 }
1652
1653 static void __exit mmc_omap_exit(void)
1654 {
1655         platform_driver_unregister(&mmc_omap_driver);
1656 }
1657
1658 module_init(mmc_omap_init);
1659 module_exit(mmc_omap_exit);
1660
1661 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1662 MODULE_LICENSE("GPL");
1663 MODULE_ALIAS(DRIVER_NAME);
1664 MODULE_AUTHOR("Juha Yrj�l�");