drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/clk.h>
  28 #include <linux/scatterlist.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40 #include <asm/arch/tps65010.h>
  41 #include <asm/arch/board-sx1.h>
  42
  43 #define OMAP_MMC_REG_CMD        0x00
  44 #define OMAP_MMC_REG_ARGL       0x04
  45 #define OMAP_MMC_REG_ARGH       0x08
  46 #define OMAP_MMC_REG_CON        0x0c
  47 #define OMAP_MMC_REG_STAT       0x10
  48 #define OMAP_MMC_REG_IE         0x14
  49 #define OMAP_MMC_REG_CTO        0x18
  50 #define OMAP_MMC_REG_DTO        0x1c
  51 #define OMAP_MMC_REG_DATA       0x20
  52 #define OMAP_MMC_REG_BLEN       0x24
  53 #define OMAP_MMC_REG_NBLK       0x28
  54 #define OMAP_MMC_REG_BUF        0x2c
  55 #define OMAP_MMC_REG_SDIO       0x34
  56 #define OMAP_MMC_REG_REV        0x3c
  57 #define OMAP_MMC_REG_RSP0       0x40
  58 #define OMAP_MMC_REG_RSP1       0x44
  59 #define OMAP_MMC_REG_RSP2       0x48
  60 #define OMAP_MMC_REG_RSP3       0x4c
  61 #define OMAP_MMC_REG_RSP4       0x50
  62 #define OMAP_MMC_REG_RSP5       0x54
  63 #define OMAP_MMC_REG_RSP6       0x58
  64 #define OMAP_MMC_REG_RSP7       0x5c
  65 #define OMAP_MMC_REG_IOSR       0x60
  66 #define OMAP_MMC_REG_SYSC       0x64
  67 #define OMAP_MMC_REG_SYSS       0x68
  68
  69 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  70 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  71 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  72 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  73 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  74 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  75 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  76 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  77 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  78 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  79 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  80 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  81 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  82
  83 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  84 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  85
  86 /*
  87  * Command types
  88  */
  89 #define OMAP_MMC_CMDTYPE_BC     0
  90 #define OMAP_MMC_CMDTYPE_BCR    1
  91 #define OMAP_MMC_CMDTYPE_AC     2
  92 #define OMAP_MMC_CMDTYPE_ADTC   3
  93
  94
  95 #define DRIVER_NAME "mmci-omap"
  96
  97 /* Specifies how often in millisecs to poll for card status changes
  98  * when the cover switch is open */
  99 #define OMAP_MMC_COVER_POLL_DELAY       500
 100
 101 struct mmc_omap_host;
 102
 103 struct mmc_omap_slot {
 104         int                     id;
 105         unsigned int            vdd;
 106         u16                     saved_con;
 107         u16                     bus_mode;
 108         unsigned int            fclk_freq;
 109         unsigned                powered:1;
 110
 111         struct tasklet_struct   cover_tasklet;
 112         struct timer_list       cover_timer;
 113         unsigned                cover_open;
 114
 115         struct mmc_request      *mrq;
 116         struct mmc_omap_host    *host;
 117         struct mmc_host         *mmc;
 118         struct omap_mmc_slot_data *pdata;
 119 };
 120
 121 struct mmc_omap_host {
 122         int                     initialized;
 123         int                     suspended;
 124         struct mmc_request *    mrq;
 125         struct mmc_command *    cmd;
 126         struct mmc_data *       data;
 127         struct mmc_host *       mmc;
 128         struct device *         dev;
 129         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 130         struct clk *            iclk;
 131         struct clk *            fclk;
 132         struct resource         *mem_res;
 133         void __iomem            *virt_base;
 134         unsigned int            phys_base;
 135         int                     irq;
 136         unsigned char           bus_mode;
 137         unsigned char           hw_bus_mode;
 138
 139         struct work_struct      cmd_abort_work;
 140         unsigned                abort:1;
 141         struct timer_list       cmd_abort_timer;
 142
 143         unsigned int            sg_len;
 144         int                     sg_idx;
 145         u16 *                   buffer;
 146         u32                     buffer_bytes_left;
 147         u32                     total_bytes_left;
 148
 149         unsigned                use_dma:1;
 150         unsigned                brs_received:1, dma_done:1;
 151         unsigned                dma_is_read:1;
 152         unsigned                dma_in_use:1;
 153         int                     dma_ch;
 154         spinlock_t              dma_lock;
 155         struct timer_list       dma_timer;
 156         unsigned                dma_len;
 157
 158         short                   power_pin;
 159
 160         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 161         struct mmc_omap_slot    *current_slot;
 162         spinlock_t              slot_lock;
 163         wait_queue_head_t       slot_wq;
 164         int                     nr_slots;
 165
 166         struct omap_mmc_platform_data *pdata;
 167 };
 168
 169 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 170 {
 171         struct mmc_omap_host *host = slot->host;
 172         unsigned long flags;
 173
 174         if (claimed)
 175                 goto no_claim;
 176         spin_lock_irqsave(&host->slot_lock, flags);
 177         while (host->mmc != NULL) {
 178                 spin_unlock_irqrestore(&host->slot_lock, flags);
 179                 wait_event(host->slot_wq, host->mmc == NULL);
 180                 spin_lock_irqsave(&host->slot_lock, flags);
 181         }
 182         host->mmc = slot->mmc;
 183         spin_unlock_irqrestore(&host->slot_lock, flags);
 184 no_claim:
 185         clk_enable(host->fclk);
 186         if (host->current_slot != slot) {
 187                 if (host->pdata->switch_slot != NULL)
 188                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 189                 host->current_slot = slot;
 190         }
 191
 192         /* Doing the dummy read here seems to work around some bug
 193          * at least in OMAP24xx silicon where the command would not
 194          * start after writing the CMD register. Sigh. */
 195         OMAP_MMC_READ(host, CON);
 196
 197         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 198 }
 199
 200 static void mmc_omap_start_request(struct mmc_omap_host *host,
 201                                    struct mmc_request *req);
 202
 203 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 204 {
 205         struct mmc_omap_host *host = slot->host;
 206         unsigned long flags;
 207         int i;
 208
 209         BUG_ON(slot == NULL || host->mmc == NULL);
 210         clk_disable(host->fclk);
 211
 212         spin_lock_irqsave(&host->slot_lock, flags);
 213         /* Check for any pending requests */
 214         for (i = 0; i < host->nr_slots; i++) {
 215                 struct mmc_omap_slot *new_slot;
 216                 struct mmc_request *rq;
 217
 218                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 219                         continue;
 220
 221                 new_slot = host->slots[i];
 222                 /* The current slot should not have a request in queue */
 223                 BUG_ON(new_slot == host->current_slot);
 224
 225                 host->mmc = new_slot->mmc;
 226                 spin_unlock_irqrestore(&host->slot_lock, flags);
 227                 mmc_omap_select_slot(new_slot, 1);
 228                 rq = new_slot->mrq;
 229                 new_slot->mrq = NULL;
 230                 mmc_omap_start_request(host, rq);
 231                 return;
 232         }
 233
 234         host->mmc = NULL;
 235         wake_up(&host->slot_wq);
 236         spin_unlock_irqrestore(&host->slot_lock, flags);
 237 }
 238
 239 static inline
 240 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 241 {
 242         if (slot->pdata->get_cover_state)
 243                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
 244         return 0;
 245 }
 246
 247 static ssize_t
 248 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 249                            char *buf)
 250 {
 251         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 252         struct mmc_omap_slot *slot = mmc_priv(mmc);
 253
 254         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 255                        "closed");
 256 }
 257
 258 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 259
 260 /* Access to the R/O switch is required for production testing
 261  * purposes. */
 262 static ssize_t
 263 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
 264 {
 265         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 266         struct mmc_omap_slot *slot = mmc_priv(mmc);
 267
 268         return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
 269                                                         slot->id));
 270 }
 271
 272 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
 273
 274 static ssize_t
 275 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 276                         char *buf)
 277 {
 278         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 279         struct mmc_omap_slot *slot = mmc_priv(mmc);
 280
 281         return sprintf(buf, "%s\n", slot->pdata->name);
 282 }
 283
 284 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 285
 286 static void
 287 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 288 {
 289         u32 cmdreg;
 290         u32 resptype;
 291         u32 cmdtype;
 292
 293         host->cmd = cmd;
 294
 295         resptype = 0;
 296         cmdtype = 0;
 297
 298         /* Our hardware needs to know exact type */
 299         switch (mmc_resp_type(cmd)) {
 300         case MMC_RSP_NONE:
 301                 break;
 302         case MMC_RSP_R1:
 303         case MMC_RSP_R1B:
 304                 /* resp 1, 1b, 6, 7 */
 305                 resptype = 1;
 306                 break;
 307         case MMC_RSP_R2:
 308                 resptype = 2;
 309                 break;
 310         case MMC_RSP_R3:
 311                 resptype = 3;
 312                 break;
 313         default:
 314                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 315                 break;
 316         }
 317
 318         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 319                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 320         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 321                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 322         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 323                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 324         } else {
 325                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 326         }
 327
 328         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 329
 330         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 331                 cmdreg |= 1 << 6;
 332
 333         if (cmd->flags & MMC_RSP_BUSY)
 334                 cmdreg |= 1 << 11;
 335
 336         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 337                 cmdreg |= 1 << 15;
 338
 339         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 340
 341         OMAP_MMC_WRITE(host, CTO, 200);
 342         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 343         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 344         OMAP_MMC_WRITE(host, IE,
 345                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 346                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 347                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 348                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 349                        OMAP_MMC_STAT_END_OF_DATA);
 350         OMAP_MMC_WRITE(host, CMD, cmdreg);
 351 }
 352
 353 static void
 354 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 355                      int abort)
 356 {
 357         enum dma_data_direction dma_data_dir;
 358
 359         BUG_ON(host->dma_ch < 0);
 360         if (data->error)
 361                 omap_stop_dma(host->dma_ch);
 362         /* Release DMA channel lazily */
 363         mod_timer(&host->dma_timer, jiffies + HZ);
 364         if (data->flags & MMC_DATA_WRITE)
 365                 dma_data_dir = DMA_TO_DEVICE;
 366         else
 367                 dma_data_dir = DMA_FROM_DEVICE;
 368         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 369                      dma_data_dir);
 370 }
 371
 372 static void
 373 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 374 {
 375         if (host->dma_in_use)
 376                 mmc_omap_release_dma(host, data, data->error);
 377
 378         host->data = NULL;
 379         host->sg_len = 0;
 380
 381         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 382          * dozens of requests until the card finishes writing data.
 383          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 384          */
 385
 386         if (!data->stop) {
 387                 struct mmc_host *mmc;
 388
 389                 host->mrq = NULL;
 390                 mmc = host->mmc;
 391                 mmc_omap_release_slot(host->current_slot);
 392                 mmc_request_done(mmc, data->mrq);
 393                 return;
 394         }
 395
 396         mmc_omap_start_command(host, data->stop);
 397 }
 398
 399 static void
 400 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 401 {
 402         struct mmc_omap_slot *slot = host->current_slot;
 403         unsigned int restarts, passes, timeout;
 404         u16 stat = 0;
 405
 406         /* Sending abort takes 80 clocks. Have some extra and round up */
 407         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 408         restarts = 0;
 409         while (restarts < maxloops) {
 410                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 411                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 412
 413                 passes = 0;
 414                 while (passes < timeout) {
 415                         stat = OMAP_MMC_READ(host, STAT);
 416                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 417                                 goto out;
 418                         udelay(1);
 419                         passes++;
 420                 }
 421
 422                 restarts++;
 423         }
 424 out:
 425         OMAP_MMC_WRITE(host, STAT, stat);
 426 }
 427
 428 static void
 429 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 430 {
 431         if (host->dma_in_use)
 432                 mmc_omap_release_dma(host, data, 1);
 433
 434         host->data = NULL;
 435         host->sg_len = 0;
 436
 437         mmc_omap_send_abort(host, 10000);
 438 }
 439
 440 static void
 441 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 442 {
 443         unsigned long flags;
 444         int done;
 445
 446         if (!host->dma_in_use) {
 447                 mmc_omap_xfer_done(host, data);
 448                 return;
 449         }
 450         done = 0;
 451         spin_lock_irqsave(&host->dma_lock, flags);
 452         if (host->dma_done)
 453                 done = 1;
 454         else
 455                 host->brs_received = 1;
 456         spin_unlock_irqrestore(&host->dma_lock, flags);
 457         if (done)
 458                 mmc_omap_xfer_done(host, data);
 459 }
 460
 461 static void
 462 mmc_omap_dma_timer(unsigned long data)
 463 {
 464         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 465
 466         BUG_ON(host->dma_ch < 0);
 467         omap_free_dma(host->dma_ch);
 468         host->dma_ch = -1;
 469 }
 470
 471 static void
 472 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 473 {
 474         unsigned long flags;
 475         int done;
 476
 477         done = 0;
 478         spin_lock_irqsave(&host->dma_lock, flags);
 479         if (host->brs_received)
 480                 done = 1;
 481         else
 482                 host->dma_done = 1;
 483         spin_unlock_irqrestore(&host->dma_lock, flags);
 484         if (done)
 485                 mmc_omap_xfer_done(host, data);
 486 }
 487
 488 static void
 489 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 490 {
 491         host->cmd = NULL;
 492
 493         del_timer(&host->cmd_abort_timer);
 494
 495         if (cmd->flags & MMC_RSP_PRESENT) {
 496                 if (cmd->flags & MMC_RSP_136) {
 497                         /* response type 2 */
 498                         cmd->resp[3] =
 499                                 OMAP_MMC_READ(host, RSP0) |
 500                                 (OMAP_MMC_READ(host, RSP1) << 16);
 501                         cmd->resp[2] =
 502                                 OMAP_MMC_READ(host, RSP2) |
 503                                 (OMAP_MMC_READ(host, RSP3) << 16);
 504                         cmd->resp[1] =
 505                                 OMAP_MMC_READ(host, RSP4) |
 506                                 (OMAP_MMC_READ(host, RSP5) << 16);
 507                         cmd->resp[0] =
 508                                 OMAP_MMC_READ(host, RSP6) |
 509                                 (OMAP_MMC_READ(host, RSP7) << 16);
 510                 } else {
 511                         /* response types 1, 1b, 3, 4, 5, 6 */
 512                         cmd->resp[0] =
 513                                 OMAP_MMC_READ(host, RSP6) |
 514                                 (OMAP_MMC_READ(host, RSP7) << 16);
 515                 }
 516         }
 517
 518         if (host->data == NULL || cmd->error) {
 519                 struct mmc_host *mmc;
 520
 521                 if (host->data != NULL)
 522                         mmc_omap_abort_xfer(host, host->data);
 523                 host->mrq = NULL;
 524                 mmc = host->mmc;
 525                 mmc_omap_release_slot(host->current_slot);
 526                 mmc_request_done(mmc, cmd->mrq);
 527         }
 528 }
 529
 530 /*
 531  * Abort stuck command. Can occur when card is removed while it is being
 532  * read.
 533  */
 534 static void mmc_omap_abort_command(struct work_struct *work)
 535 {
 536         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 537                                                   cmd_abort_work);
 538         BUG_ON(!host->cmd);
 539
 540         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 541                 host->cmd->opcode);
 542
 543         if (host->cmd->error == 0)
 544                 host->cmd->error = -ETIMEDOUT;
 545
 546         if (host->data == NULL) {
 547                 struct mmc_command *cmd;
 548                 struct mmc_host    *mmc;
 549
 550                 cmd = host->cmd;
 551                 host->cmd = NULL;
 552                 mmc_omap_send_abort(host, 10000);
 553
 554                 host->mrq = NULL;
 555                 mmc = host->mmc;
 556                 mmc_omap_release_slot(host->current_slot);
 557                 mmc_request_done(mmc, cmd->mrq);
 558         } else
 559                 mmc_omap_cmd_done(host, host->cmd);
 560
 561         host->abort = 0;
 562         enable_irq(host->irq);
 563 }
 564
 565 static void
 566 mmc_omap_cmd_timer(unsigned long data)
 567 {
 568         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 569         unsigned long flags;
 570
 571         spin_lock_irqsave(&host->slot_lock, flags);
 572         if (host->cmd != NULL && !host->abort) {
 573                 OMAP_MMC_WRITE(host, IE, 0);
 574                 disable_irq(host->irq);
 575                 host->abort = 1;
 576                 schedule_work(&host->cmd_abort_work);
 577         }
 578         spin_unlock_irqrestore(&host->slot_lock, flags);
 579 }
 580
 581 /* PIO only */
 582 static void
 583 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 584 {
 585         struct scatterlist *sg;
 586
 587         sg = host->data->sg + host->sg_idx;
 588         host->buffer_bytes_left = sg->length;
 589         host->buffer = sg_virt(sg);
 590         if (host->buffer_bytes_left > host->total_bytes_left)
 591                 host->buffer_bytes_left = host->total_bytes_left;
 592 }
 593
 594 /* PIO only */
 595 static void
 596 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 597 {
 598         int n;
 599
 600         if (host->buffer_bytes_left == 0) {
 601                 host->sg_idx++;
 602                 BUG_ON(host->sg_idx == host->sg_len);
 603                 mmc_omap_sg_to_buf(host);
 604         }
 605         n = 64;
 606         if (n > host->buffer_bytes_left)
 607                 n = host->buffer_bytes_left;
 608         host->buffer_bytes_left -= n;
 609         host->total_bytes_left -= n;
 610         host->data->bytes_xfered += n;
 611
 612         if (write) {
 613                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 614         } else {
 615                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 616         }
 617 }
 618
 619 static inline void mmc_omap_report_irq(u16 status)
 620 {
 621         static const char *mmc_omap_status_bits[] = {
 622                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 623                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 624         };
 625         int i, c = 0;
 626
 627         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 628                 if (status & (1 << i)) {
 629                         if (c)
 630                                 printk(" ");
 631                         printk("%s", mmc_omap_status_bits[i]);
 632                         c++;
 633                 }
 634 }
 635
 636 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 637 {
 638         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 639         u16 status;
 640         int end_command;
 641         int end_transfer;
 642         int transfer_error, cmd_error;
 643
 644         if (host->cmd == NULL && host->data == NULL) {
 645                 status = OMAP_MMC_READ(host, STAT);
 646                 dev_info(mmc_dev(host->slots[0]->mmc),
 647                          "Spurious IRQ 0x%04x\n", status);
 648                 if (status != 0) {
 649                         OMAP_MMC_WRITE(host, STAT, status);
 650                         OMAP_MMC_WRITE(host, IE, 0);
 651                 }
 652                 return IRQ_HANDLED;
 653         }
 654
 655         end_command = 0;
 656         end_transfer = 0;
 657         transfer_error = 0;
 658         cmd_error = 0;
 659
 660         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 661                 int cmd;
 662
 663                 OMAP_MMC_WRITE(host, STAT, status);
 664                 if (host->cmd != NULL)
 665                         cmd = host->cmd->opcode;
 666                 else
 667                         cmd = -1;
 668 #ifdef CONFIG_MMC_DEBUG
 669                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 670                         status, cmd);
 671                 mmc_omap_report_irq(status);
 672                 printk("\n");
 673 #endif
 674                 if (host->total_bytes_left) {
 675                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 676                             (status & OMAP_MMC_STAT_END_OF_DATA))
 677                                 mmc_omap_xfer_data(host, 0);
 678                         if (status & OMAP_MMC_STAT_A_EMPTY)
 679                                 mmc_omap_xfer_data(host, 1);
 680                 }
 681
 682                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 683                         end_transfer = 1;
 684
 685                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 686                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 687                                 cmd);
 688                         if (host->data) {
 689                                 host->data->error = -ETIMEDOUT;
 690                                 transfer_error = 1;
 691                         }
 692                 }
 693
 694                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 695                         if (host->data) {
 696                                 host->data->error = -EILSEQ;
 697                                 dev_dbg(mmc_dev(host->mmc),
 698                                          "data CRC error, bytes left %d\n",
 699                                         host->total_bytes_left);
 700                                 transfer_error = 1;
 701                         } else {
 702                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 703                         }
 704                 }
 705
 706                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 707                         /* Timeouts are routine with some commands */
 708                         if (host->cmd) {
 709                                 struct mmc_omap_slot *slot =
 710                                         host->current_slot;
 711                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 712                                     host->cmd->opcode != MMC_SEND_OP_COND &&
 713                                     host->cmd->opcode != MMC_APP_CMD &&
 714                                     (slot == NULL ||
 715                                      !mmc_omap_cover_is_open(slot)))
 716                                         dev_err(mmc_dev(host->mmc),
 717                                                 "command timeout (CMD%d)\n",
 718                                                 cmd);
 719                                 host->cmd->error = -ETIMEDOUT;
 720                                 end_command = 1;
 721                                 cmd_error = 1;
 722                         }
 723                 }
 724
 725                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 726                         if (host->cmd) {
 727                                 dev_err(mmc_dev(host->mmc),
 728                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 729                                         cmd, host->cmd->arg);
 730                                 host->cmd->error = -EILSEQ;
 731                                 end_command = 1;
 732                                 cmd_error = 1;
 733                         } else
 734                                 dev_err(mmc_dev(host->mmc),
 735                                         "command CRC error without cmd?\n");
 736                 }
 737
 738                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 739                         dev_dbg(mmc_dev(host->mmc),
 740                                 "ignoring card status error (CMD%d)\n",
 741                                 cmd);
 742                         end_command = 1;
 743                 }
 744
 745                 /*
 746                  * NOTE: On 1610 the END_OF_CMD may come too early when
 747                  * starting a write
 748                  */
 749                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 750                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 751                         end_command = 1;
 752                 }
 753         }
 754
 755         if (cmd_error && host->data) {
 756                 del_timer(&host->cmd_abort_timer);
 757                 host->abort = 1;
 758                 OMAP_MMC_WRITE(host, IE, 0);
 759                 disable_irq(host->irq);
 760                 schedule_work(&host->cmd_abort_work);
 761                 return IRQ_HANDLED;
 762         }
 763
 764         if (end_command)
 765                 mmc_omap_cmd_done(host, host->cmd);
 766         if (host->data != NULL) {
 767                 if (transfer_error)
 768                         mmc_omap_xfer_done(host, host->data);
 769                 else if (end_transfer)
 770                         mmc_omap_end_of_data(host, host->data);
 771         }
 772
 773         return IRQ_HANDLED;
 774 }
 775
 776 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 777 {
 778         int cover_open;
 779         struct mmc_omap_host *host = dev_get_drvdata(dev);
 780         struct mmc_omap_slot *slot = host->slots[num];
 781
 782         BUG_ON(num >= host->nr_slots);
 783
 784         /* Other subsystems can call in here before we're initialised. */
 785         if (host->nr_slots == 0 || !host->slots[num])
 786                 return;
 787
 788         cover_open = mmc_omap_cover_is_open(slot);
 789         if (cover_open != slot->cover_open) {
 790                 slot->cover_open = cover_open;
 791                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 792         }
 793
 794         tasklet_hi_schedule(&slot->cover_tasklet);
 795 }
 796
 797 static void mmc_omap_cover_timer(unsigned long arg)
 798 {
 799         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 800         tasklet_schedule(&slot->cover_tasklet);
 801 }
 802
 803 static void mmc_omap_cover_handler(unsigned long param)
 804 {
 805         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 806         int cover_open = mmc_omap_cover_is_open(slot);
 807
 808         mmc_detect_change(slot->mmc, 0);
 809         if (!cover_open)
 810                 return;
 811
 812         /*
 813          * If no card is inserted, we postpone polling until
 814          * the cover has been closed.
 815          */
 816         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 817                 return;
 818
 819         mod_timer(&slot->cover_timer,
 820                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 821 }
 822
 823 /* Prepare to transfer the next segment of a scatterlist */
 824 static void
 825 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 826 {
 827         int dma_ch = host->dma_ch;
 828         unsigned long data_addr;
 829         u16 buf, frame;
 830         u32 count;
 831         struct scatterlist *sg = &data->sg[host->sg_idx];
 832         int src_port = 0;
 833         int dst_port = 0;
 834         int sync_dev = 0;
 835
 836         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 837         frame = data->blksz;
 838         count = sg_dma_len(sg);
 839
 840         if ((data->blocks == 1) && (count > data->blksz))
 841                 count = frame;
 842
 843         host->dma_len = count;
 844
 845         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 846          * Use 16 or 32 word frames when the blocksize is at least that large.
 847          * Blocksize is usually 512 bytes; but not for some SD reads.
 848          */
 849         if (cpu_is_omap15xx() && frame > 32)
 850                 frame = 32;
 851         else if (frame > 64)
 852                 frame = 64;
 853         count /= frame;
 854         frame >>= 1;
 855
 856         if (!(data->flags & MMC_DATA_WRITE)) {
 857                 buf = 0x800f | ((frame - 1) << 8);
 858
 859                 if (cpu_class_is_omap1()) {
 860                         src_port = OMAP_DMA_PORT_TIPB;
 861                         dst_port = OMAP_DMA_PORT_EMIFF;
 862                 }
 863                 if (cpu_is_omap24xx())
 864                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 865
 866                 omap_set_dma_src_params(dma_ch, src_port,
 867                                         OMAP_DMA_AMODE_CONSTANT,
 868                                         data_addr, 0, 0);
 869                 omap_set_dma_dest_params(dma_ch, dst_port,
 870                                          OMAP_DMA_AMODE_POST_INC,
 871                                          sg_dma_address(sg), 0, 0);
 872                 omap_set_dma_dest_data_pack(dma_ch, 1);
 873                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 874         } else {
 875                 buf = 0x0f80 | ((frame - 1) << 0);
 876
 877                 if (cpu_class_is_omap1()) {
 878                         src_port = OMAP_DMA_PORT_EMIFF;
 879                         dst_port = OMAP_DMA_PORT_TIPB;
 880                 }
 881                 if (cpu_is_omap24xx())
 882                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 883
 884                 omap_set_dma_dest_params(dma_ch, dst_port,
 885                                          OMAP_DMA_AMODE_CONSTANT,
 886                                          data_addr, 0, 0);
 887                 omap_set_dma_src_params(dma_ch, src_port,
 888                                         OMAP_DMA_AMODE_POST_INC,
 889                                         sg_dma_address(sg), 0, 0);
 890                 omap_set_dma_src_data_pack(dma_ch, 1);
 891                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 892         }
 893
 894         /* Max limit for DMA frame count is 0xffff */
 895         BUG_ON(count > 0xffff);
 896
 897         OMAP_MMC_WRITE(host, BUF, buf);
 898         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 899                                      frame, count, OMAP_DMA_SYNC_FRAME,
 900                                      sync_dev, 0);
 901 }
 902
 903 /* A scatterlist segment completed */
 904 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 905 {
 906         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 907         struct mmc_data *mmcdat = host->data;
 908
 909         if (unlikely(host->dma_ch < 0)) {
 910                 dev_err(mmc_dev(host->mmc),
 911                         "DMA callback while DMA not enabled\n");
 912                 return;
 913         }
 914         /* FIXME: We really should do something to _handle_ the errors */
 915         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 916                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 917                 return;
 918         }
 919         if (ch_status & OMAP_DMA_DROP_IRQ) {
 920                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 921                 return;
 922         }
 923         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 924                 return;
 925         }
 926         mmcdat->bytes_xfered += host->dma_len;
 927         host->sg_idx++;
 928         if (host->sg_idx < host->sg_len) {
 929                 mmc_omap_prepare_dma(host, host->data);
 930                 omap_start_dma(host->dma_ch);
 931         } else
 932                 mmc_omap_dma_done(host, host->data);
 933 }
 934
 935 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 936 {
 937         const char *dev_name;
 938         int sync_dev, dma_ch, is_read, r;
 939
 940         is_read = !(data->flags & MMC_DATA_WRITE);
 941         del_timer_sync(&host->dma_timer);
 942         if (host->dma_ch >= 0) {
 943                 if (is_read == host->dma_is_read)
 944                         return 0;
 945                 omap_free_dma(host->dma_ch);
 946                 host->dma_ch = -1;
 947         }
 948
 949         if (is_read) {
 950                 if (host->id == 1) {
 951                         sync_dev = OMAP_DMA_MMC_RX;
 952                         dev_name = "MMC1 read";
 953                 } else {
 954                         sync_dev = OMAP_DMA_MMC2_RX;
 955                         dev_name = "MMC2 read";
 956                 }
 957         } else {
 958                 if (host->id == 1) {
 959                         sync_dev = OMAP_DMA_MMC_TX;
 960                         dev_name = "MMC1 write";
 961                 } else {
 962                         sync_dev = OMAP_DMA_MMC2_TX;
 963                         dev_name = "MMC2 write";
 964                 }
 965         }
 966         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 967                              host, &dma_ch);
 968         if (r != 0) {
 969                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 970                 return r;
 971         }
 972         host->dma_ch = dma_ch;
 973         host->dma_is_read = is_read;
 974
 975         return 0;
 976 }
 977
 978 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 979 {
 980         u16 reg;
 981
 982         reg = OMAP_MMC_READ(host, SDIO);
 983         reg &= ~(1 << 5);
 984         OMAP_MMC_WRITE(host, SDIO, reg);
 985         /* Set maximum timeout */
 986         OMAP_MMC_WRITE(host, CTO, 0xff);
 987 }
 988
 989 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 990 {
 991         unsigned int timeout, cycle_ns;
 992         u16 reg;
 993
 994         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 995         timeout = req->data->timeout_ns / cycle_ns;
 996         timeout += req->data->timeout_clks;
 997
 998         /* Check if we need to use timeout multiplier register */
 999         reg = OMAP_MMC_READ(host, SDIO);
1000         if (timeout > 0xffff) {
1001                 reg |= (1 << 5);
1002                 timeout /= 1024;
1003         } else
1004                 reg &= ~(1 << 5);
1005         OMAP_MMC_WRITE(host, SDIO, reg);
1006         OMAP_MMC_WRITE(host, DTO, timeout);
1007 }
1008
1009 static void
1010 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
1011 {
1012         struct mmc_data *data = req->data;
1013         int i, use_dma, block_size;
1014         unsigned sg_len;
1015
1016         host->data = data;
1017         if (data == NULL) {
1018                 OMAP_MMC_WRITE(host, BLEN, 0);
1019                 OMAP_MMC_WRITE(host, NBLK, 0);
1020                 OMAP_MMC_WRITE(host, BUF, 0);
1021                 host->dma_in_use = 0;
1022                 set_cmd_timeout(host, req);
1023                 return;
1024         }
1025
1026         block_size = data->blksz;
1027
1028         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1029         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1030         set_data_timeout(host, req);
1031
1032         /* cope with calling layer confusion; it issues "single
1033          * block" writes using multi-block scatterlists.
1034          */
1035         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1036
1037         /* Only do DMA for entire blocks */
1038         use_dma = host->use_dma;
1039         if (use_dma) {
1040                 for (i = 0; i < sg_len; i++) {
1041                         if ((data->sg[i].length % block_size) != 0) {
1042                                 use_dma = 0;
1043                                 break;
1044                         }
1045                 }
1046         }
1047
1048         host->sg_idx = 0;
1049         if (use_dma) {
1050                 if (mmc_omap_get_dma_channel(host, data) == 0) {
1051                         enum dma_data_direction dma_data_dir;
1052
1053                         if (data->flags & MMC_DATA_WRITE)
1054                                 dma_data_dir = DMA_TO_DEVICE;
1055                         else
1056                                 dma_data_dir = DMA_FROM_DEVICE;
1057
1058                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1059                                                 sg_len, dma_data_dir);
1060                         host->total_bytes_left = 0;
1061                         mmc_omap_prepare_dma(host, req->data);
1062                         host->brs_received = 0;
1063                         host->dma_done = 0;
1064                         host->dma_in_use = 1;
1065                 } else
1066                         use_dma = 0;
1067         }
1068
1069         /* Revert to PIO? */
1070         if (!use_dma) {
1071                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1072                 host->total_bytes_left = data->blocks * block_size;
1073                 host->sg_len = sg_len;
1074                 mmc_omap_sg_to_buf(host);
1075                 host->dma_in_use = 0;
1076         }
1077 }
1078
1079 static void mmc_omap_start_request(struct mmc_omap_host *host,
1080                                    struct mmc_request *req)
1081 {
1082         BUG_ON(host->mrq != NULL);
1083
1084         host->mrq = req;
1085
1086         /* only touch fifo AFTER the controller readies it */
1087         mmc_omap_prepare_data(host, req);
1088         mmc_omap_start_command(host, req->cmd);
1089         if (host->dma_in_use)
1090                 omap_start_dma(host->dma_ch);
1091         BUG_ON(irqs_disabled());
1092 }
1093
1094 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1095 {
1096         struct mmc_omap_slot *slot = mmc_priv(mmc);
1097         struct mmc_omap_host *host = slot->host;
1098         unsigned long flags;
1099
1100         spin_lock_irqsave(&host->slot_lock, flags);
1101         if (host->mmc != NULL) {
1102                 BUG_ON(slot->mrq != NULL);
1103                 slot->mrq = req;
1104                 spin_unlock_irqrestore(&host->slot_lock, flags);
1105                 return;
1106         } else
1107                 host->mmc = mmc;
1108         spin_unlock_irqrestore(&host->slot_lock, flags);
1109         mmc_omap_select_slot(slot, 1);
1110         mmc_omap_start_request(host, req);
1111 }
1112
1113 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1114                                 int vdd)
1115 {
1116         struct mmc_omap_host *host;
1117
1118         host = slot->host;
1119
1120         if (slot->pdata->set_power != NULL)
1121                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1122                                         vdd);
1123
1124         if (cpu_is_omap24xx()) {
1125                 u16 w;
1126
1127                 if (power_on) {
1128                         w = OMAP_MMC_READ(host, CON);
1129                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1130                 } else {
1131                         w = OMAP_MMC_READ(host, CON);
1132                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1133                 }
1134         }
1135 }
1136
1137 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1138 {
1139         struct mmc_omap_slot *slot = mmc_priv(mmc);
1140         struct mmc_omap_host *host = slot->host;
1141         int func_clk_rate = clk_get_rate(host->fclk);
1142         int dsor;
1143
1144         if (ios->clock == 0)
1145                 return 0;
1146
1147         dsor = func_clk_rate / ios->clock;
1148         if (dsor < 1)
1149                 dsor = 1;
1150
1151         if (func_clk_rate / dsor > ios->clock)
1152                 dsor++;
1153
1154         if (dsor > 250)
1155                 dsor = 250;
1156
1157         slot->fclk_freq = func_clk_rate / dsor;
1158
1159         if (ios->bus_width == MMC_BUS_WIDTH_4)
1160                 dsor |= 1 << 15;
1161
1162         return dsor;
1163 }
1164
1165 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1166 {
1167         struct mmc_omap_slot *slot = mmc_priv(mmc);
1168         struct mmc_omap_host *host = slot->host;
1169         int i, dsor;
1170
1171         dsor = mmc_omap_calc_divisor(mmc, ios);
1172
1173         mmc_omap_select_slot(slot, 0);
1174
1175         if (ios->vdd != slot->vdd)
1176                 slot->vdd = ios->vdd;
1177
1178         switch (ios->power_mode) {
1179         case MMC_POWER_OFF:
1180                 mmc_omap_set_power(slot, 0, ios->vdd);
1181                 break;
1182         case MMC_POWER_UP:
1183                 /* Cannot touch dsor yet, just power up MMC */
1184                 mmc_omap_set_power(slot, 1, ios->vdd);
1185                 goto exit;
1186         case MMC_POWER_ON:
1187                 dsor |= 1 << 11;
1188                 break;
1189         }
1190
1191         if (slot->bus_mode != ios->bus_mode) {
1192                 if (slot->pdata->set_bus_mode != NULL)
1193                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1194                                                   ios->bus_mode);
1195                 slot->bus_mode = ios->bus_mode;
1196         }
1197
1198         /* On insanely high arm_per frequencies something sometimes
1199          * goes somehow out of sync, and the POW bit is not being set,
1200          * which results in the while loop below getting stuck.
1201          * Writing to the CON register twice seems to do the trick. */
1202         for (i = 0; i < 2; i++)
1203                 OMAP_MMC_WRITE(host, CON, dsor);
1204         slot->saved_con = dsor;
1205         if (ios->power_mode == MMC_POWER_ON) {
1206                 /* Send clock cycles, poll completion */
1207                 OMAP_MMC_WRITE(host, IE, 0);
1208                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1209                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1210                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1211                 OMAP_MMC_WRITE(host, STAT, 1);
1212         }
1213
1214 exit:
1215         mmc_omap_release_slot(slot);
1216 }
1217
1218 static int mmc_omap_get_ro(struct mmc_host *mmc)
1219 {
1220         struct mmc_omap_slot *slot = mmc_priv(mmc);
1221
1222         if (slot->pdata->get_ro != NULL)
1223                 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1224         return 0;
1225 }
1226
1227 static const struct mmc_host_ops mmc_omap_ops = {
1228         .request        = mmc_omap_request,
1229         .set_ios        = mmc_omap_set_ios,
1230         .get_ro         = mmc_omap_get_ro,
1231 };
1232
1233 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1234 {
1235         struct mmc_omap_slot *slot = NULL;
1236         struct mmc_host *mmc;
1237         int r;
1238
1239         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1240         if (mmc == NULL)
1241                 return -ENOMEM;
1242
1243         slot = mmc_priv(mmc);
1244         slot->host = host;
1245         slot->mmc = mmc;
1246         slot->id = id;
1247         slot->pdata = &host->pdata->slots[id];
1248
1249         host->slots[id] = slot;
1250
1251         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1252                     MMC_CAP_SD_HIGHSPEED;
1253         if (host->pdata->conf.wire4)
1254                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1255
1256         mmc->ops = &mmc_omap_ops;
1257         mmc->f_min = 400000;
1258
1259         if (cpu_class_is_omap2())
1260                 mmc->f_max = 48000000;
1261         else
1262                 mmc->f_max = 24000000;
1263         if (host->pdata->max_freq)
1264                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1265         mmc->ocr_avail = slot->pdata->ocr_mask;
1266
1267         /* Use scatterlist DMA to reduce per-transfer costs.
1268          * NOTE max_seg_size assumption that small blocks aren't
1269          * normally used (except e.g. for reading SD registers).
1270          */
1271         mmc->max_phys_segs = 32;
1272         mmc->max_hw_segs = 32;
1273         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1274         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1275         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1276         mmc->max_seg_size = mmc->max_req_size;
1277
1278         r = mmc_add_host(mmc);
1279         if (r < 0)
1280                 return r;
1281
1282         if (slot->pdata->name != NULL) {
1283                 r = device_create_file(&mmc->class_dev,
1284                                         &dev_attr_slot_name);
1285                 if (r < 0)
1286                         goto err_remove_host;
1287         }
1288
1289         if (slot->pdata->get_cover_state != NULL) {
1290                 r = device_create_file(&mmc->class_dev,
1291                                         &dev_attr_cover_switch);
1292                 if (r < 0)
1293                         goto err_remove_slot_name;
1294
1295                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1296                             (unsigned long)slot);
1297                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1298                              (unsigned long)slot);
1299                 tasklet_schedule(&slot->cover_tasklet);
1300         }
1301
1302         if (slot->pdata->get_ro != NULL) {
1303                 r = device_create_file(&mmc->class_dev,
1304                                         &dev_attr_ro);
1305                 if (r < 0)
1306                         goto err_remove_cover_attr;
1307         }
1308
1309         return 0;
1310
1311 err_remove_cover_attr:
1312         if (slot->pdata->get_cover_state != NULL)
1313                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1314 err_remove_slot_name:
1315         if (slot->pdata->name != NULL)
1316                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1317 err_remove_host:
1318         mmc_remove_host(mmc);
1319         return r;
1320 }
1321
1322 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1323 {
1324         struct mmc_host *mmc = slot->mmc;
1325
1326         if (slot->pdata->name != NULL)
1327                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1328         if (slot->pdata->get_cover_state != NULL)
1329                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1330         if (slot->pdata->get_ro != NULL)
1331                 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1332
1333         tasklet_kill(&slot->cover_tasklet);
1334         del_timer_sync(&slot->cover_timer);
1335         flush_scheduled_work();
1336
1337         mmc_remove_host(mmc);
1338         mmc_free_host(mmc);
1339 }
1340
1341 static int __init mmc_omap_probe(struct platform_device *pdev)
1342 {
1343         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1344         struct mmc_omap_host *host = NULL;
1345         struct resource *res;
1346         int i, ret = 0;
1347         int irq;
1348
1349         if (pdata == NULL) {
1350                 dev_err(&pdev->dev, "platform data missing\n");
1351                 return -ENXIO;
1352         }
1353         if (pdata->nr_slots == 0) {
1354                 dev_err(&pdev->dev, "no slots\n");
1355                 return -ENXIO;
1356         }
1357
1358         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1359         irq = platform_get_irq(pdev, 0);
1360         if (res == NULL || irq < 0)
1361                 return -ENXIO;
1362
1363         res = request_mem_region(res->start, res->end - res->start + 1,
1364                                  pdev->name);
1365         if (res == NULL)
1366                 return -EBUSY;
1367
1368         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1369         if (host == NULL) {
1370                 ret = -ENOMEM;
1371                 goto err_free_mem_region;
1372         }
1373
1374         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1375         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1376                     (unsigned long) host);
1377
1378         spin_lock_init(&host->dma_lock);
1379         setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1380         spin_lock_init(&host->slot_lock);
1381         init_waitqueue_head(&host->slot_wq);
1382
1383         host->pdata = pdata;
1384         host->dev = &pdev->dev;
1385         platform_set_drvdata(pdev, host);
1386
1387         host->id = pdev->id;
1388         host->mem_res = res;
1389         host->irq = irq;
1390
1391         host->use_dma = 1;
1392         host->dma_ch = -1;
1393
1394         host->irq = irq;
1395         host->phys_base = host->mem_res->start;
1396         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1397
1398         if (cpu_is_omap24xx()) {
1399                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1400                 if (IS_ERR(host->iclk))
1401                         goto err_free_mmc_host;
1402                 clk_enable(host->iclk);
1403         }
1404
1405         if (!cpu_is_omap24xx())
1406                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1407         else
1408                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1409
1410         if (IS_ERR(host->fclk)) {
1411                 ret = PTR_ERR(host->fclk);
1412                 goto err_free_iclk;
1413         }
1414
1415         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1416         if (ret)
1417                 goto err_free_fclk;
1418
1419         if (pdata->init != NULL) {
1420                 ret = pdata->init(&pdev->dev);
1421                 if (ret < 0)
1422                         goto err_free_irq;
1423         }
1424
1425         host->nr_slots = pdata->nr_slots;
1426         for (i = 0; i < pdata->nr_slots; i++) {
1427                 ret = mmc_omap_new_slot(host, i);
1428                 if (ret < 0) {
1429                         while (--i >= 0)
1430                                 mmc_omap_remove_slot(host->slots[i]);
1431
1432                         goto err_plat_cleanup;
1433                 }
1434         }
1435
1436         return 0;
1437
1438 err_plat_cleanup:
1439         if (pdata->cleanup)
1440                 pdata->cleanup(&pdev->dev);
1441 err_free_irq:
1442         free_irq(host->irq, host);
1443 err_free_fclk:
1444         clk_put(host->fclk);
1445 err_free_iclk:
1446         if (host->iclk != NULL) {
1447                 clk_disable(host->iclk);
1448                 clk_put(host->iclk);
1449         }
1450 err_free_mmc_host:
1451         kfree(host);
1452 err_free_mem_region:
1453         release_mem_region(res->start, res->end - res->start + 1);
1454         return ret;
1455 }
1456
1457 static int mmc_omap_remove(struct platform_device *pdev)
1458 {
1459         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1460         int i;
1461
1462         platform_set_drvdata(pdev, NULL);
1463
1464         BUG_ON(host == NULL);
1465
1466         for (i = 0; i < host->nr_slots; i++)
1467                 mmc_omap_remove_slot(host->slots[i]);
1468
1469         if (host->pdata->cleanup)
1470                 host->pdata->cleanup(&pdev->dev);
1471
1472         if (host->iclk && !IS_ERR(host->iclk))
1473                 clk_put(host->iclk);
1474         if (host->fclk && !IS_ERR(host->fclk))
1475                 clk_put(host->fclk);
1476
1477         release_mem_region(pdev->resource[0].start,
1478                            pdev->resource[0].end - pdev->resource[0].start + 1);
1479
1480         kfree(host);
1481
1482         return 0;
1483 }
1484
1485 #ifdef CONFIG_PM
1486 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1487 {
1488         int i, ret = 0;
1489         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1490
1491         if (host == NULL || host->suspended)
1492                 return 0;
1493
1494         for (i = 0; i < host->nr_slots; i++) {
1495                 struct mmc_omap_slot *slot;
1496
1497                 slot = host->slots[i];
1498                 ret = mmc_suspend_host(slot->mmc, mesg);
1499                 if (ret < 0) {
1500                         while (--i >= 0) {
1501                                 slot = host->slots[i];
1502                                 mmc_resume_host(slot->mmc);
1503                         }
1504                         return ret;
1505                 }
1506         }
1507         host->suspended = 1;
1508         return 0;
1509 }
1510
1511 static int mmc_omap_resume(struct platform_device *pdev)
1512 {
1513         int i, ret = 0;
1514         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1515
1516         if (host == NULL || !host->suspended)
1517                 return 0;
1518
1519         for (i = 0; i < host->nr_slots; i++) {
1520                 struct mmc_omap_slot *slot;
1521                 slot = host->slots[i];
1522                 ret = mmc_resume_host(slot->mmc);
1523                 if (ret < 0)
1524                         return ret;
1525
1526                 host->suspended = 0;
1527         }
1528         return 0;
1529 }
1530 #else
1531 #define mmc_omap_suspend        NULL
1532 #define mmc_omap_resume         NULL
1533 #endif
1534
1535 static struct platform_driver mmc_omap_driver = {
1536         .probe          = mmc_omap_probe,
1537         .remove         = mmc_omap_remove,
1538         .suspend        = mmc_omap_suspend,
1539         .resume         = mmc_omap_resume,
1540         .driver         = {
1541                 .name   = DRIVER_NAME,
1542         },
1543 };
1544
1545 static int __init mmc_omap_init(void)
1546 {
1547         return platform_driver_register(&mmc_omap_driver);
1548 }
1549
1550 static void __exit mmc_omap_exit(void)
1551 {
1552         platform_driver_unregister(&mmc_omap_driver);
1553 }
1554
1555 module_init(mmc_omap_init);
1556 module_exit(mmc_omap_exit);
1557
1558 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1559 MODULE_LICENSE("GPL");
1560 MODULE_ALIAS(DRIVER_NAME);
1561 MODULE_AUTHOR("Juha Yrjölä");