drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why is a timer used to detect insert events?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  *
  34  * So we use the timer to check the status manually.
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/mm.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/scatterlist.h>
  44 #include <linux/leds.h>
  45 #include <linux/mmc/host.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/mach-au1x00/au1000.h>
  49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  50 #include <asm/mach-au1x00/au1100_mmc.h>
  51
  52 #define DRIVER_NAME "au1xxx-mmc"
  53
  54 /* Set this to enable special debugging macros */
  55 /* #define DEBUG */
  56
  57 #ifdef DEBUG
  58 #define DBG(fmt, idx, args...)  \
  59         printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
  60 #else
  61 #define DBG(fmt, idx, args...) do {} while (0)
  62 #endif
  63
  64 /* Hardware definitions */
  65 #define AU1XMMC_DESCRIPTOR_COUNT 1
  66 #define AU1XMMC_DESCRIPTOR_SIZE  2048
  67
  68 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
  69                      MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
  70                      MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
  71
  72 /* This gives us a hard value for the stop command that we can write directly
  73  * to the command register.
  74  */
  75 #define STOP_CMD        \
  76         (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
  77
  78 /* This is the set of interrupts that we configure by default. */
  79 #define AU1XMMC_INTERRUPTS                              \
  80         (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT |  \
  81          SD_CONFIG_CR | SD_CONFIG_I)
  82
  83 /* The poll event (looking for insert/remove events runs twice a second. */
  84 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
  85
  86 struct au1xmmc_host {
  87         struct mmc_host *mmc;
  88         struct mmc_request *mrq;
  89
  90         u32 flags;
  91         u32 iobase;
  92         u32 clock;
  93         u32 bus_width;
  94         u32 power_mode;
  95
  96         int status;
  97
  98         struct {
  99                 int len;
 100                 int dir;
 101         } dma;
 102
 103         struct {
 104                 int index;
 105                 int offset;
 106                 int len;
 107         } pio;
 108
 109         u32 tx_chan;
 110         u32 rx_chan;
 111
 112         int irq;
 113
 114         struct timer_list timer;
 115         struct tasklet_struct finish_task;
 116         struct tasklet_struct data_task;
 117         struct au1xmmc_platform_data *platdata;
 118         struct platform_device *pdev;
 119         struct resource *ioarea;
 120 };
 121
 122 /* Status flags used by the host structure */
 123 #define HOST_F_XMIT     0x0001
 124 #define HOST_F_RECV     0x0002
 125 #define HOST_F_DMA      0x0010
 126 #define HOST_F_ACTIVE   0x0100
 127 #define HOST_F_STOP     0x1000
 128
 129 #define HOST_S_IDLE     0x0001
 130 #define HOST_S_CMD      0x0002
 131 #define HOST_S_DATA     0x0003
 132 #define HOST_S_STOP     0x0004
 133
 134 /* Easy access macros */
 135 #define HOST_STATUS(h)  ((h)->iobase + SD_STATUS)
 136 #define HOST_CONFIG(h)  ((h)->iobase + SD_CONFIG)
 137 #define HOST_ENABLE(h)  ((h)->iobase + SD_ENABLE)
 138 #define HOST_TXPORT(h)  ((h)->iobase + SD_TXPORT)
 139 #define HOST_RXPORT(h)  ((h)->iobase + SD_RXPORT)
 140 #define HOST_CMDARG(h)  ((h)->iobase + SD_CMDARG)
 141 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
 142 #define HOST_CMD(h)     ((h)->iobase + SD_CMD)
 143 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
 144 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
 145 #define HOST_DEBUG(h)   ((h)->iobase + SD_DEBUG)
 146
 147 #define DMA_CHANNEL(h)  \
 148         (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
 149
 150 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
 151 {
 152         u32 val = au_readl(HOST_CONFIG(host));
 153         val |= mask;
 154         au_writel(val, HOST_CONFIG(host));
 155         au_sync();
 156 }
 157
 158 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 159 {
 160         u32 val = au_readl(HOST_CONFIG2(host));
 161
 162         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 163         au_sync_delay(1);
 164
 165         /* SEND_STOP will turn off clock control - this re-enables it */
 166         val &= ~SD_CONFIG2_DF;
 167
 168         au_writel(val, HOST_CONFIG2(host));
 169         au_sync();
 170 }
 171
 172 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 173 {
 174         u32 val = au_readl(HOST_CONFIG(host));
 175         val &= ~mask;
 176         au_writel(val, HOST_CONFIG(host));
 177         au_sync();
 178 }
 179
 180 static inline void SEND_STOP(struct au1xmmc_host *host)
 181 {
 182         u32 config2;
 183
 184         WARN_ON(host->status != HOST_S_DATA);
 185         host->status = HOST_S_STOP;
 186
 187         config2 = au_readl(HOST_CONFIG2(host));
 188         au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
 189         au_sync();
 190
 191         /* Send the stop commmand */
 192         au_writel(STOP_CMD, HOST_CMD(host));
 193 }
 194
 195 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 196 {
 197         if (host->platdata && host->platdata->set_power)
 198                 host->platdata->set_power(host->mmc, state);
 199 }
 200
 201 static int au1xmmc_card_inserted(struct au1xmmc_host *host)
 202 {
 203         int ret;
 204
 205         if (host->platdata && host->platdata->card_inserted)
 206                 ret = host->platdata->card_inserted(host->mmc);
 207         else
 208                 ret = 1;        /* assume there is a card */
 209
 210         return ret;
 211 }
 212
 213 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 214 {
 215         struct au1xmmc_host *host = mmc_priv(mmc);
 216         int ret;
 217
 218         if (host->platdata && host->platdata->card_readonly)
 219                 ret = host->platdata->card_readonly(mmc);
 220         else
 221                 ret = 0;        /* assume card is read-write */
 222
 223         return ret;
 224 }
 225
 226 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 227 {
 228         struct mmc_request *mrq = host->mrq;
 229
 230         host->mrq = NULL;
 231         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
 232
 233         host->dma.len = 0;
 234         host->dma.dir = 0;
 235
 236         host->pio.index  = 0;
 237         host->pio.offset = 0;
 238         host->pio.len = 0;
 239
 240         host->status = HOST_S_IDLE;
 241
 242         mmc_request_done(host->mmc, mrq);
 243 }
 244
 245 static void au1xmmc_tasklet_finish(unsigned long param)
 246 {
 247         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 248         au1xmmc_finish_request(host);
 249 }
 250
 251 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 252                                 struct mmc_command *cmd, struct mmc_data *data)
 253 {
 254         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 255
 256         switch (mmc_resp_type(cmd)) {
 257         case MMC_RSP_NONE:
 258                 break;
 259         case MMC_RSP_R1:
 260                 mmccmd |= SD_CMD_RT_1;
 261                 break;
 262         case MMC_RSP_R1B:
 263                 mmccmd |= SD_CMD_RT_1B;
 264                 break;
 265         case MMC_RSP_R2:
 266                 mmccmd |= SD_CMD_RT_2;
 267                 break;
 268         case MMC_RSP_R3:
 269                 mmccmd |= SD_CMD_RT_3;
 270                 break;
 271         default:
 272                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 273                         mmc_resp_type(cmd));
 274                 return -EINVAL;
 275         }
 276
 277         if (data) {
 278                 if (data->flags & MMC_DATA_READ) {
 279                         if (data->blocks > 1)
 280                                 mmccmd |= SD_CMD_CT_4;
 281                         else
 282                                 mmccmd |= SD_CMD_CT_2;
 283                 } else if (data->flags & MMC_DATA_WRITE) {
 284                         if (data->blocks > 1)
 285                                 mmccmd |= SD_CMD_CT_3;
 286                         else
 287                                 mmccmd |= SD_CMD_CT_1;
 288                 }
 289         }
 290
 291         au_writel(cmd->arg, HOST_CMDARG(host));
 292         au_sync();
 293
 294         if (wait)
 295                 IRQ_OFF(host, SD_CONFIG_CR);
 296
 297         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 298         au_sync();
 299
 300         /* Wait for the command to go on the line */
 301         while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
 302                 /* nop */;
 303
 304         /* Wait for the command to come back */
 305         if (wait) {
 306                 u32 status = au_readl(HOST_STATUS(host));
 307
 308                 while (!(status & SD_STATUS_CR))
 309                         status = au_readl(HOST_STATUS(host));
 310
 311                 /* Clear the CR status */
 312                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 313
 314                 IRQ_ON(host, SD_CONFIG_CR);
 315         }
 316
 317         return 0;
 318 }
 319
 320 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 321 {
 322         struct mmc_request *mrq = host->mrq;
 323         struct mmc_data *data;
 324         u32 crc;
 325
 326         WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
 327
 328         if (host->mrq == NULL)
 329                 return;
 330
 331         data = mrq->cmd->data;
 332
 333         if (status == 0)
 334                 status = au_readl(HOST_STATUS(host));
 335
 336         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 337         while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 338                 status = au_readl(HOST_STATUS(host));
 339
 340         data->error = 0;
 341         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 342
 343         /* Process any errors */
 344         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 345         if (host->flags & HOST_F_XMIT)
 346                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 347
 348         if (crc)
 349                 data->error = -EILSEQ;
 350
 351         /* Clear the CRC bits */
 352         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 353
 354         data->bytes_xfered = 0;
 355
 356         if (!data->error) {
 357                 if (host->flags & HOST_F_DMA) {
 358 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 359                         u32 chan = DMA_CHANNEL(host);
 360
 361                         chan_tab_t *c = *((chan_tab_t **)chan);
 362                         au1x_dma_chan_t *cp = c->chan_ptr;
 363                         data->bytes_xfered = cp->ddma_bytecnt;
 364 #endif
 365                 } else
 366                         data->bytes_xfered =
 367                                 (data->blocks * data->blksz) - host->pio.len;
 368         }
 369
 370         au1xmmc_finish_request(host);
 371 }
 372
 373 static void au1xmmc_tasklet_data(unsigned long param)
 374 {
 375         struct au1xmmc_host *host = (struct au1xmmc_host *)param;
 376
 377         u32 status = au_readl(HOST_STATUS(host));
 378         au1xmmc_data_complete(host, status);
 379 }
 380
 381 #define AU1XMMC_MAX_TRANSFER 8
 382
 383 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 384 {
 385         struct mmc_data *data;
 386         int sg_len, max, count;
 387         unsigned char *sg_ptr, val;
 388         u32 status;
 389         struct scatterlist *sg;
 390
 391         data = host->mrq->data;
 392
 393         if (!(host->flags & HOST_F_XMIT))
 394                 return;
 395
 396         /* This is the pointer to the data buffer */
 397         sg = &data->sg[host->pio.index];
 398         sg_ptr = sg_virt(sg) + host->pio.offset;
 399
 400         /* This is the space left inside the buffer */
 401         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 402
 403         /* Check if we need less than the size of the sg_buffer */
 404         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 405         if (max > AU1XMMC_MAX_TRANSFER)
 406                 max = AU1XMMC_MAX_TRANSFER;
 407
 408         for (count = 0; count < max; count++) {
 409                 status = au_readl(HOST_STATUS(host));
 410
 411                 if (!(status & SD_STATUS_TH))
 412                         break;
 413
 414                 val = *sg_ptr++;
 415
 416                 au_writel((unsigned long)val, HOST_TXPORT(host));
 417                 au_sync();
 418         }
 419
 420         host->pio.len -= count;
 421         host->pio.offset += count;
 422
 423         if (count == sg_len) {
 424                 host->pio.index++;
 425                 host->pio.offset = 0;
 426         }
 427
 428         if (host->pio.len == 0) {
 429                 IRQ_OFF(host, SD_CONFIG_TH);
 430
 431                 if (host->flags & HOST_F_STOP)
 432                         SEND_STOP(host);
 433
 434                 tasklet_schedule(&host->data_task);
 435         }
 436 }
 437
 438 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 439 {
 440         struct mmc_data *data;
 441         int max, count, sg_len = 0;
 442         unsigned char *sg_ptr = NULL;
 443         u32 status, val;
 444         struct scatterlist *sg;
 445
 446         data = host->mrq->data;
 447
 448         if (!(host->flags & HOST_F_RECV))
 449                 return;
 450
 451         max = host->pio.len;
 452
 453         if (host->pio.index < host->dma.len) {
 454                 sg = &data->sg[host->pio.index];
 455                 sg_ptr = sg_virt(sg) + host->pio.offset;
 456
 457                 /* This is the space left inside the buffer */
 458                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 459
 460                 /* Check if we need less than the size of the sg_buffer */
 461                 if (sg_len < max)
 462                         max = sg_len;
 463         }
 464
 465         if (max > AU1XMMC_MAX_TRANSFER)
 466                 max = AU1XMMC_MAX_TRANSFER;
 467
 468         for (count = 0; count < max; count++) {
 469                 status = au_readl(HOST_STATUS(host));
 470
 471                 if (!(status & SD_STATUS_NE))
 472                         break;
 473
 474                 if (status & SD_STATUS_RC) {
 475                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
 476                                         host->pio.len, count);
 477                         break;
 478                 }
 479
 480                 if (status & SD_STATUS_RO) {
 481                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
 482                                         host->pio.len, count);
 483                         break;
 484                 }
 485                 else if (status & SD_STATUS_RU) {
 486                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
 487                                         host->pio.len,  count);
 488                         break;
 489                 }
 490
 491                 val = au_readl(HOST_RXPORT(host));
 492
 493                 if (sg_ptr)
 494                         *sg_ptr++ = (unsigned char)(val & 0xFF);
 495         }
 496
 497         host->pio.len -= count;
 498         host->pio.offset += count;
 499
 500         if (sg_len && count == sg_len) {
 501                 host->pio.index++;
 502                 host->pio.offset = 0;
 503         }
 504
 505         if (host->pio.len == 0) {
 506                 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 507                 IRQ_OFF(host, SD_CONFIG_NE);
 508
 509                 if (host->flags & HOST_F_STOP)
 510                         SEND_STOP(host);
 511
 512                 tasklet_schedule(&host->data_task);
 513         }
 514 }
 515
 516 /* This is called when a command has been completed - grab the response
 517  * and check for errors.  Then start the data transfer if it is indicated.
 518  */
 519 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 520 {
 521         struct mmc_request *mrq = host->mrq;
 522         struct mmc_command *cmd;
 523         u32 r[4];
 524         int i, trans;
 525
 526         if (!host->mrq)
 527                 return;
 528
 529         cmd = mrq->cmd;
 530         cmd->error = 0;
 531
 532         if (cmd->flags & MMC_RSP_PRESENT) {
 533                 if (cmd->flags & MMC_RSP_136) {
 534                         r[0] = au_readl(host->iobase + SD_RESP3);
 535                         r[1] = au_readl(host->iobase + SD_RESP2);
 536                         r[2] = au_readl(host->iobase + SD_RESP1);
 537                         r[3] = au_readl(host->iobase + SD_RESP0);
 538
 539                         /* The CRC is omitted from the response, so really
 540                          * we only got 120 bytes, but the engine expects
 541                          * 128 bits, so we have to shift things up.
 542                          */
 543                         for (i = 0; i < 4; i++) {
 544                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 545                                 if (i != 3)
 546                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 547                         }
 548                 } else {
 549                         /* Techincally, we should be getting all 48 bits of
 550                          * the response (SD_RESP1 + SD_RESP2), but because
 551                          * our response omits the CRC, our data ends up
 552                          * being shifted 8 bits to the right.  In this case,
 553                          * that means that the OSR data starts at bit 31,
 554                          * so we can just read RESP0 and return that.
 555                          */
 556                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 557                 }
 558         }
 559
 560         /* Figure out errors */
 561         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 562                 cmd->error = -EILSEQ;
 563
 564         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 565
 566         if (!trans || cmd->error) {
 567                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
 568                 tasklet_schedule(&host->finish_task);
 569                 return;
 570         }
 571
 572         host->status = HOST_S_DATA;
 573
 574         if (host->flags & HOST_F_DMA) {
 575 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 576                 u32 channel = DMA_CHANNEL(host);
 577
 578                 /* Start the DMA as soon as the buffer gets something in it */
 579
 580                 if (host->flags & HOST_F_RECV) {
 581                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 582
 583                         while((status & mask) != mask)
 584                                 status = au_readl(HOST_STATUS(host));
 585                 }
 586
 587                 au1xxx_dbdma_start(channel);
 588 #endif
 589         }
 590 }
 591
 592 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 593 {
 594         unsigned int pbus = get_au1x00_speed();
 595         unsigned int divisor;
 596         u32 config;
 597
 598         /* From databook:
 599          * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 600          */
 601         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 602         pbus /= 2;
 603         divisor = ((pbus / rate) / 2) - 1;
 604
 605         config = au_readl(HOST_CONFIG(host));
 606
 607         config &= ~(SD_CONFIG_DIV);
 608         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 609
 610         au_writel(config, HOST_CONFIG(host));
 611         au_sync();
 612 }
 613
 614 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
 615                                 struct mmc_data *data)
 616 {
 617         int datalen = data->blocks * data->blksz;
 618
 619         if (data->flags & MMC_DATA_READ)
 620                 host->flags |= HOST_F_RECV;
 621         else
 622                 host->flags |= HOST_F_XMIT;
 623
 624         if (host->mrq->stop)
 625                 host->flags |= HOST_F_STOP;
 626
 627         host->dma.dir = DMA_BIDIRECTIONAL;
 628
 629         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 630                                    data->sg_len, host->dma.dir);
 631
 632         if (host->dma.len == 0)
 633                 return -ETIMEDOUT;
 634
 635         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 636
 637         if (host->flags & HOST_F_DMA) {
 638 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 639                 int i;
 640                 u32 channel = DMA_CHANNEL(host);
 641
 642                 au1xxx_dbdma_stop(channel);
 643
 644                 for (i = 0; i < host->dma.len; i++) {
 645                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 646                         struct scatterlist *sg = &data->sg[i];
 647                         int sg_len = sg->length;
 648
 649                         int len = (datalen > sg_len) ? sg_len : datalen;
 650
 651                         if (i == host->dma.len - 1)
 652                                 flags = DDMA_FLAGS_IE;
 653
 654                         if (host->flags & HOST_F_XMIT) {
 655                                 ret = au1xxx_dbdma_put_source_flags(channel,
 656                                         (void *)sg_virt(sg), len, flags);
 657                         } else {
 658                                 ret = au1xxx_dbdma_put_dest_flags(channel,
 659                                         (void *)sg_virt(sg), len, flags);
 660                         }
 661
 662                         if (!ret)
 663                                 goto dataerr;
 664
 665                         datalen -= len;
 666                 }
 667 #endif
 668         } else {
 669                 host->pio.index = 0;
 670                 host->pio.offset = 0;
 671                 host->pio.len = datalen;
 672
 673                 if (host->flags & HOST_F_XMIT)
 674                         IRQ_ON(host, SD_CONFIG_TH);
 675                 else
 676                         IRQ_ON(host, SD_CONFIG_NE);
 677                         /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 678         }
 679
 680         return 0;
 681
 682 dataerr:
 683         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 684                         host->dma.dir);
 685         return -ETIMEDOUT;
 686 }
 687
 688 /* This actually starts a command or data transaction */
 689 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 690 {
 691         struct au1xmmc_host *host = mmc_priv(mmc);
 692         int ret = 0;
 693
 694         WARN_ON(irqs_disabled());
 695         WARN_ON(host->status != HOST_S_IDLE);
 696
 697         host->mrq = mrq;
 698         host->status = HOST_S_CMD;
 699
 700         if (mrq->data) {
 701                 FLUSH_FIFO(host);
 702                 ret = au1xmmc_prepare_data(host, mrq->data);
 703         }
 704
 705         if (!ret)
 706                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 707
 708         if (ret) {
 709                 mrq->cmd->error = ret;
 710                 au1xmmc_finish_request(host);
 711         }
 712 }
 713
 714 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 715 {
 716         /* Apply the clock */
 717         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 718         au_sync_delay(1);
 719
 720         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 721         au_sync_delay(5);
 722
 723         au_writel(~0, HOST_STATUS(host));
 724         au_sync();
 725
 726         au_writel(0, HOST_BLKSIZE(host));
 727         au_writel(0x001fffff, HOST_TIMEOUT(host));
 728         au_sync();
 729
 730         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 731         au_sync();
 732
 733         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 734         au_sync_delay(1);
 735
 736         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 737         au_sync();
 738
 739         /* Configure interrupts */
 740         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 741         au_sync();
 742 }
 743
 744
 745 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 746 {
 747         struct au1xmmc_host *host = mmc_priv(mmc);
 748         u32 config2;
 749
 750         if (ios->power_mode == MMC_POWER_OFF)
 751                 au1xmmc_set_power(host, 0);
 752         else if (ios->power_mode == MMC_POWER_ON) {
 753                 au1xmmc_set_power(host, 1);
 754         }
 755
 756         if (ios->clock && ios->clock != host->clock) {
 757                 au1xmmc_set_clock(host, ios->clock);
 758                 host->clock = ios->clock;
 759         }
 760
 761         config2 = au_readl(HOST_CONFIG2(host));
 762         switch (ios->bus_width) {
 763         case MMC_BUS_WIDTH_4:
 764                 config2 |= SD_CONFIG2_WB;
 765                 break;
 766         case MMC_BUS_WIDTH_1:
 767                 config2 &= ~SD_CONFIG2_WB;
 768                 break;
 769         }
 770         au_writel(config2, HOST_CONFIG2(host));
 771         au_sync();
 772 }
 773
 774 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 775 #define STATUS_DATA_IN  (SD_STATUS_NE)
 776 #define STATUS_DATA_OUT (SD_STATUS_TH)
 777
 778 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 779 {
 780         struct au1xmmc_host *host = dev_id;
 781         u32 status;
 782
 783         status = au_readl(HOST_STATUS(host));
 784
 785         if (!(status & SD_STATUS_I))
 786                 return IRQ_NONE;        /* not ours */
 787
 788         if (status & SD_STATUS_SI)      /* SDIO */
 789                 mmc_signal_sdio_irq(host->mmc);
 790
 791         if (host->mrq && (status & STATUS_TIMEOUT)) {
 792                 if (status & SD_STATUS_RAT)
 793                         host->mrq->cmd->error = -ETIMEDOUT;
 794                 else if (status & SD_STATUS_DT)
 795                         host->mrq->data->error = -ETIMEDOUT;
 796
 797                 /* In PIO mode, interrupts might still be enabled */
 798                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 799
 800                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
 801                 tasklet_schedule(&host->finish_task);
 802         }
 803 #if 0
 804         else if (status & SD_STATUS_DD) {
 805                 /* Sometimes we get a DD before a NE in PIO mode */
 806                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
 807                         au1xmmc_receive_pio(host);
 808                 else {
 809                         au1xmmc_data_complete(host, status);
 810                         /* tasklet_schedule(&host->data_task); */
 811                 }
 812         }
 813 #endif
 814         else if (status & SD_STATUS_CR) {
 815                 if (host->status == HOST_S_CMD)
 816                         au1xmmc_cmd_complete(host, status);
 817
 818         } else if (!(host->flags & HOST_F_DMA)) {
 819                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
 820                         au1xmmc_send_pio(host);
 821                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
 822                         au1xmmc_receive_pio(host);
 823
 824         } else if (status & 0x203F3C70) {
 825                         DBG("Unhandled status %8.8x\n", host->pdev->id,
 826                                 status);
 827         }
 828
 829         au_writel(status, HOST_STATUS(host));
 830         au_sync();
 831
 832         return IRQ_HANDLED;
 833 }
 834
 835 #ifdef CONFIG_SOC_AU1200
 836 /* 8bit memory DMA device */
 837 static dbdev_tab_t au1xmmc_mem_dbdev = {
 838         .dev_id         = DSCR_CMD0_ALWAYS,
 839         .dev_flags      = DEV_FLAGS_ANYUSE,
 840         .dev_tsize      = 0,
 841         .dev_devwidth   = 8,
 842         .dev_physaddr   = 0x00000000,
 843         .dev_intlevel   = 0,
 844         .dev_intpolarity = 0,
 845 };
 846 static int memid;
 847
 848 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
 849 {
 850         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
 851
 852         /* Avoid spurious interrupts */
 853         if (!host->mrq)
 854                 return;
 855
 856         if (host->flags & HOST_F_STOP)
 857                 SEND_STOP(host);
 858
 859         tasklet_schedule(&host->data_task);
 860 }
 861
 862 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
 863 {
 864         struct resource *res;
 865         int txid, rxid;
 866
 867         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
 868         if (!res)
 869                 return -ENODEV;
 870         txid = res->start;
 871
 872         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
 873         if (!res)
 874                 return -ENODEV;
 875         rxid = res->start;
 876
 877         if (!memid)
 878                 return -ENODEV;
 879
 880         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
 881                                 au1xmmc_dbdma_callback, (void *)host);
 882         if (!host->tx_chan) {
 883                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
 884                 return -ENODEV;
 885         }
 886
 887         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
 888                                 au1xmmc_dbdma_callback, (void *)host);
 889         if (!host->rx_chan) {
 890                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
 891                 au1xxx_dbdma_chan_free(host->tx_chan);
 892                 return -ENODEV;
 893         }
 894
 895         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
 896         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
 897
 898         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 899         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 900
 901         /* DBDMA is good to go */
 902         host->flags |= HOST_F_DMA;
 903
 904         return 0;
 905 }
 906
 907 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
 908 {
 909         if (host->flags & HOST_F_DMA) {
 910                 host->flags &= ~HOST_F_DMA;
 911                 au1xxx_dbdma_chan_free(host->tx_chan);
 912                 au1xxx_dbdma_chan_free(host->rx_chan);
 913         }
 914 }
 915 #endif
 916
 917 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
 918 {
 919         struct au1xmmc_host *host = mmc_priv(mmc);
 920
 921         if (en)
 922                 IRQ_ON(host, SD_CONFIG_SI);
 923         else
 924                 IRQ_OFF(host, SD_CONFIG_SI);
 925 }
 926
 927 static const struct mmc_host_ops au1xmmc_ops = {
 928         .request        = au1xmmc_request,
 929         .set_ios        = au1xmmc_set_ios,
 930         .get_ro         = au1xmmc_card_readonly,
 931         .enable_sdio_irq = au1xmmc_enable_sdio_irq,
 932 };
 933
 934 static void au1xmmc_poll_event(unsigned long arg)
 935 {
 936         struct au1xmmc_host *host = (struct au1xmmc_host *)arg;
 937         int card = au1xmmc_card_inserted(host);
 938         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
 939
 940         if (card != controller) {
 941                 host->flags &= ~HOST_F_ACTIVE;
 942                 if (card)
 943                         host->flags |= HOST_F_ACTIVE;
 944                 mmc_detect_change(host->mmc, 0);
 945         }
 946
 947 #ifdef DEBUG
 948         if (host->mrq != NULL) {
 949                 u32 status = au_readl(HOST_STATUS(host));
 950                 DBG("PENDING - %8.8x\n", host->pdev->id, status);
 951         }
 952 #endif
 953         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
 954 }
 955
 956 static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host)
 957 {
 958         init_timer(&host->timer);
 959         host->timer.function = au1xmmc_poll_event;
 960         host->timer.data = (unsigned long)host;
 961         host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
 962 }
 963
 964 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 965 {
 966         struct mmc_host *mmc;
 967         struct au1xmmc_host *host;
 968         struct resource *r;
 969         int ret;
 970
 971         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 972         if (!mmc) {
 973                 dev_err(&pdev->dev, "no memory for mmc_host\n");
 974                 ret = -ENOMEM;
 975                 goto out0;
 976         }
 977
 978         host = mmc_priv(mmc);
 979         host->mmc = mmc;
 980         host->platdata = pdev->dev.platform_data;
 981         host->pdev = pdev;
 982
 983         ret = -ENODEV;
 984         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 985         if (!r) {
 986                 dev_err(&pdev->dev, "no mmio defined\n");
 987                 goto out1;
 988         }
 989
 990         host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
 991                                            pdev->name);
 992         if (!host->ioarea) {
 993                 dev_err(&pdev->dev, "mmio already in use\n");
 994                 goto out1;
 995         }
 996
 997         host->iobase = (unsigned long)ioremap(r->start, 0x3c);
 998         if (!host->iobase) {
 999                 dev_err(&pdev->dev, "cannot remap mmio\n");
1000                 goto out2;
1001         }
1002
1003         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1004         if (!r) {
1005                 dev_err(&pdev->dev, "no IRQ defined\n");
1006                 goto out3;
1007         }
1008
1009         host->irq = r->start;
1010         /* IRQ is shared among both SD controllers */
1011         ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
1012                           DRIVER_NAME, host);
1013         if (ret) {
1014                 dev_err(&pdev->dev, "cannot grab IRQ\n");
1015                 goto out3;
1016         }
1017
1018         mmc->ops = &au1xmmc_ops;
1019
1020         mmc->f_min =   450000;
1021         mmc->f_max = 24000000;
1022
1023         mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
1024         mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
1025
1026         mmc->max_blk_size = 2048;
1027         mmc->max_blk_count = 512;
1028
1029         mmc->ocr_avail = AU1XMMC_OCR;
1030         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1031
1032         host->status = HOST_S_IDLE;
1033
1034         /* board-specific carddetect setup, if any */
1035         if (host->platdata && host->platdata->cd_setup) {
1036                 ret = host->platdata->cd_setup(mmc, 1);
1037                 if (ret) {
1038                         dev_err(&pdev->dev, "board CD setup failed\n");
1039                         goto out4;
1040                 }
1041         } else {
1042                 /* poll the board-specific is-card-in-socket-? method */
1043                 au1xmmc_init_cd_poll_timer(host);
1044         }
1045
1046         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1047                         (unsigned long)host);
1048
1049         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1050                         (unsigned long)host);
1051
1052 #ifdef CONFIG_SOC_AU1200
1053         ret = au1xmmc_dbdma_init(host);
1054         if (ret)
1055                 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
1056 #endif
1057
1058 #ifdef CONFIG_LEDS_CLASS
1059         if (host->platdata && host->platdata->led) {
1060                 struct led_classdev *led = host->platdata->led;
1061                 led->name = mmc_hostname(mmc);
1062                 led->brightness = LED_OFF;
1063                 led->default_trigger = mmc_hostname(mmc);
1064                 ret = led_classdev_register(mmc_dev(mmc), led);
1065                 if (ret)
1066                         goto out5;
1067         }
1068 #endif
1069
1070         au1xmmc_reset_controller(host);
1071
1072         ret = mmc_add_host(mmc);
1073         if (ret) {
1074                 dev_err(&pdev->dev, "cannot add mmc host\n");
1075                 goto out6;
1076         }
1077
1078         platform_set_drvdata(pdev, mmc);
1079
1080         /* start the carddetect poll timer if necessary */
1081         if (!(host->platdata && host->platdata->cd_setup))
1082                 add_timer(&host->timer);
1083
1084         printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1085                 " (mode=%s)\n", pdev->id, host->iobase,
1086                 host->flags & HOST_F_DMA ? "dma" : "pio");
1087
1088         return 0;       /* all ok */
1089
1090 out6:
1091 #ifdef CONFIG_LEDS_CLASS
1092         if (host->platdata && host->platdata->led)
1093                 led_classdev_unregister(host->platdata->led);
1094 out5:
1095 #endif
1096         au_writel(0, HOST_ENABLE(host));
1097         au_writel(0, HOST_CONFIG(host));
1098         au_writel(0, HOST_CONFIG2(host));
1099         au_sync();
1100
1101 #ifdef CONFIG_SOC_AU1200
1102         au1xmmc_dbdma_shutdown(host);
1103 #endif
1104
1105         tasklet_kill(&host->data_task);
1106         tasklet_kill(&host->finish_task);
1107
1108         if (host->platdata && host->platdata->cd_setup)
1109                 host->platdata->cd_setup(mmc, 0);
1110 out4:
1111         free_irq(host->irq, host);
1112 out3:
1113         iounmap((void *)host->iobase);
1114 out2:
1115         release_resource(host->ioarea);
1116         kfree(host->ioarea);
1117 out1:
1118         mmc_free_host(mmc);
1119 out0:
1120         return ret;
1121 }
1122
1123 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1124 {
1125         struct mmc_host *mmc = platform_get_drvdata(pdev);
1126         struct au1xmmc_host *host;
1127
1128         if (mmc) {
1129                 host  = mmc_priv(mmc);
1130
1131                 mmc_remove_host(mmc);
1132
1133 #ifdef CONFIG_LEDS_CLASS
1134                 if (host->platdata && host->platdata->led)
1135                         led_classdev_unregister(host->platdata->led);
1136 #endif
1137
1138                 if (host->platdata && host->platdata->cd_setup)
1139                         host->platdata->cd_setup(mmc, 0);
1140                 else
1141                         del_timer_sync(&host->timer);
1142
1143                 au_writel(0, HOST_ENABLE(host));
1144                 au_writel(0, HOST_CONFIG(host));
1145                 au_writel(0, HOST_CONFIG2(host));
1146                 au_sync();
1147
1148                 tasklet_kill(&host->data_task);
1149                 tasklet_kill(&host->finish_task);
1150
1151 #ifdef CONFIG_SOC_AU1200
1152                 au1xmmc_dbdma_shutdown(host);
1153 #endif
1154                 au1xmmc_set_power(host, 0);
1155
1156                 free_irq(host->irq, host);
1157                 iounmap((void *)host->iobase);
1158                 release_resource(host->ioarea);
1159                 kfree(host->ioarea);
1160
1161                 mmc_free_host(mmc);
1162         }
1163         return 0;
1164 }
1165
1166 static struct platform_driver au1xmmc_driver = {
1167         .probe         = au1xmmc_probe,
1168         .remove        = au1xmmc_remove,
1169         .suspend       = NULL,
1170         .resume        = NULL,
1171         .driver        = {
1172                 .name  = DRIVER_NAME,
1173                 .owner = THIS_MODULE,
1174         },
1175 };
1176
1177 static int __init au1xmmc_init(void)
1178 {
1179 #ifdef CONFIG_SOC_AU1200
1180         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1181          * of 8 bits.  And since devices are shared, we need to create
1182          * our own to avoid freaking out other devices.
1183          */
1184         memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1185         if (!memid)
1186                 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1187 #endif
1188         return platform_driver_register(&au1xmmc_driver);
1189 }
1190
1191 static void __exit au1xmmc_exit(void)
1192 {
1193 #ifdef CONFIG_SOC_AU1200
1194         if (memid)
1195                 au1xxx_ddma_del_device(memid);
1196 #endif
1197         platform_driver_unregister(&au1xmmc_driver);
1198 }
1199
1200 module_init(au1xmmc_init);
1201 module_exit(au1xmmc_exit);
1202
1203 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1204 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1205 MODULE_LICENSE("GPL");
1206 MODULE_ALIAS("platform:au1xxx-mmc");