1 /* linux/drivers/mfd/sm501.c
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/list.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pci.h>
22 #include <linux/i2c-gpio.h>
24 #include <linux/sm501.h>
25 #include <linux/sm501-regs.h>
26 #include <linux/serial_8250.h>
31 struct list_head list;
32 struct platform_device pdev;
37 #ifdef CONFIG_MFD_SM501_GPIO
38 #include <linux/gpio.h>
40 struct sm501_gpio_chip {
41 struct gpio_chip gpio;
42 struct sm501_gpio *ourgpio; /* to get back to parent. */
43 void __iomem *regbase;
47 struct sm501_gpio_chip low;
48 struct sm501_gpio_chip high;
51 unsigned int registered : 1;
53 struct resource *regs_res;
57 /* no gpio support, empty definition for sm501_devdata. */
61 struct sm501_devdata {
63 struct mutex clock_lock;
64 struct list_head devices;
65 struct sm501_gpio gpio;
68 struct resource *io_res;
69 struct resource *mem_res;
70 struct resource *regs_claim;
71 struct sm501_platdata *platdata;
74 unsigned int in_suspend;
75 unsigned long pm_misc;
85 #define MHZ (1000 * 1000)
88 static const unsigned int div_tab[] = {
115 static unsigned long decode_div(unsigned long pll2, unsigned long val,
116 unsigned int lshft, unsigned int selbit,
122 return pll2 / div_tab[(val >> lshft) & mask];
125 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
129 * Print out the current clock configuration for the device
132 static void sm501_dump_clk(struct sm501_devdata *sm)
134 unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
135 unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
136 unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
137 unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
138 unsigned long sdclk0, sdclk1;
139 unsigned long pll2 = 0;
141 switch (misct & 0x30) {
156 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
157 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
159 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
160 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
162 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
165 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
166 fmt_freq(pll2), sdclk0, sdclk1);
168 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
170 dev_dbg(sm->dev, "PM0[%c]: "
171 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
172 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
173 (pmc & 3 ) == 0 ? '*' : '-',
174 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
175 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
176 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
177 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
179 dev_dbg(sm->dev, "PM1[%c]: "
180 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
181 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
182 (pmc & 3 ) == 1 ? '*' : '-',
183 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
184 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
185 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
186 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
189 static void sm501_dump_regs(struct sm501_devdata *sm)
191 void __iomem *regs = sm->regs;
193 dev_info(sm->dev, "System Control %08x\n",
194 readl(regs + SM501_SYSTEM_CONTROL));
195 dev_info(sm->dev, "Misc Control %08x\n",
196 readl(regs + SM501_MISC_CONTROL));
197 dev_info(sm->dev, "GPIO Control Low %08x\n",
198 readl(regs + SM501_GPIO31_0_CONTROL));
199 dev_info(sm->dev, "GPIO Control Hi %08x\n",
200 readl(regs + SM501_GPIO63_32_CONTROL));
201 dev_info(sm->dev, "DRAM Control %08x\n",
202 readl(regs + SM501_DRAM_CONTROL));
203 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
204 readl(regs + SM501_ARBTRTN_CONTROL));
205 dev_info(sm->dev, "Misc Timing %08x\n",
206 readl(regs + SM501_MISC_TIMING));
209 static void sm501_dump_gate(struct sm501_devdata *sm)
211 dev_info(sm->dev, "CurrentGate %08x\n",
212 readl(sm->regs + SM501_CURRENT_GATE));
213 dev_info(sm->dev, "CurrentClock %08x\n",
214 readl(sm->regs + SM501_CURRENT_CLOCK));
215 dev_info(sm->dev, "PowerModeControl %08x\n",
216 readl(sm->regs + SM501_POWER_MODE_CONTROL));
220 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
221 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
222 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
230 static void sm501_sync_regs(struct sm501_devdata *sm)
235 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
237 /* during suspend/resume, we are currently not allowed to sleep,
238 * so change to using mdelay() instead of msleep() if we
239 * are in one of these paths */
247 /* sm501_misc_control
249 * alters the miscellaneous control parameters
252 int sm501_misc_control(struct device *dev,
253 unsigned long set, unsigned long clear)
255 struct sm501_devdata *sm = dev_get_drvdata(dev);
260 spin_lock_irqsave(&sm->reg_lock, save);
262 misc = readl(sm->regs + SM501_MISC_CONTROL);
263 to = (misc & ~clear) | set;
266 writel(to, sm->regs + SM501_MISC_CONTROL);
269 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
272 spin_unlock_irqrestore(&sm->reg_lock, save);
276 EXPORT_SYMBOL_GPL(sm501_misc_control);
280 * Modify a register in the SM501 which may be shared with other
284 unsigned long sm501_modify_reg(struct device *dev,
289 struct sm501_devdata *sm = dev_get_drvdata(dev);
293 spin_lock_irqsave(&sm->reg_lock, save);
295 data = readl(sm->regs + reg);
299 writel(data, sm->regs + reg);
302 spin_unlock_irqrestore(&sm->reg_lock, save);
307 EXPORT_SYMBOL_GPL(sm501_modify_reg);
311 * alters the power active gate to set specific units on or off
314 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
316 struct sm501_devdata *sm = dev_get_drvdata(dev);
321 mutex_lock(&sm->clock_lock);
323 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
324 gate = readl(sm->regs + SM501_CURRENT_GATE);
325 clock = readl(sm->regs + SM501_CURRENT_CLOCK);
327 mode &= 3; /* get current power mode */
329 if (unit >= ARRAY_SIZE(sm->unit_power)) {
330 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
334 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
335 sm->unit_power[unit], to);
337 if (to == 0 && sm->unit_power[unit] == 0) {
338 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
342 sm->unit_power[unit] += to ? 1 : -1;
343 to = sm->unit_power[unit] ? 1 : 0;
346 if (gate & (1 << unit))
350 if (!(gate & (1 << unit)))
352 gate &= ~(1 << unit);
357 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
358 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
363 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
364 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
372 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
375 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
378 sm501_mdelay(sm, 16);
381 mutex_unlock(&sm->clock_lock);
385 EXPORT_SYMBOL_GPL(sm501_unit_power);
388 /* Perform a rounded division. */
389 static long sm501fb_round_div(long num, long denom)
391 /* n / d + 1 / 2 = (2n + d) / 2d */
392 return (2 * num + denom) / (2 * denom);
395 /* clock value structure. */
400 unsigned int m, n, k;
405 * Calculates the nearest discrete clock frequency that
406 * can be achieved with the specified input clock.
407 * the maximum divisor is 3 or 5
410 static int sm501_calc_clock(unsigned long freq,
411 struct sm501_clock *clock,
421 /* try dividers 1 and 3 for CRT and for panel,
422 try divider 5 for panel only.*/
424 for (divider = 1; divider <= max_div; divider += 2) {
425 /* try all 8 shift values.*/
426 for (shift = 0; shift < 8; shift++) {
427 /* Calculate difference to requested clock */
428 diff = sm501fb_round_div(mclk, divider << shift) - freq;
432 /* If it is less than the current, use it */
433 if (diff < *best_diff) {
437 clock->divider = divider;
438 clock->shift = shift;
449 * Calculates the nearest discrete clock frequency that can be
450 * achieved using the programmable PLL.
451 * the maximum divisor is 3 or 5
454 static unsigned long sm501_calc_pll(unsigned long freq,
455 struct sm501_clock *clock,
459 unsigned int m, n, k;
460 long best_diff = 999999999;
463 * The SM502 datasheet doesn't specify the min/max values for M and N.
464 * N = 1 at least doesn't work in practice.
466 for (m = 2; m <= 255; m++) {
467 for (n = 2; n <= 127; n++) {
468 for (k = 0; k <= 1; k++) {
469 mclk = (24000000UL * m / n) >> k;
471 if (sm501_calc_clock(freq, clock, max_div,
481 /* Return best clock. */
482 return clock->mclk / (clock->divider << clock->shift);
485 /* sm501_select_clock
487 * Calculates the nearest discrete clock frequency that can be
488 * achieved using the 288MHz and 336MHz PLLs.
489 * the maximum divisor is 3 or 5
492 static unsigned long sm501_select_clock(unsigned long freq,
493 struct sm501_clock *clock,
497 long best_diff = 999999999;
499 /* Try 288MHz and 336MHz clocks. */
500 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
501 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
504 /* Return best clock. */
505 return clock->mclk / (clock->divider << clock->shift);
510 * set one of the four clock sources to the closest available frequency to
514 unsigned long sm501_set_clock(struct device *dev,
516 unsigned long req_freq)
518 struct sm501_devdata *sm = dev_get_drvdata(dev);
519 unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
520 unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
521 unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
523 unsigned int pll_reg = 0;
524 unsigned long sm501_freq; /* the actual frequency acheived */
526 struct sm501_clock to;
528 /* find achivable discrete frequency and setup register value
529 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
530 * has an extra bit for the divider */
533 case SM501_CLOCK_P2XCLK:
534 /* This clock is divided in half so to achive the
535 * requested frequency the value must be multiplied by
536 * 2. This clock also has an additional pre divisor */
538 if (sm->rev >= 0xC0) {
539 /* SM502 -> use the programmable PLL */
540 sm501_freq = (sm501_calc_pll(2 * req_freq,
542 reg = to.shift & 0x07;/* bottom 3 bits are shift */
544 reg |= 0x08; /* /3 divider required */
545 else if (to.divider == 5)
546 reg |= 0x10; /* /5 divider required */
547 reg |= 0x40; /* select the programmable PLL */
548 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
550 sm501_freq = (sm501_select_clock(2 * req_freq,
552 reg = to.shift & 0x07;/* bottom 3 bits are shift */
554 reg |= 0x08; /* /3 divider required */
555 else if (to.divider == 5)
556 reg |= 0x10; /* /5 divider required */
557 if (to.mclk != 288000000)
558 reg |= 0x20; /* which mclk pll is source */
562 case SM501_CLOCK_V2XCLK:
563 /* This clock is divided in half so to achive the
564 * requested frequency the value must be multiplied by 2. */
566 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
567 reg=to.shift & 0x07; /* bottom 3 bits are shift */
569 reg |= 0x08; /* /3 divider required */
570 if (to.mclk != 288000000)
571 reg |= 0x10; /* which mclk pll is source */
574 case SM501_CLOCK_MCLK:
575 case SM501_CLOCK_M1XCLK:
576 /* These clocks are the same and not further divided */
578 sm501_freq = sm501_select_clock( req_freq, &to, 3);
579 reg=to.shift & 0x07; /* bottom 3 bits are shift */
581 reg |= 0x08; /* /3 divider required */
582 if (to.mclk != 288000000)
583 reg |= 0x10; /* which mclk pll is source */
587 return 0; /* this is bad */
590 mutex_lock(&sm->clock_lock);
592 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
593 gate = readl(sm->regs + SM501_CURRENT_GATE);
594 clock = readl(sm->regs + SM501_CURRENT_CLOCK);
596 clock = clock & ~(0xFF << clksrc);
597 clock |= reg<<clksrc;
599 mode &= 3; /* find current mode */
603 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
604 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
609 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
610 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
615 mutex_unlock(&sm->clock_lock);
619 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
622 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
626 dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
629 sm501_mdelay(sm, 16);
630 mutex_unlock(&sm->clock_lock);
637 EXPORT_SYMBOL_GPL(sm501_set_clock);
641 * finds the closest available frequency for a given clock
644 unsigned long sm501_find_clock(struct device *dev,
646 unsigned long req_freq)
648 struct sm501_devdata *sm = dev_get_drvdata(dev);
649 unsigned long sm501_freq; /* the frequency achiveable by the 501 */
650 struct sm501_clock to;
653 case SM501_CLOCK_P2XCLK:
654 if (sm->rev >= 0xC0) {
655 /* SM502 -> use the programmable PLL */
656 sm501_freq = (sm501_calc_pll(2 * req_freq,
659 sm501_freq = (sm501_select_clock(2 * req_freq,
664 case SM501_CLOCK_V2XCLK:
665 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
668 case SM501_CLOCK_MCLK:
669 case SM501_CLOCK_M1XCLK:
670 sm501_freq = sm501_select_clock(req_freq, &to, 3);
674 sm501_freq = 0; /* error */
680 EXPORT_SYMBOL_GPL(sm501_find_clock);
682 static struct sm501_device *to_sm_device(struct platform_device *pdev)
684 return container_of(pdev, struct sm501_device, pdev);
687 /* sm501_device_release
689 * A release function for the platform devices we create to allow us to
690 * free any items we allocated
693 static void sm501_device_release(struct device *dev)
695 kfree(to_sm_device(to_platform_device(dev)));
698 /* sm501_create_subdev
700 * Create a skeleton platform device with resources for passing to a
704 static struct platform_device *
705 sm501_create_subdev(struct sm501_devdata *sm, char *name,
706 unsigned int res_count, unsigned int platform_data_size)
708 struct sm501_device *smdev;
710 smdev = kzalloc(sizeof(struct sm501_device) +
711 (sizeof(struct resource) * res_count) +
712 platform_data_size, GFP_KERNEL);
716 smdev->pdev.dev.release = sm501_device_release;
718 smdev->pdev.name = name;
719 smdev->pdev.id = sm->pdev_id;
720 smdev->pdev.dev.parent = sm->dev;
723 smdev->pdev.resource = (struct resource *)(smdev+1);
724 smdev->pdev.num_resources = res_count;
726 if (platform_data_size)
727 smdev->pdev.dev.platform_data = (void *)(smdev+1);
732 /* sm501_register_device
734 * Register a platform device created with sm501_create_subdev()
737 static int sm501_register_device(struct sm501_devdata *sm,
738 struct platform_device *pdev)
740 struct sm501_device *smdev = to_sm_device(pdev);
744 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
745 printk("%s[%d] flags %08lx: %08llx..%08llx\n",
747 pdev->resource[ptr].flags,
748 (unsigned long long)pdev->resource[ptr].start,
749 (unsigned long long)pdev->resource[ptr].end);
752 ret = platform_device_register(pdev);
755 dev_dbg(sm->dev, "registered %s\n", pdev->name);
756 list_add_tail(&smdev->list, &sm->devices);
758 dev_err(sm->dev, "error registering %s (%d)\n",
764 /* sm501_create_subio
766 * Fill in an IO resource for a sub device
769 static void sm501_create_subio(struct sm501_devdata *sm,
770 struct resource *res,
771 resource_size_t offs,
772 resource_size_t size)
774 res->flags = IORESOURCE_MEM;
775 res->parent = sm->io_res;
776 res->start = sm->io_res->start + offs;
777 res->end = res->start + size - 1;
782 * Fill in an MEM resource for a sub device
785 static void sm501_create_mem(struct sm501_devdata *sm,
786 struct resource *res,
787 resource_size_t *offs,
788 resource_size_t size)
790 *offs -= size; /* adjust memory size */
792 res->flags = IORESOURCE_MEM;
793 res->parent = sm->mem_res;
794 res->start = sm->mem_res->start + *offs;
795 res->end = res->start + size - 1;
800 * Fill in an IRQ resource for a sub device
803 static void sm501_create_irq(struct sm501_devdata *sm,
804 struct resource *res)
806 res->flags = IORESOURCE_IRQ;
808 res->start = res->end = sm->irq;
811 static int sm501_register_usbhost(struct sm501_devdata *sm,
812 resource_size_t *mem_avail)
814 struct platform_device *pdev;
816 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
820 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
821 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
822 sm501_create_irq(sm, &pdev->resource[2]);
824 return sm501_register_device(sm, pdev);
827 static void sm501_setup_uart_data(struct sm501_devdata *sm,
828 struct plat_serial8250_port *uart_data,
831 uart_data->membase = sm->regs + offset;
832 uart_data->mapbase = sm->io_res->start + offset;
833 uart_data->iotype = UPIO_MEM;
834 uart_data->irq = sm->irq;
835 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
836 uart_data->regshift = 2;
837 uart_data->uartclk = (9600 * 16);
840 static int sm501_register_uart(struct sm501_devdata *sm, int devices)
842 struct platform_device *pdev;
843 struct plat_serial8250_port *uart_data;
845 pdev = sm501_create_subdev(sm, "serial8250", 0,
846 sizeof(struct plat_serial8250_port) * 3);
850 uart_data = pdev->dev.platform_data;
852 if (devices & SM501_USE_UART0) {
853 sm501_setup_uart_data(sm, uart_data++, 0x30000);
854 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
855 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
856 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
858 if (devices & SM501_USE_UART1) {
859 sm501_setup_uart_data(sm, uart_data++, 0x30020);
860 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
861 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
862 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
865 pdev->id = PLAT8250_DEV_SM501;
867 return sm501_register_device(sm, pdev);
870 static int sm501_register_display(struct sm501_devdata *sm,
871 resource_size_t *mem_avail)
873 struct platform_device *pdev;
875 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
879 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
880 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
881 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
882 sm501_create_irq(sm, &pdev->resource[3]);
884 return sm501_register_device(sm, pdev);
887 #ifdef CONFIG_MFD_SM501_GPIO
889 static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
891 return container_of(gc, struct sm501_gpio_chip, gpio);
894 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
896 return container_of(gpio, struct sm501_devdata, gpio);
899 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
902 struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
903 unsigned long result;
905 result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
911 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
914 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
915 struct sm501_gpio *smgpio = smchip->ourgpio;
916 unsigned long bit = 1 << offset;
917 void __iomem *regs = smchip->regbase;
921 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
922 __func__, chip, offset);
924 spin_lock_irqsave(&smgpio->lock, save);
926 val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
931 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
932 spin_unlock_irqrestore(&smgpio->lock, save);
935 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
937 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
938 struct sm501_gpio *smgpio = smchip->ourgpio;
939 void __iomem *regs = smchip->regbase;
940 unsigned long bit = 1 << offset;
944 dev_info(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
945 __func__, chip, offset);
947 spin_lock_irqsave(&smgpio->lock, save);
949 ddr = readl(regs + SM501_GPIO_DDR_LOW);
950 writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
952 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
953 spin_unlock_irqrestore(&smgpio->lock, save);
958 static int sm501_gpio_output(struct gpio_chip *chip,
959 unsigned offset, int value)
961 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
962 struct sm501_gpio *smgpio = smchip->ourgpio;
963 unsigned long bit = 1 << offset;
964 void __iomem *regs = smchip->regbase;
969 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
970 __func__, chip, offset, value);
972 spin_lock_irqsave(&smgpio->lock, save);
974 val = readl(regs + SM501_GPIO_DATA_LOW);
981 ddr = readl(regs + SM501_GPIO_DDR_LOW);
982 writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
984 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
985 writel(val, regs + SM501_GPIO_DATA_LOW);
987 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
988 spin_unlock_irqrestore(&smgpio->lock, save);
993 static struct gpio_chip gpio_chip_template = {
995 .direction_input = sm501_gpio_input,
996 .direction_output = sm501_gpio_output,
997 .set = sm501_gpio_set,
998 .get = sm501_gpio_get,
1001 static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm,
1002 struct sm501_gpio *gpio,
1003 struct sm501_gpio_chip *chip)
1005 struct sm501_platdata *pdata = sm->platdata;
1006 struct gpio_chip *gchip = &chip->gpio;
1007 int base = pdata->gpio_base;
1009 chip->gpio = gpio_chip_template;
1011 if (chip == &gpio->high) {
1014 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1015 gchip->label = "SM501-HIGH";
1017 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1018 gchip->label = "SM501-LOW";
1022 chip->ourgpio = gpio;
1024 return gpiochip_add(gchip);
1027 static int sm501_register_gpio(struct sm501_devdata *sm)
1029 struct sm501_gpio *gpio = &sm->gpio;
1030 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1034 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1035 (unsigned long long)iobase);
1037 spin_lock_init(&gpio->lock);
1039 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1040 if (gpio->regs_res == NULL) {
1041 dev_err(sm->dev, "gpio: failed to request region\n");
1045 gpio->regs = ioremap(iobase, 0x20);
1046 if (gpio->regs == NULL) {
1047 dev_err(sm->dev, "gpio: failed to remap registers\n");
1052 /* Register both our chips. */
1054 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1056 dev_err(sm->dev, "failed to add low chip\n");
1060 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1062 dev_err(sm->dev, "failed to add high chip\n");
1066 gpio->registered = 1;
1071 tmp = gpiochip_remove(&gpio->low.gpio);
1073 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1078 iounmap(gpio->regs);
1081 release_resource(gpio->regs_res);
1082 kfree(gpio->regs_res);
1087 static void sm501_gpio_remove(struct sm501_devdata *sm)
1089 struct sm501_gpio *gpio = &sm->gpio;
1092 if (!sm->gpio.registered)
1095 ret = gpiochip_remove(&gpio->low.gpio);
1097 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1099 ret = gpiochip_remove(&gpio->high.gpio);
1101 dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
1103 iounmap(gpio->regs);
1104 release_resource(gpio->regs_res);
1105 kfree(gpio->regs_res);
1108 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1110 struct sm501_gpio *gpio = &sm->gpio;
1111 return pin + (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1114 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1116 return sm->gpio.registered;
1119 static inline int sm501_register_gpio(struct sm501_devdata *sm)
1124 static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1128 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1133 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1139 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1140 struct sm501_platdata_gpio_i2c *iic)
1142 struct i2c_gpio_platform_data *icd;
1143 struct platform_device *pdev;
1145 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1146 sizeof(struct i2c_gpio_platform_data));
1150 icd = pdev->dev.platform_data;
1152 /* We keep the pin_sda and pin_scl fields relative in case the
1153 * same platform data is passed to >1 SM501.
1156 icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1157 icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1158 icd->timeout = iic->timeout;
1159 icd->udelay = iic->udelay;
1161 /* note, we can't use either of the pin numbers, as the i2c-gpio
1162 * driver uses the platform.id field to generate the bus number
1163 * to register with the i2c core; The i2c core doesn't have enough
1164 * entries to deal with anything we currently use.
1167 pdev->id = iic->bus_num;
1169 dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1171 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1173 return sm501_register_device(sm, pdev);
1176 static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1177 struct sm501_platdata *pdata)
1179 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1183 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1184 ret = sm501_register_gpio_i2c_instance(sm, iic);
1194 * Debug attribute to attach to parent device to show core registers
1197 static ssize_t sm501_dbg_regs(struct device *dev,
1198 struct device_attribute *attr, char *buff)
1200 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1205 for (reg = 0x00; reg < 0x70; reg += 4) {
1206 ret = sprintf(ptr, "%08x = %08x\n",
1207 reg, readl(sm->regs + reg));
1215 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
1219 * Helper function for the init code to setup a register
1221 * clear the bits which are set in r->mask, and then set
1222 * the bits set in r->set.
1225 static inline void sm501_init_reg(struct sm501_devdata *sm,
1227 struct sm501_reg_init *r)
1231 tmp = readl(sm->regs + reg);
1234 writel(tmp, sm->regs + reg);
1239 * Setup core register values
1242 static void sm501_init_regs(struct sm501_devdata *sm,
1243 struct sm501_initdata *init)
1245 sm501_misc_control(sm->dev,
1246 init->misc_control.set,
1247 init->misc_control.mask);
1249 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1250 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1251 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1254 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1255 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1259 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1260 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1265 /* Check the PLL sources for the M1CLK and M1XCLK
1267 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1268 * there is a risk (see errata AB-5) that the SM501 will cease proper
1269 * function. If this happens, then it is likely the SM501 will
1273 static int sm501_check_clocks(struct sm501_devdata *sm)
1275 unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
1276 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1277 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1279 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1282 static unsigned int sm501_mem_local[] = {
1293 * Common init code for an SM501
1296 static int sm501_init_dev(struct sm501_devdata *sm)
1298 struct sm501_initdata *idata;
1299 struct sm501_platdata *pdata;
1300 resource_size_t mem_avail;
1301 unsigned long dramctrl;
1302 unsigned long devid;
1305 mutex_init(&sm->clock_lock);
1306 spin_lock_init(&sm->reg_lock);
1308 INIT_LIST_HEAD(&sm->devices);
1310 devid = readl(sm->regs + SM501_DEVICEID);
1312 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1313 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1318 writel(0, sm->regs + SM501_IRQ_MASK);
1320 dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
1321 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1323 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1324 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1326 sm->rev = devid & SM501_DEVICEID_REVMASK;
1328 sm501_dump_gate(sm);
1330 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1332 dev_err(sm->dev, "failed to create debug regs file\n");
1336 /* check to see if we have some device initialisation */
1338 pdata = sm->platdata;
1339 idata = pdata ? pdata->init : NULL;
1342 sm501_init_regs(sm, idata);
1344 if (idata->devices & SM501_USE_USB_HOST)
1345 sm501_register_usbhost(sm, &mem_avail);
1346 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1347 sm501_register_uart(sm, idata->devices);
1348 if (idata->devices & SM501_USE_GPIO)
1349 sm501_register_gpio(sm);
1352 if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
1353 if (!sm501_gpio_isregistered(sm))
1354 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1356 sm501_register_gpio_i2c(sm, pdata);
1359 ret = sm501_check_clocks(sm);
1361 dev_err(sm->dev, "M1X and M clocks sourced from different "
1366 /* always create a framebuffer */
1367 sm501_register_display(sm, &mem_avail);
1372 static int sm501_plat_probe(struct platform_device *dev)
1374 struct sm501_devdata *sm;
1377 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1379 dev_err(&dev->dev, "no memory for device data\n");
1384 sm->dev = &dev->dev;
1385 sm->pdev_id = dev->id;
1386 sm->irq = platform_get_irq(dev, 0);
1387 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1388 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1389 sm->platdata = dev->dev.platform_data;
1392 dev_err(&dev->dev, "failed to get irq resource\n");
1397 if (sm->io_res == NULL || sm->mem_res == NULL) {
1398 dev_err(&dev->dev, "failed to get IO resource\n");
1403 sm->regs_claim = request_mem_region(sm->io_res->start,
1406 if (sm->regs_claim == NULL) {
1407 dev_err(&dev->dev, "cannot claim registers\n");
1412 platform_set_drvdata(dev, sm);
1414 sm->regs = ioremap(sm->io_res->start,
1415 (sm->io_res->end - sm->io_res->start) - 1);
1417 if (sm->regs == NULL) {
1418 dev_err(&dev->dev, "cannot remap registers\n");
1423 return sm501_init_dev(sm);
1426 release_resource(sm->regs_claim);
1427 kfree(sm->regs_claim);
1437 /* power management support */
1439 static void sm501_set_power(struct sm501_devdata *sm, int on)
1441 struct sm501_platdata *pd = sm->platdata;
1446 if (pd->get_power) {
1447 if (pd->get_power(sm->dev) == on) {
1448 dev_dbg(sm->dev, "is already %d\n", on);
1453 if (pd->set_power) {
1454 dev_dbg(sm->dev, "setting power to %d\n", on);
1456 pd->set_power(sm->dev, on);
1457 sm501_mdelay(sm, 10);
1461 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1463 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1466 sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
1468 sm501_dump_regs(sm);
1471 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1472 sm501_set_power(sm, 0);
1478 static int sm501_plat_resume(struct platform_device *pdev)
1480 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1482 sm501_set_power(sm, 1);
1484 sm501_dump_regs(sm);
1485 sm501_dump_gate(sm);
1488 /* check to see if we are in the same state as when suspended */
1490 if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1491 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1492 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1494 /* our suspend causes the controller state to change,
1495 * either by something attempting setup, power loss,
1496 * or an external reset event on power change */
1498 if (sm->platdata && sm->platdata->init) {
1499 sm501_init_regs(sm, sm->platdata->init);
1503 /* dump our state from resume */
1505 sm501_dump_regs(sm);
1513 #define sm501_plat_suspend NULL
1514 #define sm501_plat_resume NULL
1517 /* Initialisation data for PCI devices */
1519 static struct sm501_initdata sm501_pci_initdata = {
1521 .set = 0x3F000000, /* 24bit panel */
1525 .set = 0x010100, /* SDRAM timing */
1529 .set = SM501_MISC_PNL_24BIT,
1533 .devices = SM501_USE_ALL,
1535 /* Errata AB-3 says that 72MHz is the fastest available
1536 * for 33MHZ PCI with proper bus-mastering operation */
1539 .m1xclk = 144 * MHZ,
1542 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1543 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1544 SM501FB_FLAG_USE_HWCURSOR |
1545 SM501FB_FLAG_USE_HWACCEL |
1546 SM501FB_FLAG_DISABLE_AT_EXIT),
1549 static struct sm501_platdata_fb sm501_fb_pdata = {
1550 .fb_route = SM501_FB_OWN,
1551 .fb_crt = &sm501_pdata_fbsub,
1552 .fb_pnl = &sm501_pdata_fbsub,
1555 static struct sm501_platdata sm501_pci_platdata = {
1556 .init = &sm501_pci_initdata,
1557 .fb = &sm501_fb_pdata,
1561 static int sm501_pci_probe(struct pci_dev *dev,
1562 const struct pci_device_id *id)
1564 struct sm501_devdata *sm;
1567 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1569 dev_err(&dev->dev, "no memory for device data\n");
1574 /* set a default set of platform data */
1575 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1577 /* set a hopefully unique id for our child platform devices */
1578 sm->pdev_id = 32 + dev->devfn;
1580 pci_set_drvdata(dev, sm);
1582 err = pci_enable_device(dev);
1584 dev_err(&dev->dev, "cannot enable device\n");
1588 sm->dev = &dev->dev;
1592 /* if the system is big-endian, we most probably have a
1593 * translation in the IO layer making the PCI bus little endian
1594 * so make the framebuffer swapped pixels */
1596 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1599 /* check our resources */
1601 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1602 dev_err(&dev->dev, "region #0 is not memory?\n");
1607 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1608 dev_err(&dev->dev, "region #1 is not memory?\n");
1613 /* make our resources ready for sharing */
1615 sm->io_res = &dev->resource[1];
1616 sm->mem_res = &dev->resource[0];
1618 sm->regs_claim = request_mem_region(sm->io_res->start,
1620 if (sm->regs_claim == NULL) {
1621 dev_err(&dev->dev, "cannot claim registers\n");
1626 sm->regs = ioremap(pci_resource_start(dev, 1),
1627 pci_resource_len(dev, 1));
1629 if (sm->regs == NULL) {
1630 dev_err(&dev->dev, "cannot remap registers\n");
1639 release_resource(sm->regs_claim);
1640 kfree(sm->regs_claim);
1642 pci_disable_device(dev);
1644 pci_set_drvdata(dev, NULL);
1650 static void sm501_remove_sub(struct sm501_devdata *sm,
1651 struct sm501_device *smdev)
1653 list_del(&smdev->list);
1654 platform_device_unregister(&smdev->pdev);
1657 static void sm501_dev_remove(struct sm501_devdata *sm)
1659 struct sm501_device *smdev, *tmp;
1661 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1662 sm501_remove_sub(sm, smdev);
1664 device_remove_file(sm->dev, &dev_attr_dbg_regs);
1666 sm501_gpio_remove(sm);
1669 static void sm501_pci_remove(struct pci_dev *dev)
1671 struct sm501_devdata *sm = pci_get_drvdata(dev);
1673 sm501_dev_remove(sm);
1676 release_resource(sm->regs_claim);
1677 kfree(sm->regs_claim);
1679 pci_set_drvdata(dev, NULL);
1680 pci_disable_device(dev);
1683 static int sm501_plat_remove(struct platform_device *dev)
1685 struct sm501_devdata *sm = platform_get_drvdata(dev);
1687 sm501_dev_remove(sm);
1690 release_resource(sm->regs_claim);
1691 kfree(sm->regs_claim);
1696 static struct pci_device_id sm501_pci_tbl[] = {
1697 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1701 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1703 static struct pci_driver sm501_pci_drv = {
1705 .id_table = sm501_pci_tbl,
1706 .probe = sm501_pci_probe,
1707 .remove = sm501_pci_remove,
1710 MODULE_ALIAS("platform:sm501");
1712 static struct platform_driver sm501_plat_drv = {
1715 .owner = THIS_MODULE,
1717 .probe = sm501_plat_probe,
1718 .remove = sm501_plat_remove,
1719 .suspend = sm501_plat_suspend,
1720 .resume = sm501_plat_resume,
1723 static int __init sm501_base_init(void)
1725 platform_driver_register(&sm501_plat_drv);
1726 return pci_register_driver(&sm501_pci_drv);
1729 static void __exit sm501_base_exit(void)
1731 platform_driver_unregister(&sm501_plat_drv);
1732 pci_unregister_driver(&sm501_pci_drv);
1735 module_init(sm501_base_init);
1736 module_exit(sm501_base_exit);
1738 MODULE_DESCRIPTION("SM501 Core Driver");
1739 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1740 MODULE_LICENSE("GPL v2");