drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-tuner.h"
  33 #include "pvrusb2-eeprom.h"
  34 #include "pvrusb2-hdw-internal.h"
  35 #include "pvrusb2-encoder.h"
  36 #include "pvrusb2-debug.h"
  37 #include "pvrusb2-fx2-cmd.h"
  38
  39 #define TV_MIN_FREQ     55250000L
  40 #define TV_MAX_FREQ    850000000L
  41
  42 /* This defines a minimum interval that the decoder must remain quiet
  43    before we are allowed to start it running. */
  44 #define TIME_MSEC_DECODER_WAIT 50
  45
  46 /* This defines a minimum interval that the encoder must remain quiet
  47    before we are allowed to configure it.  I had this originally set to
  48    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  49    things work better when it's set to 100msec. */
  50 #define TIME_MSEC_ENCODER_WAIT 100
  51
  52 /* This defines the minimum interval that the encoder must successfully run
  53    before we consider that the encoder has run at least once since its
  54    firmware has been loaded.  This measurement is in important for cases
  55    where we can't do something until we know that the encoder has been run
  56    at least once. */
  57 #define TIME_MSEC_ENCODER_OK 250
  58
  59 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  60 static DEFINE_MUTEX(pvr2_unit_mtx);
  61
  62 static int ctlchg;
  63 static int initusbreset = 1;
  64 static int procreload;
  65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  68 static int init_pause_msec;
  69
  70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  74 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  76 module_param(procreload, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(procreload,
  78                  "Attempt init failure recovery with firmware reload");
  79 module_param_array(tuner,    int, NULL, 0444);
  80 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  81 module_param_array(video_std,    int, NULL, 0444);
  82 MODULE_PARM_DESC(video_std,"specify initial video standard");
  83 module_param_array(tolerance,    int, NULL, 0444);
  84 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  85
  86 /* US Broadcast channel 7 (175.25 MHz) */
  87 static int default_tv_freq    = 175250000L;
  88 /* 104.3 MHz, a usable FM station for my area */
  89 static int default_radio_freq = 104300000L;
  90
  91 module_param_named(tv_freq, default_tv_freq, int, 0444);
  92 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  93 module_param_named(radio_freq, default_radio_freq, int, 0444);
  94 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  95
  96 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  97 #define PVR2_CTL_READ_ENDPOINT   0x81
  98
  99 #define PVR2_GPIO_IN 0x9008
 100 #define PVR2_GPIO_OUT 0x900c
 101 #define PVR2_GPIO_DIR 0x9020
 102
 103 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 104
 105 #define PVR2_FIRMWARE_ENDPOINT   0x02
 106
 107 /* size of a firmware chunk */
 108 #define FIRMWARE_CHUNK_SIZE 0x2000
 109
 110 /* Define the list of additional controls we'll dynamically construct based
 111    on query of the cx2341x module. */
 112 struct pvr2_mpeg_ids {
 113         const char *strid;
 114         int id;
 115 };
 116 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 117         {
 118                 .strid = "audio_layer",
 119                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 120         },{
 121                 .strid = "audio_bitrate",
 122                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 123         },{
 124                 /* Already using audio_mode elsewhere :-( */
 125                 .strid = "mpeg_audio_mode",
 126                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 127         },{
 128                 .strid = "mpeg_audio_mode_extension",
 129                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 130         },{
 131                 .strid = "audio_emphasis",
 132                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 133         },{
 134                 .strid = "audio_crc",
 135                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 136         },{
 137                 .strid = "video_aspect",
 138                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 139         },{
 140                 .strid = "video_b_frames",
 141                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 142         },{
 143                 .strid = "video_gop_size",
 144                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 145         },{
 146                 .strid = "video_gop_closure",
 147                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 148         },{
 149                 .strid = "video_bitrate_mode",
 150                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 151         },{
 152                 .strid = "video_bitrate",
 153                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 154         },{
 155                 .strid = "video_bitrate_peak",
 156                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 157         },{
 158                 .strid = "video_temporal_decimation",
 159                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 160         },{
 161                 .strid = "stream_type",
 162                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 163         },{
 164                 .strid = "video_spatial_filter_mode",
 165                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 166         },{
 167                 .strid = "video_spatial_filter",
 168                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 169         },{
 170                 .strid = "video_luma_spatial_filter_type",
 171                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 172         },{
 173                 .strid = "video_chroma_spatial_filter_type",
 174                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 175         },{
 176                 .strid = "video_temporal_filter_mode",
 177                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 178         },{
 179                 .strid = "video_temporal_filter",
 180                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 181         },{
 182                 .strid = "video_median_filter_type",
 183                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 184         },{
 185                 .strid = "video_luma_median_filter_top",
 186                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 187         },{
 188                 .strid = "video_luma_median_filter_bottom",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 190         },{
 191                 .strid = "video_chroma_median_filter_top",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 193         },{
 194                 .strid = "video_chroma_median_filter_bottom",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 196         }
 197 };
 198 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 199
 200
 201 static const char *control_values_srate[] = {
 202         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 203         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 204         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 205 };
 206
 207
 208
 209 static const char *control_values_input[] = {
 210         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 211         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 212         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 213         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 214         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 215 };
 216
 217
 218 static const char *control_values_audiomode[] = {
 219         [V4L2_TUNER_MODE_MONO]   = "Mono",
 220         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 221         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 222         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 223         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 224 };
 225
 226
 227 static const char *control_values_hsm[] = {
 228         [PVR2_CVAL_HSM_FAIL] = "Fail",
 229         [PVR2_CVAL_HSM_HIGH] = "High",
 230         [PVR2_CVAL_HSM_FULL] = "Full",
 231 };
 232
 233
 234 static const char *pvr2_state_names[] = {
 235         [PVR2_STATE_NONE] =    "none",
 236         [PVR2_STATE_DEAD] =    "dead",
 237         [PVR2_STATE_COLD] =    "cold",
 238         [PVR2_STATE_WARM] =    "warm",
 239         [PVR2_STATE_ERROR] =   "error",
 240         [PVR2_STATE_READY] =   "ready",
 241         [PVR2_STATE_RUN] =     "run",
 242 };
 243
 244
 245 struct pvr2_fx2cmd_descdef {
 246         unsigned char id;
 247         unsigned char *desc;
 248 };
 249
 250 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 251         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 252         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 253         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 254         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 255         {FX2CMD_REG_WRITE, "write encoder register"},
 256         {FX2CMD_REG_READ, "read encoder register"},
 257         {FX2CMD_MEMSEL, "encoder memsel"},
 258         {FX2CMD_I2C_WRITE, "i2c write"},
 259         {FX2CMD_I2C_READ, "i2c read"},
 260         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 261         {FX2CMD_STREAMING_ON, "stream on"},
 262         {FX2CMD_STREAMING_OFF, "stream off"},
 263         {FX2CMD_FWPOST1, "fwpost1"},
 264         {FX2CMD_POWER_OFF, "power off"},
 265         {FX2CMD_POWER_ON, "power on"},
 266         {FX2CMD_DEEP_RESET, "deep reset"},
 267         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 268         {FX2CMD_GET_IR_CODE, "get IR code"},
 269         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 270         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 271         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 272         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 273         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 274         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 275         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 276 };
 277
 278
 279 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 280 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 281 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 282 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 283 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 284 static void pvr2_hdw_worker_poll(struct work_struct *work);
 285 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 286 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 287 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 288 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 289 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 290 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 291 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 292 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 293 static void pvr2_hdw_quiescent_timeout(unsigned long);
 294 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 295 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 296 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 297 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 298                                 unsigned int timeout,int probe_fl,
 299                                 void *write_data,unsigned int write_len,
 300                                 void *read_data,unsigned int read_len);
 301 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 302
 303
 304 static void trace_stbit(const char *name,int val)
 305 {
 306         pvr2_trace(PVR2_TRACE_STBITS,
 307                    "State bit %s <-- %s",
 308                    name,(val ? "true" : "false"));
 309 }
 310
 311 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 312 {
 313         struct pvr2_hdw *hdw = cptr->hdw;
 314         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 315                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 316         } else {
 317                 *vp = 0;
 318         }
 319         return 0;
 320 }
 321
 322 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 323 {
 324         struct pvr2_hdw *hdw = cptr->hdw;
 325         unsigned int slotId = hdw->freqProgSlot;
 326         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 327                 hdw->freqTable[slotId-1] = v;
 328                 /* Handle side effects correctly - if we're tuned to this
 329                    slot, then forgot the slot id relation since the stored
 330                    frequency has been changed. */
 331                 if (hdw->freqSelector) {
 332                         if (hdw->freqSlotRadio == slotId) {
 333                                 hdw->freqSlotRadio = 0;
 334                         }
 335                 } else {
 336                         if (hdw->freqSlotTelevision == slotId) {
 337                                 hdw->freqSlotTelevision = 0;
 338                         }
 339                 }
 340         }
 341         return 0;
 342 }
 343
 344 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 345 {
 346         *vp = cptr->hdw->freqProgSlot;
 347         return 0;
 348 }
 349
 350 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 351 {
 352         struct pvr2_hdw *hdw = cptr->hdw;
 353         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 354                 hdw->freqProgSlot = v;
 355         }
 356         return 0;
 357 }
 358
 359 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 360 {
 361         struct pvr2_hdw *hdw = cptr->hdw;
 362         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 363         return 0;
 364 }
 365
 366 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 367 {
 368         unsigned freq = 0;
 369         struct pvr2_hdw *hdw = cptr->hdw;
 370         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 371         if (slotId > 0) {
 372                 freq = hdw->freqTable[slotId-1];
 373                 if (!freq) return 0;
 374                 pvr2_hdw_set_cur_freq(hdw,freq);
 375         }
 376         if (hdw->freqSelector) {
 377                 hdw->freqSlotRadio = slotId;
 378         } else {
 379                 hdw->freqSlotTelevision = slotId;
 380         }
 381         return 0;
 382 }
 383
 384 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 385 {
 386         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 387         return 0;
 388 }
 389
 390 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 391 {
 392         return cptr->hdw->freqDirty != 0;
 393 }
 394
 395 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 396 {
 397         cptr->hdw->freqDirty = 0;
 398 }
 399
 400 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 401 {
 402         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 403         return 0;
 404 }
 405
 406 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 407 {
 408         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 409         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 410         if (stat != 0) {
 411                 return stat;
 412         }
 413         *left = cap->bounds.left;
 414         return 0;
 415 }
 416
 417 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 418 {
 419         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 420         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 421         if (stat != 0) {
 422                 return stat;
 423         }
 424         *left = cap->bounds.left;
 425         if (cap->bounds.width > cptr->hdw->cropw_val) {
 426                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 427         }
 428         return 0;
 429 }
 430
 431 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 432 {
 433         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 434         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 435         if (stat != 0) {
 436                 return stat;
 437         }
 438         *top = cap->bounds.top;
 439         return 0;
 440 }
 441
 442 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 443 {
 444         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 445         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 446         if (stat != 0) {
 447                 return stat;
 448         }
 449         *top = cap->bounds.top;
 450         if (cap->bounds.height > cptr->hdw->croph_val) {
 451                 *top += cap->bounds.height - cptr->hdw->croph_val;
 452         }
 453         return 0;
 454 }
 455
 456 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 457 {
 458         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 459         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 460         if (stat != 0) {
 461                 return stat;
 462         }
 463         *val = 0;
 464         if (cap->bounds.width > cptr->hdw->cropl_val) {
 465                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 466         }
 467         return 0;
 468 }
 469
 470 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 471 {
 472         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 473         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 474         if (stat != 0) {
 475                 return stat;
 476         }
 477         *val = 0;
 478         if (cap->bounds.height > cptr->hdw->cropt_val) {
 479                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 480         }
 481         return 0;
 482 }
 483
 484 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 485 {
 486         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 487         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 488         if (stat != 0) {
 489                 return stat;
 490         }
 491         *val = cap->bounds.left;
 492         return 0;
 493 }
 494
 495 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 496 {
 497         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 498         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 499         if (stat != 0) {
 500                 return stat;
 501         }
 502         *val = cap->bounds.top;
 503         return 0;
 504 }
 505
 506 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 507 {
 508         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 509         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 510         if (stat != 0) {
 511                 return stat;
 512         }
 513         *val = cap->bounds.width;
 514         return 0;
 515 }
 516
 517 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 518 {
 519         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 520         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 521         if (stat != 0) {
 522                 return stat;
 523         }
 524         *val = cap->bounds.height;
 525         return 0;
 526 }
 527
 528 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 529 {
 530         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 531         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 532         if (stat != 0) {
 533                 return stat;
 534         }
 535         *val = cap->defrect.left;
 536         return 0;
 537 }
 538
 539 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 540 {
 541         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 542         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 543         if (stat != 0) {
 544                 return stat;
 545         }
 546         *val = cap->defrect.top;
 547         return 0;
 548 }
 549
 550 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 551 {
 552         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 553         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 554         if (stat != 0) {
 555                 return stat;
 556         }
 557         *val = cap->defrect.width;
 558         return 0;
 559 }
 560
 561 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 562 {
 563         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 564         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 565         if (stat != 0) {
 566                 return stat;
 567         }
 568         *val = cap->defrect.height;
 569         return 0;
 570 }
 571
 572 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 573 {
 574         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 575         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 576         if (stat != 0) {
 577                 return stat;
 578         }
 579         *val = cap->pixelaspect.numerator;
 580         return 0;
 581 }
 582
 583 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 584 {
 585         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 586         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 587         if (stat != 0) {
 588                 return stat;
 589         }
 590         *val = cap->pixelaspect.denominator;
 591         return 0;
 592 }
 593
 594 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 595 {
 596         /* Actual maximum depends on the video standard in effect. */
 597         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 598                 *vp = 480;
 599         } else {
 600                 *vp = 576;
 601         }
 602         return 0;
 603 }
 604
 605 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 606 {
 607         /* Actual minimum depends on device digitizer type. */
 608         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 609                 *vp = 75;
 610         } else {
 611                 *vp = 17;
 612         }
 613         return 0;
 614 }
 615
 616 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 617 {
 618         *vp = cptr->hdw->input_val;
 619         return 0;
 620 }
 621
 622 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 623 {
 624         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 625 }
 626
 627 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 628 {
 629         return pvr2_hdw_set_input(cptr->hdw,v);
 630 }
 631
 632 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 633 {
 634         return cptr->hdw->input_dirty != 0;
 635 }
 636
 637 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 638 {
 639         cptr->hdw->input_dirty = 0;
 640 }
 641
 642
 643 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 644 {
 645         unsigned long fv;
 646         struct pvr2_hdw *hdw = cptr->hdw;
 647         if (hdw->tuner_signal_stale) {
 648                 pvr2_i2c_core_status_poll(hdw);
 649         }
 650         fv = hdw->tuner_signal_info.rangehigh;
 651         if (!fv) {
 652                 /* Safety fallback */
 653                 *vp = TV_MAX_FREQ;
 654                 return 0;
 655         }
 656         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 657                 fv = (fv * 125) / 2;
 658         } else {
 659                 fv = fv * 62500;
 660         }
 661         *vp = fv;
 662         return 0;
 663 }
 664
 665 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 666 {
 667         unsigned long fv;
 668         struct pvr2_hdw *hdw = cptr->hdw;
 669         if (hdw->tuner_signal_stale) {
 670                 pvr2_i2c_core_status_poll(hdw);
 671         }
 672         fv = hdw->tuner_signal_info.rangelow;
 673         if (!fv) {
 674                 /* Safety fallback */
 675                 *vp = TV_MIN_FREQ;
 676                 return 0;
 677         }
 678         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 679                 fv = (fv * 125) / 2;
 680         } else {
 681                 fv = fv * 62500;
 682         }
 683         *vp = fv;
 684         return 0;
 685 }
 686
 687 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 688 {
 689         return cptr->hdw->enc_stale != 0;
 690 }
 691
 692 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 693 {
 694         cptr->hdw->enc_stale = 0;
 695         cptr->hdw->enc_unsafe_stale = 0;
 696 }
 697
 698 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 699 {
 700         int ret;
 701         struct v4l2_ext_controls cs;
 702         struct v4l2_ext_control c1;
 703         memset(&cs,0,sizeof(cs));
 704         memset(&c1,0,sizeof(c1));
 705         cs.controls = &c1;
 706         cs.count = 1;
 707         c1.id = cptr->info->v4l_id;
 708         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 709                                 VIDIOC_G_EXT_CTRLS);
 710         if (ret) return ret;
 711         *vp = c1.value;
 712         return 0;
 713 }
 714
 715 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 716 {
 717         int ret;
 718         struct pvr2_hdw *hdw = cptr->hdw;
 719         struct v4l2_ext_controls cs;
 720         struct v4l2_ext_control c1;
 721         memset(&cs,0,sizeof(cs));
 722         memset(&c1,0,sizeof(c1));
 723         cs.controls = &c1;
 724         cs.count = 1;
 725         c1.id = cptr->info->v4l_id;
 726         c1.value = v;
 727         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 728                                 hdw->state_encoder_run, &cs,
 729                                 VIDIOC_S_EXT_CTRLS);
 730         if (ret == -EBUSY) {
 731                 /* Oops.  cx2341x is telling us it's not safe to change
 732                    this control while we're capturing.  Make a note of this
 733                    fact so that the pipeline will be stopped the next time
 734                    controls are committed.  Then go on ahead and store this
 735                    change anyway. */
 736                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 737                                         0, &cs,
 738                                         VIDIOC_S_EXT_CTRLS);
 739                 if (!ret) hdw->enc_unsafe_stale = !0;
 740         }
 741         if (ret) return ret;
 742         hdw->enc_stale = !0;
 743         return 0;
 744 }
 745
 746 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 747 {
 748         struct v4l2_queryctrl qctrl;
 749         struct pvr2_ctl_info *info;
 750         qctrl.id = cptr->info->v4l_id;
 751         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 752         /* Strip out the const so we can adjust a function pointer.  It's
 753            OK to do this here because we know this is a dynamically created
 754            control, so the underlying storage for the info pointer is (a)
 755            private to us, and (b) not in read-only storage.  Either we do
 756            this or we significantly complicate the underlying control
 757            implementation. */
 758         info = (struct pvr2_ctl_info *)(cptr->info);
 759         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 760                 if (info->set_value) {
 761                         info->set_value = NULL;
 762                 }
 763         } else {
 764                 if (!(info->set_value)) {
 765                         info->set_value = ctrl_cx2341x_set;
 766                 }
 767         }
 768         return qctrl.flags;
 769 }
 770
 771 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 772 {
 773         *vp = cptr->hdw->state_pipeline_req;
 774         return 0;
 775 }
 776
 777 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 778 {
 779         *vp = cptr->hdw->master_state;
 780         return 0;
 781 }
 782
 783 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 784 {
 785         int result = pvr2_hdw_is_hsm(cptr->hdw);
 786         *vp = PVR2_CVAL_HSM_FULL;
 787         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 788         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 789         return 0;
 790 }
 791
 792 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 793 {
 794         *vp = cptr->hdw->std_mask_avail;
 795         return 0;
 796 }
 797
 798 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 799 {
 800         struct pvr2_hdw *hdw = cptr->hdw;
 801         v4l2_std_id ns;
 802         ns = hdw->std_mask_avail;
 803         ns = (ns & ~m) | (v & m);
 804         if (ns == hdw->std_mask_avail) return 0;
 805         hdw->std_mask_avail = ns;
 806         pvr2_hdw_internal_set_std_avail(hdw);
 807         pvr2_hdw_internal_find_stdenum(hdw);
 808         return 0;
 809 }
 810
 811 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 812                                char *bufPtr,unsigned int bufSize,
 813                                unsigned int *len)
 814 {
 815         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 816         return 0;
 817 }
 818
 819 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 820                                const char *bufPtr,unsigned int bufSize,
 821                                int *mskp,int *valp)
 822 {
 823         int ret;
 824         v4l2_std_id id;
 825         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 826         if (ret < 0) return ret;
 827         if (mskp) *mskp = id;
 828         if (valp) *valp = id;
 829         return 0;
 830 }
 831
 832 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 833 {
 834         *vp = cptr->hdw->std_mask_cur;
 835         return 0;
 836 }
 837
 838 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 839 {
 840         struct pvr2_hdw *hdw = cptr->hdw;
 841         v4l2_std_id ns;
 842         ns = hdw->std_mask_cur;
 843         ns = (ns & ~m) | (v & m);
 844         if (ns == hdw->std_mask_cur) return 0;
 845         hdw->std_mask_cur = ns;
 846         hdw->std_dirty = !0;
 847         pvr2_hdw_internal_find_stdenum(hdw);
 848         return 0;
 849 }
 850
 851 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 852 {
 853         return cptr->hdw->std_dirty != 0;
 854 }
 855
 856 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 857 {
 858         cptr->hdw->std_dirty = 0;
 859 }
 860
 861 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 862 {
 863         struct pvr2_hdw *hdw = cptr->hdw;
 864         pvr2_i2c_core_status_poll(hdw);
 865         *vp = hdw->tuner_signal_info.signal;
 866         return 0;
 867 }
 868
 869 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 870 {
 871         int val = 0;
 872         unsigned int subchan;
 873         struct pvr2_hdw *hdw = cptr->hdw;
 874         pvr2_i2c_core_status_poll(hdw);
 875         subchan = hdw->tuner_signal_info.rxsubchans;
 876         if (subchan & V4L2_TUNER_SUB_MONO) {
 877                 val |= (1 << V4L2_TUNER_MODE_MONO);
 878         }
 879         if (subchan & V4L2_TUNER_SUB_STEREO) {
 880                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 881         }
 882         if (subchan & V4L2_TUNER_SUB_LANG1) {
 883                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 884         }
 885         if (subchan & V4L2_TUNER_SUB_LANG2) {
 886                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 887         }
 888         *vp = val;
 889         return 0;
 890 }
 891
 892
 893 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 894 {
 895         struct pvr2_hdw *hdw = cptr->hdw;
 896         if (v < 0) return -EINVAL;
 897         if (v > hdw->std_enum_cnt) return -EINVAL;
 898         hdw->std_enum_cur = v;
 899         if (!v) return 0;
 900         v--;
 901         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 902         hdw->std_mask_cur = hdw->std_defs[v].id;
 903         hdw->std_dirty = !0;
 904         return 0;
 905 }
 906
 907
 908 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 909 {
 910         *vp = cptr->hdw->std_enum_cur;
 911         return 0;
 912 }
 913
 914
 915 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 916 {
 917         return cptr->hdw->std_dirty != 0;
 918 }
 919
 920
 921 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 922 {
 923         cptr->hdw->std_dirty = 0;
 924 }
 925
 926
 927 #define DEFINT(vmin,vmax) \
 928         .type = pvr2_ctl_int, \
 929         .def.type_int.min_value = vmin, \
 930         .def.type_int.max_value = vmax
 931
 932 #define DEFENUM(tab) \
 933         .type = pvr2_ctl_enum, \
 934         .def.type_enum.count = ARRAY_SIZE(tab), \
 935         .def.type_enum.value_names = tab
 936
 937 #define DEFBOOL \
 938         .type = pvr2_ctl_bool
 939
 940 #define DEFMASK(msk,tab) \
 941         .type = pvr2_ctl_bitmask, \
 942         .def.type_bitmask.valid_bits = msk, \
 943         .def.type_bitmask.bit_names = tab
 944
 945 #define DEFREF(vname) \
 946         .set_value = ctrl_set_##vname, \
 947         .get_value = ctrl_get_##vname, \
 948         .is_dirty = ctrl_isdirty_##vname, \
 949         .clear_dirty = ctrl_cleardirty_##vname
 950
 951
 952 #define VCREATE_FUNCS(vname) \
 953 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 954 {*vp = cptr->hdw->vname##_val; return 0;} \
 955 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 956 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 957 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 958 {return cptr->hdw->vname##_dirty != 0;} \
 959 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 960 {cptr->hdw->vname##_dirty = 0;}
 961
 962 VCREATE_FUNCS(brightness)
 963 VCREATE_FUNCS(contrast)
 964 VCREATE_FUNCS(saturation)
 965 VCREATE_FUNCS(hue)
 966 VCREATE_FUNCS(volume)
 967 VCREATE_FUNCS(balance)
 968 VCREATE_FUNCS(bass)
 969 VCREATE_FUNCS(treble)
 970 VCREATE_FUNCS(mute)
 971 VCREATE_FUNCS(cropl)
 972 VCREATE_FUNCS(cropt)
 973 VCREATE_FUNCS(cropw)
 974 VCREATE_FUNCS(croph)
 975 VCREATE_FUNCS(audiomode)
 976 VCREATE_FUNCS(res_hor)
 977 VCREATE_FUNCS(res_ver)
 978 VCREATE_FUNCS(srate)
 979
 980 /* Table definition of all controls which can be manipulated */
 981 static const struct pvr2_ctl_info control_defs[] = {
 982         {
 983                 .v4l_id = V4L2_CID_BRIGHTNESS,
 984                 .desc = "Brightness",
 985                 .name = "brightness",
 986                 .default_value = 128,
 987                 DEFREF(brightness),
 988                 DEFINT(0,255),
 989         },{
 990                 .v4l_id = V4L2_CID_CONTRAST,
 991                 .desc = "Contrast",
 992                 .name = "contrast",
 993                 .default_value = 68,
 994                 DEFREF(contrast),
 995                 DEFINT(0,127),
 996         },{
 997                 .v4l_id = V4L2_CID_SATURATION,
 998                 .desc = "Saturation",
 999                 .name = "saturation",
1000                 .default_value = 64,
1001                 DEFREF(saturation),
1002                 DEFINT(0,127),
1003         },{
1004                 .v4l_id = V4L2_CID_HUE,
1005                 .desc = "Hue",
1006                 .name = "hue",
1007                 .default_value = 0,
1008                 DEFREF(hue),
1009                 DEFINT(-128,127),
1010         },{
1011                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1012                 .desc = "Volume",
1013                 .name = "volume",
1014                 .default_value = 62000,
1015                 DEFREF(volume),
1016                 DEFINT(0,65535),
1017         },{
1018                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1019                 .desc = "Balance",
1020                 .name = "balance",
1021                 .default_value = 0,
1022                 DEFREF(balance),
1023                 DEFINT(-32768,32767),
1024         },{
1025                 .v4l_id = V4L2_CID_AUDIO_BASS,
1026                 .desc = "Bass",
1027                 .name = "bass",
1028                 .default_value = 0,
1029                 DEFREF(bass),
1030                 DEFINT(-32768,32767),
1031         },{
1032                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1033                 .desc = "Treble",
1034                 .name = "treble",
1035                 .default_value = 0,
1036                 DEFREF(treble),
1037                 DEFINT(-32768,32767),
1038         },{
1039                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1040                 .desc = "Mute",
1041                 .name = "mute",
1042                 .default_value = 0,
1043                 DEFREF(mute),
1044                 DEFBOOL,
1045         }, {
1046                 .desc = "Capture crop left margin",
1047                 .name = "crop_left",
1048                 .internal_id = PVR2_CID_CROPL,
1049                 .default_value = 0,
1050                 DEFREF(cropl),
1051                 DEFINT(-129, 340),
1052                 .get_min_value = ctrl_cropl_min_get,
1053                 .get_max_value = ctrl_cropl_max_get,
1054                 .get_def_value = ctrl_get_cropcapdl,
1055         }, {
1056                 .desc = "Capture crop top margin",
1057                 .name = "crop_top",
1058                 .internal_id = PVR2_CID_CROPT,
1059                 .default_value = 0,
1060                 DEFREF(cropt),
1061                 DEFINT(-35, 544),
1062                 .get_min_value = ctrl_cropt_min_get,
1063                 .get_max_value = ctrl_cropt_max_get,
1064                 .get_def_value = ctrl_get_cropcapdt,
1065         }, {
1066                 .desc = "Capture crop width",
1067                 .name = "crop_width",
1068                 .internal_id = PVR2_CID_CROPW,
1069                 .default_value = 720,
1070                 DEFREF(cropw),
1071                 .get_max_value = ctrl_cropw_max_get,
1072                 .get_def_value = ctrl_get_cropcapdw,
1073         }, {
1074                 .desc = "Capture crop height",
1075                 .name = "crop_height",
1076                 .internal_id = PVR2_CID_CROPH,
1077                 .default_value = 480,
1078                 DEFREF(croph),
1079                 .get_max_value = ctrl_croph_max_get,
1080                 .get_def_value = ctrl_get_cropcapdh,
1081         }, {
1082                 .desc = "Capture capability pixel aspect numerator",
1083                 .name = "cropcap_pixel_numerator",
1084                 .internal_id = PVR2_CID_CROPCAPPAN,
1085                 .get_value = ctrl_get_cropcappan,
1086         }, {
1087                 .desc = "Capture capability pixel aspect denominator",
1088                 .name = "cropcap_pixel_denominator",
1089                 .internal_id = PVR2_CID_CROPCAPPAD,
1090                 .get_value = ctrl_get_cropcappad,
1091         }, {
1092                 .desc = "Capture capability bounds top",
1093                 .name = "cropcap_bounds_top",
1094                 .internal_id = PVR2_CID_CROPCAPBT,
1095                 .get_value = ctrl_get_cropcapbt,
1096         }, {
1097                 .desc = "Capture capability bounds left",
1098                 .name = "cropcap_bounds_left",
1099                 .internal_id = PVR2_CID_CROPCAPBL,
1100                 .get_value = ctrl_get_cropcapbl,
1101         }, {
1102                 .desc = "Capture capability bounds width",
1103                 .name = "cropcap_bounds_width",
1104                 .internal_id = PVR2_CID_CROPCAPBW,
1105                 .get_value = ctrl_get_cropcapbw,
1106         }, {
1107                 .desc = "Capture capability bounds height",
1108                 .name = "cropcap_bounds_height",
1109                 .internal_id = PVR2_CID_CROPCAPBH,
1110                 .get_value = ctrl_get_cropcapbh,
1111         },{
1112                 .desc = "Video Source",
1113                 .name = "input",
1114                 .internal_id = PVR2_CID_INPUT,
1115                 .default_value = PVR2_CVAL_INPUT_TV,
1116                 .check_value = ctrl_check_input,
1117                 DEFREF(input),
1118                 DEFENUM(control_values_input),
1119         },{
1120                 .desc = "Audio Mode",
1121                 .name = "audio_mode",
1122                 .internal_id = PVR2_CID_AUDIOMODE,
1123                 .default_value = V4L2_TUNER_MODE_STEREO,
1124                 DEFREF(audiomode),
1125                 DEFENUM(control_values_audiomode),
1126         },{
1127                 .desc = "Horizontal capture resolution",
1128                 .name = "resolution_hor",
1129                 .internal_id = PVR2_CID_HRES,
1130                 .default_value = 720,
1131                 DEFREF(res_hor),
1132                 DEFINT(19,720),
1133         },{
1134                 .desc = "Vertical capture resolution",
1135                 .name = "resolution_ver",
1136                 .internal_id = PVR2_CID_VRES,
1137                 .default_value = 480,
1138                 DEFREF(res_ver),
1139                 DEFINT(17,576),
1140                 /* Hook in check for video standard and adjust maximum
1141                    depending on the standard. */
1142                 .get_max_value = ctrl_vres_max_get,
1143                 .get_min_value = ctrl_vres_min_get,
1144         },{
1145                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1146                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1147                 .desc = "Audio Sampling Frequency",
1148                 .name = "srate",
1149                 DEFREF(srate),
1150                 DEFENUM(control_values_srate),
1151         },{
1152                 .desc = "Tuner Frequency (Hz)",
1153                 .name = "frequency",
1154                 .internal_id = PVR2_CID_FREQUENCY,
1155                 .default_value = 0,
1156                 .set_value = ctrl_freq_set,
1157                 .get_value = ctrl_freq_get,
1158                 .is_dirty = ctrl_freq_is_dirty,
1159                 .clear_dirty = ctrl_freq_clear_dirty,
1160                 DEFINT(0,0),
1161                 /* Hook in check for input value (tv/radio) and adjust
1162                    max/min values accordingly */
1163                 .get_max_value = ctrl_freq_max_get,
1164                 .get_min_value = ctrl_freq_min_get,
1165         },{
1166                 .desc = "Channel",
1167                 .name = "channel",
1168                 .set_value = ctrl_channel_set,
1169                 .get_value = ctrl_channel_get,
1170                 DEFINT(0,FREQTABLE_SIZE),
1171         },{
1172                 .desc = "Channel Program Frequency",
1173                 .name = "freq_table_value",
1174                 .set_value = ctrl_channelfreq_set,
1175                 .get_value = ctrl_channelfreq_get,
1176                 DEFINT(0,0),
1177                 /* Hook in check for input value (tv/radio) and adjust
1178                    max/min values accordingly */
1179                 .get_max_value = ctrl_freq_max_get,
1180                 .get_min_value = ctrl_freq_min_get,
1181         },{
1182                 .desc = "Channel Program ID",
1183                 .name = "freq_table_channel",
1184                 .set_value = ctrl_channelprog_set,
1185                 .get_value = ctrl_channelprog_get,
1186                 DEFINT(0,FREQTABLE_SIZE),
1187         },{
1188                 .desc = "Streaming Enabled",
1189                 .name = "streaming_enabled",
1190                 .get_value = ctrl_streamingenabled_get,
1191                 DEFBOOL,
1192         },{
1193                 .desc = "USB Speed",
1194                 .name = "usb_speed",
1195                 .get_value = ctrl_hsm_get,
1196                 DEFENUM(control_values_hsm),
1197         },{
1198                 .desc = "Master State",
1199                 .name = "master_state",
1200                 .get_value = ctrl_masterstate_get,
1201                 DEFENUM(pvr2_state_names),
1202         },{
1203                 .desc = "Signal Present",
1204                 .name = "signal_present",
1205                 .get_value = ctrl_signal_get,
1206                 DEFINT(0,65535),
1207         },{
1208                 .desc = "Audio Modes Present",
1209                 .name = "audio_modes_present",
1210                 .get_value = ctrl_audio_modes_present_get,
1211                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1212                    v4l.  Nothing outside of this module cares about this,
1213                    but I reuse it in order to also reuse the
1214                    control_values_audiomode string table. */
1215                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1216                          (1 << V4L2_TUNER_MODE_STEREO)|
1217                          (1 << V4L2_TUNER_MODE_LANG1)|
1218                          (1 << V4L2_TUNER_MODE_LANG2)),
1219                         control_values_audiomode),
1220         },{
1221                 .desc = "Video Standards Available Mask",
1222                 .name = "video_standard_mask_available",
1223                 .internal_id = PVR2_CID_STDAVAIL,
1224                 .skip_init = !0,
1225                 .get_value = ctrl_stdavail_get,
1226                 .set_value = ctrl_stdavail_set,
1227                 .val_to_sym = ctrl_std_val_to_sym,
1228                 .sym_to_val = ctrl_std_sym_to_val,
1229                 .type = pvr2_ctl_bitmask,
1230         },{
1231                 .desc = "Video Standards In Use Mask",
1232                 .name = "video_standard_mask_active",
1233                 .internal_id = PVR2_CID_STDCUR,
1234                 .skip_init = !0,
1235                 .get_value = ctrl_stdcur_get,
1236                 .set_value = ctrl_stdcur_set,
1237                 .is_dirty = ctrl_stdcur_is_dirty,
1238                 .clear_dirty = ctrl_stdcur_clear_dirty,
1239                 .val_to_sym = ctrl_std_val_to_sym,
1240                 .sym_to_val = ctrl_std_sym_to_val,
1241                 .type = pvr2_ctl_bitmask,
1242         },{
1243                 .desc = "Video Standard Name",
1244                 .name = "video_standard",
1245                 .internal_id = PVR2_CID_STDENUM,
1246                 .skip_init = !0,
1247                 .get_value = ctrl_stdenumcur_get,
1248                 .set_value = ctrl_stdenumcur_set,
1249                 .is_dirty = ctrl_stdenumcur_is_dirty,
1250                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1251                 .type = pvr2_ctl_enum,
1252         }
1253 };
1254
1255 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1256
1257
1258 const char *pvr2_config_get_name(enum pvr2_config cfg)
1259 {
1260         switch (cfg) {
1261         case pvr2_config_empty: return "empty";
1262         case pvr2_config_mpeg: return "mpeg";
1263         case pvr2_config_vbi: return "vbi";
1264         case pvr2_config_pcm: return "pcm";
1265         case pvr2_config_rawvideo: return "raw video";
1266         }
1267         return "<unknown>";
1268 }
1269
1270
1271 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1272 {
1273         return hdw->usb_dev;
1274 }
1275
1276
1277 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1278 {
1279         return hdw->serial_number;
1280 }
1281
1282
1283 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1284 {
1285         return hdw->bus_info;
1286 }
1287
1288
1289 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1290 {
1291         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1292 }
1293
1294 /* Set the currently tuned frequency and account for all possible
1295    driver-core side effects of this action. */
1296 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1297 {
1298         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1299                 if (hdw->freqSelector) {
1300                         /* Swing over to radio frequency selection */
1301                         hdw->freqSelector = 0;
1302                         hdw->freqDirty = !0;
1303                 }
1304                 if (hdw->freqValRadio != val) {
1305                         hdw->freqValRadio = val;
1306                         hdw->freqSlotRadio = 0;
1307                         hdw->freqDirty = !0;
1308                 }
1309         } else {
1310                 if (!(hdw->freqSelector)) {
1311                         /* Swing over to television frequency selection */
1312                         hdw->freqSelector = 1;
1313                         hdw->freqDirty = !0;
1314                 }
1315                 if (hdw->freqValTelevision != val) {
1316                         hdw->freqValTelevision = val;
1317                         hdw->freqSlotTelevision = 0;
1318                         hdw->freqDirty = !0;
1319                 }
1320         }
1321 }
1322
1323 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1324 {
1325         return hdw->unit_number;
1326 }
1327
1328
1329 /* Attempt to locate one of the given set of files.  Messages are logged
1330    appropriate to what has been found.  The return value will be 0 or
1331    greater on success (it will be the index of the file name found) and
1332    fw_entry will be filled in.  Otherwise a negative error is returned on
1333    failure.  If the return value is -ENOENT then no viable firmware file
1334    could be located. */
1335 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1336                                 const struct firmware **fw_entry,
1337                                 const char *fwtypename,
1338                                 unsigned int fwcount,
1339                                 const char *fwnames[])
1340 {
1341         unsigned int idx;
1342         int ret = -EINVAL;
1343         for (idx = 0; idx < fwcount; idx++) {
1344                 ret = request_firmware(fw_entry,
1345                                        fwnames[idx],
1346                                        &hdw->usb_dev->dev);
1347                 if (!ret) {
1348                         trace_firmware("Located %s firmware: %s;"
1349                                        " uploading...",
1350                                        fwtypename,
1351                                        fwnames[idx]);
1352                         return idx;
1353                 }
1354                 if (ret == -ENOENT) continue;
1355                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1356                            "request_firmware fatal error with code=%d",ret);
1357                 return ret;
1358         }
1359         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1360                    "***WARNING***"
1361                    " Device %s firmware"
1362                    " seems to be missing.",
1363                    fwtypename);
1364         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1365                    "Did you install the pvrusb2 firmware files"
1366                    " in their proper location?");
1367         if (fwcount == 1) {
1368                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1369                            "request_firmware unable to locate %s file %s",
1370                            fwtypename,fwnames[0]);
1371         } else {
1372                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1373                            "request_firmware unable to locate"
1374                            " one of the following %s files:",
1375                            fwtypename);
1376                 for (idx = 0; idx < fwcount; idx++) {
1377                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1378                                    "request_firmware: Failed to find %s",
1379                                    fwnames[idx]);
1380                 }
1381         }
1382         return ret;
1383 }
1384
1385
1386 /*
1387  * pvr2_upload_firmware1().
1388  *
1389  * Send the 8051 firmware to the device.  After the upload, arrange for
1390  * device to re-enumerate.
1391  *
1392  * NOTE : the pointer to the firmware data given by request_firmware()
1393  * is not suitable for an usb transaction.
1394  *
1395  */
1396 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1397 {
1398         const struct firmware *fw_entry = NULL;
1399         void  *fw_ptr;
1400         unsigned int pipe;
1401         int ret;
1402         u16 address;
1403
1404         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1405                 hdw->fw1_state = FW1_STATE_OK;
1406                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1407                            "Connected device type defines"
1408                            " no firmware to upload; ignoring firmware");
1409                 return -ENOTTY;
1410         }
1411
1412         hdw->fw1_state = FW1_STATE_FAILED; // default result
1413
1414         trace_firmware("pvr2_upload_firmware1");
1415
1416         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1417                                    hdw->hdw_desc->fx2_firmware.cnt,
1418                                    hdw->hdw_desc->fx2_firmware.lst);
1419         if (ret < 0) {
1420                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1421                 return ret;
1422         }
1423
1424         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1425         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1426
1427         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1428
1429         if (fw_entry->size != 0x2000){
1430                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1431                 release_firmware(fw_entry);
1432                 return -ENOMEM;
1433         }
1434
1435         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1436         if (fw_ptr == NULL){
1437                 release_firmware(fw_entry);
1438                 return -ENOMEM;
1439         }
1440
1441         /* We have to hold the CPU during firmware upload. */
1442         pvr2_hdw_cpureset_assert(hdw,1);
1443
1444         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1445            chunk. */
1446
1447         ret = 0;
1448         for(address = 0; address < fw_entry->size; address += 0x800) {
1449                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1450                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1451                                        0, fw_ptr, 0x800, HZ);
1452         }
1453
1454         trace_firmware("Upload done, releasing device's CPU");
1455
1456         /* Now release the CPU.  It will disconnect and reconnect later. */
1457         pvr2_hdw_cpureset_assert(hdw,0);
1458
1459         kfree(fw_ptr);
1460         release_firmware(fw_entry);
1461
1462         trace_firmware("Upload done (%d bytes sent)",ret);
1463
1464         /* We should have written 8192 bytes */
1465         if (ret == 8192) {
1466                 hdw->fw1_state = FW1_STATE_RELOAD;
1467                 return 0;
1468         }
1469
1470         return -EIO;
1471 }
1472
1473
1474 /*
1475  * pvr2_upload_firmware2()
1476  *
1477  * This uploads encoder firmware on endpoint 2.
1478  *
1479  */
1480
1481 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1482 {
1483         const struct firmware *fw_entry = NULL;
1484         void  *fw_ptr;
1485         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1486         int actual_length;
1487         int ret = 0;
1488         int fwidx;
1489         static const char *fw_files[] = {
1490                 CX2341X_FIRM_ENC_FILENAME,
1491         };
1492
1493         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1494                 return 0;
1495         }
1496
1497         trace_firmware("pvr2_upload_firmware2");
1498
1499         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1500                                    ARRAY_SIZE(fw_files), fw_files);
1501         if (ret < 0) return ret;
1502         fwidx = ret;
1503         ret = 0;
1504         /* Since we're about to completely reinitialize the encoder,
1505            invalidate our cached copy of its configuration state.  Next
1506            time we configure the encoder, then we'll fully configure it. */
1507         hdw->enc_cur_valid = 0;
1508
1509         /* Encoder is about to be reset so note that as far as we're
1510            concerned now, the encoder has never been run. */
1511         del_timer_sync(&hdw->encoder_run_timer);
1512         if (hdw->state_encoder_runok) {
1513                 hdw->state_encoder_runok = 0;
1514                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1515         }
1516
1517         /* First prepare firmware loading */
1518         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1519         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1520         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1521         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1522         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1523         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1524         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1525         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1526         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1527         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1528         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1529         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1530         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1531         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1532         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1533         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1534         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1535         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1536
1537         if (ret) {
1538                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1539                            "firmware2 upload prep failed, ret=%d",ret);
1540                 release_firmware(fw_entry);
1541                 goto done;
1542         }
1543
1544         /* Now send firmware */
1545
1546         fw_len = fw_entry->size;
1547
1548         if (fw_len % sizeof(u32)) {
1549                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1550                            "size of %s firmware"
1551                            " must be a multiple of %zu bytes",
1552                            fw_files[fwidx],sizeof(u32));
1553                 release_firmware(fw_entry);
1554                 ret = -EINVAL;
1555                 goto done;
1556         }
1557
1558         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1559         if (fw_ptr == NULL){
1560                 release_firmware(fw_entry);
1561                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1562                            "failed to allocate memory for firmware2 upload");
1563                 ret = -ENOMEM;
1564                 goto done;
1565         }
1566
1567         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1568
1569         fw_done = 0;
1570         for (fw_done = 0; fw_done < fw_len;) {
1571                 bcnt = fw_len - fw_done;
1572                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1573                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1574                 /* Usbsnoop log shows that we must swap bytes... */
1575                 /* Some background info: The data being swapped here is a
1576                    firmware image destined for the mpeg encoder chip that
1577                    lives at the other end of a USB endpoint.  The encoder
1578                    chip always talks in 32 bit chunks and its storage is
1579                    organized into 32 bit words.  However from the file
1580                    system to the encoder chip everything is purely a byte
1581                    stream.  The firmware file's contents are always 32 bit
1582                    swapped from what the encoder expects.  Thus the need
1583                    always exists to swap the bytes regardless of the endian
1584                    type of the host processor and therefore swab32() makes
1585                    the most sense. */
1586                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1587                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1588
1589                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1590                                     &actual_length, HZ);
1591                 ret |= (actual_length != bcnt);
1592                 if (ret) break;
1593                 fw_done += bcnt;
1594         }
1595
1596         trace_firmware("upload of %s : %i / %i ",
1597                        fw_files[fwidx],fw_done,fw_len);
1598
1599         kfree(fw_ptr);
1600         release_firmware(fw_entry);
1601
1602         if (ret) {
1603                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1604                            "firmware2 upload transfer failure");
1605                 goto done;
1606         }
1607
1608         /* Finish upload */
1609
1610         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1611         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1612         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1613
1614         if (ret) {
1615                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1616                            "firmware2 upload post-proc failure");
1617         }
1618
1619  done:
1620         if (hdw->hdw_desc->signal_routing_scheme ==
1621             PVR2_ROUTING_SCHEME_GOTVIEW) {
1622                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1623                    hardware. */
1624                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1625         }
1626         return ret;
1627 }
1628
1629
1630 static const char *pvr2_get_state_name(unsigned int st)
1631 {
1632         if (st < ARRAY_SIZE(pvr2_state_names)) {
1633                 return pvr2_state_names[st];
1634         }
1635         return "???";
1636 }
1637
1638 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1639 {
1640         if (!hdw->decoder_ctrl) {
1641                 if (!hdw->flag_decoder_missed) {
1642                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1643                                    "WARNING: No decoder present");
1644                         hdw->flag_decoder_missed = !0;
1645                         trace_stbit("flag_decoder_missed",
1646                                     hdw->flag_decoder_missed);
1647                 }
1648                 return -EIO;
1649         }
1650         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1651         return 0;
1652 }
1653
1654
1655 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1656 {
1657         if (hdw->decoder_ctrl == ptr) return;
1658         hdw->decoder_ctrl = ptr;
1659         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1660                 hdw->flag_decoder_missed = 0;
1661                 trace_stbit("flag_decoder_missed",
1662                             hdw->flag_decoder_missed);
1663                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1664                            "Decoder has appeared");
1665                 pvr2_hdw_state_sched(hdw);
1666         }
1667 }
1668
1669
1670 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1671 {
1672         return hdw->master_state;
1673 }
1674
1675
1676 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1677 {
1678         if (!hdw->flag_tripped) return 0;
1679         hdw->flag_tripped = 0;
1680         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1681                    "Clearing driver error statuss");
1682         return !0;
1683 }
1684
1685
1686 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1687 {
1688         int fl;
1689         LOCK_TAKE(hdw->big_lock); do {
1690                 fl = pvr2_hdw_untrip_unlocked(hdw);
1691         } while (0); LOCK_GIVE(hdw->big_lock);
1692         if (fl) pvr2_hdw_state_sched(hdw);
1693         return 0;
1694 }
1695
1696
1697
1698
1699 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1700 {
1701         return hdw->state_pipeline_req != 0;
1702 }
1703
1704
1705 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1706 {
1707         int ret,st;
1708         LOCK_TAKE(hdw->big_lock); do {
1709                 pvr2_hdw_untrip_unlocked(hdw);
1710                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1711                         hdw->state_pipeline_req = enable_flag != 0;
1712                         pvr2_trace(PVR2_TRACE_START_STOP,
1713                                    "/*--TRACE_STREAM--*/ %s",
1714                                    enable_flag ? "enable" : "disable");
1715                 }
1716                 pvr2_hdw_state_sched(hdw);
1717         } while (0); LOCK_GIVE(hdw->big_lock);
1718         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1719         if (enable_flag) {
1720                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1721                         if (st != PVR2_STATE_READY) return -EIO;
1722                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1723                 }
1724         }
1725         return 0;
1726 }
1727
1728
1729 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1730 {
1731         int fl;
1732         LOCK_TAKE(hdw->big_lock);
1733         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1734                 hdw->desired_stream_type = config;
1735                 hdw->state_pipeline_config = 0;
1736                 trace_stbit("state_pipeline_config",
1737                             hdw->state_pipeline_config);
1738                 pvr2_hdw_state_sched(hdw);
1739         }
1740         LOCK_GIVE(hdw->big_lock);
1741         if (fl) return 0;
1742         return pvr2_hdw_wait(hdw,0);
1743 }
1744
1745
1746 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1747 {
1748         int unit_number = hdw->unit_number;
1749         int tp = -1;
1750         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1751                 tp = tuner[unit_number];
1752         }
1753         if (tp < 0) return -EINVAL;
1754         hdw->tuner_type = tp;
1755         hdw->tuner_updated = !0;
1756         return 0;
1757 }
1758
1759
1760 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1761 {
1762         int unit_number = hdw->unit_number;
1763         int tp = 0;
1764         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1765                 tp = video_std[unit_number];
1766                 if (tp) return tp;
1767         }
1768         return 0;
1769 }
1770
1771
1772 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1773 {
1774         int unit_number = hdw->unit_number;
1775         int tp = 0;
1776         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1777                 tp = tolerance[unit_number];
1778         }
1779         return tp;
1780 }
1781
1782
1783 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1784 {
1785         /* Try a harmless request to fetch the eeprom's address over
1786            endpoint 1.  See what happens.  Only the full FX2 image can
1787            respond to this.  If this probe fails then likely the FX2
1788            firmware needs be loaded. */
1789         int result;
1790         LOCK_TAKE(hdw->ctl_lock); do {
1791                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1792                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1793                                            hdw->cmd_buffer,1,
1794                                            hdw->cmd_buffer,1);
1795                 if (result < 0) break;
1796         } while(0); LOCK_GIVE(hdw->ctl_lock);
1797         if (result) {
1798                 pvr2_trace(PVR2_TRACE_INIT,
1799                            "Probe of device endpoint 1 result status %d",
1800                            result);
1801         } else {
1802                 pvr2_trace(PVR2_TRACE_INIT,
1803                            "Probe of device endpoint 1 succeeded");
1804         }
1805         return result == 0;
1806 }
1807
1808 struct pvr2_std_hack {
1809         v4l2_std_id pat;  /* Pattern to match */
1810         v4l2_std_id msk;  /* Which bits we care about */
1811         v4l2_std_id std;  /* What additional standards or default to set */
1812 };
1813
1814 /* This data structure labels specific combinations of standards from
1815    tveeprom that we'll try to recognize.  If we recognize one, then assume
1816    a specified default standard to use.  This is here because tveeprom only
1817    tells us about available standards not the intended default standard (if
1818    any) for the device in question.  We guess the default based on what has
1819    been reported as available.  Note that this is only for guessing a
1820    default - which can always be overridden explicitly - and if the user
1821    has otherwise named a default then that default will always be used in
1822    place of this table. */
1823 static const struct pvr2_std_hack std_eeprom_maps[] = {
1824         {       /* PAL(B/G) */
1825                 .pat = V4L2_STD_B|V4L2_STD_GH,
1826                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1827         },
1828         {       /* NTSC(M) */
1829                 .pat = V4L2_STD_MN,
1830                 .std = V4L2_STD_NTSC_M,
1831         },
1832         {       /* PAL(I) */
1833                 .pat = V4L2_STD_PAL_I,
1834                 .std = V4L2_STD_PAL_I,
1835         },
1836         {       /* SECAM(L/L') */
1837                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1838                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1839         },
1840         {       /* PAL(D/D1/K) */
1841                 .pat = V4L2_STD_DK,
1842                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1843         },
1844 };
1845
1846 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1847 {
1848         char buf[40];
1849         unsigned int bcnt;
1850         v4l2_std_id std1,std2,std3;
1851
1852         std1 = get_default_standard(hdw);
1853         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1854
1855         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1856         pvr2_trace(PVR2_TRACE_STD,
1857                    "Supported video standard(s) reported available"
1858                    " in hardware: %.*s",
1859                    bcnt,buf);
1860
1861         hdw->std_mask_avail = hdw->std_mask_eeprom;
1862
1863         std2 = (std1|std3) & ~hdw->std_mask_avail;
1864         if (std2) {
1865                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1866                 pvr2_trace(PVR2_TRACE_STD,
1867                            "Expanding supported video standards"
1868                            " to include: %.*s",
1869                            bcnt,buf);
1870                 hdw->std_mask_avail |= std2;
1871         }
1872
1873         pvr2_hdw_internal_set_std_avail(hdw);
1874
1875         if (std1) {
1876                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1877                 pvr2_trace(PVR2_TRACE_STD,
1878                            "Initial video standard forced to %.*s",
1879                            bcnt,buf);
1880                 hdw->std_mask_cur = std1;
1881                 hdw->std_dirty = !0;
1882                 pvr2_hdw_internal_find_stdenum(hdw);
1883                 return;
1884         }
1885         if (std3) {
1886                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1887                 pvr2_trace(PVR2_TRACE_STD,
1888                            "Initial video standard"
1889                            " (determined by device type): %.*s",bcnt,buf);
1890                 hdw->std_mask_cur = std3;
1891                 hdw->std_dirty = !0;
1892                 pvr2_hdw_internal_find_stdenum(hdw);
1893                 return;
1894         }
1895
1896         {
1897                 unsigned int idx;
1898                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1899                         if (std_eeprom_maps[idx].msk ?
1900                             ((std_eeprom_maps[idx].pat ^
1901                              hdw->std_mask_eeprom) &
1902                              std_eeprom_maps[idx].msk) :
1903                             (std_eeprom_maps[idx].pat !=
1904                              hdw->std_mask_eeprom)) continue;
1905                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1906                                                   std_eeprom_maps[idx].std);
1907                         pvr2_trace(PVR2_TRACE_STD,
1908                                    "Initial video standard guessed as %.*s",
1909                                    bcnt,buf);
1910                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1911                         hdw->std_dirty = !0;
1912                         pvr2_hdw_internal_find_stdenum(hdw);
1913                         return;
1914                 }
1915         }
1916
1917         if (hdw->std_enum_cnt > 1) {
1918                 // Autoselect the first listed standard
1919                 hdw->std_enum_cur = 1;
1920                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1921                 hdw->std_dirty = !0;
1922                 pvr2_trace(PVR2_TRACE_STD,
1923                            "Initial video standard auto-selected to %s",
1924                            hdw->std_defs[hdw->std_enum_cur-1].name);
1925                 return;
1926         }
1927
1928         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1929                    "Unable to select a viable initial video standard");
1930 }
1931
1932
1933 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1934 {
1935         int ret;
1936         unsigned int idx;
1937         struct pvr2_ctrl *cptr;
1938         int reloadFl = 0;
1939         if (hdw->hdw_desc->fx2_firmware.cnt) {
1940                 if (!reloadFl) {
1941                         reloadFl =
1942                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1943                                  == 0);
1944                         if (reloadFl) {
1945                                 pvr2_trace(PVR2_TRACE_INIT,
1946                                            "USB endpoint config looks strange"
1947                                            "; possibly firmware needs to be"
1948                                            " loaded");
1949                         }
1950                 }
1951                 if (!reloadFl) {
1952                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1953                         if (reloadFl) {
1954                                 pvr2_trace(PVR2_TRACE_INIT,
1955                                            "Check for FX2 firmware failed"
1956                                            "; possibly firmware needs to be"
1957                                            " loaded");
1958                         }
1959                 }
1960                 if (reloadFl) {
1961                         if (pvr2_upload_firmware1(hdw) != 0) {
1962                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1963                                            "Failure uploading firmware1");
1964                         }
1965                         return;
1966                 }
1967         }
1968         hdw->fw1_state = FW1_STATE_OK;
1969
1970         if (initusbreset) {
1971                 pvr2_hdw_device_reset(hdw);
1972         }
1973         if (!pvr2_hdw_dev_ok(hdw)) return;
1974
1975         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1976                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1977         }
1978
1979         if (!hdw->hdw_desc->flag_no_powerup) {
1980                 pvr2_hdw_cmd_powerup(hdw);
1981                 if (!pvr2_hdw_dev_ok(hdw)) return;
1982         }
1983
1984         /* Take the IR chip out of reset, if appropriate */
1985         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
1986                 pvr2_issue_simple_cmd(hdw,
1987                                       FX2CMD_HCW_ZILOG_RESET |
1988                                       (1 << 8) |
1989                                       ((0) << 16));
1990         }
1991
1992         // This step MUST happen after the earlier powerup step.
1993         pvr2_i2c_core_init(hdw);
1994         if (!pvr2_hdw_dev_ok(hdw)) return;
1995
1996         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1997                 cptr = hdw->controls + idx;
1998                 if (cptr->info->skip_init) continue;
1999                 if (!cptr->info->set_value) continue;
2000                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2001         }
2002
2003         /* Set up special default values for the television and radio
2004            frequencies here.  It's not really important what these defaults
2005            are, but I set them to something usable in the Chicago area just
2006            to make driver testing a little easier. */
2007
2008         hdw->freqValTelevision = default_tv_freq;
2009         hdw->freqValRadio = default_radio_freq;
2010
2011         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2012         // thread-safe against the normal pvr2_send_request() mechanism.
2013         // (We should make it thread safe).
2014
2015         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2016                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2017                 if (!pvr2_hdw_dev_ok(hdw)) return;
2018                 if (ret < 0) {
2019                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2020                                    "Unable to determine location of eeprom,"
2021                                    " skipping");
2022                 } else {
2023                         hdw->eeprom_addr = ret;
2024                         pvr2_eeprom_analyze(hdw);
2025                         if (!pvr2_hdw_dev_ok(hdw)) return;
2026                 }
2027         } else {
2028                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2029                 hdw->tuner_updated = !0;
2030                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2031         }
2032
2033         pvr2_hdw_setup_std(hdw);
2034
2035         if (!get_default_tuner_type(hdw)) {
2036                 pvr2_trace(PVR2_TRACE_INIT,
2037                            "pvr2_hdw_setup: Tuner type overridden to %d",
2038                            hdw->tuner_type);
2039         }
2040
2041         pvr2_i2c_core_check_stale(hdw);
2042         hdw->tuner_updated = 0;
2043
2044         if (!pvr2_hdw_dev_ok(hdw)) return;
2045
2046         if (hdw->hdw_desc->signal_routing_scheme ==
2047             PVR2_ROUTING_SCHEME_GOTVIEW) {
2048                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2049                    hardware. */
2050                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2051         }
2052
2053         pvr2_hdw_commit_setup(hdw);
2054
2055         hdw->vid_stream = pvr2_stream_create();
2056         if (!pvr2_hdw_dev_ok(hdw)) return;
2057         pvr2_trace(PVR2_TRACE_INIT,
2058                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2059         if (hdw->vid_stream) {
2060                 idx = get_default_error_tolerance(hdw);
2061                 if (idx) {
2062                         pvr2_trace(PVR2_TRACE_INIT,
2063                                    "pvr2_hdw_setup: video stream %p"
2064                                    " setting tolerance %u",
2065                                    hdw->vid_stream,idx);
2066                 }
2067                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2068                                   PVR2_VID_ENDPOINT,idx);
2069         }
2070
2071         if (!pvr2_hdw_dev_ok(hdw)) return;
2072
2073         hdw->flag_init_ok = !0;
2074
2075         pvr2_hdw_state_sched(hdw);
2076 }
2077
2078
2079 /* Set up the structure and attempt to put the device into a usable state.
2080    This can be a time-consuming operation, which is why it is not done
2081    internally as part of the create() step. */
2082 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2083 {
2084         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2085         do {
2086                 pvr2_hdw_setup_low(hdw);
2087                 pvr2_trace(PVR2_TRACE_INIT,
2088                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2089                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2090                 if (pvr2_hdw_dev_ok(hdw)) {
2091                         if (hdw->flag_init_ok) {
2092                                 pvr2_trace(
2093                                         PVR2_TRACE_INFO,
2094                                         "Device initialization"
2095                                         " completed successfully.");
2096                                 break;
2097                         }
2098                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2099                                 pvr2_trace(
2100                                         PVR2_TRACE_INFO,
2101                                         "Device microcontroller firmware"
2102                                         " (re)loaded; it should now reset"
2103                                         " and reconnect.");
2104                                 break;
2105                         }
2106                         pvr2_trace(
2107                                 PVR2_TRACE_ERROR_LEGS,
2108                                 "Device initialization was not successful.");
2109                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2110                                 pvr2_trace(
2111                                         PVR2_TRACE_ERROR_LEGS,
2112                                         "Giving up since device"
2113                                         " microcontroller firmware"
2114                                         " appears to be missing.");
2115                                 break;
2116                         }
2117                 }
2118                 if (procreload) {
2119                         pvr2_trace(
2120                                 PVR2_TRACE_ERROR_LEGS,
2121                                 "Attempting pvrusb2 recovery by reloading"
2122                                 " primary firmware.");
2123                         pvr2_trace(
2124                                 PVR2_TRACE_ERROR_LEGS,
2125                                 "If this works, device should disconnect"
2126                                 " and reconnect in a sane state.");
2127                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2128                         pvr2_upload_firmware1(hdw);
2129                 } else {
2130                         pvr2_trace(
2131                                 PVR2_TRACE_ERROR_LEGS,
2132                                 "***WARNING*** pvrusb2 device hardware"
2133                                 " appears to be jammed"
2134                                 " and I can't clear it.");
2135                         pvr2_trace(
2136                                 PVR2_TRACE_ERROR_LEGS,
2137                                 "You might need to power cycle"
2138                                 " the pvrusb2 device"
2139                                 " in order to recover.");
2140                 }
2141         } while (0);
2142         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2143 }
2144
2145
2146 /* Perform second stage initialization.  Set callback pointer first so that
2147    we can avoid a possible initialization race (if the kernel thread runs
2148    before the callback has been set). */
2149 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2150                         void (*callback_func)(void *),
2151                         void *callback_data)
2152 {
2153         LOCK_TAKE(hdw->big_lock); do {
2154                 if (hdw->flag_disconnected) {
2155                         /* Handle a race here: If we're already
2156                            disconnected by this point, then give up.  If we
2157                            get past this then we'll remain connected for
2158                            the duration of initialization since the entire
2159                            initialization sequence is now protected by the
2160                            big_lock. */
2161                         break;
2162                 }
2163                 hdw->state_data = callback_data;
2164                 hdw->state_func = callback_func;
2165                 pvr2_hdw_setup(hdw);
2166         } while (0); LOCK_GIVE(hdw->big_lock);
2167         return hdw->flag_init_ok;
2168 }
2169
2170
2171 /* Create, set up, and return a structure for interacting with the
2172    underlying hardware.  */
2173 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2174                                  const struct usb_device_id *devid)
2175 {
2176         unsigned int idx,cnt1,cnt2,m;
2177         struct pvr2_hdw *hdw = NULL;
2178         int valid_std_mask;
2179         struct pvr2_ctrl *cptr;
2180         const struct pvr2_device_desc *hdw_desc;
2181         __u8 ifnum;
2182         struct v4l2_queryctrl qctrl;
2183         struct pvr2_ctl_info *ciptr;
2184
2185         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2186
2187         if (hdw_desc == NULL) {
2188                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2189                            " No device description pointer,"
2190                            " unable to continue.");
2191                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2192                            " please contact Mike Isely <isely@pobox.com>"
2193                            " to get it included in the driver\n");
2194                 goto fail;
2195         }
2196
2197         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2198         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2199                    hdw,hdw_desc->description);
2200         if (!hdw) goto fail;
2201
2202         init_timer(&hdw->quiescent_timer);
2203         hdw->quiescent_timer.data = (unsigned long)hdw;
2204         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2205
2206         init_timer(&hdw->encoder_wait_timer);
2207         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2208         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2209
2210         init_timer(&hdw->encoder_run_timer);
2211         hdw->encoder_run_timer.data = (unsigned long)hdw;
2212         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2213
2214         hdw->master_state = PVR2_STATE_DEAD;
2215
2216         init_waitqueue_head(&hdw->state_wait_data);
2217
2218         hdw->tuner_signal_stale = !0;
2219         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2220
2221         /* Calculate which inputs are OK */
2222         m = 0;
2223         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2224         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2225                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2226         }
2227         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2228         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2229         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2230         hdw->input_avail_mask = m;
2231         hdw->input_allowed_mask = hdw->input_avail_mask;
2232
2233         /* If not a hybrid device, pathway_state never changes.  So
2234            initialize it here to what it should forever be. */
2235         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2236                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2237         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2238                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2239         }
2240
2241         hdw->control_cnt = CTRLDEF_COUNT;
2242         hdw->control_cnt += MPEGDEF_COUNT;
2243         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2244                                 GFP_KERNEL);
2245         if (!hdw->controls) goto fail;
2246         hdw->hdw_desc = hdw_desc;
2247         for (idx = 0; idx < hdw->control_cnt; idx++) {
2248                 cptr = hdw->controls + idx;
2249                 cptr->hdw = hdw;
2250         }
2251         for (idx = 0; idx < 32; idx++) {
2252                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2253         }
2254         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2255                 cptr = hdw->controls + idx;
2256                 cptr->info = control_defs+idx;
2257         }
2258
2259         /* Ensure that default input choice is a valid one. */
2260         m = hdw->input_avail_mask;
2261         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2262                 if (!((1 << idx) & m)) continue;
2263                 hdw->input_val = idx;
2264                 break;
2265         }
2266
2267         /* Define and configure additional controls from cx2341x module. */
2268         hdw->mpeg_ctrl_info = kzalloc(
2269                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2270         if (!hdw->mpeg_ctrl_info) goto fail;
2271         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2272                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2273                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2274                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2275                 ciptr->name = mpeg_ids[idx].strid;
2276                 ciptr->v4l_id = mpeg_ids[idx].id;
2277                 ciptr->skip_init = !0;
2278                 ciptr->get_value = ctrl_cx2341x_get;
2279                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2280                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2281                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2282                 qctrl.id = ciptr->v4l_id;
2283                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2284                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2285                         ciptr->set_value = ctrl_cx2341x_set;
2286                 }
2287                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2288                         PVR2_CTLD_INFO_DESC_SIZE);
2289                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2290                 ciptr->default_value = qctrl.default_value;
2291                 switch (qctrl.type) {
2292                 default:
2293                 case V4L2_CTRL_TYPE_INTEGER:
2294                         ciptr->type = pvr2_ctl_int;
2295                         ciptr->def.type_int.min_value = qctrl.minimum;
2296                         ciptr->def.type_int.max_value = qctrl.maximum;
2297                         break;
2298                 case V4L2_CTRL_TYPE_BOOLEAN:
2299                         ciptr->type = pvr2_ctl_bool;
2300                         break;
2301                 case V4L2_CTRL_TYPE_MENU:
2302                         ciptr->type = pvr2_ctl_enum;
2303                         ciptr->def.type_enum.value_names =
2304                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2305                                                                 ciptr->v4l_id);
2306                         for (cnt1 = 0;
2307                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2308                              cnt1++) { }
2309                         ciptr->def.type_enum.count = cnt1;
2310                         break;
2311                 }
2312                 cptr->info = ciptr;
2313         }
2314
2315         // Initialize video standard enum dynamic control
2316         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2317         if (cptr) {
2318                 memcpy(&hdw->std_info_enum,cptr->info,
2319                        sizeof(hdw->std_info_enum));
2320                 cptr->info = &hdw->std_info_enum;
2321
2322         }
2323         // Initialize control data regarding video standard masks
2324         valid_std_mask = pvr2_std_get_usable();
2325         for (idx = 0; idx < 32; idx++) {
2326                 if (!(valid_std_mask & (1 << idx))) continue;
2327                 cnt1 = pvr2_std_id_to_str(
2328                         hdw->std_mask_names[idx],
2329                         sizeof(hdw->std_mask_names[idx])-1,
2330                         1 << idx);
2331                 hdw->std_mask_names[idx][cnt1] = 0;
2332         }
2333         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2334         if (cptr) {
2335                 memcpy(&hdw->std_info_avail,cptr->info,
2336                        sizeof(hdw->std_info_avail));
2337                 cptr->info = &hdw->std_info_avail;
2338                 hdw->std_info_avail.def.type_bitmask.bit_names =
2339                         hdw->std_mask_ptrs;
2340                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2341                         valid_std_mask;
2342         }
2343         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2344         if (cptr) {
2345                 memcpy(&hdw->std_info_cur,cptr->info,
2346                        sizeof(hdw->std_info_cur));
2347                 cptr->info = &hdw->std_info_cur;
2348                 hdw->std_info_cur.def.type_bitmask.bit_names =
2349                         hdw->std_mask_ptrs;
2350                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2351                         valid_std_mask;
2352         }
2353
2354         hdw->cropcap_stale = !0;
2355         hdw->eeprom_addr = -1;
2356         hdw->unit_number = -1;
2357         hdw->v4l_minor_number_video = -1;
2358         hdw->v4l_minor_number_vbi = -1;
2359         hdw->v4l_minor_number_radio = -1;
2360         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2361         if (!hdw->ctl_write_buffer) goto fail;
2362         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2363         if (!hdw->ctl_read_buffer) goto fail;
2364         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2365         if (!hdw->ctl_write_urb) goto fail;
2366         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2367         if (!hdw->ctl_read_urb) goto fail;
2368
2369         mutex_lock(&pvr2_unit_mtx); do {
2370                 for (idx = 0; idx < PVR_NUM; idx++) {
2371                         if (unit_pointers[idx]) continue;
2372                         hdw->unit_number = idx;
2373                         unit_pointers[idx] = hdw;
2374                         break;
2375                 }
2376         } while (0); mutex_unlock(&pvr2_unit_mtx);
2377
2378         cnt1 = 0;
2379         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2380         cnt1 += cnt2;
2381         if (hdw->unit_number >= 0) {
2382                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2383                                  ('a' + hdw->unit_number));
2384                 cnt1 += cnt2;
2385         }
2386         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2387         hdw->name[cnt1] = 0;
2388
2389         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2390         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2391         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2392
2393         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2394                    hdw->unit_number,hdw->name);
2395
2396         hdw->tuner_type = -1;
2397         hdw->flag_ok = !0;
2398
2399         hdw->usb_intf = intf;
2400         hdw->usb_dev = interface_to_usbdev(intf);
2401
2402         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2403                   "usb %s address %d",
2404                   hdw->usb_dev->dev.bus_id,
2405                   hdw->usb_dev->devnum);
2406
2407         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2408         usb_set_interface(hdw->usb_dev,ifnum,0);
2409
2410         mutex_init(&hdw->ctl_lock_mutex);
2411         mutex_init(&hdw->big_lock_mutex);
2412
2413         return hdw;
2414  fail:
2415         if (hdw) {
2416                 del_timer_sync(&hdw->quiescent_timer);
2417                 del_timer_sync(&hdw->encoder_run_timer);
2418                 del_timer_sync(&hdw->encoder_wait_timer);
2419                 if (hdw->workqueue) {
2420                         flush_workqueue(hdw->workqueue);
2421                         destroy_workqueue(hdw->workqueue);
2422                         hdw->workqueue = NULL;
2423                 }
2424                 usb_free_urb(hdw->ctl_read_urb);
2425                 usb_free_urb(hdw->ctl_write_urb);
2426                 kfree(hdw->ctl_read_buffer);
2427                 kfree(hdw->ctl_write_buffer);
2428                 kfree(hdw->controls);
2429                 kfree(hdw->mpeg_ctrl_info);
2430                 kfree(hdw->std_defs);
2431                 kfree(hdw->std_enum_names);
2432                 kfree(hdw);
2433         }
2434         return NULL;
2435 }
2436
2437
2438 /* Remove _all_ associations between this driver and the underlying USB
2439    layer. */
2440 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2441 {
2442         if (hdw->flag_disconnected) return;
2443         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2444         if (hdw->ctl_read_urb) {
2445                 usb_kill_urb(hdw->ctl_read_urb);
2446                 usb_free_urb(hdw->ctl_read_urb);
2447                 hdw->ctl_read_urb = NULL;
2448         }
2449         if (hdw->ctl_write_urb) {
2450                 usb_kill_urb(hdw->ctl_write_urb);
2451                 usb_free_urb(hdw->ctl_write_urb);
2452                 hdw->ctl_write_urb = NULL;
2453         }
2454         if (hdw->ctl_read_buffer) {
2455                 kfree(hdw->ctl_read_buffer);
2456                 hdw->ctl_read_buffer = NULL;
2457         }
2458         if (hdw->ctl_write_buffer) {
2459                 kfree(hdw->ctl_write_buffer);
2460                 hdw->ctl_write_buffer = NULL;
2461         }
2462         hdw->flag_disconnected = !0;
2463         hdw->usb_dev = NULL;
2464         hdw->usb_intf = NULL;
2465         pvr2_hdw_render_useless(hdw);
2466 }
2467
2468
2469 /* Destroy hardware interaction structure */
2470 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2471 {
2472         if (!hdw) return;
2473         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2474         if (hdw->workqueue) {
2475                 flush_workqueue(hdw->workqueue);
2476                 destroy_workqueue(hdw->workqueue);
2477                 hdw->workqueue = NULL;
2478         }
2479         del_timer_sync(&hdw->quiescent_timer);
2480         del_timer_sync(&hdw->encoder_run_timer);
2481         del_timer_sync(&hdw->encoder_wait_timer);
2482         if (hdw->fw_buffer) {
2483                 kfree(hdw->fw_buffer);
2484                 hdw->fw_buffer = NULL;
2485         }
2486         if (hdw->vid_stream) {
2487                 pvr2_stream_destroy(hdw->vid_stream);
2488                 hdw->vid_stream = NULL;
2489         }
2490         if (hdw->decoder_ctrl) {
2491                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2492         }
2493         pvr2_i2c_core_done(hdw);
2494         pvr2_hdw_remove_usb_stuff(hdw);
2495         mutex_lock(&pvr2_unit_mtx); do {
2496                 if ((hdw->unit_number >= 0) &&
2497                     (hdw->unit_number < PVR_NUM) &&
2498                     (unit_pointers[hdw->unit_number] == hdw)) {
2499                         unit_pointers[hdw->unit_number] = NULL;
2500                 }
2501         } while (0); mutex_unlock(&pvr2_unit_mtx);
2502         kfree(hdw->controls);
2503         kfree(hdw->mpeg_ctrl_info);
2504         kfree(hdw->std_defs);
2505         kfree(hdw->std_enum_names);
2506         kfree(hdw);
2507 }
2508
2509
2510 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2511 {
2512         return (hdw && hdw->flag_ok);
2513 }
2514
2515
2516 /* Called when hardware has been unplugged */
2517 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2518 {
2519         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2520         LOCK_TAKE(hdw->big_lock);
2521         LOCK_TAKE(hdw->ctl_lock);
2522         pvr2_hdw_remove_usb_stuff(hdw);
2523         LOCK_GIVE(hdw->ctl_lock);
2524         LOCK_GIVE(hdw->big_lock);
2525 }
2526
2527
2528 // Attempt to autoselect an appropriate value for std_enum_cur given
2529 // whatever is currently in std_mask_cur
2530 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2531 {
2532         unsigned int idx;
2533         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2534                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2535                         hdw->std_enum_cur = idx;
2536                         return;
2537                 }
2538         }
2539         hdw->std_enum_cur = 0;
2540 }
2541
2542
2543 // Calculate correct set of enumerated standards based on currently known
2544 // set of available standards bits.
2545 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2546 {
2547         struct v4l2_standard *newstd;
2548         unsigned int std_cnt;
2549         unsigned int idx;
2550
2551         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2552
2553         if (hdw->std_defs) {
2554                 kfree(hdw->std_defs);
2555                 hdw->std_defs = NULL;
2556         }
2557         hdw->std_enum_cnt = 0;
2558         if (hdw->std_enum_names) {
2559                 kfree(hdw->std_enum_names);
2560                 hdw->std_enum_names = NULL;
2561         }
2562
2563         if (!std_cnt) {
2564                 pvr2_trace(
2565                         PVR2_TRACE_ERROR_LEGS,
2566                         "WARNING: Failed to identify any viable standards");
2567         }
2568         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2569         hdw->std_enum_names[0] = "none";
2570         for (idx = 0; idx < std_cnt; idx++) {
2571                 hdw->std_enum_names[idx+1] =
2572                         newstd[idx].name;
2573         }
2574         // Set up the dynamic control for this standard
2575         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2576         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2577         hdw->std_defs = newstd;
2578         hdw->std_enum_cnt = std_cnt+1;
2579         hdw->std_enum_cur = 0;
2580         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2581 }
2582
2583
2584 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2585                                struct v4l2_standard *std,
2586                                unsigned int idx)
2587 {
2588         int ret = -EINVAL;
2589         if (!idx) return ret;
2590         LOCK_TAKE(hdw->big_lock); do {
2591                 if (idx >= hdw->std_enum_cnt) break;
2592                 idx--;
2593                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2594                 ret = 0;
2595         } while (0); LOCK_GIVE(hdw->big_lock);
2596         return ret;
2597 }
2598
2599
2600 /* Get the number of defined controls */
2601 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2602 {
2603         return hdw->control_cnt;
2604 }
2605
2606
2607 /* Retrieve a control handle given its index (0..count-1) */
2608 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2609                                              unsigned int idx)
2610 {
2611         if (idx >= hdw->control_cnt) return NULL;
2612         return hdw->controls + idx;
2613 }
2614
2615
2616 /* Retrieve a control handle given its index (0..count-1) */
2617 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2618                                           unsigned int ctl_id)
2619 {
2620         struct pvr2_ctrl *cptr;
2621         unsigned int idx;
2622         int i;
2623
2624         /* This could be made a lot more efficient, but for now... */
2625         for (idx = 0; idx < hdw->control_cnt; idx++) {
2626                 cptr = hdw->controls + idx;
2627                 i = cptr->info->internal_id;
2628                 if (i && (i == ctl_id)) return cptr;
2629         }
2630         return NULL;
2631 }
2632
2633
2634 /* Given a V4L ID, retrieve the control structure associated with it. */
2635 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2636 {
2637         struct pvr2_ctrl *cptr;
2638         unsigned int idx;
2639         int i;
2640
2641         /* This could be made a lot more efficient, but for now... */
2642         for (idx = 0; idx < hdw->control_cnt; idx++) {
2643                 cptr = hdw->controls + idx;
2644                 i = cptr->info->v4l_id;
2645                 if (i && (i == ctl_id)) return cptr;
2646         }
2647         return NULL;
2648 }
2649
2650
2651 /* Given a V4L ID for its immediate predecessor, retrieve the control
2652    structure associated with it. */
2653 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2654                                             unsigned int ctl_id)
2655 {
2656         struct pvr2_ctrl *cptr,*cp2;
2657         unsigned int idx;
2658         int i;
2659
2660         /* This could be made a lot more efficient, but for now... */
2661         cp2 = NULL;
2662         for (idx = 0; idx < hdw->control_cnt; idx++) {
2663                 cptr = hdw->controls + idx;
2664                 i = cptr->info->v4l_id;
2665                 if (!i) continue;
2666                 if (i <= ctl_id) continue;
2667                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2668                 cp2 = cptr;
2669         }
2670         return cp2;
2671         return NULL;
2672 }
2673
2674
2675 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2676 {
2677         switch (tp) {
2678         case pvr2_ctl_int: return "integer";
2679         case pvr2_ctl_enum: return "enum";
2680         case pvr2_ctl_bool: return "boolean";
2681         case pvr2_ctl_bitmask: return "bitmask";
2682         }
2683         return "";
2684 }
2685
2686
2687 /* Figure out if we need to commit control changes.  If so, mark internal
2688    state flags to indicate this fact and return true.  Otherwise do nothing
2689    else and return false. */
2690 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2691 {
2692         unsigned int idx;
2693         struct pvr2_ctrl *cptr;
2694         int value;
2695         int commit_flag = 0;
2696         char buf[100];
2697         unsigned int bcnt,ccnt;
2698
2699         for (idx = 0; idx < hdw->control_cnt; idx++) {
2700                 cptr = hdw->controls + idx;
2701                 if (!cptr->info->is_dirty) continue;
2702                 if (!cptr->info->is_dirty(cptr)) continue;
2703                 commit_flag = !0;
2704
2705                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2706                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2707                                  cptr->info->name);
2708                 value = 0;
2709                 cptr->info->get_value(cptr,&value);
2710                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2711                                                 buf+bcnt,
2712                                                 sizeof(buf)-bcnt,&ccnt);
2713                 bcnt += ccnt;
2714                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2715                                   get_ctrl_typename(cptr->info->type));
2716                 pvr2_trace(PVR2_TRACE_CTL,
2717                            "/*--TRACE_COMMIT--*/ %.*s",
2718                            bcnt,buf);
2719         }
2720
2721         if (!commit_flag) {
2722                 /* Nothing has changed */
2723                 return 0;
2724         }
2725
2726         hdw->state_pipeline_config = 0;
2727         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2728         pvr2_hdw_state_sched(hdw);
2729
2730         return !0;
2731 }
2732
2733
2734 /* Perform all operations needed to commit all control changes.  This must
2735    be performed in synchronization with the pipeline state and is thus
2736    expected to be called as part of the driver's worker thread.  Return
2737    true if commit successful, otherwise return false to indicate that
2738    commit isn't possible at this time. */
2739 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2740 {
2741         unsigned int idx;
2742         struct pvr2_ctrl *cptr;
2743         int disruptive_change;
2744
2745         /* Handle some required side effects when the video standard is
2746            changed.... */
2747         if (hdw->std_dirty) {
2748                 int nvres;
2749                 int gop_size;
2750                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2751                         nvres = 480;
2752                         gop_size = 15;
2753                 } else {
2754                         nvres = 576;
2755                         gop_size = 12;
2756                 }
2757                 /* Rewrite the vertical resolution to be appropriate to the
2758                    video standard that has been selected. */
2759                 if (nvres != hdw->res_ver_val) {
2760                         hdw->res_ver_val = nvres;
2761                         hdw->res_ver_dirty = !0;
2762                 }
2763                 /* Rewrite the GOP size to be appropriate to the video
2764                    standard that has been selected. */
2765                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
2766                         struct v4l2_ext_controls cs;
2767                         struct v4l2_ext_control c1;
2768                         memset(&cs, 0, sizeof(cs));
2769                         memset(&c1, 0, sizeof(c1));
2770                         cs.controls = &c1;
2771                         cs.count = 1;
2772                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
2773                         c1.value = gop_size;
2774                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
2775                                           VIDIOC_S_EXT_CTRLS);
2776                 }
2777         }
2778
2779         if (hdw->input_dirty && hdw->state_pathway_ok &&
2780             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2781               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2782              hdw->pathway_state)) {
2783                 /* Change of mode being asked for... */
2784                 hdw->state_pathway_ok = 0;
2785                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2786         }
2787         if (!hdw->state_pathway_ok) {
2788                 /* Can't commit anything until pathway is ok. */
2789                 return 0;
2790         }
2791         /* The broadcast decoder can only scale down, so if
2792          * res_*_dirty && crop window < output format ==> enlarge crop.
2793          *
2794          * The mpeg encoder receives fields of res_hor_val dots and
2795          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
2796          */
2797         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
2798                 hdw->cropw_val = hdw->res_hor_val;
2799                 hdw->cropw_dirty = !0;
2800         } else if (hdw->cropw_dirty) {
2801                 hdw->res_hor_dirty = !0;           /* must rescale */
2802                 hdw->res_hor_val = min(720, hdw->cropw_val);
2803         }
2804         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
2805                 hdw->croph_val = hdw->res_ver_val;
2806                 hdw->croph_dirty = !0;
2807         } else if (hdw->croph_dirty) {
2808                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
2809                 hdw->res_ver_dirty = !0;
2810                 hdw->res_ver_val = min(nvres, hdw->croph_val);
2811         }
2812
2813         /* If any of the below has changed, then we can't do the update
2814            while the pipeline is running.  Pipeline must be paused first
2815            and decoder -> encoder connection be made quiescent before we
2816            can proceed. */
2817         disruptive_change =
2818                 (hdw->std_dirty ||
2819                  hdw->enc_unsafe_stale ||
2820                  hdw->srate_dirty ||
2821                  hdw->res_ver_dirty ||
2822                  hdw->res_hor_dirty ||
2823                  hdw->cropw_dirty ||
2824                  hdw->croph_dirty ||
2825                  hdw->input_dirty ||
2826                  (hdw->active_stream_type != hdw->desired_stream_type));
2827         if (disruptive_change && !hdw->state_pipeline_idle) {
2828                 /* Pipeline is not idle; we can't proceed.  Arrange to
2829                    cause pipeline to stop so that we can try this again
2830                    later.... */
2831                 hdw->state_pipeline_pause = !0;
2832                 return 0;
2833         }
2834
2835         if (hdw->srate_dirty) {
2836                 /* Write new sample rate into control structure since
2837                  * the master copy is stale.  We must track srate
2838                  * separate from the mpeg control structure because
2839                  * other logic also uses this value. */
2840                 struct v4l2_ext_controls cs;
2841                 struct v4l2_ext_control c1;
2842                 memset(&cs,0,sizeof(cs));
2843                 memset(&c1,0,sizeof(c1));
2844                 cs.controls = &c1;
2845                 cs.count = 1;
2846                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2847                 c1.value = hdw->srate_val;
2848                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2849         }
2850
2851         /* Scan i2c core at this point - before we clear all the dirty
2852            bits.  Various parts of the i2c core will notice dirty bits as
2853            appropriate and arrange to broadcast or directly send updates to
2854            the client drivers in order to keep everything in sync */
2855         pvr2_i2c_core_check_stale(hdw);
2856
2857         for (idx = 0; idx < hdw->control_cnt; idx++) {
2858                 cptr = hdw->controls + idx;
2859                 if (!cptr->info->clear_dirty) continue;
2860                 cptr->info->clear_dirty(cptr);
2861         }
2862
2863         if (hdw->active_stream_type != hdw->desired_stream_type) {
2864                 /* Handle any side effects of stream config here */
2865                 hdw->active_stream_type = hdw->desired_stream_type;
2866         }
2867
2868         if (hdw->hdw_desc->signal_routing_scheme ==
2869             PVR2_ROUTING_SCHEME_GOTVIEW) {
2870                 u32 b;
2871                 /* Handle GOTVIEW audio switching */
2872                 pvr2_hdw_gpio_get_out(hdw,&b);
2873                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2874                         /* Set GPIO 11 */
2875                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
2876                 } else {
2877                         /* Clear GPIO 11 */
2878                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
2879                 }
2880         }
2881
2882         /* Now execute i2c core update */
2883         pvr2_i2c_core_sync(hdw);
2884
2885         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2886             hdw->state_encoder_run) {
2887                 /* If encoder isn't running or it can't be touched, then
2888                    this will get worked out later when we start the
2889                    encoder. */
2890                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2891         }
2892
2893         hdw->state_pipeline_config = !0;
2894         /* Hardware state may have changed in a way to cause the cropping
2895            capabilities to have changed.  So mark it stale, which will
2896            cause a later re-fetch. */
2897         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2898         return !0;
2899 }
2900
2901
2902 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2903 {
2904         int fl;
2905         LOCK_TAKE(hdw->big_lock);
2906         fl = pvr2_hdw_commit_setup(hdw);
2907         LOCK_GIVE(hdw->big_lock);
2908         if (!fl) return 0;
2909         return pvr2_hdw_wait(hdw,0);
2910 }
2911
2912
2913 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2914 {
2915         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2916         LOCK_TAKE(hdw->big_lock); do {
2917                 pvr2_i2c_core_sync(hdw);
2918         } while (0); LOCK_GIVE(hdw->big_lock);
2919 }
2920
2921
2922 static void pvr2_hdw_worker_poll(struct work_struct *work)
2923 {
2924         int fl = 0;
2925         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2926         LOCK_TAKE(hdw->big_lock); do {
2927                 fl = pvr2_hdw_state_eval(hdw);
2928         } while (0); LOCK_GIVE(hdw->big_lock);
2929         if (fl && hdw->state_func) {
2930                 hdw->state_func(hdw->state_data);
2931         }
2932 }
2933
2934
2935 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2936 {
2937         return wait_event_interruptible(
2938                 hdw->state_wait_data,
2939                 (hdw->state_stale == 0) &&
2940                 (!state || (hdw->master_state != state)));
2941 }
2942
2943
2944 /* Return name for this driver instance */
2945 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2946 {
2947         return hdw->name;
2948 }
2949
2950
2951 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2952 {
2953         return hdw->hdw_desc->description;
2954 }
2955
2956
2957 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2958 {
2959         return hdw->hdw_desc->shortname;
2960 }
2961
2962
2963 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2964 {
2965         int result;
2966         LOCK_TAKE(hdw->ctl_lock); do {
2967                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2968                 result = pvr2_send_request(hdw,
2969                                            hdw->cmd_buffer,1,
2970                                            hdw->cmd_buffer,1);
2971                 if (result < 0) break;
2972                 result = (hdw->cmd_buffer[0] != 0);
2973         } while(0); LOCK_GIVE(hdw->ctl_lock);
2974         return result;
2975 }
2976
2977
2978 /* Execute poll of tuner status */
2979 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2980 {
2981         LOCK_TAKE(hdw->big_lock); do {
2982                 pvr2_i2c_core_status_poll(hdw);
2983         } while (0); LOCK_GIVE(hdw->big_lock);
2984 }
2985
2986
2987 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
2988 {
2989         if (!hdw->cropcap_stale) {
2990                 return 0;
2991         }
2992         pvr2_i2c_core_status_poll(hdw);
2993         if (hdw->cropcap_stale) {
2994                 return -EIO;
2995         }
2996         return 0;
2997 }
2998
2999
3000 /* Return information about cropping capabilities */
3001 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3002 {
3003         int stat = 0;
3004         LOCK_TAKE(hdw->big_lock);
3005         stat = pvr2_hdw_check_cropcap(hdw);
3006         if (!stat) {
3007                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3008         }
3009         LOCK_GIVE(hdw->big_lock);
3010         return stat;
3011 }
3012
3013
3014 /* Return information about the tuner */
3015 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3016 {
3017         LOCK_TAKE(hdw->big_lock); do {
3018                 if (hdw->tuner_signal_stale) {
3019                         pvr2_i2c_core_status_poll(hdw);
3020                 }
3021                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3022         } while (0); LOCK_GIVE(hdw->big_lock);
3023         return 0;
3024 }
3025
3026
3027 /* Get handle to video output stream */
3028 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3029 {
3030         return hp->vid_stream;
3031 }
3032
3033
3034 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3035 {
3036         int nr = pvr2_hdw_get_unit_number(hdw);
3037         LOCK_TAKE(hdw->big_lock); do {
3038                 hdw->log_requested = !0;
3039                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3040                 pvr2_i2c_core_check_stale(hdw);
3041                 hdw->log_requested = 0;
3042                 pvr2_i2c_core_sync(hdw);
3043                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3044                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3045                 pvr2_hdw_state_log_state(hdw);
3046                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3047         } while (0); LOCK_GIVE(hdw->big_lock);
3048 }
3049
3050
3051 /* Grab EEPROM contents, needed for direct method. */
3052 #define EEPROM_SIZE 8192
3053 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3054 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3055 {
3056         struct i2c_msg msg[2];
3057         u8 *eeprom;
3058         u8 iadd[2];
3059         u8 addr;
3060         u16 eepromSize;
3061         unsigned int offs;
3062         int ret;
3063         int mode16 = 0;
3064         unsigned pcnt,tcnt;
3065         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3066         if (!eeprom) {
3067                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3068                            "Failed to allocate memory"
3069                            " required to read eeprom");
3070                 return NULL;
3071         }
3072
3073         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3074                      hdw->eeprom_addr);
3075         addr = hdw->eeprom_addr;
3076         /* Seems that if the high bit is set, then the *real* eeprom
3077            address is shifted right now bit position (noticed this in
3078            newer PVR USB2 hardware) */
3079         if (addr & 0x80) addr >>= 1;
3080
3081         /* FX2 documentation states that a 16bit-addressed eeprom is
3082            expected if the I2C address is an odd number (yeah, this is
3083            strange but it's what they do) */
3084         mode16 = (addr & 1);
3085         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3086         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3087                      " using %d bit addressing",eepromSize,addr,
3088                      mode16 ? 16 : 8);
3089
3090         msg[0].addr = addr;
3091         msg[0].flags = 0;
3092         msg[0].len = mode16 ? 2 : 1;
3093         msg[0].buf = iadd;
3094         msg[1].addr = addr;
3095         msg[1].flags = I2C_M_RD;
3096
3097         /* We have to do the actual eeprom data fetch ourselves, because
3098            (1) we're only fetching part of the eeprom, and (2) if we were
3099            getting the whole thing our I2C driver can't grab it in one
3100            pass - which is what tveeprom is otherwise going to attempt */
3101         memset(eeprom,0,EEPROM_SIZE);
3102         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3103                 pcnt = 16;
3104                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3105                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3106                 if (mode16) {
3107                         iadd[0] = offs >> 8;
3108                         iadd[1] = offs;
3109                 } else {
3110                         iadd[0] = offs;
3111                 }
3112                 msg[1].len = pcnt;
3113                 msg[1].buf = eeprom+tcnt;
3114                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3115                                         msg,ARRAY_SIZE(msg))) != 2) {
3116                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3117                                    "eeprom fetch set offs err=%d",ret);
3118                         kfree(eeprom);
3119                         return NULL;
3120                 }
3121         }
3122         return eeprom;
3123 }
3124
3125
3126 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3127                                 int prom_flag,
3128                                 int enable_flag)
3129 {
3130         int ret;
3131         u16 address;
3132         unsigned int pipe;
3133         LOCK_TAKE(hdw->big_lock); do {
3134                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3135
3136                 if (!enable_flag) {
3137                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3138                                    "Cleaning up after CPU firmware fetch");
3139                         kfree(hdw->fw_buffer);
3140                         hdw->fw_buffer = NULL;
3141                         hdw->fw_size = 0;
3142                         if (hdw->fw_cpu_flag) {
3143                                 /* Now release the CPU.  It will disconnect
3144                                    and reconnect later. */
3145                                 pvr2_hdw_cpureset_assert(hdw,0);
3146                         }
3147                         break;
3148                 }
3149
3150                 hdw->fw_cpu_flag = (prom_flag == 0);
3151                 if (hdw->fw_cpu_flag) {
3152                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3153                                    "Preparing to suck out CPU firmware");
3154                         hdw->fw_size = 0x2000;
3155                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3156                         if (!hdw->fw_buffer) {
3157                                 hdw->fw_size = 0;
3158                                 break;
3159                         }
3160
3161                         /* We have to hold the CPU during firmware upload. */
3162                         pvr2_hdw_cpureset_assert(hdw,1);
3163
3164                         /* download the firmware from address 0000-1fff in 2048
3165                            (=0x800) bytes chunk. */
3166
3167                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3168                                    "Grabbing CPU firmware");
3169                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3170                         for(address = 0; address < hdw->fw_size;
3171                             address += 0x800) {
3172                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3173                                                       0xa0,0xc0,
3174                                                       address,0,
3175                                                       hdw->fw_buffer+address,
3176                                                       0x800,HZ);
3177                                 if (ret < 0) break;
3178                         }
3179
3180                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3181                                    "Done grabbing CPU firmware");
3182                 } else {
3183                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3184                                    "Sucking down EEPROM contents");
3185                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3186                         if (!hdw->fw_buffer) {
3187                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3188                                            "EEPROM content suck failed.");
3189                                 break;
3190                         }
3191                         hdw->fw_size = EEPROM_SIZE;
3192                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3193                                    "Done sucking down EEPROM contents");
3194                 }
3195
3196         } while (0); LOCK_GIVE(hdw->big_lock);
3197 }
3198
3199
3200 /* Return true if we're in a mode for retrieval CPU firmware */
3201 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3202 {
3203         return hdw->fw_buffer != NULL;
3204 }
3205
3206
3207 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3208                        char *buf,unsigned int cnt)
3209 {
3210         int ret = -EINVAL;
3211         LOCK_TAKE(hdw->big_lock); do {
3212                 if (!buf) break;
3213                 if (!cnt) break;
3214
3215                 if (!hdw->fw_buffer) {
3216                         ret = -EIO;
3217                         break;
3218                 }
3219
3220                 if (offs >= hdw->fw_size) {
3221                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3222                                    "Read firmware data offs=%d EOF",
3223                                    offs);
3224                         ret = 0;
3225                         break;
3226                 }
3227
3228                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3229
3230                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3231
3232                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3233                            "Read firmware data offs=%d cnt=%d",
3234                            offs,cnt);
3235                 ret = cnt;
3236         } while (0); LOCK_GIVE(hdw->big_lock);
3237
3238         return ret;
3239 }
3240
3241
3242 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3243                                   enum pvr2_v4l_type index)
3244 {
3245         switch (index) {
3246         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3247         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3248         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3249         default: return -1;
3250         }
3251 }
3252
3253
3254 /* Store a v4l minor device number */
3255 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3256                                      enum pvr2_v4l_type index,int v)
3257 {
3258         switch (index) {
3259         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3260         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3261         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3262         default: break;
3263         }
3264 }
3265
3266
3267 static void pvr2_ctl_write_complete(struct urb *urb)
3268 {
3269         struct pvr2_hdw *hdw = urb->context;
3270         hdw->ctl_write_pend_flag = 0;
3271         if (hdw->ctl_read_pend_flag) return;
3272         complete(&hdw->ctl_done);
3273 }
3274
3275
3276 static void pvr2_ctl_read_complete(struct urb *urb)
3277 {
3278         struct pvr2_hdw *hdw = urb->context;
3279         hdw->ctl_read_pend_flag = 0;
3280         if (hdw->ctl_write_pend_flag) return;
3281         complete(&hdw->ctl_done);
3282 }
3283
3284
3285 static void pvr2_ctl_timeout(unsigned long data)
3286 {
3287         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3288         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3289                 hdw->ctl_timeout_flag = !0;
3290                 if (hdw->ctl_write_pend_flag)
3291                         usb_unlink_urb(hdw->ctl_write_urb);
3292                 if (hdw->ctl_read_pend_flag)
3293                         usb_unlink_urb(hdw->ctl_read_urb);
3294         }
3295 }
3296
3297
3298 /* Issue a command and get a response from the device.  This extended
3299    version includes a probe flag (which if set means that device errors
3300    should not be logged or treated as fatal) and a timeout in jiffies.
3301    This can be used to non-lethally probe the health of endpoint 1. */
3302 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3303                                 unsigned int timeout,int probe_fl,
3304                                 void *write_data,unsigned int write_len,
3305                                 void *read_data,unsigned int read_len)
3306 {
3307         unsigned int idx;
3308         int status = 0;
3309         struct timer_list timer;
3310         if (!hdw->ctl_lock_held) {
3311                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3312                            "Attempted to execute control transfer"
3313                            " without lock!!");
3314                 return -EDEADLK;
3315         }
3316         if (!hdw->flag_ok && !probe_fl) {
3317                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3318                            "Attempted to execute control transfer"
3319                            " when device not ok");
3320                 return -EIO;
3321         }
3322         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3323                 if (!probe_fl) {
3324                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3325                                    "Attempted to execute control transfer"
3326                                    " when USB is disconnected");
3327                 }
3328                 return -ENOTTY;
3329         }
3330
3331         /* Ensure that we have sane parameters */
3332         if (!write_data) write_len = 0;
3333         if (!read_data) read_len = 0;
3334         if (write_len > PVR2_CTL_BUFFSIZE) {
3335                 pvr2_trace(
3336                         PVR2_TRACE_ERROR_LEGS,
3337                         "Attempted to execute %d byte"
3338                         " control-write transfer (limit=%d)",
3339                         write_len,PVR2_CTL_BUFFSIZE);
3340                 return -EINVAL;
3341         }
3342         if (read_len > PVR2_CTL_BUFFSIZE) {
3343                 pvr2_trace(
3344                         PVR2_TRACE_ERROR_LEGS,
3345                         "Attempted to execute %d byte"
3346                         " control-read transfer (limit=%d)",
3347                         write_len,PVR2_CTL_BUFFSIZE);
3348                 return -EINVAL;
3349         }
3350         if ((!write_len) && (!read_len)) {
3351                 pvr2_trace(
3352                         PVR2_TRACE_ERROR_LEGS,
3353                         "Attempted to execute null control transfer?");
3354                 return -EINVAL;
3355         }
3356
3357
3358         hdw->cmd_debug_state = 1;
3359         if (write_len) {
3360                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3361         } else {
3362                 hdw->cmd_debug_code = 0;
3363         }
3364         hdw->cmd_debug_write_len = write_len;
3365         hdw->cmd_debug_read_len = read_len;
3366
3367         /* Initialize common stuff */
3368         init_completion(&hdw->ctl_done);
3369         hdw->ctl_timeout_flag = 0;
3370         hdw->ctl_write_pend_flag = 0;
3371         hdw->ctl_read_pend_flag = 0;
3372         init_timer(&timer);
3373         timer.expires = jiffies + timeout;
3374         timer.data = (unsigned long)hdw;
3375         timer.function = pvr2_ctl_timeout;
3376
3377         if (write_len) {
3378                 hdw->cmd_debug_state = 2;
3379                 /* Transfer write data to internal buffer */
3380                 for (idx = 0; idx < write_len; idx++) {
3381                         hdw->ctl_write_buffer[idx] =
3382                                 ((unsigned char *)write_data)[idx];
3383                 }
3384                 /* Initiate a write request */
3385                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3386                                   hdw->usb_dev,
3387                                   usb_sndbulkpipe(hdw->usb_dev,
3388                                                   PVR2_CTL_WRITE_ENDPOINT),
3389                                   hdw->ctl_write_buffer,
3390                                   write_len,
3391                                   pvr2_ctl_write_complete,
3392                                   hdw);
3393                 hdw->ctl_write_urb->actual_length = 0;
3394                 hdw->ctl_write_pend_flag = !0;
3395                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3396                 if (status < 0) {
3397                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3398                                    "Failed to submit write-control"
3399                                    " URB status=%d",status);
3400                         hdw->ctl_write_pend_flag = 0;
3401                         goto done;
3402                 }
3403         }
3404
3405         if (read_len) {
3406                 hdw->cmd_debug_state = 3;
3407                 memset(hdw->ctl_read_buffer,0x43,read_len);
3408                 /* Initiate a read request */
3409                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3410                                   hdw->usb_dev,
3411                                   usb_rcvbulkpipe(hdw->usb_dev,
3412                                                   PVR2_CTL_READ_ENDPOINT),
3413                                   hdw->ctl_read_buffer,
3414                                   read_len,
3415                                   pvr2_ctl_read_complete,
3416                                   hdw);
3417                 hdw->ctl_read_urb->actual_length = 0;
3418                 hdw->ctl_read_pend_flag = !0;
3419                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3420                 if (status < 0) {
3421                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3422                                    "Failed to submit read-control"
3423                                    " URB status=%d",status);
3424                         hdw->ctl_read_pend_flag = 0;
3425                         goto done;
3426                 }
3427         }
3428
3429         /* Start timer */
3430         add_timer(&timer);
3431
3432         /* Now wait for all I/O to complete */
3433         hdw->cmd_debug_state = 4;
3434         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3435                 wait_for_completion(&hdw->ctl_done);
3436         }
3437         hdw->cmd_debug_state = 5;
3438
3439         /* Stop timer */
3440         del_timer_sync(&timer);
3441
3442         hdw->cmd_debug_state = 6;
3443         status = 0;
3444
3445         if (hdw->ctl_timeout_flag) {
3446                 status = -ETIMEDOUT;
3447                 if (!probe_fl) {
3448                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3449                                    "Timed out control-write");
3450                 }
3451                 goto done;
3452         }
3453
3454         if (write_len) {
3455                 /* Validate results of write request */
3456                 if ((hdw->ctl_write_urb->status != 0) &&
3457                     (hdw->ctl_write_urb->status != -ENOENT) &&
3458                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3459                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3460                         /* USB subsystem is reporting some kind of failure
3461                            on the write */
3462                         status = hdw->ctl_write_urb->status;
3463                         if (!probe_fl) {
3464                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3465                                            "control-write URB failure,"
3466                                            " status=%d",
3467                                            status);
3468                         }
3469                         goto done;
3470                 }
3471                 if (hdw->ctl_write_urb->actual_length < write_len) {
3472                         /* Failed to write enough data */
3473                         status = -EIO;
3474                         if (!probe_fl) {
3475                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3476                                            "control-write URB short,"
3477                                            " expected=%d got=%d",
3478                                            write_len,
3479                                            hdw->ctl_write_urb->actual_length);
3480                         }
3481                         goto done;
3482                 }
3483         }
3484         if (read_len) {
3485                 /* Validate results of read request */
3486                 if ((hdw->ctl_read_urb->status != 0) &&
3487                     (hdw->ctl_read_urb->status != -ENOENT) &&
3488                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3489                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3490                         /* USB subsystem is reporting some kind of failure
3491                            on the read */
3492                         status = hdw->ctl_read_urb->status;
3493                         if (!probe_fl) {
3494                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3495                                            "control-read URB failure,"
3496                                            " status=%d",
3497                                            status);
3498                         }
3499                         goto done;
3500                 }
3501                 if (hdw->ctl_read_urb->actual_length < read_len) {
3502                         /* Failed to read enough data */
3503                         status = -EIO;
3504                         if (!probe_fl) {
3505                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3506                                            "control-read URB short,"
3507                                            " expected=%d got=%d",
3508                                            read_len,
3509                                            hdw->ctl_read_urb->actual_length);
3510                         }
3511                         goto done;
3512                 }
3513                 /* Transfer retrieved data out from internal buffer */
3514                 for (idx = 0; idx < read_len; idx++) {
3515                         ((unsigned char *)read_data)[idx] =
3516                                 hdw->ctl_read_buffer[idx];
3517                 }
3518         }
3519
3520  done:
3521
3522         hdw->cmd_debug_state = 0;
3523         if ((status < 0) && (!probe_fl)) {
3524                 pvr2_hdw_render_useless(hdw);
3525         }
3526         return status;
3527 }
3528
3529
3530 int pvr2_send_request(struct pvr2_hdw *hdw,
3531                       void *write_data,unsigned int write_len,
3532                       void *read_data,unsigned int read_len)
3533 {
3534         return pvr2_send_request_ex(hdw,HZ*4,0,
3535                                     write_data,write_len,
3536                                     read_data,read_len);
3537 }
3538
3539
3540 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3541 {
3542         int ret;
3543         unsigned int cnt = 1;
3544         unsigned int args = 0;
3545         LOCK_TAKE(hdw->ctl_lock);
3546         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3547         args = (cmdcode >> 8) & 0xffu;
3548         args = (args > 2) ? 2 : args;
3549         if (args) {
3550                 cnt += args;
3551                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3552                 if (args > 1) {
3553                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3554                 }
3555         }
3556         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3557                 unsigned int idx;
3558                 unsigned int ccnt,bcnt;
3559                 char tbuf[50];
3560                 cmdcode &= 0xffu;
3561                 bcnt = 0;
3562                 ccnt = scnprintf(tbuf+bcnt,
3563                                  sizeof(tbuf)-bcnt,
3564                                  "Sending FX2 command 0x%x",cmdcode);
3565                 bcnt += ccnt;
3566                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3567                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3568                                 ccnt = scnprintf(tbuf+bcnt,
3569                                                  sizeof(tbuf)-bcnt,
3570                                                  " \"%s\"",
3571                                                  pvr2_fx2cmd_desc[idx].desc);
3572                                 bcnt += ccnt;
3573                                 break;
3574                         }
3575                 }
3576                 if (args) {
3577                         ccnt = scnprintf(tbuf+bcnt,
3578                                          sizeof(tbuf)-bcnt,
3579                                          " (%u",hdw->cmd_buffer[1]);
3580                         bcnt += ccnt;
3581                         if (args > 1) {
3582                                 ccnt = scnprintf(tbuf+bcnt,
3583                                                  sizeof(tbuf)-bcnt,
3584                                                  ",%u",hdw->cmd_buffer[2]);
3585                                 bcnt += ccnt;
3586                         }
3587                         ccnt = scnprintf(tbuf+bcnt,
3588                                          sizeof(tbuf)-bcnt,
3589                                          ")");
3590                         bcnt += ccnt;
3591                 }
3592                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3593         }
3594         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3595         LOCK_GIVE(hdw->ctl_lock);
3596         return ret;
3597 }
3598
3599
3600 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3601 {
3602         int ret;
3603
3604         LOCK_TAKE(hdw->ctl_lock);
3605
3606         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3607         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3608         hdw->cmd_buffer[5] = 0;
3609         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3610         hdw->cmd_buffer[7] = reg & 0xff;
3611
3612
3613         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3614
3615         LOCK_GIVE(hdw->ctl_lock);
3616
3617         return ret;
3618 }
3619
3620
3621 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3622 {
3623         int ret = 0;
3624
3625         LOCK_TAKE(hdw->ctl_lock);
3626
3627         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3628         hdw->cmd_buffer[1] = 0;
3629         hdw->cmd_buffer[2] = 0;
3630         hdw->cmd_buffer[3] = 0;
3631         hdw->cmd_buffer[4] = 0;
3632         hdw->cmd_buffer[5] = 0;
3633         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3634         hdw->cmd_buffer[7] = reg & 0xff;
3635
3636         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3637         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3638
3639         LOCK_GIVE(hdw->ctl_lock);
3640
3641         return ret;
3642 }
3643
3644
3645 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3646 {
3647         if (!hdw->flag_ok) return;
3648         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3649                    "Device being rendered inoperable");
3650         if (hdw->vid_stream) {
3651                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3652         }
3653         hdw->flag_ok = 0;
3654         trace_stbit("flag_ok",hdw->flag_ok);
3655         pvr2_hdw_state_sched(hdw);
3656 }
3657
3658
3659 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3660 {
3661         int ret;
3662         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3663         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3664         if (ret == 1) {
3665                 ret = usb_reset_device(hdw->usb_dev);
3666                 usb_unlock_device(hdw->usb_dev);
3667         } else {
3668                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3669                            "Failed to lock USB device ret=%d",ret);
3670         }
3671         if (init_pause_msec) {
3672                 pvr2_trace(PVR2_TRACE_INFO,
3673                            "Waiting %u msec for hardware to settle",
3674                            init_pause_msec);
3675                 msleep(init_pause_msec);
3676         }
3677
3678 }
3679
3680
3681 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3682 {
3683         char da[1];
3684         unsigned int pipe;
3685         int ret;
3686
3687         if (!hdw->usb_dev) return;
3688
3689         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3690
3691         da[0] = val ? 0x01 : 0x00;
3692
3693         /* Write the CPUCS register on the 8051.  The lsb of the register
3694            is the reset bit; a 1 asserts reset while a 0 clears it. */
3695         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3696         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3697         if (ret < 0) {
3698                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3699                            "cpureset_assert(%d) error=%d",val,ret);
3700                 pvr2_hdw_render_useless(hdw);
3701         }
3702 }
3703
3704
3705 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3706 {
3707         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3708 }
3709
3710
3711 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3712 {
3713         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3714 }
3715
3716
3717 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3718 {
3719         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3720 }
3721
3722
3723 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3724 {
3725         if (!hdw->decoder_ctrl) {
3726                 pvr2_trace(PVR2_TRACE_INIT,
3727                            "Unable to reset decoder: nothing attached");
3728                 return -ENOTTY;
3729         }
3730
3731         if (!hdw->decoder_ctrl->force_reset) {
3732                 pvr2_trace(PVR2_TRACE_INIT,
3733                            "Unable to reset decoder: not implemented");
3734                 return -ENOTTY;
3735         }
3736
3737         pvr2_trace(PVR2_TRACE_INIT,
3738                    "Requesting decoder reset");
3739         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3740         return 0;
3741 }
3742
3743
3744 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3745 {
3746         hdw->flag_ok = !0;
3747         return pvr2_issue_simple_cmd(hdw,
3748                                      FX2CMD_HCW_DEMOD_RESETIN |
3749                                      (1 << 8) |
3750                                      ((onoff ? 1 : 0) << 16));
3751 }
3752
3753
3754 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3755 {
3756         hdw->flag_ok = !0;
3757         return pvr2_issue_simple_cmd(hdw,(onoff ?
3758                                           FX2CMD_ONAIR_DTV_POWER_ON :
3759                                           FX2CMD_ONAIR_DTV_POWER_OFF));
3760 }
3761
3762
3763 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3764                                                 int onoff)
3765 {
3766         return pvr2_issue_simple_cmd(hdw,(onoff ?
3767                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
3768                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
3769 }
3770
3771
3772 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3773 {
3774         int cmode;
3775         /* Compare digital/analog desired setting with current setting.  If
3776            they don't match, fix it... */
3777         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3778         if (cmode == hdw->pathway_state) {
3779                 /* They match; nothing to do */
3780                 return;
3781         }
3782
3783         switch (hdw->hdw_desc->digital_control_scheme) {
3784         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3785                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3786                 if (cmode == PVR2_PATHWAY_ANALOG) {
3787                         /* If moving to analog mode, also force the decoder
3788                            to reset.  If no decoder is attached, then it's
3789                            ok to ignore this because if/when the decoder
3790                            attaches, it will reset itself at that time. */
3791                         pvr2_hdw_cmd_decoder_reset(hdw);
3792                 }
3793                 break;
3794         case PVR2_DIGITAL_SCHEME_ONAIR:
3795                 /* Supposedly we should always have the power on whether in
3796                    digital or analog mode.  But for now do what appears to
3797                    work... */
3798                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3799                 break;
3800         default: break;
3801         }
3802
3803         pvr2_hdw_untrip_unlocked(hdw);
3804         hdw->pathway_state = cmode;
3805 }
3806
3807
3808 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3809 {
3810         /* change some GPIO data
3811          *
3812          * note: bit d7 of dir appears to control the LED,
3813          * so we shut it off here.
3814          *
3815          */
3816         if (onoff) {
3817                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3818         } else {
3819                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3820         }
3821         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3822 }
3823
3824
3825 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3826
3827 static led_method_func led_methods[] = {
3828         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3829 };
3830
3831
3832 /* Toggle LED */
3833 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3834 {
3835         unsigned int scheme_id;
3836         led_method_func fp;
3837
3838         if ((!onoff) == (!hdw->led_on)) return;
3839
3840         hdw->led_on = onoff != 0;
3841
3842         scheme_id = hdw->hdw_desc->led_scheme;
3843         if (scheme_id < ARRAY_SIZE(led_methods)) {
3844                 fp = led_methods[scheme_id];
3845         } else {
3846                 fp = NULL;
3847         }
3848
3849         if (fp) (*fp)(hdw,onoff);
3850 }
3851
3852
3853 /* Stop / start video stream transport */
3854 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3855 {
3856         int ret;
3857
3858         /* If we're in analog mode, then just issue the usual analog
3859            command. */
3860         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3861                 return pvr2_issue_simple_cmd(hdw,
3862                                              (runFl ?
3863                                               FX2CMD_STREAMING_ON :
3864                                               FX2CMD_STREAMING_OFF));
3865                 /*Note: Not reached */
3866         }
3867
3868         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3869                 /* Whoops, we don't know what mode we're in... */
3870                 return -EINVAL;
3871         }
3872
3873         /* To get here we have to be in digital mode.  The mechanism here
3874            is unfortunately different for different vendors.  So we switch
3875            on the device's digital scheme attribute in order to figure out
3876            what to do. */
3877         switch (hdw->hdw_desc->digital_control_scheme) {
3878         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3879                 return pvr2_issue_simple_cmd(hdw,
3880                                              (runFl ?
3881                                               FX2CMD_HCW_DTV_STREAMING_ON :
3882                                               FX2CMD_HCW_DTV_STREAMING_OFF));
3883         case PVR2_DIGITAL_SCHEME_ONAIR:
3884                 ret = pvr2_issue_simple_cmd(hdw,
3885                                             (runFl ?
3886                                              FX2CMD_STREAMING_ON :
3887                                              FX2CMD_STREAMING_OFF));
3888                 if (ret) return ret;
3889                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3890         default:
3891                 return -EINVAL;
3892         }
3893 }
3894
3895
3896 /* Evaluate whether or not state_pathway_ok can change */
3897 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3898 {
3899         if (hdw->state_pathway_ok) {
3900                 /* Nothing to do if pathway is already ok */
3901                 return 0;
3902         }
3903         if (!hdw->state_pipeline_idle) {
3904                 /* Not allowed to change anything if pipeline is not idle */
3905                 return 0;
3906         }
3907         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3908         hdw->state_pathway_ok = !0;
3909         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3910         return !0;
3911 }
3912
3913
3914 /* Evaluate whether or not state_encoder_ok can change */
3915 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3916 {
3917         if (hdw->state_encoder_ok) return 0;
3918         if (hdw->flag_tripped) return 0;
3919         if (hdw->state_encoder_run) return 0;
3920         if (hdw->state_encoder_config) return 0;
3921         if (hdw->state_decoder_run) return 0;
3922         if (hdw->state_usbstream_run) return 0;
3923         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3924                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3925         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3926                 return 0;
3927         }
3928
3929         if (pvr2_upload_firmware2(hdw) < 0) {
3930                 hdw->flag_tripped = !0;
3931                 trace_stbit("flag_tripped",hdw->flag_tripped);
3932                 return !0;
3933         }
3934         hdw->state_encoder_ok = !0;
3935         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3936         return !0;
3937 }
3938
3939
3940 /* Evaluate whether or not state_encoder_config can change */
3941 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3942 {
3943         if (hdw->state_encoder_config) {
3944                 if (hdw->state_encoder_ok) {
3945                         if (hdw->state_pipeline_req &&
3946                             !hdw->state_pipeline_pause) return 0;
3947                 }
3948                 hdw->state_encoder_config = 0;
3949                 hdw->state_encoder_waitok = 0;
3950                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3951                 /* paranoia - solve race if timer just completed */
3952                 del_timer_sync(&hdw->encoder_wait_timer);
3953         } else {
3954                 if (!hdw->state_pathway_ok ||
3955                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3956                     !hdw->state_encoder_ok ||
3957                     !hdw->state_pipeline_idle ||
3958                     hdw->state_pipeline_pause ||
3959                     !hdw->state_pipeline_req ||
3960                     !hdw->state_pipeline_config) {
3961                         /* We must reset the enforced wait interval if
3962                            anything has happened that might have disturbed
3963                            the encoder.  This should be a rare case. */
3964                         if (timer_pending(&hdw->encoder_wait_timer)) {
3965                                 del_timer_sync(&hdw->encoder_wait_timer);
3966                         }
3967                         if (hdw->state_encoder_waitok) {
3968                                 /* Must clear the state - therefore we did
3969                                    something to a state bit and must also
3970                                    return true. */
3971                                 hdw->state_encoder_waitok = 0;
3972                                 trace_stbit("state_encoder_waitok",
3973                                             hdw->state_encoder_waitok);
3974                                 return !0;
3975                         }
3976                         return 0;
3977                 }
3978                 if (!hdw->state_encoder_waitok) {
3979                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3980                                 /* waitok flag wasn't set and timer isn't
3981                                    running.  Check flag once more to avoid
3982                                    a race then start the timer.  This is
3983                                    the point when we measure out a minimal
3984                                    quiet interval before doing something to
3985                                    the encoder. */
3986                                 if (!hdw->state_encoder_waitok) {
3987                                         hdw->encoder_wait_timer.expires =
3988                                                 jiffies +
3989                                                 (HZ * TIME_MSEC_ENCODER_WAIT
3990                                                  / 1000);
3991                                         add_timer(&hdw->encoder_wait_timer);
3992                                 }
3993                         }
3994                         /* We can't continue until we know we have been
3995                            quiet for the interval measured by this
3996                            timer. */
3997                         return 0;
3998                 }
3999                 pvr2_encoder_configure(hdw);
4000                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4001         }
4002         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4003         return !0;
4004 }
4005
4006
4007 /* Return true if the encoder should not be running. */
4008 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4009 {
4010         if (!hdw->state_encoder_ok) {
4011                 /* Encoder isn't healthy at the moment, so stop it. */
4012                 return !0;
4013         }
4014         if (!hdw->state_pathway_ok) {
4015                 /* Mode is not understood at the moment (i.e. it wants to
4016                    change), so encoder must be stopped. */
4017                 return !0;
4018         }
4019
4020         switch (hdw->pathway_state) {
4021         case PVR2_PATHWAY_ANALOG:
4022                 if (!hdw->state_decoder_run) {
4023                         /* We're in analog mode and the decoder is not
4024                            running; thus the encoder should be stopped as
4025                            well. */
4026                         return !0;
4027                 }
4028                 break;
4029         case PVR2_PATHWAY_DIGITAL:
4030                 if (hdw->state_encoder_runok) {
4031                         /* This is a funny case.  We're in digital mode so
4032                            really the encoder should be stopped.  However
4033                            if it really is running, only kill it after
4034                            runok has been set.  This gives a chance for the
4035                            onair quirk to function (encoder must run
4036                            briefly first, at least once, before onair
4037                            digital streaming can work). */
4038                         return !0;
4039                 }
4040                 break;
4041         default:
4042                 /* Unknown mode; so encoder should be stopped. */
4043                 return !0;
4044         }
4045
4046         /* If we get here, we haven't found a reason to stop the
4047            encoder. */
4048         return 0;
4049 }
4050
4051
4052 /* Return true if the encoder should be running. */
4053 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4054 {
4055         if (!hdw->state_encoder_ok) {
4056                 /* Don't run the encoder if it isn't healthy... */
4057                 return 0;
4058         }
4059         if (!hdw->state_pathway_ok) {
4060                 /* Don't run the encoder if we don't (yet) know what mode
4061                    we need to be in... */
4062                 return 0;
4063         }
4064
4065         switch (hdw->pathway_state) {
4066         case PVR2_PATHWAY_ANALOG:
4067                 if (hdw->state_decoder_run) {
4068                         /* In analog mode, if the decoder is running, then
4069                            run the encoder. */
4070                         return !0;
4071                 }
4072                 break;
4073         case PVR2_PATHWAY_DIGITAL:
4074                 if ((hdw->hdw_desc->digital_control_scheme ==
4075                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4076                     !hdw->state_encoder_runok) {
4077                         /* This is a quirk.  OnAir hardware won't stream
4078                            digital until the encoder has been run at least
4079                            once, for a minimal period of time (empiricially
4080                            measured to be 1/4 second).  So if we're on
4081                            OnAir hardware and the encoder has never been
4082                            run at all, then start the encoder.  Normal
4083                            state machine logic in the driver will
4084                            automatically handle the remaining bits. */
4085                         return !0;
4086                 }
4087                 break;
4088         default:
4089                 /* For completeness (unknown mode; encoder won't run ever) */
4090                 break;
4091         }
4092         /* If we get here, then we haven't found any reason to run the
4093            encoder, so don't run it. */
4094         return 0;
4095 }
4096
4097
4098 /* Evaluate whether or not state_encoder_run can change */
4099 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4100 {
4101         if (hdw->state_encoder_run) {
4102                 if (!state_check_disable_encoder_run(hdw)) return 0;
4103                 if (hdw->state_encoder_ok) {
4104                         del_timer_sync(&hdw->encoder_run_timer);
4105                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4106                 }
4107                 hdw->state_encoder_run = 0;
4108         } else {
4109                 if (!state_check_enable_encoder_run(hdw)) return 0;
4110                 if (pvr2_encoder_start(hdw) < 0) return !0;
4111                 hdw->state_encoder_run = !0;
4112                 if (!hdw->state_encoder_runok) {
4113                         hdw->encoder_run_timer.expires =
4114                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4115                         add_timer(&hdw->encoder_run_timer);
4116                 }
4117         }
4118         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4119         return !0;
4120 }
4121
4122
4123 /* Timeout function for quiescent timer. */
4124 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4125 {
4126         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4127         hdw->state_decoder_quiescent = !0;
4128         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4129         hdw->state_stale = !0;
4130         queue_work(hdw->workqueue,&hdw->workpoll);
4131 }
4132
4133
4134 /* Timeout function for encoder wait timer. */
4135 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4136 {
4137         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4138         hdw->state_encoder_waitok = !0;
4139         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4140         hdw->state_stale = !0;
4141         queue_work(hdw->workqueue,&hdw->workpoll);
4142 }
4143
4144
4145 /* Timeout function for encoder run timer. */
4146 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4147 {
4148         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4149         if (!hdw->state_encoder_runok) {
4150                 hdw->state_encoder_runok = !0;
4151                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4152                 hdw->state_stale = !0;
4153                 queue_work(hdw->workqueue,&hdw->workpoll);
4154         }
4155 }
4156
4157
4158 /* Evaluate whether or not state_decoder_run can change */
4159 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4160 {
4161         if (hdw->state_decoder_run) {
4162                 if (hdw->state_encoder_ok) {
4163                         if (hdw->state_pipeline_req &&
4164                             !hdw->state_pipeline_pause &&
4165                             hdw->state_pathway_ok) return 0;
4166                 }
4167                 if (!hdw->flag_decoder_missed) {
4168                         pvr2_decoder_enable(hdw,0);
4169                 }
4170                 hdw->state_decoder_quiescent = 0;
4171                 hdw->state_decoder_run = 0;
4172                 /* paranoia - solve race if timer just completed */
4173                 del_timer_sync(&hdw->quiescent_timer);
4174         } else {
4175                 if (!hdw->state_decoder_quiescent) {
4176                         if (!timer_pending(&hdw->quiescent_timer)) {
4177                                 /* We don't do something about the
4178                                    quiescent timer until right here because
4179                                    we also want to catch cases where the
4180                                    decoder was already not running (like
4181                                    after initialization) as opposed to
4182                                    knowing that we had just stopped it.
4183                                    The second flag check is here to cover a
4184                                    race - the timer could have run and set
4185                                    this flag just after the previous check
4186                                    but before we did the pending check. */
4187                                 if (!hdw->state_decoder_quiescent) {
4188                                         hdw->quiescent_timer.expires =
4189                                                 jiffies +
4190                                                 (HZ * TIME_MSEC_DECODER_WAIT
4191                                                  / 1000);
4192                                         add_timer(&hdw->quiescent_timer);
4193                                 }
4194                         }
4195                         /* Don't allow decoder to start again until it has
4196                            been quiesced first.  This little detail should
4197                            hopefully further stabilize the encoder. */
4198                         return 0;
4199                 }
4200                 if (!hdw->state_pathway_ok ||
4201                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4202                     !hdw->state_pipeline_req ||
4203                     hdw->state_pipeline_pause ||
4204                     !hdw->state_pipeline_config ||
4205                     !hdw->state_encoder_config ||
4206                     !hdw->state_encoder_ok) return 0;
4207                 del_timer_sync(&hdw->quiescent_timer);
4208                 if (hdw->flag_decoder_missed) return 0;
4209                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4210                 hdw->state_decoder_quiescent = 0;
4211                 hdw->state_decoder_run = !0;
4212         }
4213         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4214         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4215         return !0;
4216 }
4217
4218
4219 /* Evaluate whether or not state_usbstream_run can change */
4220 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4221 {
4222         if (hdw->state_usbstream_run) {
4223                 int fl = !0;
4224                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4225                         fl = (hdw->state_encoder_ok &&
4226                               hdw->state_encoder_run);
4227                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4228                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4229                         fl = hdw->state_encoder_ok;
4230                 }
4231                 if (fl &&
4232                     hdw->state_pipeline_req &&
4233                     !hdw->state_pipeline_pause &&
4234                     hdw->state_pathway_ok) {
4235                         return 0;
4236                 }
4237                 pvr2_hdw_cmd_usbstream(hdw,0);
4238                 hdw->state_usbstream_run = 0;
4239         } else {
4240                 if (!hdw->state_pipeline_req ||
4241                     hdw->state_pipeline_pause ||
4242                     !hdw->state_pathway_ok) return 0;
4243                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4244                         if (!hdw->state_encoder_ok ||
4245                             !hdw->state_encoder_run) return 0;
4246                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4247                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4248                         if (!hdw->state_encoder_ok) return 0;
4249                         if (hdw->state_encoder_run) return 0;
4250                         if (hdw->hdw_desc->digital_control_scheme ==
4251                             PVR2_DIGITAL_SCHEME_ONAIR) {
4252                                 /* OnAir digital receivers won't stream
4253                                    unless the analog encoder has run first.
4254                                    Why?  I have no idea.  But don't even
4255                                    try until we know the analog side is
4256                                    known to have run. */
4257                                 if (!hdw->state_encoder_runok) return 0;
4258                         }
4259                 }
4260                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4261                 hdw->state_usbstream_run = !0;
4262         }
4263         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4264         return !0;
4265 }
4266
4267
4268 /* Attempt to configure pipeline, if needed */
4269 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4270 {
4271         if (hdw->state_pipeline_config ||
4272             hdw->state_pipeline_pause) return 0;
4273         pvr2_hdw_commit_execute(hdw);
4274         return !0;
4275 }
4276
4277
4278 /* Update pipeline idle and pipeline pause tracking states based on other
4279    inputs.  This must be called whenever the other relevant inputs have
4280    changed. */
4281 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4282 {
4283         unsigned int st;
4284         int updatedFl = 0;
4285         /* Update pipeline state */
4286         st = !(hdw->state_encoder_run ||
4287                hdw->state_decoder_run ||
4288                hdw->state_usbstream_run ||
4289                (!hdw->state_decoder_quiescent));
4290         if (!st != !hdw->state_pipeline_idle) {
4291                 hdw->state_pipeline_idle = st;
4292                 updatedFl = !0;
4293         }
4294         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4295                 hdw->state_pipeline_pause = 0;
4296                 updatedFl = !0;
4297         }
4298         return updatedFl;
4299 }
4300
4301
4302 typedef int (*state_eval_func)(struct pvr2_hdw *);
4303
4304 /* Set of functions to be run to evaluate various states in the driver. */
4305 static const state_eval_func eval_funcs[] = {
4306         state_eval_pathway_ok,
4307         state_eval_pipeline_config,
4308         state_eval_encoder_ok,
4309         state_eval_encoder_config,
4310         state_eval_decoder_run,
4311         state_eval_encoder_run,
4312         state_eval_usbstream_run,
4313 };
4314
4315
4316 /* Process various states and return true if we did anything interesting. */
4317 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4318 {
4319         unsigned int i;
4320         int state_updated = 0;
4321         int check_flag;
4322
4323         if (!hdw->state_stale) return 0;
4324         if ((hdw->fw1_state != FW1_STATE_OK) ||
4325             !hdw->flag_ok) {
4326                 hdw->state_stale = 0;
4327                 return !0;
4328         }
4329         /* This loop is the heart of the entire driver.  It keeps trying to
4330            evaluate various bits of driver state until nothing changes for
4331            one full iteration.  Each "bit of state" tracks some global
4332            aspect of the driver, e.g. whether decoder should run, if
4333            pipeline is configured, usb streaming is on, etc.  We separately
4334            evaluate each of those questions based on other driver state to
4335            arrive at the correct running configuration. */
4336         do {
4337                 check_flag = 0;
4338                 state_update_pipeline_state(hdw);
4339                 /* Iterate over each bit of state */
4340                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4341                         if ((*eval_funcs[i])(hdw)) {
4342                                 check_flag = !0;
4343                                 state_updated = !0;
4344                                 state_update_pipeline_state(hdw);
4345                         }
4346                 }
4347         } while (check_flag && hdw->flag_ok);
4348         hdw->state_stale = 0;
4349         trace_stbit("state_stale",hdw->state_stale);
4350         return state_updated;
4351 }
4352
4353
4354 static unsigned int print_input_mask(unsigned int msk,
4355                                      char *buf,unsigned int acnt)
4356 {
4357         unsigned int idx,ccnt;
4358         unsigned int tcnt = 0;
4359         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4360                 if (!((1 << idx) & msk)) continue;
4361                 ccnt = scnprintf(buf+tcnt,
4362                                  acnt-tcnt,
4363                                  "%s%s",
4364                                  (tcnt ? ", " : ""),
4365                                  control_values_input[idx]);
4366                 tcnt += ccnt;
4367         }
4368         return tcnt;
4369 }
4370
4371
4372 static const char *pvr2_pathway_state_name(int id)
4373 {
4374         switch (id) {
4375         case PVR2_PATHWAY_ANALOG: return "analog";
4376         case PVR2_PATHWAY_DIGITAL: return "digital";
4377         default: return "unknown";
4378         }
4379 }
4380
4381
4382 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4383                                              char *buf,unsigned int acnt)
4384 {
4385         switch (which) {
4386         case 0:
4387                 return scnprintf(
4388                         buf,acnt,
4389                         "driver:%s%s%s%s%s <mode=%s>",
4390                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4391                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4392                         (hdw->flag_disconnected ? " <disconnected>" :
4393                          " <connected>"),
4394                         (hdw->flag_tripped ? " <tripped>" : ""),
4395                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4396                         pvr2_pathway_state_name(hdw->pathway_state));
4397
4398         case 1:
4399                 return scnprintf(
4400                         buf,acnt,
4401                         "pipeline:%s%s%s%s",
4402                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4403                         (hdw->state_pipeline_config ?
4404                          " <configok>" : " <stale>"),
4405                         (hdw->state_pipeline_req ? " <req>" : ""),
4406                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4407         case 2:
4408                 return scnprintf(
4409                         buf,acnt,
4410                         "worker:%s%s%s%s%s%s%s",
4411                         (hdw->state_decoder_run ?
4412                          " <decode:run>" :
4413                          (hdw->state_decoder_quiescent ?
4414                           "" : " <decode:stop>")),
4415                         (hdw->state_decoder_quiescent ?
4416                          " <decode:quiescent>" : ""),
4417                         (hdw->state_encoder_ok ?
4418                          "" : " <encode:init>"),
4419                         (hdw->state_encoder_run ?
4420                          (hdw->state_encoder_runok ?
4421                           " <encode:run>" :
4422                           " <encode:firstrun>") :
4423                          (hdw->state_encoder_runok ?
4424                           " <encode:stop>" :
4425                           " <encode:virgin>")),
4426                         (hdw->state_encoder_config ?
4427                          " <encode:configok>" :
4428                          (hdw->state_encoder_waitok ?
4429                           "" : " <encode:waitok>")),
4430                         (hdw->state_usbstream_run ?
4431                          " <usb:run>" : " <usb:stop>"),
4432                         (hdw->state_pathway_ok ?
4433                          " <pathway:ok>" : ""));
4434         case 3:
4435                 return scnprintf(
4436                         buf,acnt,
4437                         "state: %s",
4438                         pvr2_get_state_name(hdw->master_state));
4439         case 4: {
4440                 unsigned int tcnt = 0;
4441                 unsigned int ccnt;
4442
4443                 ccnt = scnprintf(buf,
4444                                  acnt,
4445                                  "Hardware supported inputs: ");
4446                 tcnt += ccnt;
4447                 tcnt += print_input_mask(hdw->input_avail_mask,
4448                                          buf+tcnt,
4449                                          acnt-tcnt);
4450                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4451                         ccnt = scnprintf(buf+tcnt,
4452                                          acnt-tcnt,
4453                                          "; allowed inputs: ");
4454                         tcnt += ccnt;
4455                         tcnt += print_input_mask(hdw->input_allowed_mask,
4456                                                  buf+tcnt,
4457                                                  acnt-tcnt);
4458                 }
4459                 return tcnt;
4460         }
4461         case 5: {
4462                 struct pvr2_stream_stats stats;
4463                 if (!hdw->vid_stream) break;
4464                 pvr2_stream_get_stats(hdw->vid_stream,
4465                                       &stats,
4466                                       0);
4467                 return scnprintf(
4468                         buf,acnt,
4469                         "Bytes streamed=%u"
4470                         " URBs: queued=%u idle=%u ready=%u"
4471                         " processed=%u failed=%u",
4472                         stats.bytes_processed,
4473                         stats.buffers_in_queue,
4474                         stats.buffers_in_idle,
4475                         stats.buffers_in_ready,
4476                         stats.buffers_processed,
4477                         stats.buffers_failed);
4478         }
4479         default: break;
4480         }
4481         return 0;
4482 }
4483
4484
4485 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4486                                    char *buf,unsigned int acnt)
4487 {
4488         unsigned int bcnt,ccnt,idx;
4489         bcnt = 0;
4490         LOCK_TAKE(hdw->big_lock);
4491         for (idx = 0; ; idx++) {
4492                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4493                 if (!ccnt) break;
4494                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4495                 if (!acnt) break;
4496                 buf[0] = '\n'; ccnt = 1;
4497                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4498         }
4499         LOCK_GIVE(hdw->big_lock);
4500         return bcnt;
4501 }
4502
4503
4504 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4505 {
4506         char buf[128];
4507         unsigned int idx,ccnt;
4508
4509         for (idx = 0; ; idx++) {
4510                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4511                 if (!ccnt) break;
4512                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4513         }
4514 }
4515
4516
4517 /* Evaluate and update the driver's current state, taking various actions
4518    as appropriate for the update. */
4519 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4520 {
4521         unsigned int st;
4522         int state_updated = 0;
4523         int callback_flag = 0;
4524         int analog_mode;
4525
4526         pvr2_trace(PVR2_TRACE_STBITS,
4527                    "Drive state check START");
4528         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4529                 pvr2_hdw_state_log_state(hdw);
4530         }
4531
4532         /* Process all state and get back over disposition */
4533         state_updated = pvr2_hdw_state_update(hdw);
4534
4535         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4536
4537         /* Update master state based upon all other states. */
4538         if (!hdw->flag_ok) {
4539                 st = PVR2_STATE_DEAD;
4540         } else if (hdw->fw1_state != FW1_STATE_OK) {
4541                 st = PVR2_STATE_COLD;
4542         } else if ((analog_mode ||
4543                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4544                    !hdw->state_encoder_ok) {
4545                 st = PVR2_STATE_WARM;
4546         } else if (hdw->flag_tripped ||
4547                    (analog_mode && hdw->flag_decoder_missed)) {
4548                 st = PVR2_STATE_ERROR;
4549         } else if (hdw->state_usbstream_run &&
4550                    (!analog_mode ||
4551                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4552                 st = PVR2_STATE_RUN;
4553         } else {
4554                 st = PVR2_STATE_READY;
4555         }
4556         if (hdw->master_state != st) {
4557                 pvr2_trace(PVR2_TRACE_STATE,
4558                            "Device state change from %s to %s",
4559                            pvr2_get_state_name(hdw->master_state),
4560                            pvr2_get_state_name(st));
4561                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4562                 hdw->master_state = st;
4563                 state_updated = !0;
4564                 callback_flag = !0;
4565         }
4566         if (state_updated) {
4567                 /* Trigger anyone waiting on any state changes here. */
4568                 wake_up(&hdw->state_wait_data);
4569         }
4570
4571         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4572                 pvr2_hdw_state_log_state(hdw);
4573         }
4574         pvr2_trace(PVR2_TRACE_STBITS,
4575                    "Drive state check DONE callback=%d",callback_flag);
4576
4577         return callback_flag;
4578 }
4579
4580
4581 /* Cause kernel thread to check / update driver state */
4582 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4583 {
4584         if (hdw->state_stale) return;
4585         hdw->state_stale = !0;
4586         trace_stbit("state_stale",hdw->state_stale);
4587         queue_work(hdw->workqueue,&hdw->workpoll);
4588 }
4589
4590
4591 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4592 {
4593         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4594 }
4595
4596
4597 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4598 {
4599         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4600 }
4601
4602
4603 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4604 {
4605         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4606 }
4607
4608
4609 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4610 {
4611         u32 cval,nval;
4612         int ret;
4613         if (~msk) {
4614                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4615                 if (ret) return ret;
4616                 nval = (cval & ~msk) | (val & msk);
4617                 pvr2_trace(PVR2_TRACE_GPIO,
4618                            "GPIO direction changing 0x%x:0x%x"
4619                            " from 0x%x to 0x%x",
4620                            msk,val,cval,nval);
4621         } else {
4622                 nval = val;
4623                 pvr2_trace(PVR2_TRACE_GPIO,
4624                            "GPIO direction changing to 0x%x",nval);
4625         }
4626         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4627 }
4628
4629
4630 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4631 {
4632         u32 cval,nval;
4633         int ret;
4634         if (~msk) {
4635                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4636                 if (ret) return ret;
4637                 nval = (cval & ~msk) | (val & msk);
4638                 pvr2_trace(PVR2_TRACE_GPIO,
4639                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4640                            msk,val,cval,nval);
4641         } else {
4642                 nval = val;
4643                 pvr2_trace(PVR2_TRACE_GPIO,
4644                            "GPIO output changing to 0x%x",nval);
4645         }
4646         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4647 }
4648
4649
4650 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4651 {
4652         return hdw->input_avail_mask;
4653 }
4654
4655
4656 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4657 {
4658         return hdw->input_allowed_mask;
4659 }
4660
4661
4662 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4663 {
4664         if (hdw->input_val != v) {
4665                 hdw->input_val = v;
4666                 hdw->input_dirty = !0;
4667         }
4668
4669         /* Handle side effects - if we switch to a mode that needs the RF
4670            tuner, then select the right frequency choice as well and mark
4671            it dirty. */
4672         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4673                 hdw->freqSelector = 0;
4674                 hdw->freqDirty = !0;
4675         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4676                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4677                 hdw->freqSelector = 1;
4678                 hdw->freqDirty = !0;
4679         }
4680         return 0;
4681 }
4682
4683
4684 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4685                                unsigned int change_mask,
4686                                unsigned int change_val)
4687 {
4688         int ret = 0;
4689         unsigned int nv,m,idx;
4690         LOCK_TAKE(hdw->big_lock);
4691         do {
4692                 nv = hdw->input_allowed_mask & ~change_mask;
4693                 nv |= (change_val & change_mask);
4694                 nv &= hdw->input_avail_mask;
4695                 if (!nv) {
4696                         /* No legal modes left; return error instead. */
4697                         ret = -EPERM;
4698                         break;
4699                 }
4700                 hdw->input_allowed_mask = nv;
4701                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4702                         /* Current mode is still in the allowed mask, so
4703                            we're done. */
4704                         break;
4705                 }
4706                 /* Select and switch to a mode that is still in the allowed
4707                    mask */
4708                 if (!hdw->input_allowed_mask) {
4709                         /* Nothing legal; give up */
4710                         break;
4711                 }
4712                 m = hdw->input_allowed_mask;
4713                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4714                         if (!((1 << idx) & m)) continue;
4715                         pvr2_hdw_set_input(hdw,idx);
4716                         break;
4717                 }
4718         } while (0);
4719         LOCK_GIVE(hdw->big_lock);
4720         return ret;
4721 }
4722
4723
4724 /* Find I2C address of eeprom */
4725 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4726 {
4727         int result;
4728         LOCK_TAKE(hdw->ctl_lock); do {
4729                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4730                 result = pvr2_send_request(hdw,
4731                                            hdw->cmd_buffer,1,
4732                                            hdw->cmd_buffer,1);
4733                 if (result < 0) break;
4734                 result = hdw->cmd_buffer[0];
4735         } while(0); LOCK_GIVE(hdw->ctl_lock);
4736         return result;
4737 }
4738
4739
4740 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4741                              u32 match_type, u32 match_chip, u64 reg_id,
4742                              int setFl,u64 *val_ptr)
4743 {
4744 #ifdef CONFIG_VIDEO_ADV_DEBUG
4745         struct pvr2_i2c_client *cp;
4746         struct v4l2_register req;
4747         int stat = 0;
4748         int okFl = 0;
4749
4750         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4751
4752         req.match_type = match_type;
4753         req.match_chip = match_chip;
4754         req.reg = reg_id;
4755         if (setFl) req.val = *val_ptr;
4756         mutex_lock(&hdw->i2c_list_lock); do {
4757                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4758                         if (!v4l2_chip_match_i2c_client(
4759                                     cp->client,
4760                                     req.match_type, req.match_chip)) {
4761                                 continue;
4762                         }
4763                         stat = pvr2_i2c_client_cmd(
4764                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4765                                     VIDIOC_DBG_G_REGISTER),&req);
4766                         if (!setFl) *val_ptr = req.val;
4767                         okFl = !0;
4768                         break;
4769                 }
4770         } while (0); mutex_unlock(&hdw->i2c_list_lock);
4771         if (okFl) {
4772                 return stat;
4773         }
4774         return -EINVAL;
4775 #else
4776         return -ENOSYS;
4777 #endif
4778 }
4779
4780
4781 /*
4782   Stuff for Emacs to see, in order to encourage consistent editing style:
4783   *** Local Variables: ***
4784   *** mode: c ***
4785   *** fill-column: 75 ***
4786   *** tab-width: 8 ***
4787   *** c-basic-offset: 8 ***
4788   *** End: ***
4789   */