3 * drivers/media/video/omap/sensor_ov9640.c
5 * Ov9640 Sensor driver for OMAP camera sensor interface
7 * Author: Andy Lowe (source@mvista.com)
9 * Copyright (C) 2004 MontaVista Software, Inc.
10 * Copyright (C) 2004 Texas Instruments.
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
17 #include <linux/errno.h>
18 #include <linux/i2c.h>
19 #include <linux/videodev.h>
20 #include <media/video-buf.h>
21 #include <linux/delay.h>
22 #include <asm/mach-types.h>
24 #include "sensor_if.h"
26 #include "h3sensorpower.h"
31 struct ov9640_sensor {
33 struct i2c_client client;
34 struct i2c_driver driver;
35 int ver; /* OV9640 version */
38 static struct ov9640_sensor ov9640;
40 /* list of image formats supported by OV9640 sensor */
41 const static struct v4l2_fmtdesc ov9640_formats[] = {
43 /* Note: V4L2 defines RGB565 as:
46 * g2 g1 g0 r4 r3 r2 r1 r0 b4 b3 b2 b1 b0 g5 g4 g3
48 * We interpret RGB565 as:
51 * g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3
53 .description = "RGB565, le",
54 .pixelformat = V4L2_PIX_FMT_RGB565,
56 /* Note: V4L2 defines RGB565X as:
59 * b4 b3 b2 b1 b0 g5 g4 g3 g2 g1 g0 r4 r3 r2 r1 r0
61 * We interpret RGB565X as:
64 * r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
66 .description = "RGB565, be",
67 .pixelformat = V4L2_PIX_FMT_RGB565X,
70 .description = "YUYV (YUV 4:2:2), packed",
71 .pixelformat = V4L2_PIX_FMT_YUYV,
73 .description = "UYVY, packed",
74 .pixelformat = V4L2_PIX_FMT_UYVY,
77 /* Note: V4L2 defines RGB555 as:
80 * g2 g1 g0 r4 r3 r2 r1 r0 x b4 b3 b2 b1 b0 g4 g3
82 * We interpret RGB555 as:
85 * g2 g1 g0 b4 b3 b2 b1 b0 x r4 r3 r2 r1 r0 g4 g3
87 .description = "RGB555, le",
88 .pixelformat = V4L2_PIX_FMT_RGB555,
90 /* Note: V4L2 defines RGB555X as:
93 * x b4 b3 b2 b1 b0 g4 g3 g2 g1 g0 r4 r3 r2 r1 r0
95 * We interpret RGB555X as:
98 * x r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
100 .description = "RGB555, be",
101 .pixelformat = V4L2_PIX_FMT_RGB555X,
105 #define NUM_CAPTURE_FORMATS (sizeof(ov9640_formats)/sizeof(ov9640_formats[0]))
106 #define NUM_OVERLAY_FORMATS 2
108 /* register initialization tables for OV9640 */
110 #define OV9640_REG_TERM 0xFF /* terminating list entry for reg */
111 #define OV9640_VAL_TERM 0xFF /* terminating list entry for val */
113 /* common OV9640 register initialization for all image sizes, pixel formats,
116 const static struct ov9640_reg ov9640_common[] = {
117 { 0x12, 0x80 }, { 0x11, 0x80 }, { 0x13, 0x88 }, /* COM7, CLKRC, COM8 */
118 { 0x01, 0x58 }, { 0x02, 0x24 }, { 0x04, 0x00 }, /* BLUE, RED, COM1 */
119 { 0x0E, 0x81 }, { 0x0F, 0x4F }, { 0x14, 0xcA }, /* COM5, COM6, COM9 */
120 { 0x16, 0x02 }, { 0x1B, 0x01 }, { 0x24, 0x70 }, /* ?, PSHFT, AEW */
121 { 0x25, 0x68 }, { 0x26, 0xD3 }, { 0x27, 0x90 }, /* AEB, VPT, BBIAS */
122 { 0x2A, 0x00 }, { 0x2B, 0x00 }, { 0x32, 0x24 }, /* EXHCH, EXHCL, HREF */
123 { 0x33, 0x02 }, { 0x37, 0x02 }, { 0x38, 0x13 }, /* CHLF, ADC, ACOM */
124 { 0x39, 0xF0 }, { 0x3A, 0x00 }, { 0x3B, 0x01 }, /* OFON, TSLB, COM11 */
125 { 0x3D, 0x90 }, { 0x3E, 0x02 }, { 0x3F, 0xF2 }, /* COM13, COM14, EDGE */
126 { 0x41, 0x02 }, { 0x42, 0xC8 }, /* COM16, COM17 */
127 { 0x43, 0xF0 }, { 0x44, 0x10 }, { 0x45, 0x6C }, /* ?, ?, ? */
128 { 0x46, 0x6C }, { 0x47, 0x44 }, { 0x48, 0x44 }, /* ?, ?, ? */
129 { 0x49, 0x03 }, { 0x59, 0x49 }, { 0x5A, 0x94 }, /* ?, ?, ? */
130 { 0x5B, 0x46 }, { 0x5C, 0x84 }, { 0x5D, 0x5C }, /* ?, ?, ? */
131 { 0x5E, 0x08 }, { 0x5F, 0x00 }, { 0x60, 0x14 }, /* ?, ?, ? */
132 { 0x61, 0xCE }, /* ? */
133 { 0x62, 0x70 }, { 0x63, 0x00 }, { 0x64, 0x04 }, /* LCC1, LCC2, LCC3 */
134 { 0x65, 0x00 }, { 0x66, 0x00 }, /* LCC4, LCC5 */
135 { 0x69, 0x00 }, { 0x6A, 0x3E }, { 0x6B, 0x3F }, /* HV, MBD, DBLV */
136 { 0x6C, 0x40 }, { 0x6D, 0x30 }, { 0x6E, 0x4B }, /* GSP1, GSP2, GSP3 */
137 { 0x6F, 0x60 }, { 0x70, 0x70 }, { 0x71, 0x70 }, /* GSP4, GSP5, GSP6 */
138 { 0x72, 0x70 }, { 0x73, 0x70 }, { 0x74, 0x60 }, /* GSP7, GSP8, GSP9 */
139 { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 }, /* GSP10,GSP11,GSP12 */
140 { 0x78, 0x3A }, { 0x79, 0x2E }, { 0x7A, 0x28 }, /* GSP13,GSP14,GSP15 */
141 { 0x7B, 0x22 }, { 0x7C, 0x04 }, { 0x7D, 0x07 }, /* GSP16,GST1, GST2 */
142 { 0x7E, 0x10 }, { 0x7F, 0x28 }, { 0x80, 0x36 }, /* GST3, GST4, GST5 */
143 { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 }, /* GST6, GST7, GST8 */
144 { 0x84, 0x6C }, { 0x85, 0x78 }, { 0x86, 0x8C }, /* GST9, GST10,GST11 */
145 { 0x87, 0x9E }, { 0x88, 0xBB }, { 0x89, 0xD2 }, /* GST12,GST13,GST14 */
146 { 0x8A, 0xE6 }, { 0x13, 0xaF }, { 0x15, 0x02 }, /* GST15, COM8 */
147 { 0x22, 0x8a }, /* GROS */
148 { OV9640_REG_TERM, OV9640_VAL_TERM }
151 /* OV9640 register configuration for all combinations of pixel format and
154 /* YUV (YCbCr) QQCIF */
155 const static struct ov9640_reg qqcif_yuv[] = {
156 { 0x12, 0x08 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
157 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
158 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
159 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
160 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
161 { 0x58, 0x0F }, /* MTXS */
162 { OV9640_REG_TERM, OV9640_VAL_TERM }
164 /* YUV (YCbCr) QQVGA */
165 const static struct ov9640_reg qqvga_yuv[] = {
166 { 0x12, 0x10 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
167 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
168 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
169 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
170 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
171 { 0x58, 0x0F }, /* MTXS */
172 { OV9640_REG_TERM, OV9640_VAL_TERM }
174 /* YUV (YCbCr) QCIF */
175 const static struct ov9640_reg qcif_yuv[] = {
176 { 0x12, 0x08 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
177 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
178 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
179 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
180 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
181 { 0x58, 0x0F }, /* MTXS */
182 { OV9640_REG_TERM, OV9640_VAL_TERM }
184 /* YUV (YCbCr) QVGA */
185 const static struct ov9640_reg qvga_yuv[] = {
186 { 0x12, 0x10 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
187 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
188 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
189 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
190 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
191 { 0x58, 0x0F }, /* MTXS */
192 { OV9640_REG_TERM, OV9640_VAL_TERM }
194 /* YUV (YCbCr) CIF */
195 const static struct ov9640_reg cif_yuv[] = {
196 { 0x12, 0x20 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
197 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
198 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
199 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
200 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
201 { 0x58, 0x0F }, /* MTXS */
202 { OV9640_REG_TERM, OV9640_VAL_TERM }
204 /* YUV (YCbCr) VGA */
205 const static struct ov9640_reg vga_yuv[] = {
206 { 0x12, 0x40 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
207 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
208 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
209 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
210 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
211 { 0x58, 0x0F }, /* MTXS */
212 { OV9640_REG_TERM, OV9640_VAL_TERM }
214 /* YUV (YCbCr) SXGA */
215 const static struct ov9640_reg sxga_yuv[] = {
216 { 0x12, 0x00 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
217 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
218 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
219 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
220 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
221 { 0x58, 0x0F }, /* MTXS */
222 { OV9640_REG_TERM, OV9640_VAL_TERM }
225 const static struct ov9640_reg qqcif_565[] = {
226 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
227 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
228 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
229 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
230 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
231 { 0x58, 0x65 }, /* MTXS */
232 { OV9640_REG_TERM, OV9640_VAL_TERM }
235 const static struct ov9640_reg qqvga_565[] = {
236 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
237 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
238 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
239 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
240 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
241 { 0x58, 0x65 }, /* MTXS */
242 { OV9640_REG_TERM, OV9640_VAL_TERM }
245 const static struct ov9640_reg qcif_565[] = {
246 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
247 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
248 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
249 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
250 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
251 { 0x58, 0x65 }, /* MTXS */
252 { OV9640_REG_TERM, OV9640_VAL_TERM }
255 const static struct ov9640_reg qvga_565[] = {
256 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
257 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
258 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
259 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
260 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
261 { 0x58, 0x65 }, /* MTXS */
262 { OV9640_REG_TERM, OV9640_VAL_TERM }
265 const static struct ov9640_reg cif_565[] = {
266 { 0x12, 0x24 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
267 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
268 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
269 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
270 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
271 { 0x58, 0x65 }, /* MTXS */
272 { OV9640_REG_TERM, OV9640_VAL_TERM }
275 const static struct ov9640_reg vga_565[] = {
276 { 0x12, 0x44 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
277 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
278 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
279 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
280 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
281 { 0x58, 0x65 }, /* MTXS */
282 { OV9640_REG_TERM, OV9640_VAL_TERM }
285 const static struct ov9640_reg sxga_565[] = {
286 { 0x12, 0x04 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
287 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
288 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
289 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
290 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
291 { 0x58, 0x65 }, /* MTXS */
292 { OV9640_REG_TERM, OV9640_VAL_TERM }
295 const static struct ov9640_reg qqcif_555[] = {
296 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
297 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
298 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
299 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
300 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
301 { 0x58, 0x65 }, /* MTXS */
302 { OV9640_REG_TERM, OV9640_VAL_TERM }
305 const static struct ov9640_reg qqvga_555[] = {
306 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
307 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
308 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
309 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
310 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
311 { 0x58, 0x65 }, /* MTXS */
312 { OV9640_REG_TERM, OV9640_VAL_TERM }
315 const static struct ov9640_reg qcif_555[] = {
316 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
317 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
318 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
319 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
320 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
321 { 0x58, 0x65 }, /* MTXS */
322 { OV9640_REG_TERM, OV9640_VAL_TERM }
325 const static struct ov9640_reg qvga_555[] = {
326 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
327 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
328 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
329 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
330 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
331 { 0x58, 0x65 }, /* MTXS */
332 { OV9640_REG_TERM, OV9640_VAL_TERM }
335 const static struct ov9640_reg cif_555[] = {
336 { 0x12, 0x24 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
337 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
338 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
339 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
340 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
341 { 0x58, 0x65 }, /* MTXS */
342 { OV9640_REG_TERM, OV9640_VAL_TERM }
345 const static struct ov9640_reg vga_555[] = {
346 { 0x12, 0x44 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
347 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
348 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
349 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
350 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
351 { 0x58, 0x65 }, /* MTXS */
352 { OV9640_REG_TERM, OV9640_VAL_TERM }
355 const static struct ov9640_reg sxga_555[] = {
356 { 0x12, 0x04 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
357 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
358 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
359 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
360 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
361 { 0x58, 0x65 }, /* MTXS */
362 { OV9640_REG_TERM, OV9640_VAL_TERM }
367 #define DEF_AUTOGAIN 1
368 #define DEF_EXPOSURE 154
370 #define DEF_FREEZE_AGCAEC 0
372 #define DEF_RED (255 - DEF_BLUE)
377 /* Our own specific controls */
378 #define V4L2_CID_FREEZE_AGCAEC V4L2_CID_PRIVATE_BASE+0
379 #define V4L2_CID_AUTOEXPOSURE V4L2_CID_PRIVATE_BASE+1
380 #define V4L2_CID_LAST_PRIV V4L2_CID_AUTOEXPOSURE
383 static struct vcontrol {
384 struct v4l2_queryctrl qc;
390 { { V4L2_CID_GAIN, V4L2_CTRL_TYPE_INTEGER, "Gain", 0, 63, 1,
392 0, OV9640_GAIN, 0x3f, 0 },
393 { { V4L2_CID_AUTOGAIN, V4L2_CTRL_TYPE_BOOLEAN, "Auto Gain", 0, 1, 0,
395 0, OV9640_COM8, 0x04, 2 },
396 { { V4L2_CID_EXPOSURE, V4L2_CTRL_TYPE_INTEGER, "Exposure", 0, 255, 1,
398 0, OV9640_AECH, 0xff, 0 },
399 { { V4L2_CID_AUTOEXPOSURE, V4L2_CTRL_TYPE_BOOLEAN, "Auto Exposure", 0, 1, 0,
401 0, OV9640_COM8, 0x01, 0 },
402 { { V4L2_CID_FREEZE_AGCAEC, V4L2_CTRL_TYPE_BOOLEAN, "Freeze AGC/AEC", 0,1,0,
404 0, OV9640_COM9, 0x01, 0 },
405 { { V4L2_CID_RED_BALANCE, V4L2_CTRL_TYPE_INTEGER, "Red Balance", 0, 255, 1,
407 0, OV9640_RED, 0xff, 0 },
408 { { V4L2_CID_BLUE_BALANCE, V4L2_CTRL_TYPE_INTEGER, "Blue Balance", 0, 255, 1,
410 0, OV9640_BLUE, 0xff, 0 },
411 { { V4L2_CID_AUTO_WHITE_BALANCE, V4L2_CTRL_TYPE_BOOLEAN, "Auto White Balance", 0,1,0,
413 0, OV9640_COM8, 0x02, 1 },
414 { { V4L2_CID_HFLIP, V4L2_CTRL_TYPE_BOOLEAN, "Mirror Image", 0, 1, 0,
416 0, OV9640_MVFP, 0x20, 5 },
417 { { V4L2_CID_VFLIP, V4L2_CTRL_TYPE_BOOLEAN, "Vertical Flip", 0, 1, 0,
419 0, OV9640_MVFP, 0x10, 4 },
422 #define NUM_CONTROLS (sizeof(control)/sizeof(control[0]))
424 const static struct ov9640_reg *
425 ov9640_reg_init[NUM_PIXEL_FORMATS][NUM_IMAGE_SIZES] =
427 { qqcif_yuv, qqvga_yuv, qcif_yuv, qvga_yuv, cif_yuv, vga_yuv, sxga_yuv },
428 { qqcif_565, qqvga_565, qcif_565, qvga_565, cif_565, vga_565, sxga_565 },
429 { qqcif_555, qqvga_555, qcif_555, qvga_555, cif_555, vga_555, sxga_555 },
434 * Read a value from a register in an OV9640 sensor device. The value is
436 * Returns zero if successful, or non-zero otherwise.
439 ov9640_read_reg(struct i2c_client *client, u8 reg, u8 *val)
442 struct i2c_msg msg[1];
443 unsigned char data[1];
445 if (!client->adapter)
448 msg->addr = client->addr;
453 err = i2c_transfer(client->adapter, msg, 1);
455 msg->flags = I2C_M_RD;
456 err = i2c_transfer(client->adapter, msg, 1);
465 /* Write a value to a register in an OV9640 sensor device.
466 * Returns zero if successful, or non-zero otherwise.
469 ov9640_write_reg(struct i2c_client *client, u8 reg, u8 val)
472 struct i2c_msg msg[1];
473 unsigned char data[2];
475 if (!client->adapter)
478 msg->addr = client->addr;
484 err = i2c_transfer(client->adapter, msg, 1);
491 ov9640_write_reg_mask(struct i2c_client *client, u8 reg, u8 *val, u8 mask)
499 /* need to do read - modify - write */
500 if ((rc = ov9640_read_reg(client, reg, &oldval)))
502 oldval &= (~mask); /* Clear the masked bits */
503 *val &= mask; /* Enforce mask on value */
504 newval = oldval | *val; /* Set the desired bits */
507 /* write the new value to the register */
508 if ((rc = ov9640_write_reg(client, reg, newval)))
511 if ((rc = ov9640_read_reg(client, reg, &newval)))
514 *val = newval & mask;
519 ov9640_read_reg_mask(struct i2c_client *client, u8 reg, u8 *val, u8 mask)
523 if ((rc = ov9640_read_reg(client, reg, val)))
530 /* Initialize a list of OV9640 registers.
531 * The list of registers is terminated by the pair of values
532 * { OV9640_REG_TERM, OV9640_VAL_TERM }.
533 * Returns zero if successful, or non-zero otherwise.
536 ov9640_write_regs(struct i2c_client *client, const struct ov9640_reg reglist[])
539 const struct ov9640_reg *next = reglist;
541 while (!((next->reg == OV9640_REG_TERM)
542 && (next->val == OV9640_VAL_TERM)))
544 err = ov9640_write_reg(client, next->reg, next->val);
553 /* Returns the index of the requested ID from the control structure array */
559 if (id < V4L2_CID_BASE)
562 for (i = NUM_CONTROLS - 1; i >= 0; i--)
563 if (control[i].qc.id == id)
570 /* Calculate the internal clock divisor (value of the CLKRC register) of the
571 * OV9640 given the image size, the frequency (in Hz) of its XCLK input and a
572 * desired frame period (in seconds). The frame period 'fper' is expressed as
573 * a fraction. The frame period is an input/output parameter.
574 * Returns the value of the OV9640 CLKRC register that will yield the frame
575 * period returned in 'fper' at the specified xclk frequency. The
576 * returned period will be as close to the requested period as possible.
579 ov9640_clkrc(enum image_size isize, unsigned long xclk, struct v4l2_fract *fper)
581 unsigned long fpm, fpm_max; /* frames per minute */
582 unsigned long divisor;
583 const unsigned long divisor_max = 64;
584 const static unsigned long clks_per_frame[] =
585 { 200000, 200000, 200000, 200000, 400000, 800000, 3200000 };
587 if (fper->numerator > 0)
588 fpm = (fper->denominator*60)/fper->numerator;
591 fpm_max = (xclk*60)/clks_per_frame[isize];
598 divisor = fpm_max/fpm;
599 if (divisor > divisor_max)
600 divisor = divisor_max;
601 fper->numerator = divisor*60;
602 fper->denominator = fpm_max;
604 /* try to reduce the fraction */
605 while (!(fper->denominator % 5) && !(fper->numerator % 5)) {
606 fper->numerator /= 5;
607 fper->denominator /= 5;
609 while (!(fper->denominator % 3) && !(fper->numerator % 3)) {
610 fper->numerator /= 3;
611 fper->denominator /= 3;
613 while (!(fper->denominator % 2) && !(fper->numerator % 2)) {
614 fper->numerator /= 2;
615 fper->denominator /= 2;
617 if (fper->numerator < fper->denominator) {
618 if (!(fper->denominator % fper->numerator)) {
619 fper->denominator /= fper->numerator;
624 if (!(fper->numerator % fper->denominator)) {
625 fper->numerator /= fper->denominator;
626 fper->denominator = 1;
630 /* we set bit 7 in CLKRC to enable the digital PLL */
631 return (0x80 | (divisor - 1));
634 /* Configure the OV9640 for a specified image size, pixel format, and frame
635 * period. xclk is the frequency (in Hz) of the xclk input to the OV9640.
636 * fper is the frame period (in seconds) expressed as a fraction.
637 * Returns zero if successful, or non-zero otherwise.
638 * The actual frame period is returned in fper.
641 ov9640_configure(struct i2c_client *client,
642 enum image_size isize,
643 enum pixel_format pfmt,
645 struct v4l2_fract *fper)
650 /* common register initialization */
651 err = ov9640_write_regs(client, ov9640_common);
655 /* configure image size and pixel format */
656 err = ov9640_write_regs(client, ov9640_reg_init[pfmt][isize]);
660 /* configure frame rate */
661 clkrc = ov9640_clkrc(isize, xclk, fper);
662 err = ov9640_write_reg(client, OV9640_CLKRC, clkrc);
674 if (machine_is_omap_h2())
677 if (machine_is_omap_h3()) {
678 err = h3_sensor_powerup();
686 ov9640_powerdown(void)
690 if (machine_is_omap_h2())
693 if (machine_is_omap_h3()) {
694 err = h3_sensor_powerdown();
703 ov9640sensor_power_on(void *priv)
705 return ov9640_powerup();
709 ov9640sensor_power_off(void *priv)
711 return ov9640_powerdown();
714 /* Detect if an OV9640 is present, and if so which revision.
715 * A device is considered to be detected if the manufacturer ID (MIDH and MIDL)
716 * and the product ID (PID) registers match the expected values.
717 * Any value of the version ID (VER) register is accepted.
718 * Here are the version numbers we know about:
719 * 0x48 --> OV9640 Revision 1 or OV9640 Revision 2
720 * 0x49 --> OV9640 Revision 3
721 * Returns a negative error number if no device is detected, or the
722 * non-negative value of the version ID register if a device is detected.
725 ov9640_detect(struct i2c_client *client)
727 u8 midh, midl, pid, ver;
732 if (ov9640_read_reg(client, OV9640_MIDH, &midh))
734 if (ov9640_read_reg(client, OV9640_MIDL, &midl))
736 if (ov9640_read_reg(client, OV9640_PID, &pid))
738 if (ov9640_read_reg(client, OV9640_VER, &ver))
741 if ((midh != OV9640_MIDH_MAGIC)
742 || (midl != OV9640_MIDL_MAGIC)
743 || (pid != OV9640_PID_MAGIC))
745 /* We didn't read the values we expected, so
746 * this must not be an OV9640.
753 /* This function registers an I2C client via i2c_attach_client() for an OV9640
754 * sensor device. If 'probe' is non-zero, then the I2C client is only
755 * registered if the device can be detected. If 'probe' is zero, then no
756 * device detection is attempted and the I2C client is always registered.
757 * Returns zero if an I2C client is successfully registered, or non-zero
761 ov9640_i2c_attach_client(struct i2c_adapter *adap, int addr, int probe)
763 struct ov9640_sensor *sensor = &ov9640;
764 struct i2c_client *client = &sensor->client;
768 return -EBUSY; /* our client is already attached */
771 client->driver = &sensor->driver;
772 client->adapter = adap;
774 err = i2c_attach_client(client);
776 client->adapter = NULL;
781 err = ov9640_detect(client);
783 i2c_detach_client(client);
784 client->adapter = NULL;
792 /* This function is called by i2c_del_adapter() and i2c_del_driver()
793 * if the adapter or driver with which this I2C client is associated is
794 * removed. This function unregisters the client via i2c_detach_client().
795 * Returns zero if the client is successfully detached, or non-zero
799 ov9640_i2c_detach_client(struct i2c_client *client)
803 if (!client->adapter)
804 return -ENODEV; /* our client isn't attached */
806 err = i2c_detach_client(client);
807 client->adapter = NULL;
812 /* This function will be called for each registered I2C bus adapter when our
813 * I2C driver is registered via i2c_add_driver(). It will also be called
814 * whenever a new I2C adapter is registered after our I2C driver is registered.
815 * This function probes the specified I2C bus adapter to determine if an
816 * OV9640 sensor device is present. If a device is detected, an I2C client
817 * is registered for it via ov9640_i2c_attach_client(). Note that we can't use
818 * the standard i2c_probe() function to look for the sensor because the OMAP
819 * I2C controller doesn't support probing.
820 * Returns zero if an OV9640 device is detected and an I2C client successfully
821 * registered for it, or non-zero otherwise.
824 ov9640_i2c_probe_adapter(struct i2c_adapter *adap)
826 return ov9640_i2c_attach_client(adap, OV9640_I2C_ADDR, 1);
829 /* Find the best match for a requested image capture size. The best match
830 * is chosen as the nearest match that has the same number or fewer pixels
831 * as the requested size, or the smallest image size if the requested size
832 * has fewer pixels than the smallest image.
834 static enum image_size
835 ov9640_find_size(unsigned int width, unsigned int height)
837 enum image_size isize;
838 unsigned long pixels = width*height;
840 for (isize = QQCIF; isize < SXGA; isize++) {
841 if (ov9640_sizes[isize + 1].height*
842 ov9640_sizes[isize + 1].width > pixels)
850 /* following are sensor interface functions implemented by
851 * OV9640 sensor driver.
854 ov9640sensor_query_control(struct v4l2_queryctrl *qc, void *priv)
858 i = find_vctrl (qc->id);
860 qc->flags = V4L2_CTRL_FLAG_DISABLED;
871 ov9640sensor_get_control(struct v4l2_control *vc, void *priv)
873 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
874 struct i2c_client *client = &sensor->client;
876 struct vcontrol * lvc;
878 i = find_vctrl(vc->id);
883 if (ov9640_read_reg_mask(client, lvc->reg, (u8 *)&val, lvc->mask))
886 val = val >> lvc->start_bit;
888 vc->value = lvc->current_value = val;
895 ov9640sensor_set_control(struct v4l2_control *vc, void *priv)
897 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
898 struct i2c_client *client = &sensor->client;
899 struct vcontrol *lvc;
903 i = find_vctrl(vc->id);
908 val = val << lvc->start_bit;
909 if (ov9640_write_reg_mask(client, lvc->reg, (u8 *)&val, (u8)lvc->mask))
912 val = val>> lvc->start_bit;
914 lvc->current_value = val;
920 /* Implement the VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
923 ov9640sensor_enum_pixformat(struct v4l2_fmtdesc *fmt, void *priv)
925 int index = fmt->index;
926 enum v4l2_buf_type type = fmt->type;
928 memset(fmt, 0, sizeof(*fmt));
933 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
934 if (index >= NUM_CAPTURE_FORMATS)
938 case V4L2_BUF_TYPE_VIDEO_OVERLAY:
939 if (index >= NUM_OVERLAY_FORMATS)
947 fmt->flags = ov9640_formats[index].flags;
948 strlcpy(fmt->description, ov9640_formats[index].description, sizeof(fmt->description));
949 fmt->pixelformat = ov9640_formats[index].pixelformat;
954 /* Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This
955 * ioctl is used to negotiate the image capture size and pixel format
956 * without actually making it take effect.
959 ov9640sensor_try_format(struct v4l2_pix_format *pix, void *priv)
961 enum image_size isize;
964 isize = ov9640_find_size(pix->width, pix->height);
965 pix->width = ov9640_sizes[isize].width;
966 pix->height = ov9640_sizes[isize].height;
967 for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) {
968 if (pix->pixelformat == ov9640_formats[ifmt].pixelformat)
971 if (ifmt == NUM_CAPTURE_FORMATS)
973 pix->pixelformat = ov9640_formats[ifmt].pixelformat;
974 pix->field = V4L2_FIELD_NONE;
975 pix->bytesperline = pix->width*2;
976 pix->sizeimage = pix->bytesperline*pix->height;
978 switch (pix->pixelformat) {
979 case V4L2_PIX_FMT_YUYV:
980 case V4L2_PIX_FMT_UYVY:
982 pix->colorspace = V4L2_COLORSPACE_JPEG;
984 case V4L2_PIX_FMT_RGB565:
985 case V4L2_PIX_FMT_RGB565X:
986 case V4L2_PIX_FMT_RGB555:
987 case V4L2_PIX_FMT_RGB555X:
988 pix->colorspace = V4L2_COLORSPACE_SRGB;
994 /* Given the image capture format in pix, the nominal frame period in
995 * timeperframe, calculate the required xclk frequency
996 * The nominal xclk input frequency of the OV9640 is 24MHz, maximum
997 * frequency is 48MHz, and minimum frequency is 10MHz.
1000 ov9640sensor_calc_xclk(struct v4l2_pix_format *pix,
1001 struct v4l2_fract *timeperframe, void *priv)
1003 unsigned long tgt_xclk; /* target xclk */
1004 unsigned long tgt_fpm; /* target frames per minute */
1005 enum image_size isize;
1007 /* We use arbitrary rules to select the xclk frequency. If the
1008 * capture size is VGA and the frame rate is greater than 900
1009 * frames per minute, or if the capture size is SXGA and the
1010 * frame rate is greater than 450 frames per minutes, then the
1011 * xclk frequency will be set to 48MHz. Otherwise, the xclk
1012 * frequency will be set to 24MHz. If the mclk frequency is such that
1013 * the target xclk frequency is not achievable, then xclk will be set
1014 * as close as to the target as possible.
1016 if ((timeperframe->numerator == 0)
1017 || (timeperframe->denominator == 0))
1019 /* supply a default nominal_timeperframe of 15 fps */
1020 timeperframe->numerator = 1;
1021 timeperframe->denominator = 15;
1023 tgt_fpm = (timeperframe->denominator*60)
1024 / timeperframe->numerator;
1025 tgt_xclk = 24000000;
1026 isize = ov9640_find_size(pix->width, pix->height);
1030 tgt_xclk = 48000000;
1034 tgt_xclk = 48000000;
1042 /* Given a capture format in pix, the frame period in timeperframe, and
1043 * the xclk frequency, set the capture format of the OV9640 sensor.
1044 * The actual frame period will be returned in timeperframe.
1047 ov9640sensor_configure(struct v4l2_pix_format *pix, unsigned long xclk,
1048 struct v4l2_fract *timeperframe, void *priv)
1050 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
1051 enum pixel_format pfmt = YUV;
1053 switch (pix->pixelformat) {
1054 case V4L2_PIX_FMT_RGB565:
1055 case V4L2_PIX_FMT_RGB565X:
1058 case V4L2_PIX_FMT_RGB555:
1059 case V4L2_PIX_FMT_RGB555X:
1062 case V4L2_PIX_FMT_YUYV:
1063 case V4L2_PIX_FMT_UYVY:
1068 return ov9640_configure(&sensor->client,
1069 ov9640_find_size(pix->width, pix->height),
1070 pfmt, xclk, timeperframe);
1073 /* Prepare for the driver to exit.
1074 * Balances ov9640sensor_init().
1075 * This function must de-initialize the sensor and its associated data
1079 ov9640sensor_cleanup(void *priv)
1081 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
1084 i2c_del_driver(&sensor->driver);
1090 /* Initialize the OV9640 sensor.
1091 * This routine allocates and initializes the data structure for the sensor,
1092 * powers up the sensor, registers the I2C driver, and sets a default image
1093 * capture format in pix. The capture format is not actually programmed
1094 * into the OV9640 sensor by this routine.
1095 * This function must return a non-NULL value to indicate that
1096 * initialization is successful.
1099 ov9640sensor_init(struct v4l2_pix_format *pix)
1101 struct ov9640_sensor *sensor = &ov9640;
1102 struct i2c_driver *driver = &sensor->driver;
1105 memset(sensor, 0, sizeof(*sensor));
1107 /* power-up the sensor */
1108 if (ov9640_powerup())
1111 strlcpy(driver->driver.name, "OV9640 I2C driver", sizeof(driver->driver.name));
1112 driver->id = I2C_DRIVERID_MISC;
1113 driver->attach_adapter = ov9640_i2c_probe_adapter;
1114 driver->detach_client = ov9640_i2c_detach_client;
1116 err = i2c_add_driver(driver);
1118 printk(KERN_ERR "Failed to register OV9640 I2C client.\n");
1121 if (!sensor->client.adapter) {
1123 "Failed to detect OV9640 sensor chip.\n");
1128 "OV9640 sensor chip version 0x%02x detected\n", sensor->ver);
1131 /* Make the default capture format QCIF RGB565 */
1132 pix->width = ov9640_sizes[QCIF].width;
1133 pix->height = ov9640_sizes[QCIF].height;
1134 pix->pixelformat = V4L2_PIX_FMT_RGB565;
1135 ov9640sensor_try_format(pix, NULL);
1137 return (void *)sensor;
1140 struct camera_sensor camera_sensor_if = {
1143 .init = ov9640sensor_init,
1144 .cleanup = ov9640sensor_cleanup,
1145 .enum_pixformat = ov9640sensor_enum_pixformat,
1146 .try_format = ov9640sensor_try_format,
1147 .calc_xclk = ov9640sensor_calc_xclk,
1148 .configure = ov9640sensor_configure,
1149 .query_control = ov9640sensor_query_control,
1150 .get_control = ov9640sensor_get_control,
1151 .set_control = ov9640sensor_set_control,
1152 .power_on = ov9640sensor_power_on,
1153 .power_off = ov9640sensor_power_off,
1156 void print_ov9640_regs(void *priv)
1158 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
1160 for (reg=0x00; reg <=0x8A; reg++)
1161 if (ov9640_read_reg(&sensor->client,reg,&val))
1162 printk("error reading %x\n", reg);
1164 printk("reg %x = %x\n", reg, val);
1167 #endif /* ifdef CAMERA_OV9640 */