3 * drivers/media/video/omap/sensor_ov9640.c
5 * Ov9640 Sensor driver for OMAP camera sensor interface
7 * Author: Andy Lowe (source@mvista.com)
9 * Copyright (C) 2004 MontaVista Software, Inc.
10 * Copyright (C) 2004 Texas Instruments.
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
17 #include <linux/errno.h>
18 #include <linux/i2c.h>
19 #include <linux/videodev.h>
20 #include <media/video-buf.h>
21 #include <linux/delay.h>
22 #include <asm/mach-types.h>
24 #include "sensor_if.h"
26 #include "h3sensorpower.h"
27 #include "h4sensorpower.h"
32 struct ov9640_sensor {
34 struct i2c_client client;
35 int ver; /* OV9640 version */
38 static struct ov9640_sensor ov9640;
40 /* list of image formats supported by OV9640 sensor */
41 const static struct v4l2_fmtdesc ov9640_formats[] = {
43 /* Note: V4L2 defines RGB565 as:
46 * g2 g1 g0 r4 r3 r2 r1 r0 b4 b3 b2 b1 b0 g5 g4 g3
48 * We interpret RGB565 as:
51 * g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3
53 .description = "RGB565, le",
54 .pixelformat = V4L2_PIX_FMT_RGB565,
56 /* Note: V4L2 defines RGB565X as:
59 * b4 b3 b2 b1 b0 g5 g4 g3 g2 g1 g0 r4 r3 r2 r1 r0
61 * We interpret RGB565X as:
64 * r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
66 .description = "RGB565, be",
67 .pixelformat = V4L2_PIX_FMT_RGB565X,
70 .description = "YUYV (YUV 4:2:2), packed",
71 .pixelformat = V4L2_PIX_FMT_YUYV,
73 .description = "UYVY, packed",
74 .pixelformat = V4L2_PIX_FMT_UYVY,
77 /* Note: V4L2 defines RGB555 as:
80 * g2 g1 g0 r4 r3 r2 r1 r0 x b4 b3 b2 b1 b0 g4 g3
82 * We interpret RGB555 as:
85 * g2 g1 g0 b4 b3 b2 b1 b0 x r4 r3 r2 r1 r0 g4 g3
87 .description = "RGB555, le",
88 .pixelformat = V4L2_PIX_FMT_RGB555,
90 /* Note: V4L2 defines RGB555X as:
93 * x b4 b3 b2 b1 b0 g4 g3 g2 g1 g0 r4 r3 r2 r1 r0
95 * We interpret RGB555X as:
98 * x r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
100 .description = "RGB555, be",
101 .pixelformat = V4L2_PIX_FMT_RGB555X,
105 #define NUM_CAPTURE_FORMATS ARRAY_SIZE(ov9640_formats)
106 #ifdef CONFIG_ARCH_OMAP24XX
107 #define NUM_OVERLAY_FORMATS 4
109 #define NUM_OVERLAY_FORMATS 2
112 /* register initialization tables for OV9640 */
114 #define OV9640_REG_TERM 0xFF /* terminating list entry for reg */
115 #define OV9640_VAL_TERM 0xFF /* terminating list entry for val */
117 /* common OV9640 register initialization for all image sizes, pixel formats,
120 const static struct ov9640_reg ov9640_common[] = {
121 #ifdef CONFIG_ARCH_OMAP24XX
122 { 0x12, 0x80 }, { 0x11, 0x80 }, { 0x13, 0x8F }, /* COM7, CLKRC, COM8 */
123 { 0x01, 0x80 }, { 0x02, 0x80 }, { 0x04, 0x00 }, /* BLUE, RED, COM1 */
124 { 0x0E, 0x81 }, { 0x0F, 0x4F }, { 0x14, 0x4A }, /* COM5, COM6, COM9 */
126 { 0x12, 0x80 }, { 0x11, 0x80 }, { 0x13, 0x88 }, /* COM7, CLKRC, COM8 */
127 { 0x01, 0x58 }, { 0x02, 0x24 }, { 0x04, 0x00 }, /* BLUE, RED, COM1 */
128 { 0x0E, 0x81 }, { 0x0F, 0x4F }, { 0x14, 0xcA }, /* COM5, COM6, COM9 */
130 { 0x16, 0x02 }, { 0x1B, 0x01 }, { 0x24, 0x70 }, /* ?, PSHFT, AEW */
131 { 0x25, 0x68 }, { 0x26, 0xD3 }, { 0x27, 0x90 }, /* AEB, VPT, BBIAS */
132 { 0x2A, 0x00 }, { 0x2B, 0x00 }, { 0x32, 0x24 }, /* EXHCH, EXHCL, HREF */
133 { 0x33, 0x02 }, { 0x37, 0x02 }, { 0x38, 0x13 }, /* CHLF, ADC, ACOM */
134 { 0x39, 0xF0 }, { 0x3A, 0x00 }, { 0x3B, 0x01 }, /* OFON, TSLB, COM11 */
135 { 0x3D, 0x90 }, { 0x3E, 0x02 }, { 0x3F, 0xF2 }, /* COM13, COM14, EDGE */
136 { 0x41, 0x02 }, { 0x42, 0xC8 }, /* COM16, COM17 */
137 { 0x43, 0xF0 }, { 0x44, 0x10 }, { 0x45, 0x6C }, /* ?, ?, ? */
138 { 0x46, 0x6C }, { 0x47, 0x44 }, { 0x48, 0x44 }, /* ?, ?, ? */
139 { 0x49, 0x03 }, { 0x59, 0x49 }, { 0x5A, 0x94 }, /* ?, ?, ? */
140 { 0x5B, 0x46 }, { 0x5C, 0x84 }, { 0x5D, 0x5C }, /* ?, ?, ? */
141 { 0x5E, 0x08 }, { 0x5F, 0x00 }, { 0x60, 0x14 }, /* ?, ?, ? */
142 { 0x61, 0xCE }, /* ? */
143 { 0x62, 0x70 }, { 0x63, 0x00 }, { 0x64, 0x04 }, /* LCC1, LCC2, LCC3 */
144 { 0x65, 0x00 }, { 0x66, 0x00 }, /* LCC4, LCC5 */
145 { 0x69, 0x00 }, { 0x6A, 0x3E }, { 0x6B, 0x3F }, /* HV, MBD, DBLV */
146 { 0x6C, 0x40 }, { 0x6D, 0x30 }, { 0x6E, 0x4B }, /* GSP1, GSP2, GSP3 */
147 { 0x6F, 0x60 }, { 0x70, 0x70 }, { 0x71, 0x70 }, /* GSP4, GSP5, GSP6 */
148 { 0x72, 0x70 }, { 0x73, 0x70 }, { 0x74, 0x60 }, /* GSP7, GSP8, GSP9 */
149 { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 }, /* GSP10,GSP11,GSP12 */
150 { 0x78, 0x3A }, { 0x79, 0x2E }, { 0x7A, 0x28 }, /* GSP13,GSP14,GSP15 */
151 { 0x7B, 0x22 }, { 0x7C, 0x04 }, { 0x7D, 0x07 }, /* GSP16,GST1, GST2 */
152 { 0x7E, 0x10 }, { 0x7F, 0x28 }, { 0x80, 0x36 }, /* GST3, GST4, GST5 */
153 { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 }, /* GST6, GST7, GST8 */
154 { 0x84, 0x6C }, { 0x85, 0x78 }, { 0x86, 0x8C }, /* GST9, GST10,GST11 */
155 { 0x87, 0x9E }, { 0x88, 0xBB }, { 0x89, 0xD2 }, /* GST12,GST13,GST14 */
156 #ifdef CONFIG_ARCH_OMAP24XX
157 { 0x8A, 0xE6 }, { 0x13, 0x8F }, { 0x00, 0x7F }, /* GST15, COM8 */
159 { 0x8A, 0xE6 }, { 0x13, 0xaF }, { 0x15, 0x02 }, /* GST15, COM8 */
160 { 0x22, 0x8a }, /* GROS */
162 { OV9640_REG_TERM, OV9640_VAL_TERM }
165 /* OV9640 register configuration for all combinations of pixel format and
168 /* YUV (YCbCr) QQCIF */
169 const static struct ov9640_reg qqcif_yuv[] = {
170 { 0x12, 0x08 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
171 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
172 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
173 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
174 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
175 { 0x58, 0x0F }, /* MTXS */
176 { OV9640_REG_TERM, OV9640_VAL_TERM }
178 /* YUV (YCbCr) QQVGA */
179 const static struct ov9640_reg qqvga_yuv[] = {
180 { 0x12, 0x10 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
181 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
182 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
183 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
184 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
185 { 0x58, 0x0F }, /* MTXS */
186 { OV9640_REG_TERM, OV9640_VAL_TERM }
188 /* YUV (YCbCr) QCIF */
189 const static struct ov9640_reg qcif_yuv[] = {
190 { 0x12, 0x08 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
191 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
192 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
193 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
194 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
195 { 0x58, 0x0F }, /* MTXS */
196 { OV9640_REG_TERM, OV9640_VAL_TERM }
198 /* YUV (YCbCr) QVGA */
199 const static struct ov9640_reg qvga_yuv[] = {
200 { 0x12, 0x10 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
201 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
202 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
203 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
204 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
205 { 0x58, 0x0F }, /* MTXS */
206 { OV9640_REG_TERM, OV9640_VAL_TERM }
208 /* YUV (YCbCr) CIF */
209 const static struct ov9640_reg cif_yuv[] = {
210 { 0x12, 0x20 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
211 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
212 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
213 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
214 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
215 { 0x58, 0x0F }, /* MTXS */
216 { OV9640_REG_TERM, OV9640_VAL_TERM }
218 /* YUV (YCbCr) VGA */
219 const static struct ov9640_reg vga_yuv[] = {
220 { 0x12, 0x40 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
221 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
222 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
223 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
224 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
225 { 0x58, 0x0F }, /* MTXS */
226 { OV9640_REG_TERM, OV9640_VAL_TERM }
228 /* YUV (YCbCr) SXGA */
229 const static struct ov9640_reg sxga_yuv[] = {
230 { 0x12, 0x00 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
231 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
232 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
233 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
234 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
235 { 0x58, 0x0F }, /* MTXS */
236 { OV9640_REG_TERM, OV9640_VAL_TERM }
239 const static struct ov9640_reg qqcif_565[] = {
240 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
241 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
242 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
243 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
244 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
245 { 0x58, 0x65 }, /* MTXS */
246 { OV9640_REG_TERM, OV9640_VAL_TERM }
249 const static struct ov9640_reg qqvga_565[] = {
250 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
251 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
252 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
253 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
254 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
255 { 0x58, 0x65 }, /* MTXS */
256 { OV9640_REG_TERM, OV9640_VAL_TERM }
259 const static struct ov9640_reg qcif_565[] = {
260 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
261 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
262 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
263 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
264 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
265 { 0x58, 0x65 }, /* MTXS */
266 { OV9640_REG_TERM, OV9640_VAL_TERM }
269 const static struct ov9640_reg qvga_565[] = {
270 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
271 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
272 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
273 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
274 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
275 { 0x58, 0x65 }, /* MTXS */
276 { OV9640_REG_TERM, OV9640_VAL_TERM }
279 const static struct ov9640_reg cif_565[] = {
280 { 0x12, 0x24 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
281 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
282 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
283 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
284 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
285 { 0x58, 0x65 }, /* MTXS */
286 { OV9640_REG_TERM, OV9640_VAL_TERM }
289 const static struct ov9640_reg vga_565[] = {
290 { 0x12, 0x44 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
291 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
292 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
293 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
294 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
295 { 0x58, 0x65 }, /* MTXS */
296 { OV9640_REG_TERM, OV9640_VAL_TERM }
299 const static struct ov9640_reg sxga_565[] = {
300 { 0x12, 0x04 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
301 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
302 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
303 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
304 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
305 { 0x58, 0x65 }, /* MTXS */
306 { OV9640_REG_TERM, OV9640_VAL_TERM }
309 const static struct ov9640_reg qqcif_555[] = {
310 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
311 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
312 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
313 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
314 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
315 { 0x58, 0x65 }, /* MTXS */
316 { OV9640_REG_TERM, OV9640_VAL_TERM }
319 const static struct ov9640_reg qqvga_555[] = {
320 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
321 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
322 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
323 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
324 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
325 { 0x58, 0x65 }, /* MTXS */
326 { OV9640_REG_TERM, OV9640_VAL_TERM }
329 const static struct ov9640_reg qcif_555[] = {
330 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
331 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
332 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
333 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
334 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
335 { 0x58, 0x65 }, /* MTXS */
336 { OV9640_REG_TERM, OV9640_VAL_TERM }
339 const static struct ov9640_reg qvga_555[] = {
340 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
341 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
342 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
343 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
344 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
345 { 0x58, 0x65 }, /* MTXS */
346 { OV9640_REG_TERM, OV9640_VAL_TERM }
349 const static struct ov9640_reg cif_555[] = {
350 { 0x12, 0x24 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
351 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
352 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
353 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
354 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
355 { 0x58, 0x65 }, /* MTXS */
356 { OV9640_REG_TERM, OV9640_VAL_TERM }
359 const static struct ov9640_reg vga_555[] = {
360 { 0x12, 0x44 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
361 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
362 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
363 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
364 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
365 { 0x58, 0x65 }, /* MTXS */
366 { OV9640_REG_TERM, OV9640_VAL_TERM }
369 const static struct ov9640_reg sxga_555[] = {
370 { 0x12, 0x04 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
371 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
372 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
373 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
374 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
375 { 0x58, 0x65 }, /* MTXS */
376 { OV9640_REG_TERM, OV9640_VAL_TERM }
381 #define DEF_AUTOGAIN 1
382 #define DEF_EXPOSURE 154
384 #define DEF_FREEZE_AGCAEC 0
386 #define DEF_RED (255 - DEF_BLUE)
391 /* Our own specific controls */
392 #define V4L2_CID_FREEZE_AGCAEC V4L2_CID_PRIVATE_BASE+0
393 #define V4L2_CID_AUTOEXPOSURE V4L2_CID_PRIVATE_BASE+1
394 #define V4L2_CID_LAST_PRIV V4L2_CID_AUTOEXPOSURE
397 static struct vcontrol {
398 struct v4l2_queryctrl qc;
404 { { V4L2_CID_GAIN, V4L2_CTRL_TYPE_INTEGER, "Gain", 0, 63, 1,
406 0, OV9640_GAIN, 0x3f, 0 },
407 { { V4L2_CID_AUTOGAIN, V4L2_CTRL_TYPE_BOOLEAN, "Auto Gain", 0, 1, 0,
409 0, OV9640_COM8, 0x04, 2 },
410 { { V4L2_CID_EXPOSURE, V4L2_CTRL_TYPE_INTEGER, "Exposure", 0, 255, 1,
412 0, OV9640_AECH, 0xff, 0 },
413 { { V4L2_CID_AUTOEXPOSURE, V4L2_CTRL_TYPE_BOOLEAN, "Auto Exposure", 0, 1, 0,
415 0, OV9640_COM8, 0x01, 0 },
416 { { V4L2_CID_FREEZE_AGCAEC, V4L2_CTRL_TYPE_BOOLEAN, "Freeze AGC/AEC", 0,1,0,
418 0, OV9640_COM9, 0x01, 0 },
419 { { V4L2_CID_RED_BALANCE, V4L2_CTRL_TYPE_INTEGER, "Red Balance", 0, 255, 1,
421 0, OV9640_RED, 0xff, 0 },
422 { { V4L2_CID_BLUE_BALANCE, V4L2_CTRL_TYPE_INTEGER, "Blue Balance", 0, 255, 1,
424 0, OV9640_BLUE, 0xff, 0 },
425 { { V4L2_CID_AUTO_WHITE_BALANCE, V4L2_CTRL_TYPE_BOOLEAN, "Auto White Balance", 0,1,0,
427 0, OV9640_COM8, 0x02, 1 },
428 { { V4L2_CID_HFLIP, V4L2_CTRL_TYPE_BOOLEAN, "Mirror Image", 0, 1, 0,
430 0, OV9640_MVFP, 0x20, 5 },
431 { { V4L2_CID_VFLIP, V4L2_CTRL_TYPE_BOOLEAN, "Vertical Flip", 0, 1, 0,
433 0, OV9640_MVFP, 0x10, 4 },
436 #define NUM_CONTROLS ARRAY_SIZE(control)
438 const static struct ov9640_reg *
439 ov9640_reg_init[NUM_PIXEL_FORMATS][NUM_IMAGE_SIZES] =
441 { qqcif_yuv, qqvga_yuv, qcif_yuv, qvga_yuv, cif_yuv, vga_yuv, sxga_yuv },
442 { qqcif_565, qqvga_565, qcif_565, qvga_565, cif_565, vga_565, sxga_565 },
443 { qqcif_555, qqvga_555, qcif_555, qvga_555, cif_555, vga_555, sxga_555 },
448 * Read a value from a register in an OV9640 sensor device. The value is
450 * Returns zero if successful, or non-zero otherwise.
453 ov9640_read_reg(struct i2c_client *client, u8 reg, u8 *val)
456 struct i2c_msg msg[1];
457 unsigned char data[1];
459 if (!client->adapter)
462 msg->addr = client->addr;
467 err = i2c_transfer(client->adapter, msg, 1);
469 msg->flags = I2C_M_RD;
470 err = i2c_transfer(client->adapter, msg, 1);
479 /* Write a value to a register in an OV9640 sensor device.
480 * Returns zero if successful, or non-zero otherwise.
483 ov9640_write_reg(struct i2c_client *client, u8 reg, u8 val)
486 struct i2c_msg msg[1];
487 unsigned char data[2];
489 if (!client->adapter)
492 msg->addr = client->addr;
498 err = i2c_transfer(client->adapter, msg, 1);
505 ov9640_write_reg_mask(struct i2c_client *client, u8 reg, u8 *val, u8 mask)
513 /* need to do read - modify - write */
514 if ((rc = ov9640_read_reg(client, reg, &oldval)))
516 oldval &= (~mask); /* Clear the masked bits */
517 *val &= mask; /* Enforce mask on value */
518 newval = oldval | *val; /* Set the desired bits */
521 /* write the new value to the register */
522 if ((rc = ov9640_write_reg(client, reg, newval)))
525 if ((rc = ov9640_read_reg(client, reg, &newval)))
528 *val = newval & mask;
533 ov9640_read_reg_mask(struct i2c_client *client, u8 reg, u8 *val, u8 mask)
537 if ((rc = ov9640_read_reg(client, reg, val)))
544 /* Initialize a list of OV9640 registers.
545 * The list of registers is terminated by the pair of values
546 * { OV9640_REG_TERM, OV9640_VAL_TERM }.
547 * Returns zero if successful, or non-zero otherwise.
550 ov9640_write_regs(struct i2c_client *client, const struct ov9640_reg reglist[])
553 const struct ov9640_reg *next = reglist;
555 while (!((next->reg == OV9640_REG_TERM)
556 && (next->val == OV9640_VAL_TERM)))
558 err = ov9640_write_reg(client, next->reg, next->val);
567 /* Returns the index of the requested ID from the control structure array */
573 if (id < V4L2_CID_BASE)
576 for (i = NUM_CONTROLS - 1; i >= 0; i--)
577 if (control[i].qc.id == id)
584 /* Calculate the internal clock divisor (value of the CLKRC register) of the
585 * OV9640 given the image size, the frequency (in Hz) of its XCLK input and a
586 * desired frame period (in seconds). The frame period 'fper' is expressed as
587 * a fraction. The frame period is an input/output parameter.
588 * Returns the value of the OV9640 CLKRC register that will yield the frame
589 * period returned in 'fper' at the specified xclk frequency. The
590 * returned period will be as close to the requested period as possible.
593 ov9640_clkrc(enum image_size isize, unsigned long xclk, struct v4l2_fract *fper)
595 unsigned long fpm, fpm_max; /* frames per minute */
596 unsigned long divisor;
597 const unsigned long divisor_max = 64;
598 #ifdef CONFIG_ARCH_OMAP24XX
599 const static unsigned long clks_per_frame[] =
600 { 200000, 400000, 200000, 400000, 400000, 800000, 3200000 };
601 /* QQCIF QQVGA QCIF QVGA CIF VGA SXGA
602 * 199680,400000, 199680, 400000, 399360, 800000, 3200000
605 const static unsigned long clks_per_frame[] =
606 { 200000, 200000, 200000, 200000, 400000, 800000, 3200000 };
609 if (fper->numerator > 0)
610 fpm = (fper->denominator*60)/fper->numerator;
613 fpm_max = (xclk*60)/clks_per_frame[isize];
620 divisor = fpm_max/fpm;
621 if (divisor > divisor_max)
622 divisor = divisor_max;
623 fper->numerator = divisor*60;
624 fper->denominator = fpm_max;
626 /* try to reduce the fraction */
627 while (!(fper->denominator % 5) && !(fper->numerator % 5)) {
628 fper->numerator /= 5;
629 fper->denominator /= 5;
631 while (!(fper->denominator % 3) && !(fper->numerator % 3)) {
632 fper->numerator /= 3;
633 fper->denominator /= 3;
635 while (!(fper->denominator % 2) && !(fper->numerator % 2)) {
636 fper->numerator /= 2;
637 fper->denominator /= 2;
639 if (fper->numerator < fper->denominator) {
640 if (!(fper->denominator % fper->numerator)) {
641 fper->denominator /= fper->numerator;
646 if (!(fper->numerator % fper->denominator)) {
647 fper->numerator /= fper->denominator;
648 fper->denominator = 1;
652 /* we set bit 7 in CLKRC to enable the digital PLL */
653 return (0x80 | (divisor - 1));
656 /* Configure the OV9640 for a specified image size, pixel format, and frame
657 * period. xclk is the frequency (in Hz) of the xclk input to the OV9640.
658 * fper is the frame period (in seconds) expressed as a fraction.
659 * Returns zero if successful, or non-zero otherwise.
660 * The actual frame period is returned in fper.
663 ov9640_configure(struct i2c_client *client,
664 enum image_size isize,
665 enum pixel_format pfmt,
667 struct v4l2_fract *fper)
672 /* common register initialization */
673 err = ov9640_write_regs(client, ov9640_common);
677 /* configure image size and pixel format */
678 err = ov9640_write_regs(client, ov9640_reg_init[pfmt][isize]);
682 /* configure frame rate */
683 clkrc = ov9640_clkrc(isize, xclk, fper);
684 err = ov9640_write_reg(client, OV9640_CLKRC, clkrc);
696 if (machine_is_omap_h2())
699 if (machine_is_omap_h3()) {
700 err = h3_sensor_powerup();
705 if (machine_is_omap_h4()) {
706 err = h4_sensor_powerup();
714 ov9640_powerdown(void)
718 if (machine_is_omap_h2())
721 if (machine_is_omap_h3()) {
722 err = h3_sensor_powerdown();
727 if (machine_is_omap_h4()) {
728 err = h4_sensor_powerdown();
737 ov9640sensor_power_on(void *priv)
739 return ov9640_powerup();
743 ov9640sensor_power_off(void *priv)
745 return ov9640_powerdown();
748 /* Detect if an OV9640 is present, and if so which revision.
749 * A device is considered to be detected if the manufacturer ID (MIDH and MIDL)
750 * and the product ID (PID) registers match the expected values.
751 * Any value of the version ID (VER) register is accepted.
752 * Here are the version numbers we know about:
753 * 0x48 --> OV9640 Revision 1 or OV9640 Revision 2
754 * 0x49 --> OV9640 Revision 3
755 * Returns a negative error number if no device is detected, or the
756 * non-negative value of the version ID register if a device is detected.
759 ov9640_detect(struct i2c_client *client)
761 u8 midh, midl, pid, ver;
766 if (ov9640_read_reg(client, OV9640_MIDH, &midh))
768 if (ov9640_read_reg(client, OV9640_MIDL, &midl))
770 if (ov9640_read_reg(client, OV9640_PID, &pid))
772 if (ov9640_read_reg(client, OV9640_VER, &ver))
775 if ((midh != OV9640_MIDH_MAGIC)
776 || (midl != OV9640_MIDL_MAGIC)
777 || (pid != OV9640_PID_MAGIC))
779 /* We didn't read the values we expected, so
780 * this must not be an OV9640.
787 static struct i2c_driver ov9640sensor_i2c_driver;
789 /* This function registers an I2C client via i2c_attach_client() for an OV9640
790 * sensor device. If 'probe' is non-zero, then the I2C client is only
791 * registered if the device can be detected. If 'probe' is zero, then no
792 * device detection is attempted and the I2C client is always registered.
793 * Returns zero if an I2C client is successfully registered, or non-zero
797 ov9640_i2c_attach_client(struct i2c_adapter *adap, int addr, int probe)
799 struct ov9640_sensor *sensor = &ov9640;
800 struct i2c_client *client = &sensor->client;
804 return -EBUSY; /* our client is already attached */
807 client->driver = &ov9640sensor_i2c_driver;
808 client->adapter = adap;
810 err = i2c_attach_client(client);
812 client->adapter = NULL;
817 err = ov9640_detect(client);
819 i2c_detach_client(client);
820 client->adapter = NULL;
828 /* This function is called by i2c_del_adapter() and i2c_del_driver()
829 * if the adapter or driver with which this I2C client is associated is
830 * removed. This function unregisters the client via i2c_detach_client().
831 * Returns zero if the client is successfully detached, or non-zero
835 ov9640_i2c_detach_client(struct i2c_client *client)
839 if (!client->adapter)
840 return -ENODEV; /* our client isn't attached */
842 err = i2c_detach_client(client);
843 client->adapter = NULL;
848 /* This function will be called for each registered I2C bus adapter when our
849 * I2C driver is registered via i2c_add_driver(). It will also be called
850 * whenever a new I2C adapter is registered after our I2C driver is registered.
851 * This function probes the specified I2C bus adapter to determine if an
852 * OV9640 sensor device is present. If a device is detected, an I2C client
853 * is registered for it via ov9640_i2c_attach_client(). Note that we can't use
854 * the standard i2c_probe() function to look for the sensor because the OMAP
855 * I2C controller doesn't support probing.
856 * Returns zero if an OV9640 device is detected and an I2C client successfully
857 * registered for it, or non-zero otherwise.
860 ov9640_i2c_probe_adapter(struct i2c_adapter *adap)
862 return ov9640_i2c_attach_client(adap, OV9640_I2C_ADDR, 1);
865 /* Find the best match for a requested image capture size. The best match
866 * is chosen as the nearest match that has the same number or fewer pixels
867 * as the requested size, or the smallest image size if the requested size
868 * has fewer pixels than the smallest image.
870 static enum image_size
871 ov9640_find_size(unsigned int width, unsigned int height)
873 enum image_size isize;
874 unsigned long pixels = width*height;
876 for (isize = QQCIF; isize < SXGA; isize++) {
877 if (ov9640_sizes[isize + 1].height*
878 ov9640_sizes[isize + 1].width > pixels)
886 /* following are sensor interface functions implemented by
887 * OV9640 sensor driver.
890 ov9640sensor_query_control(struct v4l2_queryctrl *qc, void *priv)
894 i = find_vctrl (qc->id);
896 qc->flags = V4L2_CTRL_FLAG_DISABLED;
907 ov9640sensor_get_control(struct v4l2_control *vc, void *priv)
909 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
910 struct i2c_client *client = &sensor->client;
912 struct vcontrol * lvc;
914 i = find_vctrl(vc->id);
919 if (ov9640_read_reg_mask(client, lvc->reg, (u8 *)&val, lvc->mask))
922 val = val >> lvc->start_bit;
924 vc->value = lvc->current_value = val;
931 ov9640sensor_set_control(struct v4l2_control *vc, void *priv)
933 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
934 struct i2c_client *client = &sensor->client;
935 struct vcontrol *lvc;
939 i = find_vctrl(vc->id);
944 val = val << lvc->start_bit;
945 if (ov9640_write_reg_mask(client, lvc->reg, (u8 *)&val, (u8)lvc->mask))
948 val = val>> lvc->start_bit;
950 lvc->current_value = val;
956 /* Implement the VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
959 ov9640sensor_enum_pixformat(struct v4l2_fmtdesc *fmt, void *priv)
961 int index = fmt->index;
962 enum v4l2_buf_type type = fmt->type;
964 memset(fmt, 0, sizeof(*fmt));
969 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
970 if (index >= NUM_CAPTURE_FORMATS)
974 case V4L2_BUF_TYPE_VIDEO_OVERLAY:
975 if (index >= NUM_OVERLAY_FORMATS)
983 fmt->flags = ov9640_formats[index].flags;
984 strlcpy(fmt->description, ov9640_formats[index].description, sizeof(fmt->description));
985 fmt->pixelformat = ov9640_formats[index].pixelformat;
990 /* Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This
991 * ioctl is used to negotiate the image capture size and pixel format
992 * without actually making it take effect.
995 ov9640sensor_try_format(struct v4l2_pix_format *pix, void *priv)
997 enum image_size isize;
1000 isize = ov9640_find_size(pix->width, pix->height);
1001 pix->width = ov9640_sizes[isize].width;
1002 pix->height = ov9640_sizes[isize].height;
1003 for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) {
1004 if (pix->pixelformat == ov9640_formats[ifmt].pixelformat)
1007 if (ifmt == NUM_CAPTURE_FORMATS)
1009 pix->pixelformat = ov9640_formats[ifmt].pixelformat;
1010 pix->field = V4L2_FIELD_NONE;
1011 pix->bytesperline = pix->width*2;
1012 pix->sizeimage = pix->bytesperline*pix->height;
1014 switch (pix->pixelformat) {
1015 case V4L2_PIX_FMT_YUYV:
1016 case V4L2_PIX_FMT_UYVY:
1018 pix->colorspace = V4L2_COLORSPACE_JPEG;
1020 case V4L2_PIX_FMT_RGB565:
1021 case V4L2_PIX_FMT_RGB565X:
1022 case V4L2_PIX_FMT_RGB555:
1023 case V4L2_PIX_FMT_RGB555X:
1024 pix->colorspace = V4L2_COLORSPACE_SRGB;
1030 /* Given the image capture format in pix, the nominal frame period in
1031 * timeperframe, calculate the required xclk frequency
1032 * The nominal xclk input frequency of the OV9640 is 24MHz, maximum
1033 * frequency is 48MHz, and minimum frequency is 10MHz.
1035 static unsigned long
1036 ov9640sensor_calc_xclk(struct v4l2_pix_format *pix,
1037 struct v4l2_fract *timeperframe, void *priv)
1039 unsigned long tgt_xclk; /* target xclk */
1040 unsigned long tgt_fpm; /* target frames per minute */
1041 enum image_size isize;
1043 /* We use arbitrary rules to select the xclk frequency. If the
1044 * capture size is VGA and the frame rate is greater than 900
1045 * frames per minute, or if the capture size is SXGA and the
1046 * frame rate is greater than 450 frames per minutes, then the
1047 * xclk frequency will be set to 48MHz. Otherwise, the xclk
1048 * frequency will be set to 24MHz. If the mclk frequency is such that
1049 * the target xclk frequency is not achievable, then xclk will be set
1050 * as close as to the target as possible.
1052 if ((timeperframe->numerator == 0)
1053 || (timeperframe->denominator == 0))
1055 /* supply a default nominal_timeperframe of 15 fps */
1056 timeperframe->numerator = 1;
1057 timeperframe->denominator = 15;
1059 tgt_fpm = (timeperframe->denominator*60)
1060 / timeperframe->numerator;
1061 tgt_xclk = 24000000;
1062 isize = ov9640_find_size(pix->width, pix->height);
1066 tgt_xclk = 48000000;
1070 tgt_xclk = 48000000;
1078 /* Given a capture format in pix, the frame period in timeperframe, and
1079 * the xclk frequency, set the capture format of the OV9640 sensor.
1080 * The actual frame period will be returned in timeperframe.
1083 ov9640sensor_configure(struct v4l2_pix_format *pix, unsigned long xclk,
1084 struct v4l2_fract *timeperframe, void *priv)
1086 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
1087 enum pixel_format pfmt = YUV;
1089 switch (pix->pixelformat) {
1090 case V4L2_PIX_FMT_RGB565:
1091 case V4L2_PIX_FMT_RGB565X:
1094 case V4L2_PIX_FMT_RGB555:
1095 case V4L2_PIX_FMT_RGB555X:
1098 case V4L2_PIX_FMT_YUYV:
1099 case V4L2_PIX_FMT_UYVY:
1104 return ov9640_configure(&sensor->client,
1105 ov9640_find_size(pix->width, pix->height),
1106 pfmt, xclk, timeperframe);
1109 /* Prepare for the driver to exit.
1110 * Balances ov9640sensor_init().
1111 * This function must de-initialize the sensor and its associated data
1115 ov9640sensor_cleanup(void *priv)
1117 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
1120 i2c_del_driver(&ov9640sensor_i2c_driver);
1127 static struct i2c_driver ov9640sensor_i2c_driver = {
1131 .id = I2C_DRIVERID_MISC, /*FIXME:accroding to i2c-ids.h */
1132 .attach_adapter = ov9640_i2c_probe_adapter,
1133 .detach_client = ov9640_i2c_detach_client,
1137 /* Initialize the OV9640 sensor.
1138 * This routine allocates and initializes the data structure for the sensor,
1139 * powers up the sensor, registers the I2C driver, and sets a default image
1140 * capture format in pix. The capture format is not actually programmed
1141 * into the OV9640 sensor by this routine.
1142 * This function must return a non-NULL value to indicate that
1143 * initialization is successful.
1146 ov9640sensor_init(struct v4l2_pix_format *pix, struct v4l2_pix_format *pix2)
1148 struct ov9640_sensor *sensor = &ov9640;
1151 memset(sensor, 0, sizeof(*sensor));
1153 /* power-up the sensor */
1154 if (ov9640_powerup())
1157 err = i2c_add_driver(&ov9640sensor_i2c_driver);
1159 printk(KERN_ERR "Failed to register OV9640 I2C client.\n");
1162 if (!sensor->client.adapter) {
1164 "Failed to detect OV9640 sensor chip.\n");
1169 "OV9640 sensor chip version 0x%02x detected\n", sensor->ver);
1171 /* Make the default capture format QCIF RGB565 */
1172 pix->width = ov9640_sizes[QCIF].width;
1173 pix->height = ov9640_sizes[QCIF].height;
1174 pix->pixelformat = V4L2_PIX_FMT_RGB565;
1175 ov9640sensor_try_format(pix, NULL);
1177 return (void *)sensor;
1180 struct camera_sensor camera_sensor_if = {
1183 .parallel_mode = PAR_MODE_NOBT8,
1184 .hs_polarity = SYNC_ACTIVE_HIGH,
1185 .vs_polarity = SYNC_ACTIVE_LOW,
1187 .init = ov9640sensor_init,
1188 .cleanup = ov9640sensor_cleanup,
1189 .enum_pixformat = ov9640sensor_enum_pixformat,
1190 .try_format = ov9640sensor_try_format,
1191 .calc_xclk = ov9640sensor_calc_xclk,
1192 .configure = ov9640sensor_configure,
1193 .query_control = ov9640sensor_query_control,
1194 .get_control = ov9640sensor_get_control,
1195 .set_control = ov9640sensor_set_control,
1196 .power_on = ov9640sensor_power_on,
1197 .power_off = ov9640sensor_power_off,
1200 void print_ov9640_regs(void *priv)
1202 struct ov9640_sensor *sensor = (struct ov9640_sensor *) priv;
1204 for (reg=0x00; reg <=0x8A; reg++)
1205 if (ov9640_read_reg(&sensor->client,reg,&val))
1206 printk("error reading %x\n", reg);
1208 printk("reg %x = %x\n", reg, val);
1211 #endif /* ifdef CAMERA_OV9640 */