drivers/media/video/cx231xx/cx231xx-reg.h

   1 /*
   2    cx231xx-reg.h - driver for Conexant Cx23100/101/102 USB video capture devices
   3
   4    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef _CX231XX_REG_H
  22 #define _CX231XX_REG_H
  23
  24 /*****************************************************************************
  25                     * VBI codes *
  26 *****************************************************************************/
  27
  28 #define SAV_ACTIVE_VIDEO_FIELD1       0x80
  29 #define EAV_ACTIVE_VIDEO_FIELD1           0x90
  30
  31 #define SAV_ACTIVE_VIDEO_FIELD2           0xC0
  32 #define EAV_ACTIVE_VIDEO_FIELD2           0xD0
  33
  34 #define SAV_VBLANK_FIELD1                     0xA0
  35 #define EAV_VBLANK_FIELD1                     0xB0
  36
  37 #define SAV_VBLANK_FIELD2                     0xE0
  38 #define EAV_VBLANK_FIELD2                     0xF0
  39
  40 #define SAV_VBI_FIELD1                0x20
  41 #define EAV_VBI_FIELD1                0x30
  42
  43 #define SAV_VBI_FIELD2                0x60
  44 #define EAV_VBI_FIELD2                0x70
  45
  46 /*****************************************************************************/
  47 /* Audio ADC Registers */
  48 #define CH_PWR_CTRL1                  0x0000000E
  49 #define CH_PWR_CTRL2                  0x0000000F
  50 /*****************************************************************************/
  51
  52 #define      HOST_REG1                0x000
  53 #define      FLD_FORCE_CHIP_SEL       0x80
  54 #define      FLD_AUTO_INC_DIS         0x20
  55 #define      FLD_PREFETCH_EN          0x10
  56 /* Reserved [2:3] */
  57 #define      FLD_DIGITAL_PWR_DN       0x02
  58 #define      FLD_SLEEP                0x01
  59
  60 /*****************************************************************************/
  61 #define      HOST_REG2                0x001
  62
  63
  64 /*****************************************************************************/
  65 #define      HOST_REG3                0x002
  66
  67 /*****************************************************************************/
  68 /* added for polaris */
  69 #define      GPIO_PIN_CTL0            0x3
  70 #define      GPIO_PIN_CTL1            0x4
  71 #define      GPIO_PIN_CTL2            0x5
  72 #define      GPIO_PIN_CTL3            0x6
  73 #define      TS1_PIN_CTL0             0x7
  74 #define      TS1_PIN_CTL1             0x8
  75 /*****************************************************************************/
  76
  77 #define      FLD_CLK_IN_EN           0x80
  78 #define      FLD_XTAL_CTRL           0x70
  79 #define      FLD_BB_CLK_MODE         0x0C
  80 #define      FLD_REF_DIV_PLL         0x02
  81 #define      FLD_REF_SEL_PLL1        0x01
  82
  83 /*****************************************************************************/
  84 #define      CHIP_CTRL                0x100
  85 /* Reserved [27] */
  86 /* Reserved [31:21] */
  87 #define      FLD_CHIP_ACFG_DIS        0x00100000
  88 /* Reserved [19] */
  89 #define      FLD_DUAL_MODE_ADC2       0x00040000
  90 #define      FLD_SIF_EN               0x00020000
  91 #define      FLD_SOFT_RST             0x00010000
  92 #define      FLD_DEVICE_ID            0x0000FFFF
  93
  94 /*****************************************************************************/
  95 #define      AFE_CTRL                 0x104
  96 #define      AFE_CTRL_C2HH_SRC_CTRL   0x104
  97 #define      FLD_DIF_OUT_SEL          0xC0000000
  98 #define      FLD_AUX_PLL_CLK_ALT_SEL  0x3C000000
  99 #define      FLD_UV_ORDER_MODE        0x02000000
 100 #define      FLD_FUNC_MODE            0x01800000
 101 #define      FLD_ROT1_PHASE_CTL       0x007F8000
 102 #define      FLD_AUD_IN_SEL           0x00004000
 103 #define      FLD_LUMA_IN_SEL          0x00002000
 104 #define      FLD_CHROMA_IN_SEL        0x00001000
 105 /* reserve [11:10] */
 106 #define      FLD_INV_SPEC_DIS         0x00000200
 107 #define      FLD_VGA_SEL_CH3          0x00000100
 108 #define      FLD_VGA_SEL_CH2          0x00000080
 109 #define      FLD_VGA_SEL_CH1          0x00000040
 110 #define      FLD_DCR_BYP_CH1          0x00000020
 111 #define      FLD_DCR_BYP_CH2          0x00000010
 112 #define      FLD_DCR_BYP_CH3          0x00000008
 113 #define      FLD_EN_12DB_CH3          0x00000004
 114 #define      FLD_EN_12DB_CH2          0x00000002
 115 #define      FLD_EN_12DB_CH1          0x00000001
 116
 117 /* redefine in Cx231xx */
 118 /*****************************************************************************/
 119 #define      DC_CTRL1                 0x108
 120 /* reserve [31:30] */
 121 #define      FLD_CLAMP_LVL_CH1        0x3FFF8000
 122 #define      FLD_CLAMP_LVL_CH2        0x00007FFF
 123 /*****************************************************************************/
 124
 125 /*****************************************************************************/
 126 #define      DC_CTRL2                 0x10c
 127 /* reserve [31:28] */
 128 #define      FLD_CLAMP_LVL_CH3        0x00FFFE00
 129 #define      FLD_CLAMP_WIND_LENTH     0x000001E0
 130 #define      FLD_C2HH_SAT_MIN         0x0000001E
 131 #define      FLD_FLT_BYP_SEL          0x00000001
 132 /*****************************************************************************/
 133
 134 /*****************************************************************************/
 135 #define      DC_CTRL3                 0x110
 136 /* reserve [31:16] */
 137 #define      FLD_ERR_GAIN_CTL         0x00070000
 138 #define      FLD_LPF_MIN              0x0000FFFF
 139 /*****************************************************************************/
 140
 141 /*****************************************************************************/
 142 #define      DC_CTRL4                 0x114
 143 /* reserve [31:31] */
 144 #define      FLD_INTG_CH1             0x7FFFFFFF
 145 /*****************************************************************************/
 146
 147 /*****************************************************************************/
 148 #define      DC_CTRL5                 0x118
 149 /* reserve [31:31] */
 150 #define      FLD_INTG_CH2             0x7FFFFFFF
 151 /*****************************************************************************/
 152
 153 /*****************************************************************************/
 154 #define      DC_CTRL6                 0x11c
 155 /* reserve [31:31] */
 156 #define      FLD_INTG_CH3             0x7FFFFFFF
 157 /*****************************************************************************/
 158
 159 /*****************************************************************************/
 160 #define      PIN_CTRL                 0x120
 161 #define      FLD_OEF_AGC_RF           0x00000001
 162 #define      FLD_OEF_AGC_IFVGA        0x00000002
 163 #define      FLD_OEF_AGC_IF           0x00000004
 164 #define      FLD_REG_BO_PUD           0x80000000
 165 #define      FLD_IR_IRQ_STAT          0x40000000
 166 #define      FLD_AUD_IRQ_STAT         0x20000000
 167 #define      FLD_VID_IRQ_STAT         0x10000000
 168 /* Reserved [27:26] */
 169 #define      FLD_IRQ_N_OUT_EN         0x02000000
 170 #define      FLD_IRQ_N_POLAR          0x01000000
 171 /* Reserved [23:6] */
 172 #define      FLD_OE_AUX_PLL_CLK       0x00000020
 173 #define      FLD_OE_I2S_BCLK          0x00000010
 174 #define      FLD_OE_I2S_WCLK          0x00000008
 175 #define      FLD_OE_AGC_IF            0x00000004
 176 #define      FLD_OE_AGC_IFVGA         0x00000002
 177 #define      FLD_OE_AGC_RF            0x00000001
 178
 179 /*****************************************************************************/
 180 #define      AUD_IO_CTRL              0x124
 181 /* Reserved [31:8] */
 182 #define      FLD_I2S_PORT_DIR         0x00000080
 183 #define      FLD_I2S_OUT_SRC          0x00000040
 184 #define      FLD_AUD_CHAN3_SRC        0x00000030
 185 #define      FLD_AUD_CHAN2_SRC        0x0000000C
 186 #define      FLD_AUD_CHAN1_SRC        0x00000003
 187
 188 /*****************************************************************************/
 189 #define      AUD_LOCK1                0x128
 190 #define      FLD_AUD_LOCK_KI_SHIFT    0xC0000000
 191 #define      FLD_AUD_LOCK_KD_SHIFT    0x30000000
 192 /* Reserved [27:25] */
 193 #define      FLD_EN_AV_LOCK           0x01000000
 194 #define      FLD_VID_COUNT            0x00FFFFFF
 195
 196 /*****************************************************************************/
 197 #define      AUD_LOCK2                0x12C
 198 #define      FLD_AUD_LOCK_KI_MULT     0xF0000000
 199 #define      FLD_AUD_LOCK_KD_MULT     0x0F000000
 200 /* Reserved [23:22] */
 201 #define      FLD_AUD_LOCK_FREQ_SHIFT  0x00300000
 202 #define      FLD_AUD_COUNT            0x000FFFFF
 203
 204 /*****************************************************************************/
 205 #define      AFE_DIAG_CTRL1           0x134
 206 /* Reserved [31:16] */
 207 #define      FLD_CUV_DLY_LENGTH       0x0000FF00
 208 #define      FLD_YC_DLY_LENGTH        0x000000FF
 209
 210 /*****************************************************************************/
 211 /* Poalris redefine */
 212 #define      AFE_DIAG_CTRL3           0x138
 213 /* Reserved [31:26] */
 214 #define      FLD_AUD_DUAL_FLAG_POL    0x02000000
 215 #define      FLD_VID_DUAL_FLAG_POL    0x01000000
 216 /* Reserved [23:23] */
 217 #define      FLD_COL_CLAMP_DIS_CH1    0x00400000
 218 #define      FLD_COL_CLAMP_DIS_CH2    0x00200000
 219 #define      FLD_COL_CLAMP_DIS_CH3    0x00100000
 220
 221 #define      TEST_CTRL1                 0x144
 222 /* Reserved [31:29] */
 223 #define      FLD_LBIST_EN               0x10000000
 224 /* Reserved [27:10] */
 225 #define      FLD_FI_BIST_INTR_R         0x0000200
 226 #define      FLD_FI_BIST_INTR_L         0x0000100
 227 #define      FLD_BIST_FAIL_AUD_PLL      0x0000080
 228 #define      FLD_BIST_INTR_AUD_PLL      0x0000040
 229 #define      FLD_BIST_FAIL_VID_PLL      0x0000020
 230 #define      FLD_BIST_INTR_VID_PLL      0x0000010
 231 /* Reserved [3:1] */
 232 #define      FLD_CIR_TEST_DIS           0x00000001
 233
 234
 235 /*****************************************************************************/
 236 #define      TEST_CTRL2               0x148
 237 #define      FLD_TSXCLK_POL_CTL       0x80000000
 238 #define      FLD_ISO_CTL_SEL          0x40000000
 239 #define      FLD_ISO_CTL_EN           0x20000000
 240 #define      FLD_BIST_DEBUGZ          0x10000000
 241 #define      FLD_AUD_BIST_TEST_H      0x0F000000
 242 /* Reserved [23:22] */
 243 #define      FLD_FLTRN_BIST_TEST_H    0x00020000
 244 #define      FLD_VID_BIST_TEST_H      0x00010000
 245 /* Reserved [19:17] */
 246 #define      FLD_BIST_TEST_H          0x00010000
 247 /* Reserved [15:13] */
 248 #define      FLD_TAB_EN               0x00001000
 249 /* Reserved [11:0] */
 250
 251 /*****************************************************************************/
 252 #define      BIST_STAT                0x14C
 253 #define      FLD_AUD_BIST_FAIL_H      0xFFF00000
 254 #define      FLD_FLTRN_BIST_FAIL_H    0x00180000
 255 #define      FLD_VID_BIST_FAIL_H      0x00070000
 256 #define      FLD_AUD_BIST_TST_DONE    0x0000FFF0
 257 #define      FLD_FLTRN_BIST_TST_DONE  0x00000008
 258 #define      FLD_VID_BIST_TST_DONE    0x00000007
 259
 260
 261 /*****************************************************************************/
 262 /* DirectIF registers definition have been moved to DIF_reg.h                */
 263 /*****************************************************************************/
 264 #define      MODE_CTRL                0x400
 265 #define      FLD_AFD_PAL60_DIS        0x20000000
 266 #define      FLD_AFD_FORCE_SECAM      0x10000000
 267 #define      FLD_AFD_FORCE_PALNC      0x08000000
 268 #define      FLD_AFD_FORCE_PAL        0x04000000
 269 #define      FLD_AFD_PALM_SEL         0x03000000
 270 #define      FLD_CKILL_MODE           0x00300000
 271 #define      FLD_COMB_NOTCH_MODE      0x00c00000       /* bit[19:18] */
 272 #define      FLD_CLR_LOCK_STAT        0x00020000
 273 #define      FLD_FAST_LOCK_MD         0x00010000
 274 #define      FLD_WCEN                 0x00008000
 275 #define      FLD_CAGCEN               0x00004000
 276 #define      FLD_CKILLEN              0x00002000
 277 #define      FLD_AUTO_SC_LOCK         0x00001000
 278 #define      FLD_MAN_SC_FAST_LOCK     0x00000800
 279 #define      FLD_INPUT_MODE           0x00000600
 280 #define      FLD_AFD_ACQUIRE          0x00000100
 281 #define      FLD_AFD_NTSC_SEL         0x00000080
 282 #define      FLD_AFD_PAL_SEL          0x00000040
 283 #define      FLD_ACFG_DIS             0x00000020
 284 #define      FLD_SQ_PIXEL             0x00000010
 285 #define      FLD_VID_FMT_SEL          0x0000000F
 286
 287 /*****************************************************************************/
 288 #define      OUT_CTRL1                0x404
 289 #define      FLD_POLAR                0x7F000000
 290 /* Reserved [23] */
 291 #define      FLD_RND_MODE             0x00600000
 292 #define      FLD_VIPCLAMP_EN          0x00100000
 293 #define      FLD_VIPBLANK_EN          0x00080000
 294 #define      FLD_VIP_OPT_AL           0x00040000
 295 #define      FLD_IDID0_SOURCE         0x00020000
 296 #define      FLD_DCMODE               0x00010000
 297 #define      FLD_CLK_GATING           0x0000C000
 298 #define      FLD_CLK_INVERT           0x00002000
 299 #define      FLD_HSFMT                0x00001000
 300 #define      FLD_VALIDFMT             0x00000800
 301 #define      FLD_ACTFMT               0x00000400
 302 #define      FLD_SWAPRAW              0x00000200
 303 #define      FLD_CLAMPRAW_EN          0x00000100
 304 #define      FLD_BLUE_FIELD_EN        0x00000080
 305 #define      FLD_BLUE_FIELD_ACT       0x00000040
 306 #define      FLD_TASKBIT_VAL          0x00000020
 307 #define      FLD_ANC_DATA_EN          0x00000010
 308 #define      FLD_VBIHACTRAW_EN        0x00000008
 309 #define      FLD_MODE10B              0x00000004
 310 #define      FLD_OUT_MODE             0x00000003
 311
 312 /*****************************************************************************/
 313 #define      OUT_CTRL2                0x408
 314 #define      FLD_AUD_GRP              0xC0000000
 315 #define      FLD_SAMPLE_RATE          0x30000000
 316 #define      FLD_AUD_ANC_EN           0x08000000
 317 #define      FLD_EN_C                 0x04000000
 318 #define      FLD_EN_B                 0x02000000
 319 #define      FLD_EN_A                 0x01000000
 320 /* Reserved [23:20] */
 321 #define      FLD_IDID1_LSB            0x000C0000
 322 #define      FLD_IDID0_LSB            0x00030000
 323 #define      FLD_IDID1_MSB            0x0000FF00
 324 #define      FLD_IDID0_MSB            0x000000FF
 325
 326 /*****************************************************************************/
 327 #define      GEN_STAT                 0x40C
 328 #define      FLD_VCR_DETECT           0x00800000
 329 #define      FLD_SPECIAL_PLAY_N       0x00400000
 330 #define      FLD_VPRES                0x00200000
 331 #define      FLD_AGC_LOCK             0x00100000
 332 #define      FLD_CSC_LOCK             0x00080000
 333 #define      FLD_VLOCK                0x00040000
 334 #define      FLD_SRC_LOCK             0x00020000
 335 #define      FLD_HLOCK                0x00010000
 336 #define      FLD_VSYNC_N              0x00008000
 337 #define      FLD_SRC_FIFO_UFLOW       0x00004000
 338 #define      FLD_SRC_FIFO_OFLOW       0x00002000
 339 #define      FLD_FIELD                0x00001000
 340 #define      FLD_AFD_FMT_STAT         0x00000F00
 341 #define      FLD_MV_TYPE2_PAIR        0x00000080
 342 #define      FLD_MV_T3CS              0x00000040
 343 #define      FLD_MV_CS                0x00000020
 344 #define      FLD_MV_PSP               0x00000010
 345 /* Reserved [3] */
 346 #define      FLD_MV_CDAT              0x00000003
 347
 348 /*****************************************************************************/
 349 #define      INT_STAT_MASK            0x410
 350 #define      FLD_COMB_3D_FIFO_MSK     0x80000000
 351 #define      FLD_WSS_DAT_AVAIL_MSK    0x40000000
 352 #define      FLD_GS2_DAT_AVAIL_MSK    0x20000000
 353 #define      FLD_GS1_DAT_AVAIL_MSK    0x10000000
 354 #define      FLD_CC_DAT_AVAIL_MSK     0x08000000
 355 #define      FLD_VPRES_CHANGE_MSK     0x04000000
 356 #define      FLD_MV_CHANGE_MSK        0x02000000
 357 #define      FLD_END_VBI_EVEN_MSK     0x01000000
 358 #define      FLD_END_VBI_ODD_MSK      0x00800000
 359 #define      FLD_FMT_CHANGE_MSK       0x00400000
 360 #define      FLD_VSYNC_TRAIL_MSK      0x00200000
 361 #define      FLD_HLOCK_CHANGE_MSK     0x00100000
 362 #define      FLD_VLOCK_CHANGE_MSK     0x00080000
 363 #define      FLD_CSC_LOCK_CHANGE_MSK  0x00040000
 364 #define      FLD_SRC_FIFO_UFLOW_MSK   0x00020000
 365 #define      FLD_SRC_FIFO_OFLOW_MSK   0x00010000
 366 #define      FLD_COMB_3D_FIFO_STAT    0x00008000
 367 #define      FLD_WSS_DAT_AVAIL_STAT   0x00004000
 368 #define      FLD_GS2_DAT_AVAIL_STAT   0x00002000
 369 #define      FLD_GS1_DAT_AVAIL_STAT   0x00001000
 370 #define      FLD_CC_DAT_AVAIL_STAT    0x00000800
 371 #define      FLD_VPRES_CHANGE_STAT    0x00000400
 372 #define      FLD_MV_CHANGE_STAT       0x00000200
 373 #define      FLD_END_VBI_EVEN_STAT    0x00000100
 374 #define      FLD_END_VBI_ODD_STAT     0x00000080
 375 #define      FLD_FMT_CHANGE_STAT      0x00000040
 376 #define      FLD_VSYNC_TRAIL_STAT     0x00000020
 377 #define      FLD_HLOCK_CHANGE_STAT    0x00000010
 378 #define      FLD_VLOCK_CHANGE_STAT    0x00000008
 379 #define      FLD_CSC_LOCK_CHANGE_STAT 0x00000004
 380 #define      FLD_SRC_FIFO_UFLOW_STAT  0x00000002
 381 #define      FLD_SRC_FIFO_OFLOW_STAT  0x00000001
 382
 383 /*****************************************************************************/
 384 #define      LUMA_CTRL                0x414
 385 #define      BRIGHTNESS_CTRL_BYTE     0x414
 386 #define      CONTRAST_CTRL_BYTE       0x415
 387 #define      LUMA_CTRL_BYTE_3         0x416
 388 #define      FLD_LUMA_CORE_SEL        0x00C00000
 389 #define      FLD_RANGE                0x00300000
 390 /* Reserved [19] */
 391 #define      FLD_PEAK_EN              0x00040000
 392 #define      FLD_PEAK_SEL             0x00030000
 393 #define      FLD_CNTRST               0x0000FF00
 394 #define      FLD_BRITE                0x000000FF
 395
 396 /*****************************************************************************/
 397 #define      HSCALE_CTRL              0x418
 398 #define      FLD_HFILT                0x03000000
 399 #define      FLD_HSCALE               0x00FFFFFF
 400
 401 /*****************************************************************************/
 402 #define      VSCALE_CTRL              0x41C
 403 #define      FLD_LINE_AVG_DIS         0x01000000
 404 /* Reserved [23:20] */
 405 #define      FLD_VS_INTRLACE          0x00080000
 406 #define      FLD_VFILT                0x00070000
 407 /* Reserved [15:13] */
 408 #define      FLD_VSCALE               0x00001FFF
 409
 410 /*****************************************************************************/
 411 #define      CHROMA_CTRL              0x420
 412 #define      USAT_CTRL_BYTE           0x420
 413 #define      VSAT_CTRL_BYTE           0x421
 414 #define      HUE_CTRL_BYTE            0x422
 415 #define      FLD_C_LPF_EN             0x20000000
 416 #define      FLD_CHR_DELAY            0x1C000000
 417 #define      FLD_C_CORE_SEL           0x03000000
 418 #define      FLD_HUE                  0x00FF0000
 419 #define      FLD_VSAT                 0x0000FF00
 420 #define      FLD_USAT                 0x000000FF
 421
 422 /*****************************************************************************/
 423 #define      VBI_LINE_CTRL1           0x424
 424 #define      FLD_VBI_MD_LINE4         0xFF000000
 425 #define      FLD_VBI_MD_LINE3         0x00FF0000
 426 #define      FLD_VBI_MD_LINE2         0x0000FF00
 427 #define      FLD_VBI_MD_LINE1         0x000000FF
 428
 429 /*****************************************************************************/
 430 #define      VBI_LINE_CTRL2           0x428
 431 #define      FLD_VBI_MD_LINE8         0xFF000000
 432 #define      FLD_VBI_MD_LINE7         0x00FF0000
 433 #define      FLD_VBI_MD_LINE6         0x0000FF00
 434 #define      FLD_VBI_MD_LINE5         0x000000FF
 435
 436 /*****************************************************************************/
 437 #define      VBI_LINE_CTRL3           0x42C
 438 #define      FLD_VBI_MD_LINE12        0xFF000000
 439 #define      FLD_VBI_MD_LINE11        0x00FF0000
 440 #define      FLD_VBI_MD_LINE10        0x0000FF00
 441 #define      FLD_VBI_MD_LINE9         0x000000FF
 442
 443 /*****************************************************************************/
 444 #define      VBI_LINE_CTRL4           0x430
 445 #define      FLD_VBI_MD_LINE16        0xFF000000
 446 #define      FLD_VBI_MD_LINE15        0x00FF0000
 447 #define      FLD_VBI_MD_LINE14        0x0000FF00
 448 #define      FLD_VBI_MD_LINE13        0x000000FF
 449
 450 /*****************************************************************************/
 451 #define      VBI_LINE_CTRL5           0x434
 452 #define      FLD_VBI_MD_LINE17        0x000000FF
 453
 454 /*****************************************************************************/
 455 #define      VBI_FC_CFG               0x438
 456 #define      FLD_FC_ALT2              0xFF000000
 457 #define      FLD_FC_ALT1              0x00FF0000
 458 #define      FLD_FC_ALT2_TYPE         0x0000F000
 459 #define      FLD_FC_ALT1_TYPE         0x00000F00
 460 /* Reserved [7:1] */
 461 #define      FLD_FC_SEARCH_MODE       0x00000001
 462
 463 /*****************************************************************************/
 464 #define      VBI_MISC_CFG1            0x43C
 465 #define      FLD_TTX_PKTADRU          0xFFF00000
 466 #define      FLD_TTX_PKTADRL          0x000FFF00
 467 /* Reserved [7:6] */
 468 #define      FLD_MOJI_PACK_DIS        0x00000020
 469 #define      FLD_VPS_DEC_DIS          0x00000010
 470 #define      FLD_CRI_MARG_SCALE       0x0000000C
 471 #define      FLD_EDGE_RESYNC_EN       0x00000002
 472 #define      FLD_ADAPT_SLICE_DIS      0x00000001
 473
 474 /*****************************************************************************/
 475 #define      VBI_MISC_CFG2            0x440
 476 #define      FLD_HAMMING_TYPE         0x0F000000
 477 /* Reserved [23:20] */
 478 #define      FLD_WSS_FIFO_RST         0x00080000
 479 #define      FLD_GS2_FIFO_RST         0x00040000
 480 #define      FLD_GS1_FIFO_RST         0x00020000
 481 #define      FLD_CC_FIFO_RST          0x00010000
 482 /* Reserved [15:12] */
 483 #define      FLD_VBI3_SDID            0x00000F00
 484 #define      FLD_VBI2_SDID            0x000000F0
 485 #define      FLD_VBI1_SDID            0x0000000F
 486
 487 /*****************************************************************************/
 488 #define      VBI_PAY1                 0x444
 489 #define      FLD_GS1_FIFO_DAT         0xFF000000
 490 #define      FLD_GS1_STAT             0x00FF0000
 491 #define      FLD_CC_FIFO_DAT          0x0000FF00
 492 #define      FLD_CC_STAT              0x000000FF
 493
 494 /*****************************************************************************/
 495 #define      VBI_PAY2                 0x448
 496 #define      FLD_WSS_FIFO_DAT         0xFF000000
 497 #define      FLD_WSS_STAT             0x00FF0000
 498 #define      FLD_GS2_FIFO_DAT         0x0000FF00
 499 #define      FLD_GS2_STAT             0x000000FF
 500
 501 /*****************************************************************************/
 502 #define      VBI_CUST1_CFG1           0x44C
 503 /* Reserved [31] */
 504 #define      FLD_VBI1_CRIWIN          0x7F000000
 505 #define      FLD_VBI1_SLICE_DIST      0x00F00000
 506 #define      FLD_VBI1_BITINC          0x000FFF00
 507 #define      FLD_VBI1_HDELAY          0x000000FF
 508
 509 /*****************************************************************************/
 510 #define      VBI_CUST1_CFG2           0x450
 511 #define      FLD_VBI1_FC_LENGTH       0x1F000000
 512 #define      FLD_VBI1_FRAME_CODE      0x00FFFFFF
 513
 514 /*****************************************************************************/
 515 #define      VBI_CUST1_CFG3           0x454
 516 #define      FLD_VBI1_HAM_EN          0x80000000
 517 #define      FLD_VBI1_FIFO_MODE       0x70000000
 518 #define      FLD_VBI1_FORMAT_TYPE     0x0F000000
 519 #define      FLD_VBI1_PAYLD_LENGTH    0x00FF0000
 520 #define      FLD_VBI1_CRI_LENGTH      0x0000F000
 521 #define      FLD_VBI1_CRI_MARGIN      0x00000F00
 522 #define      FLD_VBI1_CRI_TIME        0x000000FF
 523
 524 /*****************************************************************************/
 525 #define      VBI_CUST2_CFG1           0x458
 526 /* Reserved [31] */
 527 #define      FLD_VBI2_CRIWIN          0x7F000000
 528 #define      FLD_VBI2_SLICE_DIST      0x00F00000
 529 #define      FLD_VBI2_BITINC          0x000FFF00
 530 #define      FLD_VBI2_HDELAY          0x000000FF
 531
 532 /*****************************************************************************/
 533 #define      VBI_CUST2_CFG2           0x45C
 534 #define      FLD_VBI2_FC_LENGTH       0x1F000000
 535 #define      FLD_VBI2_FRAME_CODE      0x00FFFFFF
 536
 537 /*****************************************************************************/
 538 #define      VBI_CUST2_CFG3           0x460
 539 #define      FLD_VBI2_HAM_EN          0x80000000
 540 #define      FLD_VBI2_FIFO_MODE       0x70000000
 541 #define      FLD_VBI2_FORMAT_TYPE     0x0F000000
 542 #define      FLD_VBI2_PAYLD_LENGTH    0x00FF0000
 543 #define      FLD_VBI2_CRI_LENGTH      0x0000F000
 544 #define      FLD_VBI2_CRI_MARGIN      0x00000F00
 545 #define      FLD_VBI2_CRI_TIME        0x000000FF
 546
 547 /*****************************************************************************/
 548 #define      VBI_CUST3_CFG1           0x464
 549 /* Reserved [31] */
 550 #define      FLD_VBI3_CRIWIN          0x7F000000
 551 #define      FLD_VBI3_SLICE_DIST      0x00F00000
 552 #define      FLD_VBI3_BITINC          0x000FFF00
 553 #define      FLD_VBI3_HDELAY          0x000000FF
 554
 555 /*****************************************************************************/
 556 #define      VBI_CUST3_CFG2           0x468
 557 #define      FLD_VBI3_FC_LENGTH       0x1F000000
 558 #define      FLD_VBI3_FRAME_CODE      0x00FFFFFF
 559
 560 /*****************************************************************************/
 561 #define      VBI_CUST3_CFG3           0x46C
 562 #define      FLD_VBI3_HAM_EN          0x80000000
 563 #define      FLD_VBI3_FIFO_MODE       0x70000000
 564 #define      FLD_VBI3_FORMAT_TYPE     0x0F000000
 565 #define      FLD_VBI3_PAYLD_LENGTH    0x00FF0000
 566 #define      FLD_VBI3_CRI_LENGTH      0x0000F000
 567 #define      FLD_VBI3_CRI_MARGIN      0x00000F00
 568 #define      FLD_VBI3_CRI_TIME        0x000000FF
 569
 570 /*****************************************************************************/
 571 #define      HORIZ_TIM_CTRL           0x470
 572 #define      FLD_BGDEL_CNT            0xFF000000
 573 /* Reserved [23:22] */
 574 #define      FLD_HACTIVE_CNT          0x003FF000
 575 /* Reserved [11:10] */
 576 #define      FLD_HBLANK_CNT           0x000003FF
 577
 578 /*****************************************************************************/
 579 #define      VERT_TIM_CTRL            0x474
 580 #define      FLD_V656BLANK_CNT        0xFF000000
 581 /* Reserved [23:22] */
 582 #define      FLD_VACTIVE_CNT          0x003FF000
 583 /* Reserved [11:10] */
 584 #define      FLD_VBLANK_CNT           0x000003FF
 585
 586 /*****************************************************************************/
 587 #define      SRC_COMB_CFG             0x478
 588 #define      FLD_CCOMB_2LN_CHECK      0x80000000
 589 #define      FLD_CCOMB_3LN_EN         0x40000000
 590 #define      FLD_CCOMB_2LN_EN         0x20000000
 591 #define      FLD_CCOMB_3D_EN          0x10000000
 592 /* Reserved [27] */
 593 #define      FLD_LCOMB_3LN_EN         0x04000000
 594 #define      FLD_LCOMB_2LN_EN         0x02000000
 595 #define      FLD_LCOMB_3D_EN          0x01000000
 596 #define      FLD_LUMA_LPF_SEL         0x00C00000
 597 #define      FLD_UV_LPF_SEL           0x00300000
 598 #define      FLD_BLEND_SLOPE          0x000F0000
 599 #define      FLD_CCOMB_REDUCE_EN      0x00008000
 600 /* Reserved [14:10] */
 601 #define      FLD_SRC_DECIM_RATIO      0x000003FF
 602
 603 /*****************************************************************************/
 604 #define      CHROMA_VBIOFF_CFG        0x47C
 605 #define      FLD_VBI_VOFFSET          0x1F000000
 606 /* Reserved [23:20] */
 607 #define      FLD_SC_STEP              0x000FFFFF
 608
 609 /*****************************************************************************/
 610 #define      FIELD_COUNT              0x480
 611 #define      FLD_FIELD_COUNT_FLD      0x000003FF
 612
 613 /*****************************************************************************/
 614 #define      MISC_TIM_CTRL            0x484
 615 #define      FLD_DEBOUNCE_COUNT       0xC0000000
 616 #define      FLD_VT_LINE_CNT_HYST     0x30000000
 617 /* Reserved [27] */
 618 #define      FLD_AFD_STAT             0x07FF0000
 619 #define      FLD_VPRES_VERT_EN        0x00008000
 620 /* Reserved [14:12] */
 621 #define      FLD_HR32                 0x00000800
 622 #define      FLD_TDALGN               0x00000400
 623 #define      FLD_TDFIELD              0x00000200
 624 /* Reserved [8:6] */
 625 #define      FLD_TEMPDEC              0x0000003F
 626
 627 /*****************************************************************************/
 628 #define      DFE_CTRL1                0x488
 629 #define      FLD_CLAMP_AUTO_EN        0x80000000
 630 #define      FLD_AGC_AUTO_EN          0x40000000
 631 #define      FLD_VGA_CRUSH_EN         0x20000000
 632 #define      FLD_VGA_AUTO_EN          0x10000000
 633 #define      FLD_VBI_GATE_EN          0x08000000
 634 #define      FLD_CLAMP_LEVEL          0x07000000
 635 /* Reserved [23:22] */
 636 #define      FLD_CLAMP_SKIP_CNT       0x00300000
 637 #define      FLD_AGC_GAIN             0x000FFF00
 638 /* Reserved [7:6] */
 639 #define      FLD_VGA_GAIN             0x0000003F
 640
 641 /*****************************************************************************/
 642 #define      DFE_CTRL2                0x48C
 643 #define      FLD_VGA_ACQUIRE_RANGE    0x00FF0000
 644 #define      FLD_VGA_TRACK_RANGE      0x0000FF00
 645 #define      FLD_VGA_SYNC             0x000000FF
 646
 647 /*****************************************************************************/
 648 #define      DFE_CTRL3                0x490
 649 #define      FLD_BP_PERCENT           0xFF000000
 650 #define      FLD_DFT_THRESHOLD        0x00FF0000
 651 /* Reserved [15:12] */
 652 #define      FLD_SYNC_WIDTH_SEL       0x00000600
 653 #define      FLD_BP_LOOP_GAIN         0x00000300
 654 #define      FLD_SYNC_LOOP_GAIN       0x000000C0
 655 /* Reserved [5:4] */
 656 #define      FLD_AGC_LOOP_GAIN        0x0000000C
 657 #define      FLD_DCC_LOOP_GAIN        0x00000003
 658
 659 /*****************************************************************************/
 660 #define      PLL_CTRL                 0x494
 661 #define      FLD_PLL_KD               0xFF000000
 662 #define      FLD_PLL_KI               0x00FF0000
 663 #define      FLD_PLL_MAX_OFFSET       0x0000FFFF
 664
 665
 666 /*****************************************************************************/
 667 #define      HTL_CTRL                 0x498
 668 /* Reserved [31:24] */
 669 #define      FLD_AUTO_LOCK_SPD        0x00080000
 670 #define      FLD_MAN_FAST_LOCK        0x00040000
 671 #define      FLD_HTL_15K_EN           0x00020000
 672 #define      FLD_HTL_500K_EN          0x00010000
 673 #define      FLD_HTL_KD               0x0000FF00
 674 #define      FLD_HTL_KI               0x000000FF
 675
 676 /*****************************************************************************/
 677 #define      COMB_CTRL                0x49C
 678 #define      FLD_COMB_PHASE_LIMIT     0xFF000000
 679 #define      FLD_CCOMB_ERR_LIMIT      0x00FF0000
 680 #define      FLD_LUMA_THRESHOLD       0x0000FF00
 681 #define      FLD_LCOMB_ERR_LIMIT      0x000000FF
 682
 683 /*****************************************************************************/
 684 #define      CRUSH_CTRL               0x4A0
 685 #define      FLD_WTW_EN               0x00400000
 686 #define      FLD_CRUSH_FREQ           0x00200000
 687 #define      FLD_MAJ_SEL_EN           0x00100000
 688 #define      FLD_MAJ_SEL              0x000C0000
 689 /* Reserved [17:15] */
 690 #define      FLD_SYNC_TIP_REDUCE      0x00007E00
 691 /* Reserved [8:6] */
 692 #define      FLD_SYNC_TIP_INC         0x0000003F
 693
 694 /*****************************************************************************/
 695 #define      SOFT_RST_CTRL            0x4A4
 696 #define      FLD_VD_SOFT_RST          0x00008000
 697 /* Reserved [14:12] */
 698 #define      FLD_REG_RST_MSK          0x00000800
 699 #define      FLD_VOF_RST_MSK          0x00000400
 700 #define      FLD_MVDET_RST_MSK        0x00000200
 701 #define      FLD_VBI_RST_MSK          0x00000100
 702 #define      FLD_SCALE_RST_MSK        0x00000080
 703 #define      FLD_CHROMA_RST_MSK       0x00000040
 704 #define      FLD_LUMA_RST_MSK         0x00000020
 705 #define      FLD_VTG_RST_MSK          0x00000010
 706 #define      FLD_YCSEP_RST_MSK        0x00000008
 707 #define      FLD_SRC_RST_MSK          0x00000004
 708 #define      FLD_DFE_RST_MSK          0x00000002
 709 /* Reserved [0] */
 710
 711 /*****************************************************************************/
 712 #define      MV_DT_CTRL1              0x4A8
 713 /* Reserved [31:29] */
 714 #define      FLD_PSP_STOP_LINE        0x1F000000
 715 /* Reserved [23:21] */
 716 #define      FLD_PSP_STRT_LINE        0x001F0000
 717 /* Reserved [15] */
 718 #define      FLD_PSP_LLIMW            0x00007F00
 719 /* Reserved [7] */
 720 #define      FLD_PSP_ULIMW            0x0000007F
 721
 722 /*****************************************************************************/
 723 #define      MV_DT_CTRL2              0x4AC
 724 #define      FLD_CS_STOPWIN           0xFF000000
 725 #define      FLD_CS_STRTWIN           0x00FF0000
 726 #define      FLD_CS_WIDTH             0x0000FF00
 727 #define      FLD_PSP_SPEC_VAL         0x000000FF
 728
 729 /*****************************************************************************/
 730 #define      MV_DT_CTRL3              0x4B0
 731 #define      FLD_AUTO_RATE_DIS        0x80000000
 732 #define      FLD_HLOCK_DIS            0x40000000
 733 #define      FLD_SEL_FIELD_CNT        0x20000000
 734 #define      FLD_CS_TYPE2_SEL         0x10000000
 735 #define      FLD_CS_LINE_THRSH_SEL    0x08000000
 736 #define      FLD_CS_ATHRESH_SEL       0x04000000
 737 #define      FLD_PSP_SPEC_SEL         0x02000000
 738 #define      FLD_PSP_LINES_SEL        0x01000000
 739 #define      FLD_FIELD_CNT            0x00F00000
 740 #define      FLD_CS_TYPE2_CNT         0x000FC000
 741 #define      FLD_CS_LINE_CNT          0x00003F00
 742 #define      FLD_CS_ATHRESH_LEV       0x000000FF
 743
 744 /*****************************************************************************/
 745 #define      CHIP_VERSION             0x4B4
 746 /* Cx231xx redefine  */
 747 #define      VERSION                  0x4B4
 748 #define      FLD_REV_ID               0x000000FF
 749
 750 /*****************************************************************************/
 751 #define      MISC_DIAG_CTRL           0x4B8
 752 /* Reserved [31:24] */
 753 #define      FLD_SC_CONVERGE_THRESH   0x00FF0000
 754 #define      FLD_CCOMB_ERR_LIMIT_3D   0x0000FF00
 755 #define      FLD_LCOMB_ERR_LIMIT_3D   0x000000FF
 756
 757 /*****************************************************************************/
 758 #define      VBI_PASS_CTRL            0x4BC
 759 #define      FLD_VBI_PASS_MD          0x00200000
 760 #define      FLD_VBI_SETUP_DIS        0x00100000
 761 #define      FLD_PASS_LINE_CTRL       0x000FFFFF
 762
 763 /*****************************************************************************/
 764 /* Cx231xx redefine */
 765 #define      VCR_DET_CTRL             0x4c0
 766 #define      FLD_EN_FIELD_PHASE_DET   0x80000000
 767 #define      FLD_EN_HEAD_SW_DET       0x40000000
 768 #define      FLD_FIELD_PHASE_LENGTH   0x01FF0000
 769 /* Reserved [29:25] */
 770 #define      FLD_FIELD_PHASE_DELAY    0x0000FF00
 771 #define      FLD_FIELD_PHASE_LIMIT    0x000000F0
 772 #define      FLD_HEAD_SW_DET_LIMIT    0x0000000F
 773
 774
 775 /*****************************************************************************/
 776 #define      DL_CTL                   0x800
 777 #define      DL_CTL_ADDRESS_LOW       0x800    /* Byte 1 in DL_CTL */
 778 #define      DL_CTL_ADDRESS_HIGH      0x801    /* Byte 2 in DL_CTL */
 779 #define      DL_CTL_DATA              0x802    /* Byte 3 in DL_CTL */
 780 #define      DL_CTL_CONTROL           0x803    /* Byte 4 in DL_CTL */
 781 /* Reserved [31:5] */
 782 #define      FLD_START_8051           0x10000000
 783 #define      FLD_DL_ENABLE            0x08000000
 784 #define      FLD_DL_AUTO_INC          0x04000000
 785 #define      FLD_DL_MAP               0x03000000
 786
 787 /*****************************************************************************/
 788 #define      STD_DET_STATUS           0x804
 789 #define      FLD_SPARE_STATUS1        0xFF000000
 790 #define      FLD_SPARE_STATUS0        0x00FF0000
 791 #define      FLD_MOD_DET_STATUS1      0x0000FF00
 792 #define      FLD_MOD_DET_STATUS0      0x000000FF
 793
 794 /*****************************************************************************/
 795 #define      AUD_BUILD_NUM            0x806
 796 #define      AUD_VER_NUM              0x807
 797 #define      STD_DET_CTL              0x808
 798 #define      STD_DET_CTL_AUD_CTL      0x808  /* Byte 1 in STD_DET_CTL */
 799 #define      STD_DET_CTL_PREF_MODE    0x809  /* Byte 2 in STD_DET_CTL */
 800 #define      FLD_SPARE_CTL0           0xFF000000
 801 #define      FLD_DIS_DBX              0x00800000
 802 #define      FLD_DIS_BTSC             0x00400000
 803 #define      FLD_DIS_NICAM_A2         0x00200000
 804 #define      FLD_VIDEO_PRESENT        0x00100000
 805 #define      FLD_DW8051_VIDEO_FORMAT  0x000F0000
 806 #define      FLD_PREF_DEC_MODE        0x0000FF00
 807 #define      FLD_AUD_CONFIG           0x000000FF
 808
 809 /*****************************************************************************/
 810 #define      DW8051_INT               0x80C
 811 #define      FLD_VIDEO_PRESENT_CHANGE 0x80000000
 812 #define      FLD_VIDEO_CHANGE         0x40000000
 813 #define      FLD_RDS_READY            0x20000000
 814 #define      FLD_AC97_INT             0x10000000
 815 #define      FLD_NICAM_BIT_ERROR_TOO_HIGH         0x08000000
 816 #define      FLD_NICAM_LOCK           0x04000000
 817 #define      FLD_NICAM_UNLOCK         0x02000000
 818 #define      FLD_DFT4_TH_CMP          0x01000000
 819 /* Reserved [23:22] */
 820 #define      FLD_LOCK_IND_INT         0x00200000
 821 #define      FLD_DFT3_TH_CMP          0x00100000
 822 #define      FLD_DFT2_TH_CMP          0x00080000
 823 #define      FLD_DFT1_TH_CMP          0x00040000
 824 #define      FLD_FM2_DFT_TH_CMP       0x00020000
 825 #define      FLD_FM1_DFT_TH_CMP       0x00010000
 826 #define      FLD_VIDEO_PRESENT_EN     0x00008000
 827 #define      FLD_VIDEO_CHANGE_EN      0x00004000
 828 #define      FLD_RDS_READY_EN         0x00002000
 829 #define      FLD_AC97_INT_EN          0x00001000
 830 #define      FLD_NICAM_BIT_ERROR_TOO_HIGH_EN      0x00000800
 831 #define      FLD_NICAM_LOCK_EN        0x00000400
 832 #define      FLD_NICAM_UNLOCK_EN      0x00000200
 833 #define      FLD_DFT4_TH_CMP_EN       0x00000100
 834 /* Reserved [7] */
 835 #define      FLD_DW8051_INT6_CTL1     0x00000040
 836 #define      FLD_DW8051_INT5_CTL1     0x00000020
 837 #define      FLD_DW8051_INT4_CTL1     0x00000010
 838 #define      FLD_DW8051_INT3_CTL1     0x00000008
 839 #define      FLD_DW8051_INT2_CTL1     0x00000004
 840 #define      FLD_DW8051_INT1_CTL1     0x00000002
 841 #define      FLD_DW8051_INT0_CTL1     0x00000001
 842
 843 /*****************************************************************************/
 844 #define      GENERAL_CTL              0x810
 845 #define      FLD_RDS_INT              0x80000000
 846 #define      FLD_NBER_INT             0x40000000
 847 #define      FLD_NLL_INT              0x20000000
 848 #define      FLD_IFL_INT              0x10000000
 849 #define      FLD_FDL_INT              0x08000000
 850 #define      FLD_AFC_INT              0x04000000
 851 #define      FLD_AMC_INT              0x02000000
 852 #define      FLD_AC97_INT_CTL         0x01000000
 853 #define      FLD_RDS_INT_DIS          0x00800000
 854 #define      FLD_NBER_INT_DIS         0x00400000
 855 #define      FLD_NLL_INT_DIS          0x00200000
 856 #define      FLD_IFL_INT_DIS          0x00100000
 857 #define      FLD_FDL_INT_DIS          0x00080000
 858 #define      FLD_FC_INT_DIS           0x00040000
 859 #define      FLD_AMC_INT_DIS          0x00020000
 860 #define      FLD_AC97_INT_DIS         0x00010000
 861 #define      FLD_REV_NUM              0x0000FF00
 862 /* Reserved [7:5] */
 863 #define      FLD_DBX_SOFT_RESET_REG   0x00000010
 864 #define      FLD_AD_SOFT_RESET_REG    0x00000008
 865 #define      FLD_SRC_SOFT_RESET_REG   0x00000004
 866 #define      FLD_CDMOD_SOFT_RESET     0x00000002
 867 #define      FLD_8051_SOFT_RESET      0x00000001
 868
 869 /*****************************************************************************/
 870 #define      AAGC_CTL                 0x814
 871 #define      FLD_AFE_12DB_EN          0x80000000
 872 #define      FLD_AAGC_DEFAULT_EN      0x40000000
 873 #define      FLD_AAGC_DEFAULT         0x3F000000
 874 /* Reserved [23] */
 875 #define      FLD_AAGC_GAIN            0x00600000
 876 #define      FLD_AAGC_TH              0x001F0000
 877 /* Reserved [15:14] */
 878 #define      FLD_AAGC_HYST2           0x00003F00
 879 /* Reserved [7:6] */
 880 #define      FLD_AAGC_HYST1           0x0000003F
 881
 882 /*****************************************************************************/
 883 #define      IF_SRC_CTL               0x818
 884 #define      FLD_DBX_BYPASS           0x80000000
 885 /* Reserved [30:25] */
 886 #define      FLD_IF_SRC_MODE          0x01000000
 887 /* Reserved [23:18] */
 888 #define      FLD_IF_SRC_PHASE_INC     0x0001FFFF
 889
 890 /*****************************************************************************/
 891 #define      ANALOG_DEMOD_CTL         0x81C
 892 #define      FLD_ROT1_PHACC_PROG      0xFFFF0000
 893 /* Reserved [15] */
 894 #define      FLD_FM1_DELAY_FIX        0x00007000
 895 #define      FLD_PDF4_SHIFT           0x00000C00
 896 #define      FLD_PDF3_SHIFT           0x00000300
 897 #define      FLD_PDF2_SHIFT           0x000000C0
 898 #define      FLD_PDF1_SHIFT           0x00000030
 899 #define      FLD_FMBYPASS_MODE2       0x00000008
 900 #define      FLD_FMBYPASS_MODE1       0x00000004
 901 #define      FLD_NICAM_MODE           0x00000002
 902 #define      FLD_BTSC_FMRADIO_MODE    0x00000001
 903
 904 /*****************************************************************************/
 905 #define      ROT_FREQ_CTL             0x820
 906 #define      FLD_ROT3_PHACC_PROG      0xFFFF0000
 907 #define      FLD_ROT2_PHACC_PROG      0x0000FFFF
 908
 909 /*****************************************************************************/
 910 #define      FM_CTL                   0x824
 911 #define      FLD_FM2_DC_FB_SHIFT      0xF0000000
 912 #define      FLD_FM2_DC_INT_SHIFT     0x0F000000
 913 #define      FLD_FM2_AFC_RESET        0x00800000
 914 #define      FLD_FM2_DC_PASS_IN       0x00400000
 915 #define      FLD_FM2_DAGC_SHIFT       0x00380000
 916 #define      FLD_FM2_CORDIC_SHIFT     0x00070000
 917 #define      FLD_FM1_DC_FB_SHIFT      0x0000F000
 918 #define      FLD_FM1_DC_INT_SHIFT     0x00000F00
 919 #define      FLD_FM1_AFC_RESET        0x00000080
 920 #define      FLD_FM1_DC_PASS_IN       0x00000040
 921 #define      FLD_FM1_DAGC_SHIFT       0x00000038
 922 #define      FLD_FM1_CORDIC_SHIFT     0x00000007
 923
 924 /*****************************************************************************/
 925 #define      LPF_PDF_CTL              0x828
 926 /* Reserved [31:30] */
 927 #define      FLD_LPF32_SHIFT1         0x30000000
 928 #define      FLD_LPF32_SHIFT2         0x0C000000
 929 #define      FLD_LPF160_SHIFTA        0x03000000
 930 #define      FLD_LPF160_SHIFTB        0x00C00000
 931 #define      FLD_LPF160_SHIFTC        0x00300000
 932 #define      FLD_LPF32_COEF_SEL2      0x000C0000
 933 #define      FLD_LPF32_COEF_SEL1      0x00030000
 934 #define      FLD_LPF160_COEF_SELC     0x0000C000
 935 #define      FLD_LPF160_COEF_SELB     0x00003000
 936 #define      FLD_LPF160_COEF_SELA     0x00000C00
 937 #define      FLD_LPF160_IN_EN_REG     0x00000300
 938 #define      FLD_PDF4_PDF_SEL         0x000000C0
 939 #define      FLD_PDF3_PDF_SEL         0x00000030
 940 #define      FLD_PDF2_PDF_SEL         0x0000000C
 941 #define      FLD_PDF1_PDF_SEL         0x00000003
 942
 943 /*****************************************************************************/
 944 #define      DFT1_CTL1                0x82C
 945 #define      FLD_DFT1_DWELL           0xFFFF0000
 946 #define      FLD_DFT1_FREQ            0x0000FFFF
 947
 948 /*****************************************************************************/
 949 #define      DFT1_CTL2                0x830
 950 #define      FLD_DFT1_THRESHOLD       0xFFFFFF00
 951 #define      FLD_DFT1_CMP_CTL         0x00000080
 952 #define      FLD_DFT1_AVG             0x00000070
 953 /* Reserved [3:1] */
 954 #define      FLD_DFT1_START           0x00000001
 955
 956 /*****************************************************************************/
 957 #define      DFT1_STATUS              0x834
 958 #define      FLD_DFT1_DONE            0x80000000
 959 #define      FLD_DFT1_TH_CMP_STAT     0x40000000
 960 #define      FLD_DFT1_RESULT          0x3FFFFFFF
 961
 962 /*****************************************************************************/
 963 #define      DFT2_CTL1                0x838
 964 #define      FLD_DFT2_DWELL           0xFFFF0000
 965 #define      FLD_DFT2_FREQ            0x0000FFFF
 966
 967 /*****************************************************************************/
 968 #define      DFT2_CTL2                0x83C
 969 #define      FLD_DFT2_THRESHOLD       0xFFFFFF00
 970 #define      FLD_DFT2_CMP_CTL         0x00000080
 971 #define      FLD_DFT2_AVG             0x00000070
 972 /* Reserved [3:1] */
 973 #define      FLD_DFT2_START           0x00000001
 974
 975 /*****************************************************************************/
 976 #define      DFT2_STATUS              0x840
 977 #define      FLD_DFT2_DONE            0x80000000
 978 #define      FLD_DFT2_TH_CMP_STAT     0x40000000
 979 #define      FLD_DFT2_RESULT          0x3FFFFFFF
 980
 981 /*****************************************************************************/
 982 #define      DFT3_CTL1                0x844
 983 #define      FLD_DFT3_DWELL           0xFFFF0000
 984 #define      FLD_DFT3_FREQ            0x0000FFFF
 985
 986 /*****************************************************************************/
 987 #define      DFT3_CTL2                0x848
 988 #define      FLD_DFT3_THRESHOLD       0xFFFFFF00
 989 #define      FLD_DFT3_CMP_CTL         0x00000080
 990 #define      FLD_DFT3_AVG             0x00000070
 991 /* Reserved [3:1] */
 992 #define      FLD_DFT3_START           0x00000001
 993
 994 /*****************************************************************************/
 995 #define      DFT3_STATUS              0x84C
 996 #define      FLD_DFT3_DONE            0x80000000
 997 #define      FLD_DFT3_TH_CMP_STAT     0x40000000
 998 #define      FLD_DFT3_RESULT          0x3FFFFFFF
 999
1000 /*****************************************************************************/
1001 #define      DFT4_CTL1                0x850
1002 #define      FLD_DFT4_DWELL           0xFFFF0000
1003 #define      FLD_DFT4_FREQ            0x0000FFFF
1004
1005 /*****************************************************************************/
1006 #define      DFT4_CTL2                0x854
1007 #define      FLD_DFT4_THRESHOLD       0xFFFFFF00
1008 #define      FLD_DFT4_CMP_CTL         0x00000080
1009 #define      FLD_DFT4_AVG             0x00000070
1010 /* Reserved [3:1] */
1011 #define      FLD_DFT4_START           0x00000001
1012
1013 /*****************************************************************************/
1014 #define      DFT4_STATUS              0x858
1015 #define      FLD_DFT4_DONE            0x80000000
1016 #define      FLD_DFT4_TH_CMP_STAT     0x40000000
1017 #define      FLD_DFT4_RESULT          0x3FFFFFFF
1018
1019 /*****************************************************************************/
1020 #define      AM_MTS_DET               0x85C
1021 #define      FLD_AM_MTS_MODE          0x80000000
1022 /* Reserved [30:26] */
1023 #define      FLD_AM_SUB               0x02000000
1024 #define      FLD_AM_GAIN_EN           0x01000000
1025 /* Reserved [23:16] */
1026 #define      FLD_AMMTS_GAIN_SCALE     0x0000E000
1027 #define      FLD_MTS_PDF_SHIFT        0x00001800
1028 #define      FLD_AM_REG_GAIN          0x00000700
1029 #define      FLD_AGC_REF              0x000000FF
1030
1031 /*****************************************************************************/
1032 #define      ANALOG_MUX_CTL           0x860
1033 /* Reserved [31:29] */
1034 #define      FLD_MUX21_SEL            0x10000000
1035 #define      FLD_MUX20_SEL            0x08000000
1036 #define      FLD_MUX19_SEL            0x04000000
1037 #define      FLD_MUX18_SEL            0x02000000
1038 #define      FLD_MUX17_SEL            0x01000000
1039 #define      FLD_MUX16_SEL            0x00800000
1040 #define      FLD_MUX15_SEL            0x00400000
1041 #define      FLD_MUX14_SEL            0x00300000
1042 #define      FLD_MUX13_SEL            0x000C0000
1043 #define      FLD_MUX12_SEL            0x00020000
1044 #define      FLD_MUX11_SEL            0x00018000
1045 #define      FLD_MUX10_SEL            0x00004000
1046 #define      FLD_MUX9_SEL             0x00002000
1047 #define      FLD_MUX8_SEL             0x00001000
1048 #define      FLD_MUX7_SEL             0x00000800
1049 #define      FLD_MUX6_SEL             0x00000600
1050 #define      FLD_MUX5_SEL             0x00000100
1051 #define      FLD_MUX4_SEL             0x000000C0
1052 #define      FLD_MUX3_SEL             0x00000030
1053 #define      FLD_MUX2_SEL             0x0000000C
1054 #define      FLD_MUX1_SEL             0x00000003
1055
1056 /*****************************************************************************/
1057 /* Cx231xx redefine */
1058 #define      DPLL_CTRL1               0x864
1059 #define      DIG_PLL_CTL1             0x864
1060
1061 #define      FLD_PLL_STATUS           0x07000000
1062 #define      FLD_BANDWIDTH_SELECT     0x00030000
1063 #define      FLD_PLL_SHIFT_REG        0x00007000
1064 #define      FLD_PHASE_SHIFT          0x000007FF
1065
1066 /*****************************************************************************/
1067 /* Cx231xx redefine */
1068 #define      DPLL_CTRL2               0x868
1069 #define      DIG_PLL_CTL2             0x868
1070 #define      FLD_PLL_UNLOCK_THR       0xFF000000
1071 #define      FLD_PLL_LOCK_THR         0x00FF0000
1072 /* Reserved [15:8] */
1073 #define      FLD_AM_PDF_SEL2          0x000000C0
1074 #define      FLD_AM_PDF_SEL1          0x00000030
1075 #define      FLD_DPLL_FSM_CTRL        0x0000000C
1076 /* Reserved [1] */
1077 #define      FLD_PLL_PILOT_DET        0x00000001
1078
1079 /*****************************************************************************/
1080 /* Cx231xx redefine */
1081 #define      DPLL_CTRL3               0x86C
1082 #define      DIG_PLL_CTL3             0x86C
1083 #define      FLD_DISABLE_LOOP         0x01000000
1084 #define      FLD_A1_DS1_SEL           0x000C0000
1085 #define      FLD_A1_DS2_SEL           0x00030000
1086 #define      FLD_A1_KI                0x0000FF00
1087 #define      FLD_A1_KD                0x000000FF
1088
1089 /*****************************************************************************/
1090 /* Cx231xx redefine */
1091 #define      DPLL_CTRL4               0x870
1092 #define      DIG_PLL_CTL4             0x870
1093 #define      FLD_A2_DS1_SEL           0x000C0000
1094 #define      FLD_A2_DS2_SEL           0x00030000
1095 #define      FLD_A2_KI                0x0000FF00
1096 #define      FLD_A2_KD                0x000000FF
1097
1098 /*****************************************************************************/
1099 /* Cx231xx redefine */
1100 #define      DPLL_CTRL5               0x874
1101 #define      DIG_PLL_CTL5             0x874
1102 #define      FLD_TRK_DS1_SEL          0x000C0000
1103 #define      FLD_TRK_DS2_SEL          0x00030000
1104 #define      FLD_TRK_KI               0x0000FF00
1105 #define      FLD_TRK_KD               0x000000FF
1106
1107 /*****************************************************************************/
1108 #define      DEEMPH_GAIN_CTL          0x878
1109 #define      FLD_DEEMPH2_GAIN         0xFFFF0000
1110 #define      FLD_DEEMPH1_GAIN         0x0000FFFF
1111
1112 /*****************************************************************************/
1113 /* Cx231xx redefine */
1114 #define      DEEMPH_COEFF1            0x87C
1115 #define      DEEMPH_COEF1             0x87C
1116 #define      FLD_DEEMPH_B0            0xFFFF0000
1117 #define      FLD_DEEMPH_A0            0x0000FFFF
1118
1119 /*****************************************************************************/
1120 /* Cx231xx redefine */
1121 #define      DEEMPH_COEFF2            0x880
1122 #define      DEEMPH_COEF2             0x880
1123 #define      FLD_DEEMPH_B1            0xFFFF0000
1124 #define      FLD_DEEMPH_A1            0x0000FFFF
1125
1126 /*****************************************************************************/
1127 #define      DBX1_CTL1                0x884
1128 #define      FLD_DBX1_WBE_GAIN        0xFFFF0000
1129 #define      FLD_DBX1_IN_GAIN         0x0000FFFF
1130
1131 /*****************************************************************************/
1132 #define      DBX1_CTL2                0x888
1133 #define      FLD_DBX1_SE_BYPASS       0xFFFF0000
1134 #define      FLD_DBX1_SE_GAIN         0x0000FFFF
1135
1136 /*****************************************************************************/
1137 #define      DBX1_RMS_SE              0x88C
1138 #define      FLD_DBX1_RMS_WBE         0xFFFF0000
1139 #define      FLD_DBX1_RMS_SE_FLD      0x0000FFFF
1140
1141 /*****************************************************************************/
1142 #define      DBX2_CTL1                0x890
1143 #define      FLD_DBX2_WBE_GAIN        0xFFFF0000
1144 #define      FLD_DBX2_IN_GAIN         0x0000FFFF
1145
1146 /*****************************************************************************/
1147 #define      DBX2_CTL2                0x894
1148 #define      FLD_DBX2_SE_BYPASS       0xFFFF0000
1149 #define      FLD_DBX2_SE_GAIN         0x0000FFFF
1150
1151 /*****************************************************************************/
1152 #define      DBX2_RMS_SE              0x898
1153 #define      FLD_DBX2_RMS_WBE         0xFFFF0000
1154 #define      FLD_DBX2_RMS_SE_FLD      0x0000FFFF
1155
1156 /*****************************************************************************/
1157 #define      AM_FM_DIFF               0x89C
1158 /* Reserved [31] */
1159 #define      FLD_FM_DIFF_OUT          0x7FFF0000
1160 /* Reserved [15] */
1161 #define      FLD_AM_DIFF_OUT          0x00007FFF
1162
1163 /*****************************************************************************/
1164 #define      NICAM_FAW                0x8A0
1165 #define      FLD_FAWDETWINEND         0xFC000000
1166 #define      FLD_FAWDETWINSTR         0x03FF0000
1167 /* Reserved [15:12] */
1168 #define      FLD_FAWDETTHRSHLD3       0x00000F00
1169 #define      FLD_FAWDETTHRSHLD2       0x000000F0
1170 #define      FLD_FAWDETTHRSHLD1       0x0000000F
1171
1172 /*****************************************************************************/
1173 /* Cx231xx redefine */
1174 #define      DEEMPH_GAIN              0x8A4
1175 #define      NICAM_DEEMPHGAIN         0x8A4
1176 /* Reserved [31:18] */
1177 #define      FLD_DEEMPHGAIN           0x0003FFFF
1178
1179 /*****************************************************************************/
1180 /* Cx231xx redefine */
1181 #define      DEEMPH_NUMER1            0x8A8
1182 #define      NICAM_DEEMPHNUMER1       0x8A8
1183 /* Reserved [31:18] */
1184 #define      FLD_DEEMPHNUMER1         0x0003FFFF
1185
1186 /*****************************************************************************/
1187 /* Cx231xx redefine */
1188 #define      DEEMPH_NUMER2            0x8AC
1189 #define      NICAM_DEEMPHNUMER2       0x8AC
1190 /* Reserved [31:18] */
1191 #define      FLD_DEEMPHNUMER2         0x0003FFFF
1192
1193 /*****************************************************************************/
1194 /* Cx231xx redefine */
1195 #define      DEEMPH_DENOM1            0x8B0
1196 #define      NICAM_DEEMPHDENOM1       0x8B0
1197 /* Reserved [31:18] */
1198 #define      FLD_DEEMPHDENOM1         0x0003FFFF
1199
1200 /*****************************************************************************/
1201 /* Cx231xx redefine */
1202 #define      DEEMPH_DENOM2            0x8B4
1203 #define      NICAM_DEEMPHDENOM2       0x8B4
1204 /* Reserved [31:18] */
1205 #define      FLD_DEEMPHDENOM2         0x0003FFFF
1206
1207 /*****************************************************************************/
1208 #define      NICAM_ERRLOG_CTL1        0x8B8
1209 /* Reserved [31:28] */
1210 #define      FLD_ERRINTRPTTHSHLD1     0x0FFF0000
1211 /* Reserved [15:12] */
1212 #define      FLD_ERRLOGPERIOD         0x00000FFF
1213
1214 /*****************************************************************************/
1215 #define      NICAM_ERRLOG_CTL2        0x8BC
1216 /* Reserved [31:28] */
1217 #define      FLD_ERRINTRPTTHSHLD3     0x0FFF0000
1218 /* Reserved [15:12] */
1219 #define      FLD_ERRINTRPTTHSHLD2     0x00000FFF
1220
1221 /*****************************************************************************/
1222 #define      NICAM_ERRLOG_STS1        0x8C0
1223 /* Reserved [31:28] */
1224 #define      FLD_ERRLOG2              0x0FFF0000
1225 /* Reserved [15:12] */
1226 #define      FLD_ERRLOG1              0x00000FFF
1227
1228 /*****************************************************************************/
1229 #define      NICAM_ERRLOG_STS2        0x8C4
1230 /* Reserved [31:12] */
1231 #define      FLD_ERRLOG3              0x00000FFF
1232
1233 /*****************************************************************************/
1234 #define      NICAM_STATUS             0x8C8
1235 /* Reserved [31:20] */
1236 #define      FLD_NICAM_CIB            0x000C0000
1237 #define      FLD_NICAM_LOCK_STAT      0x00020000
1238 #define      FLD_NICAM_MUTE           0x00010000
1239 #define      FLD_NICAMADDIT_DATA      0x0000FFE0
1240 #define      FLD_NICAMCNTRL           0x0000001F
1241
1242 /*****************************************************************************/
1243 #define      DEMATRIX_CTL             0x8CC
1244 #define      FLD_AC97_IN_SHIFT        0xF0000000
1245 #define      FLD_I2S_IN_SHIFT         0x0F000000
1246 #define      FLD_DEMATRIX_SEL_CTL     0x00FF0000
1247 /* Reserved [15:11] */
1248 #define      FLD_DMTRX_BYPASS         0x00000400
1249 #define      FLD_DEMATRIX_MODE        0x00000300
1250 /* Reserved [7:6] */
1251 #define      FLD_PH_DBX_SEL           0x00000020
1252 #define      FLD_PH_CH_SEL            0x00000010
1253 #define      FLD_PHASE_FIX            0x0000000F
1254
1255 /*****************************************************************************/
1256 #define      PATH1_CTL1               0x8D0
1257 /* Reserved [31:29] */
1258 #define      FLD_PATH1_MUTE_CTL       0x1F000000
1259 /* Reserved [23:22] */
1260 #define      FLD_PATH1_AVC_CG         0x00300000
1261 #define      FLD_PATH1_AVC_RT         0x000F0000
1262 #define      FLD_PATH1_AVC_AT         0x0000F000
1263 #define      FLD_PATH1_AVC_STEREO     0x00000800
1264 #define      FLD_PATH1_AVC_CR         0x00000700
1265 #define      FLD_PATH1_AVC_RMS_CON    0x000000F0
1266 #define      FLD_PATH1_SEL_CTL        0x0000000F
1267
1268 /*****************************************************************************/
1269 #define      PATH1_VOL_CTL            0x8D4
1270 #define      FLD_PATH1_AVC_THRESHOLD  0x7FFF0000
1271 #define      FLD_PATH1_BAL_LEFT       0x00008000
1272 #define      FLD_PATH1_BAL_LEVEL      0x00007F00
1273 #define      FLD_PATH1_VOLUME         0x000000FF
1274
1275 /*****************************************************************************/
1276 #define      PATH1_EQ_CTL             0x8D8
1277 /* Reserved [31:30] */
1278 #define      FLD_PATH1_EQ_TREBLE_VOL  0x3F000000
1279 /* Reserved [23:22] */
1280 #define      FLD_PATH1_EQ_MID_VOL     0x003F0000
1281 /* Reserved [15:14] */
1282 #define      FLD_PATH1_EQ_BASS_VOL    0x00003F00
1283 /* Reserved [7:1] */
1284 #define      FLD_PATH1_EQ_BAND_SEL    0x00000001
1285
1286 /*****************************************************************************/
1287 #define      PATH1_SC_CTL             0x8DC
1288 #define      FLD_PATH1_SC_THRESHOLD   0x7FFF0000
1289 #define      FLD_PATH1_SC_RT          0x0000F000
1290 #define      FLD_PATH1_SC_AT          0x00000F00
1291 #define      FLD_PATH1_SC_STEREO      0x00000080
1292 #define      FLD_PATH1_SC_CR          0x00000070
1293 #define      FLD_PATH1_SC_RMS_CON     0x0000000F
1294
1295 /*****************************************************************************/
1296 #define      PATH2_CTL1               0x8E0
1297 /* Reserved [31:26] */
1298 #define      FLD_PATH2_MUTE_CTL       0x03000000
1299 /* Reserved [23:22] */
1300 #define      FLD_PATH2_AVC_CG         0x00300000
1301 #define      FLD_PATH2_AVC_RT         0x000F0000
1302 #define      FLD_PATH2_AVC_AT         0x0000F000
1303 #define      FLD_PATH2_AVC_STEREO     0x00000800
1304 #define      FLD_PATH2_AVC_CR         0x00000700
1305 #define      FLD_PATH2_AVC_RMS_CON    0x000000F0
1306 #define      FLD_PATH2_SEL_CTL        0x0000000F
1307
1308 /*****************************************************************************/
1309 #define      PATH2_VOL_CTL            0x8E4
1310 #define      FLD_PATH2_AVC_THRESHOLD  0xFFFF0000
1311 #define      FLD_PATH2_BAL_LEFT       0x00008000
1312 #define      FLD_PATH2_BAL_LEVEL      0x00007F00
1313 #define      FLD_PATH2_VOLUME         0x000000FF
1314
1315 /*****************************************************************************/
1316 #define      PATH2_EQ_CTL             0x8E8
1317 /* Reserved [31:30] */
1318 #define      FLD_PATH2_EQ_TREBLE_VOL  0x3F000000
1319 /* Reserved [23:22] */
1320 #define      FLD_PATH2_EQ_MID_VOL     0x003F0000
1321 /* Reserved [15:14] */
1322 #define      FLD_PATH2_EQ_BASS_VOL    0x00003F00
1323 /* Reserved [7:1] */
1324 #define      FLD_PATH2_EQ_BAND_SEL    0x00000001
1325
1326 /*****************************************************************************/
1327 #define      PATH2_SC_CTL             0x8EC
1328 #define      FLD_PATH2_SC_THRESHOLD   0xFFFF0000
1329 #define      FLD_PATH2_SC_RT          0x0000F000
1330 #define      FLD_PATH2_SC_AT          0x00000F00
1331 #define      FLD_PATH2_SC_STEREO      0x00000080
1332 #define      FLD_PATH2_SC_CR          0x00000070
1333 #define      FLD_PATH2_SC_RMS_CON     0x0000000F
1334
1335 /*****************************************************************************/
1336 #define      SRC_CTL                  0x8F0
1337 #define      FLD_SRC_STATUS           0xFFFFFF00
1338 #define      FLD_FIFO_LF_EN           0x000000FC
1339 #define      FLD_BYPASS_LI            0x00000002
1340 #define      FLD_BYPASS_PF            0x00000001
1341
1342 /*****************************************************************************/
1343 #define      SRC_LF_COEF              0x8F4
1344 #define      FLD_LOOP_FILTER_COEF2    0xFFFF0000
1345 #define      FLD_LOOP_FILTER_COEF1    0x0000FFFF
1346
1347 /*****************************************************************************/
1348 #define      SRC1_CTL                 0x8F8
1349 /* Reserved [31:28] */
1350 #define      FLD_SRC1_FIFO_RD_TH      0x0F000000
1351 /* Reserved [23:18] */
1352 #define      FLD_SRC1_PHASE_INC       0x0003FFFF
1353
1354 /*****************************************************************************/
1355 #define      SRC2_CTL                 0x8FC
1356 /* Reserved [31:28] */
1357 #define      FLD_SRC2_FIFO_RD_TH      0x0F000000
1358 /* Reserved [23:18] */
1359 #define      FLD_SRC2_PHASE_INC       0x0003FFFF
1360
1361 /*****************************************************************************/
1362 #define      SRC3_CTL                 0x900
1363 /* Reserved [31:28] */
1364 #define      FLD_SRC3_FIFO_RD_TH      0x0F000000
1365 /* Reserved [23:18] */
1366 #define      FLD_SRC3_PHASE_INC       0x0003FFFF
1367
1368 /*****************************************************************************/
1369 #define      SRC4_CTL                 0x904
1370 /* Reserved [31:28] */
1371 #define      FLD_SRC4_FIFO_RD_TH      0x0F000000
1372 /* Reserved [23:18] */
1373 #define      FLD_SRC4_PHASE_INC       0x0003FFFF
1374
1375 /*****************************************************************************/
1376 #define      SRC5_CTL                 0x908
1377 /* Reserved [31:28] */
1378 #define      FLD_SRC5_FIFO_RD_TH      0x0F000000
1379 /* Reserved [23:18] */
1380 #define      FLD_SRC5_PHASE_INC       0x0003FFFF
1381
1382 /*****************************************************************************/
1383 #define      SRC6_CTL                 0x90C
1384 /* Reserved [31:28] */
1385 #define      FLD_SRC6_FIFO_RD_TH      0x0F000000
1386 /* Reserved [23:18] */
1387 #define      FLD_SRC6_PHASE_INC       0x0003FFFF
1388
1389 /*****************************************************************************/
1390 #define      BAND_OUT_SEL             0x910
1391 #define      FLD_SRC6_IN_SEL          0xC0000000
1392 #define      FLD_SRC6_CLK_SEL         0x30000000
1393 #define      FLD_SRC5_IN_SEL          0x0C000000
1394 #define      FLD_SRC5_CLK_SEL         0x03000000
1395 #define      FLD_SRC4_IN_SEL          0x00C00000
1396 #define      FLD_SRC4_CLK_SEL         0x00300000
1397 #define      FLD_SRC3_IN_SEL          0x000C0000
1398 #define      FLD_SRC3_CLK_SEL         0x00030000
1399 #define      FLD_BASEBAND_BYPASS_CTL  0x0000FF00
1400 #define      FLD_AC97_SRC_SEL         0x000000C0
1401 #define      FLD_I2S_SRC_SEL          0x00000030
1402 #define      FLD_PARALLEL2_SRC_SEL    0x0000000C
1403 #define      FLD_PARALLEL1_SRC_SEL    0x00000003
1404
1405 /*****************************************************************************/
1406 #define      I2S_IN_CTL               0x914
1407 /* Reserved [31:11] */
1408 #define      FLD_I2S_UP2X_BW20K       0x00000400
1409 #define      FLD_I2S_UP2X_BYPASS      0x00000200
1410 #define      FLD_I2S_IN_MASTER_MODE   0x00000100
1411 #define      FLD_I2S_IN_SONY_MODE     0x00000080
1412 #define      FLD_I2S_IN_RIGHT_JUST    0x00000040
1413 #define      FLD_I2S_IN_WS_SEL        0x00000020
1414 #define      FLD_I2S_IN_BCN_DEL       0x0000001F
1415
1416 /*****************************************************************************/
1417 #define      I2S_OUT_CTL              0x918
1418 /* Reserved [31:17] */
1419 #define      FLD_I2S_OUT_SOFT_RESET_EN  0x00010000
1420 /* Reserved [15:9] */
1421 #define      FLD_I2S_OUT_MASTER_MODE  0x00000100
1422 #define      FLD_I2S_OUT_SONY_MODE    0x00000080
1423 #define      FLD_I2S_OUT_RIGHT_JUST   0x00000040
1424 #define      FLD_I2S_OUT_WS_SEL       0x00000020
1425 #define      FLD_I2S_OUT_BCN_DEL      0x0000001F
1426
1427
1428 /*****************************************************************************/
1429 #define      AC97_CTL                 0x91C
1430 /* Reserved [31:26] */
1431 #define      FLD_AC97_UP2X_BW20K      0x02000000
1432 #define      FLD_AC97_UP2X_BYPASS     0x01000000
1433 /* Reserved [23:17] */
1434 #define      FLD_AC97_RST_ACL         0x00010000
1435 /* Reserved [15:9] */
1436 #define      FLD_AC97_WAKE_UP_SYNC    0x00000100
1437 /* Reserved [7:1] */
1438 #define      FLD_AC97_SHUTDOWN        0x00000001
1439
1440
1441 /* Cx231xx redefine */
1442 #define      QPSK_IAGC_CTL1  0x94c
1443 #define      QPSK_IAGC_CTL2  0x950
1444 #define      QPSK_FEPR_FREQ  0x954
1445 #define      QPSK_BTL_CTL1  0x958
1446 #define      QPSK_BTL_CTL2  0x95c
1447 #define      QPSK_CTL_CTL1  0x960
1448 #define      QPSK_CTL_CTL2  0x964
1449 #define      QPSK_MF_FAGC_CTL  0x968
1450 #define      QPSK_EQ_CTL  0x96c
1451 #define      QPSK_LOCK_CTL  0x970
1452
1453
1454 /*****************************************************************************/
1455 #define      FM1_DFT_CTL              0x9A8
1456 #define      FLD_FM1_DFT_THRESHOLD    0xFFFF0000
1457 /* Reserved [15:8] */
1458 #define      FLD_FM1_DFT_CMP_CTL      0x00000080
1459 #define      FLD_FM1_DFT_AVG          0x00000070
1460 /* Reserved [3:1] */
1461 #define      FLD_FM1_DFT_START        0x00000001
1462
1463 /*****************************************************************************/
1464 #define      FM1_DFT_STATUS           0x9AC
1465 #define      FLD_FM1_DFT_DONE         0x80000000
1466 /* Reserved [30:19] */
1467 #define      FLD_FM_DFT_TH_CMP        0x00040000
1468 #define      FLD_FM1_DFT              0x0003FFFF
1469
1470 /*****************************************************************************/
1471 #define      FM2_DFT_CTL              0x9B0
1472 #define      FLD_FM2_DFT_THRESHOLD    0xFFFF0000
1473 /* Reserved [15:8] */
1474 #define      FLD_FM2_DFT_CMP_CTL      0x00000080
1475 #define      FLD_FM2_DFT_AVG          0x00000070
1476 /* Reserved [3:1] */
1477 #define      FLD_FM2_DFT_START        0x00000001
1478
1479 /*****************************************************************************/
1480 #define      FM2_DFT_STATUS           0x9B4
1481 #define      FLD_FM2_DFT_DONE         0x80000000
1482 /* Reserved [30:19] */
1483 #define      FLD_FM2_DFT_TH_CMP_STAT  0x00040000
1484 #define      FLD_FM2_DFT              0x0003FFFF
1485
1486 /*****************************************************************************/
1487 /* Cx231xx redefine */
1488 #define      AAGC_STATUS_REG          0x9B8
1489 #define      AAGC_STATUS              0x9B8
1490 /* Reserved [31:27] */
1491 #define      FLD_FM2_DAGC_OUT         0x07000000
1492 /* Reserved [23:19] */
1493 #define      FLD_FM1_DAGC_OUT         0x00070000
1494 /* Reserved [15:6] */
1495 #define      FLD_AFE_VGA_OUT          0x0000003F
1496
1497
1498
1499 /*****************************************************************************/
1500 #define      MTS_GAIN_STATUS          0x9BC
1501 /* Reserved [31:14] */
1502 #define      FLD_MTS_GAIN             0x00003FFF
1503
1504 #define      RDS_OUT                  0x9C0
1505 #define      FLD_RDS_Q                0xFFFF0000
1506 #define      FLD_RDS_I                0x0000FFFF
1507
1508 /*****************************************************************************/
1509 #define      AUTOCONFIG_REG           0x9C4
1510 /* Reserved [31:4] */
1511 #define      FLD_AUTOCONFIG_MODE      0x0000000F
1512
1513 #define      FM_AFC                   0x9C8
1514 #define      FLD_FM2_AFC              0xFFFF0000
1515 #define      FLD_FM1_AFC              0x0000FFFF
1516
1517 /*****************************************************************************/
1518 /* Cx231xx redefine */
1519 #define      NEW_SPARE                0x9CC
1520 #define      NEW_SPARE_REG            0x9CC
1521
1522 /*****************************************************************************/
1523 #define      DBX_ADJ                  0x9D0
1524 /* Reserved [31:28] */
1525 #define      FLD_DBX2_ADJ             0x0FFF0000
1526 /* Reserved [15:12] */
1527 #define      FLD_DBX1_ADJ             0x00000FFF
1528
1529 #define      VID_FMT_AUTO              0
1530 #define      VID_FMT_NTSC_M            1
1531 #define      VID_FMT_NTSC_J            2
1532 #define      VID_FMT_NTSC_443          3
1533 #define      VID_FMT_PAL_BDGHI         4
1534 #define      VID_FMT_PAL_M             5
1535 #define      VID_FMT_PAL_N             6
1536 #define      VID_FMT_PAL_NC            7
1537 #define      VID_FMT_PAL_60            8
1538 #define      VID_FMT_SECAM             12
1539 #define      VID_FMT_SECAM_60          13
1540
1541 #define      INPUT_MODE_CVBS_0         0   /* INPUT_MODE_VALUE(0) */
1542 #define      INPUT_MODE_YC_1           1   /* INPUT_MODE_VALUE(1) */
1543 #define      INPUT_MODE_YC2_2          2   /* INPUT_MODE_VALUE(2) */
1544 #define      INPUT_MODE_YUV_3          3   /* INPUT_MODE_VALUE(3) */
1545
1546
1547 #define      LUMA_LPF_LOW_BANDPASS     0   /* 0.6Mhz lowpass filter bandwidth */
1548 #define      LUMA_LPF_MEDIUM_BANDPASS  1   /* 1.0Mhz lowpass filter bandwidth */
1549 #define      LUMA_LPF_HIGH_BANDPASS    2   /* 1.5Mhz lowpass filter bandwidth */
1550
1551 #define      UV_LPF_LOW_BANDPASS       0   /* 0.6Mhz lowpass filter bandwidth */
1552 #define      UV_LPF_MEDIUM_BANDPASS    1   /* 1.0Mhz lowpass filter bandwidth */
1553 #define      UV_LPF_HIGH_BANDPASS      2   /* 1.5Mhz lowpass filter bandwidth */
1554
1555 #define      TWO_TAP_FILT              0
1556 #define      THREE_TAP_FILT            1
1557 #define      FOUR_TAP_FILT             2
1558 #define      FIVE_TAP_FILT             3
1559
1560 #define      AUD_CHAN_SRC_PARALLEL     0
1561 #define      AUD_CHAN_SRC_I2S_INPUT    1
1562 #define      AUD_CHAN_SRC_FLATIRON     2
1563 #define      AUD_CHAN_SRC_PARALLEL3    3
1564
1565 #define      OUT_MODE_601              0
1566 #define      OUT_MODE_656              1
1567 #define      OUT_MODE_VIP11            2
1568 #define      OUT_MODE_VIP20            3
1569
1570 #define      PHASE_INC_49MHZ          0x0DF22
1571 #define      PHASE_INC_56MHZ          0x0FA5B
1572 #define      PHASE_INC_28MHZ          0x010000
1573
1574 #endif