drivers/media/video/cx231xx/cx231xx-avcore.c

   1 /*
   2    cx231xx_avcore.c - driver for Conexant Cx23100/101/102 USB video capture devices
   3
   4    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   5
   6    This program contains the specific code to control the avdecoder chip and
   7    other related usb control functions for cx231xx based chipset.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/bitmap.h>
  29 #include <linux/usb.h>
  30 #include <linux/i2c.h>
  31 #include <linux/version.h>
  32 #include <linux/mm.h>
  33 #include <linux/mutex.h>
  34
  35 #include <media/v4l2-common.h>
  36 #include <media/v4l2-ioctl.h>
  37 #include <media/v4l2-chip-ident.h>
  38
  39 #include "cx231xx.h"
  40
  41
  42 /*************************************************************************************
  43  *            C O L I B R I - B L O C K    C O N T R O L   functions                 *
  44  *************************************************************************************/
  45 int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
  46 {
  47     int status = 0;
  48     u8 temp = 0;
  49     u32 colibri_power_status = 0;
  50     int i = 0;
  51
  52     /* super block initialize */
  53     temp = (u8)(ref_count & 0xff);
  54     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, temp, 1);
  55
  56     status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, &colibri_power_status, 1);
  57
  58     temp = (u8)((ref_count & 0x300) >> 8);
  59     temp |= 0x40;
  60     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, 2, temp, 1);
  61     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2, 0x0f, 1);
  62
  63     /* enable pll     */
  64     while(colibri_power_status != 0x18)
  65     {
  66         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, 0x18, 1);
  67         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1);
  68         colibri_power_status &= 0xff;
  69         if(status < 0) {
  70             cx231xx_info(": Init Super Block failed in sending/receiving cmds\n");
  71             break;
  72         }
  73         i++;
  74         if( i == 10) {
  75             cx231xx_info(": Init Super Block force break in loop !!!!\n");
  76             status = -1;
  77             break;
  78         }
  79     }
  80
  81     if(status < 0 )
  82         return status;
  83
  84     /* start tuning filter */
  85     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x40, 1);
  86     msleep(5);
  87
  88     /* exit tuning */
  89     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x00, 1);
  90
  91     return status;
  92 }
  93
  94 int cx231xx_colibri_init_channels(struct cx231xx *dev)
  95 {
  96     int status = 0;
  97
  98     /* power up all 3 channels, clear pd_buffer */
  99     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1);
 100     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
 101     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
 102
 103     /* Enable quantizer calibration */
 104     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_COM_QUANT, 2, 0x02, 1);
 105
 106     /* channel initialize, force modulator (fb) reset */
 107     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x17, 1);
 108     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x17, 1);
 109     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x17, 1);
 110
 111     /* start quantilizer calibration  */
 112     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH1, 2, 0x10, 1);
 113     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH2, 2, 0x10, 1);
 114     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH3, 2, 0x10, 1);
 115     msleep(5);
 116
 117     /* exit modulator (fb) reset */
 118     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x07, 1);
 119     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x07, 1);
 120     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x07, 1);
 121
 122     /* enable the pre_clamp in each channel for single-ended input */
 123     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1);
 124     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1);
 125     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1);
 126
 127     /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
 128     status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
 129     status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
 130     status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
 131
 132     /* dynamic element matching off */
 133     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH1, 2, 0x03, 1);
 134     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH2, 2, 0x03, 1);
 135     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH3, 2, 0x03, 1);
 136
 137     return status;
 138 }
 139
 140 int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev)
 141 {
 142     u32 c_value = 0;
 143     int status = 0;
 144
 145     status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1);
 146     c_value &= (~(0x50));
 147     status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, c_value, 1);
 148
 149     return status;
 150 }
 151
 152 /*
 153         we have 3 channel
 154         channel 1 ----- pin 1  to pin4(in reg is 1-4)
 155         channel 2 ----- pin 5  to pin8(in reg is 5-8)
 156         channel 3 ----- pin 9 to pin 12(in reg is 9-11)
 157 */
 158 int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux)
 159 {
 160     u8 ch1_setting = (u8)input_mux;
 161     u8 ch2_setting = (u8)(input_mux >> 8);
 162     u8 ch3_setting = (u8)(input_mux >> 16);
 163     int status = 0;
 164     u32 value = 0;
 165
 166     if(ch1_setting != 0)
 167     {
 168         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, &value, 1);
 169         value &= (!INPUT_SEL_MASK);
 170         value |= (ch1_setting-1)<<4;
 171         value &= 0xff;
 172         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, value, 1);
 173     }
 174
 175     if(ch2_setting != 0)
 176     {
 177         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH2, 2, &value, 1);
 178         value &= (!INPUT_SEL_MASK);
 179         value |= (ch2_setting-1)<<4;
 180         value &= 0xff;
 181         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH2, 2, value, 1);
 182     }
 183
 184     /* For ch3_setting, the value to put in the register is 7 less than the input number */
 185     if(ch3_setting != 0)
 186     {
 187         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &value, 1);
 188         value &= (!INPUT_SEL_MASK);
 189         value |= (ch3_setting-1)<<4;
 190         value &= 0xff;
 191         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, value, 1);
 192     }
 193
 194     return status;
 195 }
 196
 197 int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
 198 {
 199     int status = 0;
 200
 201     switch(mode) {
 202         case AFE_MODE_LOW_IF:
 203             /* SetupAFEforLowIF();  */
 204             break;
 205         case AFE_MODE_BASEBAND:
 206             status = cx231xx_colibri_setup_AFE_for_baseband(dev);
 207             break;
 208         case AFE_MODE_EU_HI_IF:
 209             /* SetupAFEforEuHiIF(); */
 210             break;
 211         case AFE_MODE_US_HI_IF:
 212             /* SetupAFEforUsHiIF(); */
 213             break;
 214         case AFE_MODE_JAPAN_HI_IF:
 215             /* SetupAFEforJapanHiIF(); */
 216             break;
 217     }
 218
 219     if((mode != dev->colibri_mode) && (dev->video_input == CX231XX_VMUX_TELEVISION)) {
 220         status = cx231xx_colibri_adjust_ref_count(dev, CX231XX_VMUX_TELEVISION);
 221     }
 222
 223     dev->colibri_mode  = mode;
 224
 225     return status;
 226 }
 227
 228 /* For power saving in the EVK */
 229 int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
 230 {
 231    u32 colibri_power_status = 0;
 232    int status = 0;
 233
 234    switch (dev->model) {
 235        case CX231XX_BOARD_CNXT_RDE_250:
 236        case CX231XX_BOARD_CNXT_RDU_250:
 237
 238                if(avmode==POLARIS_AVMODE_ANALOGT_TV)
 239                {
 240                        while(colibri_power_status != 0x18) {
 241                    status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 242                                      SUP_BLK_PWRDN, 2, 0x18, 1);
 243                    status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 244                                      SUP_BLK_PWRDN, 2, &colibri_power_status, 1);
 245                    if(status < 0 )
 246                        break;
 247                        }
 248
 249                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 250                                      ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1);
 251                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 252                                      ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
 253                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 254                                      ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
 255                }
 256            else if(avmode==POLARIS_AVMODE_DIGITAL)  {
 257                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 258                                      ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1);
 259                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 260                                      ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1);
 261                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 262                                      ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1);
 263
 264                status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 265                                      SUP_BLK_PWRDN, 2, &colibri_power_status, 1);
 266                        colibri_power_status |=0x07;
 267                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 268                                      SUP_BLK_PWRDN, 2, colibri_power_status, 1);
 269                }
 270                else if(avmode==POLARIS_AVMODE_ENXTERNAL_AV)  {
 271
 272                        while(colibri_power_status != 0x18) {
 273                                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 274                                      SUP_BLK_PWRDN, 2, 0x18, 1);
 275                    status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 276                                      SUP_BLK_PWRDN, 2, &colibri_power_status, 1);
 277                    if(status < 0 )
 278                        break;
 279                        }
 280
 281                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 282                                      ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1);
 283                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 284                                      ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
 285                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 286                                      ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
 287                }
 288                else {
 289                        cx231xx_info("Invalid AV mode input\n");
 290                status = -1;
 291                }
 292                break;
 293        default:
 294                if(avmode==POLARIS_AVMODE_ANALOGT_TV)
 295                {
 296                        while(colibri_power_status != 0x18)  {
 297                                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 298                                      SUP_BLK_PWRDN, 2, 0x18, 1);
 299                    status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 300                                      SUP_BLK_PWRDN, 2, &colibri_power_status, 1);
 301                    if(status < 0 )
 302                        break;
 303                        }
 304
 305                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 306                                      ADC_PWRDN_CLAMP_CH1, 2, 0x40, 1);
 307                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 308                                      ADC_PWRDN_CLAMP_CH2, 2, 0x40, 1);
 309                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 310                                      ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
 311            }
 312            else if(avmode==POLARIS_AVMODE_DIGITAL)  {
 313                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 314                                      ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1);
 315                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 316                                      ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1);
 317                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 318                                      ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1);
 319
 320                status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 321                                      SUP_BLK_PWRDN, 2, &colibri_power_status, 1);
 322                colibri_power_status |=0x07;
 323                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 324                                      SUP_BLK_PWRDN, 2, colibri_power_status, 1);
 325            }
 326            else if(avmode==POLARIS_AVMODE_ENXTERNAL_AV) {
 327                while(colibri_power_status != 0x18)  {
 328                                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 329                                      SUP_BLK_PWRDN, 2, 0x18, 1);
 330                    status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 331                                      SUP_BLK_PWRDN, 2, &colibri_power_status, 1);
 332                    if(status < 0 )
 333                        break;
 334                        }
 335
 336                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 337                                      ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1);
 338                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 339                                      ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
 340                status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 341                                      ADC_PWRDN_CLAMP_CH3, 2, 0x40, 1);
 342            }
 343            else  {
 344                 cx231xx_info("Invalid AV mode input\n");
 345                 status = -1;
 346            }
 347     } /* switch  */
 348
 349     return status;
 350 }
 351
 352 int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
 353 {
 354     u32 input_mode = 0;
 355     u32 ntf_mode = 0;
 356     int status = 0;
 357
 358     dev->video_input = video_input;
 359
 360     if(video_input == CX231XX_VMUX_TELEVISION) {
 361         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &input_mode, 1);
 362         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 363                             ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode, 1);
 364     }
 365     else {
 366         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, &input_mode, 1);
 367         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 368                             ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode, 1);
 369     }
 370
 371     input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
 372
 373     switch(input_mode)
 374     {
 375     case SINGLE_ENDED:
 376         dev->colibri_ref_count = 0x23C;
 377         break;
 378     case LOW_IF:
 379         dev->colibri_ref_count = 0x24C;
 380         break;
 381     case EU_IF:
 382         dev->colibri_ref_count = 0x258;
 383         break;
 384     case US_IF:
 385         dev->colibri_ref_count = 0x260;
 386         break;
 387     default:
 388         break;
 389     }
 390
 391     status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count);
 392
 393     return status;
 394 }
 395
 396
 397
 398 /*************************************************************************************
 399  *       V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions         *
 400  *************************************************************************************/
 401 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
 402 {
 403     int status = 0;
 404
 405     switch(INPUT(input)->type) {
 406         case CX231XX_VMUX_COMPOSITE1:
 407         case CX231XX_VMUX_SVIDEO:
 408             if((dev->current_pcb_config.type == USB_BUS_POWER) &&
 409                         (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
 410                 status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV); /* External AV */
 411                 if (status < 0) {
 412                     cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
 413                                     __func__, status);
 414                             return status;
 415                     }
 416             }
 417             status = cx231xx_set_decoder_video_input(dev, INPUT(input)->type, INPUT(input)->vmux);
 418             break;
 419         case CX231XX_VMUX_TELEVISION:
 420         case CX231XX_VMUX_CABLE:
 421             if((dev->current_pcb_config.type == USB_BUS_POWER) &&
 422                         (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
 423                 status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); /* Tuner */
 424                 if (status < 0) {
 425                     cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n",
 426                                     __func__, status);
 427                             return status;
 428                     }
 429             }
 430             status = cx231xx_set_decoder_video_input(dev, CX231XX_VMUX_COMPOSITE1, INPUT(input)->vmux);
 431             break;
 432         default:
 433             cx231xx_errdev("%s: cx231xx_set_power_mode : Unknown Input %d !\n",
 434                                     __func__, INPUT(input)->type);
 435             break;
 436     }
 437
 438     /* save the selection */
 439     dev->video_input = input;
 440
 441     return status;
 442 }
 443
 444 int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input)
 445 {
 446     int status = 0;
 447     u32 value = 0;
 448
 449     if(pin_type != dev->video_input) {
 450         status = cx231xx_colibri_adjust_ref_count(dev, pin_type);
 451         if(status < 0 ) {
 452             cx231xx_errdev("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n",
 453                                         __func__, status);
 454             return status;
 455         }
 456     }
 457
 458     /* call colibri block to set video inputs */
 459     status = cx231xx_colibri_set_input_mux(dev, input);
 460     if(status < 0 ) {
 461         cx231xx_errdev("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n",
 462                                     __func__, status);
 463         return status;
 464     }
 465
 466     switch(pin_type) {
 467         case CX231XX_VMUX_COMPOSITE1:
 468             {
 469                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4);
 470                 value |= (0<<13)|(1<<4);
 471                 value  &= ~(1<<5);
 472
 473                 value &= (~(0x1FF8000));        /* set [24:23] [22:15] to 0  */
 474                 value |= 0x1000000;             /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
 475                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4);
 476
 477                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4);
 478                 value |= (1<<7);
 479                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4);
 480
 481                 /* Set vip 1.1 output mode */
 482                 status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 483                                        OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11);
 484
 485                 /* Tell DIF object to go to baseband mode  */
 486                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 487                 if (status < 0) {
 488                             cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
 489                                     __func__, status);
 490                             return status;
 491                     }
 492
 493                 /* Read the DFE_CTRL1 register */
 494                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4);
 495
 496                 /* enable the VBI_GATE_EN */
 497                 value |= FLD_VBI_GATE_EN;
 498
 499                 /* Enable the auto-VGA enable */
 500                 value |= FLD_VGA_AUTO_EN;
 501
 502                 /* Write it back */
 503                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4);
 504
 505                 /* Disable auto config of registers */
 506                 status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 507                                        MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1));
 508
 509                 /* Set CVBS input mode */
 510                 status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 511                                        MODE_CTRL, FLD_INPUT_MODE,
 512                                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 513             }
 514             break;
 515         case CX231XX_VMUX_SVIDEO:
 516             {
 517                 /* Disable the use of  DIF */
 518
 519                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4);
 520
 521                 value &= (~(0x1FF8000));    /* set [24:23] [22:15] to 0 */
 522                 value |= 0x1000010;         /* set FUNC_MODE[24:23] = 2
 523                                                IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
 524                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4);
 525
 526                 /* Tell DIF object to go to baseband mode */
 527                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 528                 if (status < 0) {
 529                             cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
 530                                     __func__, status);
 531                             return status;
 532                     }
 533
 534                 /* Read the DFE_CTRL1 register */
 535                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4);
 536
 537                 /* enable the VBI_GATE_EN */
 538                 value |= FLD_VBI_GATE_EN;
 539
 540                 /* Enable the auto-VGA enable */
 541                 value |= FLD_VGA_AUTO_EN;
 542
 543                 /* Write it back */
 544                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4);
 545
 546                 /* Disable auto config of registers  */
 547                 status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 548                                        MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1));
 549
 550                 /* Set YC input mode */
 551                 status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 552                                        MODE_CTRL, FLD_INPUT_MODE,
 553                                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
 554
 555                 /* Chroma to ADC2 */
 556                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4);
 557                 value |= FLD_CHROMA_IN_SEL;         /* set the chroma in select */
 558
 559                 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)  This sets them to use video
 560                    rather than audio.  Only one of the two will be in use. */
 561                 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
 562
 563                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4);
 564
 565                 status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND);
 566             }
 567             break;
 568         case CX231XX_VMUX_TELEVISION:
 569         case CX231XX_VMUX_CABLE:
 570         default:
 571             {
 572                 switch(dev->model)  {
 573                         case CX231XX_BOARD_CNXT_RDE_250:
 574                         case CX231XX_BOARD_CNXT_RDU_250:
 575                                 {
 576                                         /* Disable the use of  DIF   */
 577
 578                         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4);
 579                                         value |= (0<<13)|(1<<4);
 580                                         value  &= ~(1<<5);
 581
 582                                         value &= (~(0x1FF8000));    /* set [24:23] [22:15] to 0 */
 583                                         value |= 0x1000000;         /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
 584                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4);
 585
 586                         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4);
 587                                         value |= (1<<7);
 588                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4);
 589
 590                                         /* Set vip 1.1 output mode */
 591                         status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 592                                        OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11);
 593
 594                         /* Tell DIF object to go to baseband mode */
 595                         status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 596                         if (status < 0) {
 597                                     cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
 598                                             __func__, status);
 599                                     return status;
 600                             }
 601
 602                                         /* Read the DFE_CTRL1 register */
 603                         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4);
 604
 605                                         /* enable the VBI_GATE_EN */
 606                                         value |= FLD_VBI_GATE_EN;
 607
 608                                         /* Enable the auto-VGA enable */
 609                                         value |= FLD_VGA_AUTO_EN;
 610
 611                                         /* Write it back */
 612                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4);
 613
 614                                         /* Disable auto config of registers */
 615                         status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 616                                        MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1));
 617
 618                         /* Set CVBS input mode */
 619                         status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 620                                        MODE_CTRL, FLD_INPUT_MODE,
 621                                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 622                                 }
 623                                 break;
 624                         default:
 625                                 {
 626                                         /* Enable the DIF for the tuner */
 627
 628                                         /* Reinitialize the DIF */
 629                         status = cx231xx_dif_set_standard(dev, dev->norm);
 630                         if (status < 0) {
 631                                     cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
 632                                             __func__, status);
 633                                     return status;
 634                             }
 635
 636                                         /* Make sure bypass is cleared */
 637                         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, &value, 4);
 638
 639                                         /* Clear the bypass bit */
 640                                         value &= ~FLD_DIF_DIF_BYPASS;
 641
 642                                         /* Enable the use of the DIF block */
 643                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, value, 4);
 644
 645                                         /* Read the DFE_CTRL1 register */
 646                         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4);
 647
 648                                         /* Disable the VBI_GATE_EN */
 649                                         value &= ~FLD_VBI_GATE_EN;
 650
 651                                         /* Enable the auto-VGA enable, AGC, and set the skip count to 2 */
 652                                         value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
 653
 654                                         /* Write it back */
 655                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4);
 656
 657                                         /* Wait 15 ms */
 658                                         msleep(1);
 659
 660                                         /* Disable the auto-VGA enable AGC */
 661                                         value &= ~(FLD_VGA_AUTO_EN);
 662
 663                                         /* Write it back */
 664                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4);
 665
 666                                         /* Enable Polaris B0 AGC output */
 667                         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, &value, 4);
 668                                         value |=(FLD_OEF_AGC_RF)|(FLD_OEF_AGC_IFVGA)|(FLD_OEF_AGC_IF);
 669                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, value, 4);
 670
 671                                         /* Set vip 1.1 output mode */
 672                         status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 673                                        OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11);
 674
 675                                         /* Disable auto config of registers */
 676                         status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 677                                        MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1));
 678
 679                                         /* Set CVBS input mode */
 680                         status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 681                                        MODE_CTRL, FLD_INPUT_MODE,
 682                                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 683
 684                                         /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */
 685                                         /* Clear clamp for channels 2 and 3      (bit 16-17) */
 686                                         /* Clear droop comp                      (bit 19-20) */
 687                                         /* Set VGA_SEL (for audio control)       (bit 7-8) */
 688                         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4);
 689
 690                                         value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
 691
 692                         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4);
 693                                 }
 694                                 break;
 695
 696                         }
 697             }
 698             break;
 699     }
 700
 701     /* Set raw VBI mode */
 702     status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 703                                        OUT_CTRL1, FLD_VBIHACTRAW_EN,
 704                                        cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
 705
 706     status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4);
 707     if(value & 0x02) {
 708         value |=(1<<19);
 709         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4);
 710     }
 711
 712     return status;
 713 }
 714
 715 /*
 716  * Handle any video-mode specific overrides that are different on a per video standards
 717  * basis after touching the MODE_CTRL register which resets many values for autodetect
 718  */
 719 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
 720 {
 721     int status = 0;
 722
 723     cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", (unsigned int)dev->norm);
 724
 725     /* Change the DFE_CTRL3 bp_percent to fix flagging */
 726     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL3, 2, 0xCD3F0280, 4);
 727
 728     if( dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M) ) {
 729         cx231xx_info("do_mode_ctrl_overrides NTSC\n");
 730
 731             /* Move the close caption lines out of active video, adjust the active video start point */
 732             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 733                                        VERT_TIM_CTRL, FLD_VBLANK_CNT,0x18);
 734             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 735                                        VERT_TIM_CTRL, FLD_VACTIVE_CNT,0x1E6000);
 736             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 737                                        VERT_TIM_CTRL, FLD_V656BLANK_CNT,0x1E000000);
 738
 739             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 740                                        HORIZ_TIM_CTRL, FLD_HBLANK_CNT,
 741                                        cx231xx_set_field(FLD_HBLANK_CNT, 0x79));
 742     } else if ( dev->norm & ( V4L2_STD_PAL_B | V4L2_STD_PAL_G | V4L2_STD_PAL_D |
 743         V4L2_STD_PAL_I | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) ) {
 744             cx231xx_info("do_mode_ctrl_overrides PAL\n");
 745             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 746                                        VERT_TIM_CTRL, FLD_VBLANK_CNT,0x24);
 747             /* Adjust the active video horizontal start point */
 748             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 749                                        HORIZ_TIM_CTRL, FLD_HBLANK_CNT,
 750                                        cx231xx_set_field(FLD_HBLANK_CNT, 0x85));
 751     } else if (dev->norm & ( V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
 752                             V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L |
 753                             V4L2_STD_SECAM_LC) ) {
 754             cx231xx_info("do_mode_ctrl_overrides SECAM\n");
 755             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 756                                        VERT_TIM_CTRL, FLD_VBLANK_CNT,0x24);
 757             /* Adjust the active video horizontal start point */
 758             status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 759                                        HORIZ_TIM_CTRL, FLD_HBLANK_CNT,
 760                                        cx231xx_set_field(FLD_HBLANK_CNT, 0x85));
 761     }
 762
 763     return status;
 764 }
 765
 766 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
 767 {
 768     int status = 0;
 769     enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
 770
 771     switch(INPUT(input)->amux) {
 772         case CX231XX_AMUX_VIDEO:
 773             ainput = AUDIO_INPUT_TUNER_TV;
 774             break;
 775         case CX231XX_AMUX_LINE_IN:
 776             status = cx231xx_flatiron_set_audio_input(dev, input);
 777             ainput = AUDIO_INPUT_LINE;
 778             break;
 779         default:
 780             break;
 781     }
 782
 783     status = cx231xx_set_audio_decoder_input(dev, ainput);
 784
 785     return status;
 786 }
 787
 788 int cx231xx_set_audio_decoder_input(struct cx231xx *dev, enum AUDIO_INPUT audio_input)
 789 {
 790     u32 dwval;
 791     int status;
 792     u32 gen_ctrl;
 793     u32 value = 0;
 794
 795     /* Put it in soft reset   */
 796     status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, &gen_ctrl, 1);
 797     gen_ctrl |= 1;
 798     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, gen_ctrl, 1);
 799
 800     switch(audio_input)
 801     {
 802     case AUDIO_INPUT_LINE:
 803
 804         /* setup AUD_IO control from Merlin paralle output */
 805         value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL);
 806         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AUD_IO_CTRL, 2, value, 4);
 807
 808         /* setup input to Merlin, SRC2 connect to AC97
 809            bypass upsample-by-2, slave mode, sony mode, left justify
 810            adr 091c, dat 01000000 */
 811         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 2, &dwval, 4);
 812
 813         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 2, (dwval | FLD_AC97_UP2X_BYPASS), 4);
 814
 815         /* select the parallel1 and SRC3 */
 816         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, BAND_OUT_SEL, 2,
 817                      cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0)|
 818                      cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0)|
 819                      cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0), 4);
 820
 821         /* unmute all, AC97 in, independence mode
 822           adr 08d0, data 0x00063073 */
 823         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063073, 4);
 824
 825         /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
 826         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2, &dwval, 4);
 827         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2,
 828                             (dwval | FLD_PATH1_AVC_THRESHOLD), 4);
 829
 830         /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
 831         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2, &dwval, 4);
 832         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2,
 833                             (dwval | FLD_PATH1_SC_THRESHOLD), 4);
 834         break;
 835
 836     case AUDIO_INPUT_TUNER_TV:
 837     default:
 838
 839          /* Setup SRC sources and clocks */
 840          status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, BAND_OUT_SEL, 2,
 841                 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)|
 842                 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)|
 843                 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)|
 844                 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)|
 845                 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)|
 846                 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)|
 847                 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)|
 848                 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)|
 849                 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00)|
 850                 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)|
 851                 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)|
 852                 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)|
 853                 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01) , 4);
 854
 855          /* Setup the AUD_IO control */
 856          status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AUD_IO_CTRL, 2,
 857                 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)|
 858                 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)|
 859                 cx231xx_set_field(FLD_AUD_CHAN3_SRC,0x00)|
 860                 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00)|
 861                 cx231xx_set_field(FLD_AUD_CHAN1_SRC,0x03 ), 4);
 862
 863          status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F063870, 4);
 864
 865          /* setAudioStandard(_audio_standard); */
 866
 867          status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063870, 4);
 868              switch(dev->model)
 869              {
 870                  case CX231XX_BOARD_CNXT_RDE_250:
 871                  case CX231XX_BOARD_CNXT_RDU_250:
 872                  status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS,
 873                                                CHIP_CTRL, FLD_SIF_EN,
 874                                                cx231xx_set_field(FLD_SIF_EN, 1));
 875                         break;
 876                  default:
 877                 break;
 878              }
 879          break;
 880
 881     case AUDIO_INPUT_TUNER_FM:
 882         /*  use SIF for FM radio
 883         setupFM();
 884         setAudioStandard(_audio_standard);
 885         */
 886         break;
 887
 888     case AUDIO_INPUT_MUTE:
 889         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F011012, 4);
 890         break;
 891     }
 892
 893     /* Take it out of soft reset */
 894     status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, &gen_ctrl, 1);
 895     gen_ctrl &= ~1;
 896     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, gen_ctrl, 1);
 897
 898     return status;
 899 }
 900
 901
 902
 903 /* Set resolution of the video */
 904 int cx231xx_resolution_set(struct cx231xx *dev)
 905 {
 906         int width, height;
 907     u32 hscale, vscale;
 908     int status = 0;
 909
 910         width = dev->width;
 911         height = dev->height;
 912
 913     get_scale(dev,width, height,&hscale, &vscale);
 914
 915     /* set horzontal scale */
 916     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, HSCALE_CTRL, 2, hscale, 4);
 917
 918     /* set vertical scale */
 919     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, VSCALE_CTRL, 2, vscale, 4);
 920
 921     return status;
 922 }
 923
 924 /*************************************************************************************
 925  *                        C H I P Specific  C O N T R O L   functions                *
 926  *************************************************************************************/
 927 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
 928 {
 929     u32 value;
 930     int status = 0;
 931
 932     status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, &value, 4);
 933     value |=(~dev->board.ctl_pin_status_mask);
 934     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, value, 4);
 935
 936     return status;
 937 }
 938
 939 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, u8 analog_or_digital)
 940 {
 941     int status = 0;
 942
 943     /* first set the direction to output */
 944     status = cx231xx_set_gpio_direction(dev, dev->board.agc_analog_digital_select_gpio, 1);
 945
 946     /* 0 - demod ; 1 - Analog mode */
 947     status = cx231xx_set_gpio_value(dev, dev->board.agc_analog_digital_select_gpio,
 948                                     analog_or_digital);
 949
 950     return status;
 951 }
 952
 953 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
 954 {
 955     u8 value[4] ={0,0,0,0};
 956     int status = 0;
 957
 958     cx231xx_info("Changing the i2c port for tuner to %d\n",I2CIndex);
 959
 960     status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
 961     if(status < 0)
 962         return status;
 963
 964     if(I2CIndex==I2C_1) {
 965         if(value[0] & I2C_DEMOD_EN) {
 966             value[0] &= ~I2C_DEMOD_EN;
 967             status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
 968         }
 969     } else  {
 970         if(!(value[0] & I2C_DEMOD_EN)) {
 971             value[0] |= I2C_DEMOD_EN;
 972             status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
 973         }
 974     }
 975
 976     return status;
 977
 978 }
 979
 980
 981 /*************************************************************************************
 982  *                     D I F - B L O C K    C O N T R O L   functions                *
 983  *************************************************************************************/
 984 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
 985                                           u32 function_mode, u32 standard)
 986 {
 987     int status = 0;
 988
 989     if(mode == V4L2_TUNER_RADIO) {
 990         /* C2HH */
 991         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
 992                             AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);           /* lo if big signal */
 993         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
 994                             AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */
 995         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
 996                             AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);          /* IF_MODE */
 997         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
 998                             AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);             /* no inv */
 999     }
1000     else {
1001         switch(standard) {
1002             case V4L2_STD_NTSC_M:                                           /* 75 IRE Setup */
1003             case V4L2_STD_NTSC_M_JP:                                        /* Japan,  0 IRE Setup */
1004             case V4L2_STD_PAL_M:
1005             case V4L2_STD_PAL_N:
1006             case V4L2_STD_PAL_Nc:
1007                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1008                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);           /* lo if big signal */
1009                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1010                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */
1011                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1012                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);           /* IF_MODE */
1013                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1014                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);             /* no inv */
1015                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1016                                 AUD_IO_CTRL, 0, 31, 0x00000003);                /* 0x124, AUD_CHAN1_SRC = 0x3 */
1017             break;
1018
1019             case V4L2_STD_PAL_B:
1020             case V4L2_STD_PAL_G:
1021                  /* C2HH setup */
1022                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1023                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);           /* lo if big signal */
1024                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1025                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */
1026                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1027                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);           /* IF_MODE */
1028                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1029                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);             /* no inv */
1030                  break;
1031
1032             case V4L2_STD_PAL_D:
1033             case V4L2_STD_PAL_I:
1034             case V4L2_STD_SECAM_L:
1035             case V4L2_STD_SECAM_LC:
1036             case V4L2_STD_SECAM_B:
1037             case V4L2_STD_SECAM_D:
1038             case V4L2_STD_SECAM_G:
1039             case V4L2_STD_SECAM_K:
1040             case V4L2_STD_SECAM_K1:
1041                  /* C2HH setup */
1042                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1043                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);           /* lo if big signal */
1044                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1045                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */
1046                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1047                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);           /* IF_MODE */
1048                  status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1049                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);             /* no inv */
1050                              break;
1051
1052             case DIF_USE_BASEBAND:
1053             default:
1054                 /* do nothing to config C2HH for baseband */
1055                 break;
1056         }
1057     }
1058
1059     return status;
1060 }
1061
1062 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1063 {
1064     int status = 0;
1065     u32 dif_misc_ctrl_value = 0;
1066     u32 func_mode = 0;
1067
1068     cx231xx_info("%s: setStandard to %x\n",__func__,standard);
1069
1070     status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1071                                      DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, 4);
1072     if(standard != DIF_USE_BASEBAND )
1073         dev->norm = standard;
1074
1075     switch (dev->model) {
1076        case CX231XX_BOARD_CNXT_RDE_250:
1077        case CX231XX_BOARD_CNXT_RDU_250:
1078             func_mode=0x03;
1079             break;
1080         default:
1081             func_mode=0x01;
1082     }
1083
1084     status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, func_mode, standard);
1085
1086
1087     if(standard == DIF_USE_BASEBAND ) {  /* base band */
1088
1089         /* There is a different SRC_PHASE_INC value for baseband vs. DIF */
1090         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1091                                  DIF_SRC_PHASE_INC, 2, 0xDF7DF83, 4);
1092         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1093                                  DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, 4);
1094         dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1095         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1096                                  DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4);
1097
1098     } else if ( standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G) ) {
1099
1100         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL, 0, 31,  0x6503bc0c);
1101         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL1, 0, 31,  0xbd038c85);
1102         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL2, 0, 31,  0x1db4640a);
1103         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL3, 0, 31,  0x00008800);
1104         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1105         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1106         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1107         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1108         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_INT_CURRENT, 0, 31,  0x26001700);
1109         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_RF_CURRENT, 0, 31,  0x00002660);
1110         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VIDEO_AGC_CTRL, 0, 31,  0x72500800);
1111         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VID_AUD_OVERRIDE, 0, 31,  0x27000100);
1112         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AV_SEP_CTRL, 0, 31,  0x3F3530EC);
1113         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_COMP_FLT_CTRL, 0, 31,  0x00A653A8);
1114         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_PHASE_INC, 0, 31,  0x1befbf06);
1115         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_GAIN_CONTROL, 0, 31,  0x000035e8);
1116         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_RPT_VARIANCE, 0, 31,  0x00000000);
1117         /* Save the Spec Inversion value */
1118         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1119         dif_misc_ctrl_value |=0x3a013F11;
1120
1121     } else if( standard & V4L2_STD_PAL_D ) {
1122
1123         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL, 0, 31,  0x6503bc0c);
1124         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL1, 0, 31,  0xbd038c85);
1125         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL2, 0, 31,  0x1db4640a);
1126         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL3, 0, 31,  0x00008800);
1127         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1128         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1129         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1130         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1131         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_INT_CURRENT, 0, 31,  0x26001700);
1132         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_RF_CURRENT, 0, 31,  0x00002660);
1133         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VIDEO_AGC_CTRL, 0, 31,  0x72500800);
1134         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VID_AUD_OVERRIDE, 0, 31,  0x27000100);
1135         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AV_SEP_CTRL, 0, 31,   0x3F3934EA);
1136         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_COMP_FLT_CTRL, 0, 31,  0x00000000);
1137         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_PHASE_INC, 0, 31,  0x1befbf06);
1138         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_GAIN_CONTROL, 0, 31,  0x000035e8);
1139         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_RPT_VARIANCE, 0, 31,  0x00000000);
1140         /* Save the Spec Inversion value */
1141         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1142         dif_misc_ctrl_value |=0x3a023F11;
1143
1144     } else if( standard & V4L2_STD_PAL_I ) {
1145
1146         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL, 0, 31,  0x6503bc0c);
1147         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL1, 0, 31,  0xbd038c85);
1148         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL2, 0, 31,  0x1db4640a);
1149         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL3, 0, 31,  0x00008800);
1150         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1151         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1152         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1153         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1154         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_INT_CURRENT, 0, 31,  0x26001700);
1155         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_RF_CURRENT, 0, 31,  0x00002660);
1156         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VIDEO_AGC_CTRL, 0, 31,  0x72500800);
1157         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VID_AUD_OVERRIDE, 0, 31,  0x27000100);
1158         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AV_SEP_CTRL, 0, 31,   0x5F39A934);
1159         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_COMP_FLT_CTRL, 0, 31,  0x00000000);
1160         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_PHASE_INC, 0, 31,  0x1befbf06);
1161         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_GAIN_CONTROL, 0, 31,  0x000035e8);
1162         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_RPT_VARIANCE, 0, 31,  0x00000000);
1163         /* Save the Spec Inversion value */
1164         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1165         dif_misc_ctrl_value |=0x3a033F11;
1166
1167     } else if( standard & V4L2_STD_PAL_M ) {
1168
1169         /* improved Low Frequency Phase Noise */
1170         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1171                                  DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1172         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1173                                  DIF_PLL_CTRL1, 2, 0xbd038c85, 4);
1174         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1175                                  DIF_PLL_CTRL2,  2, 0x1db4640a, 4);
1176         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1177                                  DIF_PLL_CTRL3,  2, 0x00008800, 4);
1178         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1179                                  DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1180         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1181                                  DIF_AGC_IF_INT_CURRENT,  2, 0x26001700, 4);
1182         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1183                                  DIF_AGC_RF_CURRENT,  2, 0x00002660, 4);
1184         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1185                                  DIF_VIDEO_AGC_CTRL,  2, 0x72500800, 4);
1186         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1187                                  DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4);
1188         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1189                                  DIF_AV_SEP_CTRL,  2, 0x012c405d, 4);
1190         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1191                                  DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1192         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1193                                  DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1194         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1195                                  DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4);
1196         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1197                                  DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4);
1198
1199         /* Save the Spec Inversion value */
1200         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1201         dif_misc_ctrl_value |= 0x3A0A3F10;
1202
1203     } else if( standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) ) {
1204
1205         /* improved Low Frequency Phase Noise */
1206         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1207         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xbd038c85, 4);
1208         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1db4640a, 4);
1209         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4);
1210         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1211         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4);
1212         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4);
1213         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 4);
1214         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4);
1215         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1216         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1217         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1218         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4);
1219         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4);
1220
1221         /* Save the Spec Inversion value */
1222         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1223         dif_misc_ctrl_value = 0x3A093F10;
1224
1225     } else if( standard & ( V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1226                             V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1) ) {
1227
1228         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL, 0, 31,  0x6503bc0c);
1229         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL1, 0, 31,  0xbd038c85);
1230         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL2, 0, 31,  0x1db4640a);
1231         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL3, 0, 31,  0x00008800);
1232         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1233         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1234         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1235         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1236         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_INT_CURRENT, 0, 31,  0x26001700);
1237         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_RF_CURRENT, 0, 31,  0x00002660);
1238         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VID_AUD_OVERRIDE, 0, 31,  0x27000100);
1239         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AV_SEP_CTRL, 0, 31,   0x3F3530ec);
1240         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_COMP_FLT_CTRL, 0, 31,  0x00000000);
1241         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_PHASE_INC, 0, 31,  0x1befbf06);
1242         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_GAIN_CONTROL, 0, 31,  0x000035e8);
1243         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_RPT_VARIANCE, 0, 31,  0x00000000);
1244         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VIDEO_AGC_CTRL, 0, 31,  0xf4000000);
1245
1246         /* Save the Spec Inversion value */
1247         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1248         dif_misc_ctrl_value |=0x3a023F11;
1249
1250     } else if( standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) ) {
1251
1252         /* Is it SECAM_L1? */
1253         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL, 0, 31,  0x6503bc0c);
1254         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL1, 0, 31,  0xbd038c85);
1255         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL2, 0, 31,  0x1db4640a);
1256         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_PLL_CTRL3, 0, 31,  0x00008800);
1257         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1258         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1259         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1260         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1261         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_IF_INT_CURRENT, 0, 31,  0x26001700);
1262         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AGC_RF_CURRENT, 0, 31,  0x00002660);
1263         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VID_AUD_OVERRIDE, 0, 31,  0x27000100);
1264         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_AV_SEP_CTRL, 0, 31,   0x3F3530ec);
1265         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_COMP_FLT_CTRL, 0, 31,  0x00000000);
1266         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_PHASE_INC, 0, 31,  0x1befbf06);
1267         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_SRC_GAIN_CONTROL, 0, 31,  0x000035e8);
1268         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_RPT_VARIANCE, 0, 31,  0x00000000);
1269         status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS,  32, DIF_VIDEO_AGC_CTRL, 0, 31,  0xf2560000);
1270
1271         /* Save the Spec Inversion value */
1272         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1273         dif_misc_ctrl_value |=0x3a023F11;
1274
1275     } else  { /* V4L2_STD_NTSC_M (75 IRE Setup) Or  V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
1276
1277         /* For NTSC the centre frequency of video coming out of sidewinder is
1278            around 7.1MHz or 3.6MHz depending on the spectral inversion.
1279            so for a non spectrally inverted channel the pll freq word is 0x03420c49
1280         */
1281
1282         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0x6503BC0C, 4);
1283         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xBD038C85, 4);
1284         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1DB4640A, 4);
1285         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4);
1286         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C0380, 4);
1287         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4);
1288         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4);
1289         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x04000800, 4);
1290         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4);
1291         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4);
1292
1293         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1294         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1295         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4);
1296
1297         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_IF, 2, 0xC2262600, 4);
1298         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_INT, 2, 0xC2262600, 4);
1299         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_RF, 2, 0xC2262600, 4);
1300
1301         /* Save the Spec Inversion value */
1302         dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1303         dif_misc_ctrl_value |= 0x3a003F10;
1304
1305     }
1306
1307     /* The AGC values should be the same for all standards,
1308        AUD_SRC_SEL[19] should always be disabled    */
1309     dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
1310
1311     /* It is still possible to get Set Standard calls even when we are in FM mode
1312        This is done to override the value for FM. */
1313     if (dev->active_mode == V4L2_TUNER_RADIO)
1314         dif_misc_ctrl_value = 0x7a080000;
1315
1316     /* Write the calculated value for misc ontrol register      */
1317     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4);
1318
1319     return status;
1320 }
1321
1322 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1323 {
1324         int status = 0;
1325         u32 dwval;
1326
1327         /* Set the RF and IF k_agc values to 3 */
1328     status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1329                                      DIF_AGC_IF_REF, 2, &dwval, 4);
1330         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1331         dwval |= 0x33000000;
1332
1333     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1334                                      DIF_AGC_IF_REF, 2, dwval, 4);
1335
1336     return status;
1337 }
1338
1339 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1340 {
1341     int status = 0;
1342         u32 dwval;
1343
1344     /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */
1345     status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1346                                      DIF_AGC_IF_REF, 2, &dwval, 4);
1347     dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1348
1349     if(dev->norm & ( V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | V4L2_STD_SECAM_D) ) {
1350         dwval |= 0x88000000;
1351     } else {
1352         dwval |= 0x44000000;
1353     }
1354
1355     status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1356                                      DIF_AGC_IF_REF, 2, dwval, 4);
1357
1358     return status;
1359 }
1360
1361
1362
1363 /*************************************************************************************
1364  *            F L A T I R O N - B L O C K    C O N T R O L   functions               *
1365  *************************************************************************************/
1366 int cx231xx_flatiron_initialize(struct cx231xx *dev)
1367 {
1368     int status = 0;
1369     u32 value;
1370
1371     status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, &value, 1);
1372     /* enables clock to delta-sigma and decimation filter */
1373     value |= 0x80;
1374     status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1375                                      CH_PWR_CTRL1, 1, value, 1);
1376     /* power up all channel */
1377     status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1378                                      CH_PWR_CTRL2, 1, 0x00, 1);
1379
1380     return status;
1381 }
1382
1383 int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode)
1384 {
1385     int status = 0;
1386     u32 value=0;
1387
1388     if(avmode!=POLARIS_AVMODE_ENXTERNAL_AV) {
1389         status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, &value, 1);
1390         value |= 0xfe;
1391         status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1392                                      CH_PWR_CTRL2, 1, value, 1);
1393     }
1394     else {
1395         status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1396                                      CH_PWR_CTRL2, 1, 0x00, 1);
1397     }
1398
1399     return status;
1400 }
1401
1402 /* set flatiron for audio input types */
1403 int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input)
1404 {
1405     int status = 0;
1406
1407     switch(audio_input) {
1408         case CX231XX_AMUX_LINE_IN:
1409
1410             status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1411                                      CH_PWR_CTRL2, 1, 0x00, 1);
1412             status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1413                                      CH_PWR_CTRL1, 1, 0x80, 1);
1414             break;
1415         case CX231XX_AMUX_VIDEO:
1416         default:
1417             break;
1418     }
1419
1420     dev->ctl_ainput = audio_input;
1421
1422     return status;
1423 }
1424
1425 /*************************************************************************************
1426  *                      P O W E R      C O N T R O L   functions                     *
1427  *************************************************************************************/
1428 int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode)
1429 {
1430     u8 value[4] ={0,0,0,0};
1431     u32 tmp = 0;
1432     int status = 0;
1433
1434     if(dev->power_mode != mode)
1435         dev->power_mode = mode;
1436     else {
1437         cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",mode);
1438         return 0;
1439     }
1440
1441     cx231xx_info(" setPowerMode::mode = %d\n",mode);
1442
1443     status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
1444     if(status < 0)
1445         return status;
1446
1447     tmp = *((u32 *)value);
1448
1449     switch(mode)  {
1450         case POLARIS_AVMODE_ENXTERNAL_AV:
1451
1452             tmp &= (~PWR_MODE_MASK);
1453
1454             tmp |= PWR_AV_EN;
1455             value[0]=(u8)tmp;
1456             value[1]=(u8)(tmp>>8);
1457             value[2]=(u8)(tmp>>16);
1458             value[3]=(u8)(tmp>>24);
1459             status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1460             msleep(PWR_SLEEP_INTERVAL);
1461
1462             tmp |= PWR_ISO_EN;
1463             value[0]=(u8)tmp;
1464             value[1]=(u8)(tmp>>8);
1465             value[2]=(u8)(tmp>>16);
1466             value[3]=(u8)(tmp>>24);
1467             status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1468             msleep(PWR_SLEEP_INTERVAL);
1469
1470             tmp |=POLARIS_AVMODE_ENXTERNAL_AV;
1471             value[0]=(u8)tmp;
1472             value[1]=(u8)(tmp>>8);
1473             value[2]=(u8)(tmp>>16);
1474             value[3]=(u8)(tmp>>24);
1475             status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1476
1477             dev->xc_fw_load_done = 0; /* reset state of xceive tuner */
1478             break;
1479
1480         case POLARIS_AVMODE_ANALOGT_TV:
1481
1482             tmp &= (~PWR_DEMOD_EN);
1483             tmp |= (I2C_DEMOD_EN);
1484             value[0]=(u8)tmp;
1485             value[1]=(u8)(tmp>>8);
1486             value[2]=(u8)(tmp>>16);
1487             value[3]=(u8)(tmp>>24);
1488             status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1489             msleep(PWR_SLEEP_INTERVAL);
1490
1491             if(!(tmp & PWR_TUNER_EN)) {
1492                 tmp |= (PWR_TUNER_EN);
1493                 value[0]=(u8)tmp;
1494                 value[1]=(u8)(tmp>>8);
1495                 value[2]=(u8)(tmp>>16);
1496                 value[3]=(u8)(tmp>>24);
1497                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1498                 msleep(PWR_SLEEP_INTERVAL);
1499             }
1500
1501             if(!(tmp & PWR_AV_EN)) {
1502                 tmp |= PWR_AV_EN;
1503                 value[0]=(u8)tmp;
1504                 value[1]=(u8)(tmp>>8);
1505                 value[2]=(u8)(tmp>>16);
1506                 value[3]=(u8)(tmp>>24);
1507                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1508                 msleep(PWR_SLEEP_INTERVAL);
1509             }
1510             if(!(tmp & PWR_ISO_EN )) {
1511                 tmp |= PWR_ISO_EN;
1512                 value[0]=(u8)tmp;
1513                 value[1]=(u8)(tmp>>8);
1514                 value[2]=(u8)(tmp>>16);
1515                 value[3]=(u8)(tmp>>24);
1516                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1517                 msleep(PWR_SLEEP_INTERVAL);
1518             }
1519
1520             if(!(tmp & POLARIS_AVMODE_ANALOGT_TV )) {
1521                 tmp |= POLARIS_AVMODE_ANALOGT_TV;
1522                 value[0]=(u8)tmp;
1523                 value[1]=(u8)(tmp>>8);
1524                 value[2]=(u8)(tmp>>16);
1525                 value[3]=(u8)(tmp>>24);
1526                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1527                 msleep(PWR_SLEEP_INTERVAL);
1528             }
1529
1530             if( (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1531                 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1532
1533                     /* tuner path to channel 1 from port 3 */
1534                     cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1535
1536                     if(dev->cx231xx_reset_analog_tuner)
1537                         dev->cx231xx_reset_analog_tuner(dev);
1538             }
1539             break;
1540
1541         case POLARIS_AVMODE_DIGITAL:
1542
1543             if(!(tmp & PWR_TUNER_EN)) {
1544                 tmp |= (PWR_TUNER_EN);
1545                 value[0]=(u8)tmp;
1546                 value[1]=(u8)(tmp>>8);
1547                 value[2]=(u8)(tmp>>16);
1548                 value[3]=(u8)(tmp>>24);
1549                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1550                 msleep(PWR_SLEEP_INTERVAL);
1551             }
1552             if(!(tmp & PWR_AV_EN)) {
1553                 tmp |= PWR_AV_EN;
1554                 value[0]=(u8)tmp;
1555                 value[1]=(u8)(tmp>>8);
1556                 value[2]=(u8)(tmp>>16);
1557                 value[3]=(u8)(tmp>>24);
1558                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1559                 msleep(PWR_SLEEP_INTERVAL);
1560             }
1561             if(!(tmp & PWR_ISO_EN)) {
1562                 tmp |= PWR_ISO_EN;
1563                 value[0]=(u8)tmp;
1564                 value[1]=(u8)(tmp>>8);
1565                 value[2]=(u8)(tmp>>16);
1566                 value[3]=(u8)(tmp>>24);
1567                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1568                 msleep(PWR_SLEEP_INTERVAL);
1569             }
1570
1571             tmp |= POLARIS_AVMODE_DIGITAL|I2C_DEMOD_EN;
1572             value[0]=(u8)tmp;
1573             value[1]=(u8)(tmp>>8);
1574             value[2]=(u8)(tmp>>16);
1575             value[3]=(u8)(tmp>>24);
1576             status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1577             msleep(PWR_SLEEP_INTERVAL);
1578
1579             if(!(tmp & PWR_DEMOD_EN)) {
1580                 tmp |= PWR_DEMOD_EN;
1581                 value[0]=(u8)tmp;
1582                 value[1]=(u8)(tmp>>8);
1583                 value[2]=(u8)(tmp>>16);
1584                 value[3]=(u8)(tmp>>24);
1585                 status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1586                 msleep(PWR_SLEEP_INTERVAL);
1587             }
1588
1589             if( (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1590                 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1591
1592                     /* tuner path to channel 1 from port 3 */
1593                     cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1594
1595                     if(dev->cx231xx_reset_analog_tuner)
1596                         dev->cx231xx_reset_analog_tuner(dev);
1597             }
1598             break;
1599
1600         default:
1601             break;
1602     }
1603
1604     msleep(PWR_SLEEP_INTERVAL);
1605
1606     /* For power saving, only enable Pwr_resetout_n when digital TV is selected. */
1607     if(mode == POLARIS_AVMODE_DIGITAL) {
1608         tmp |= PWR_RESETOUT_EN;
1609         value[0]=(u8)tmp;
1610         value[1]=(u8)(tmp>>8);
1611         value[2]=(u8)(tmp>>16);
1612         value[3]=(u8)(tmp>>24);
1613         status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1614         msleep(PWR_SLEEP_INTERVAL);
1615     }
1616
1617     /* update power control for colibri */
1618     status = cx231xx_colibri_update_power_control(dev, mode);
1619
1620     /* update power control for flatiron */
1621     status = cx231xx_flatiron_update_power_control(dev, mode);
1622
1623     status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
1624     cx231xx_info(" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n",value[0],value[1],value[2],value[3]);
1625
1626     return status;
1627 }
1628
1629 int cx231xx_power_suspend(struct cx231xx *dev)
1630 {
1631     u8 value[4] ={0,0,0,0};
1632     u32 tmp = 0;
1633     int status = 0;
1634
1635     status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4);
1636     if(status > 0)
1637         return status;
1638
1639     tmp = *((u32 *)value);
1640     tmp &= (~PWR_MODE_MASK);
1641
1642     value[0]=(u8)tmp;
1643     value[1]=(u8)(tmp>>8);
1644     value[2]=(u8)(tmp>>16);
1645     value[3]=(u8)(tmp>>24);
1646     status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4);
1647
1648     return status;
1649 }
1650
1651
1652 /*************************************************************************************
1653  *                      S T R E A M    C O N T R O L   functions                     *
1654  *************************************************************************************/
1655 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
1656 {
1657         u8  value[4] = {0x0, 0x0, 0x0, 0x0};
1658     u32 tmp =0;
1659     int status = 0;
1660
1661     cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
1662     status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, EP_MODE_SET,value,4);
1663     if(status < 0)
1664         return status;
1665
1666     tmp = *((u32 *)value);
1667     tmp |= ep_mask;
1668     value[0]=(u8) tmp;
1669     value[1]=(u8)(tmp>>8);
1670     value[2]=(u8)(tmp>>16);
1671     value[3]=(u8)(tmp>>24);
1672
1673     status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, EP_MODE_SET,value,4);
1674
1675     return status;
1676 }
1677
1678 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
1679 {
1680     u8  value[4] = {0x0, 0x0, 0x0, 0x0};
1681     u32 tmp =0;
1682     int status = 0;
1683
1684     cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
1685     status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, EP_MODE_SET,value,4);
1686     if(status < 0)
1687         return status;
1688
1689     tmp = *((u32 *)value);
1690     tmp&= (~ep_mask);
1691     value[0]=(u8) tmp;
1692     value[1]=(u8)(tmp>>8);
1693     value[2]=(u8)(tmp>>16);
1694     value[3]=(u8)(tmp>>24);
1695
1696     status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, EP_MODE_SET,value,4);
1697
1698     return status;
1699 }
1700
1701 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
1702 {
1703     int status = 0;
1704
1705     if(dev->udev->speed == USB_SPEED_HIGH)
1706     {
1707         switch(media_type)
1708         {
1709             case 81: /* audio */
1710                 cx231xx_info("%s: Audio enter HANC\n",__func__);
1711                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
1712                 break;
1713
1714             case 2: /* vbi */
1715                 cx231xx_info("%s: set vanc registers\n",__func__);
1716                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
1717                 break;
1718
1719             case 3: /* sliced cc */
1720                 cx231xx_info("%s: set hanc registers\n",__func__);
1721                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
1722                 break;
1723
1724             case 0: /* video */
1725                 cx231xx_info("%s: set video registers\n",__func__);
1726                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
1727                 break;
1728
1729             case 4: /* ts1 */
1730                 cx231xx_info("%s: set ts1 registers\n",__func__);
1731                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
1732                 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
1733                 break;
1734             case 6: /* ts1 parallel mode */
1735                 cx231xx_info("%s: set ts1 parrallel mode registers\n",__func__);
1736                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
1737                 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
1738                 break;
1739         }
1740     }
1741     else
1742     {
1743         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
1744     }
1745
1746     return status;
1747 }
1748
1749
1750
1751
1752 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
1753 {
1754         int rc;
1755     u32 ep_mask = -1;
1756     PPCB_CONFIG pcb_config;
1757
1758     /* get EP for media type */
1759     pcb_config  = &dev->current_pcb_config;
1760
1761     if(pcb_config->config_num==1)
1762     {
1763         switch (media_type)
1764         {
1765             case 0:                     /* Video */
1766                 ep_mask =ENABLE_EP4;    /* ep4  [00:1000] */
1767                 break;
1768             case 1:                     /* Audio */
1769                 ep_mask =ENABLE_EP3;    /* ep3  [00:0100] */
1770                 break;
1771             case 2:                     /* Vbi */
1772                 ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
1773                 break;
1774             case 3:                     /* Sliced_cc */
1775                 ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
1776                 break;
1777             case 4:                     /* ts1 */
1778             case 6:                     /* ts1 parallel mode */
1779                 ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
1780                 break;
1781             case 5:                     /* ts2 */
1782                 ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
1783                 break;
1784             }
1785
1786     }
1787     else if(pcb_config->config_num>1)
1788     {
1789         switch (media_type)
1790         {
1791             case 0:                     /* Video */
1792                 ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
1793                 break;
1794             case 1:                     /* Audio */
1795                 ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
1796                 break;
1797             case 2:                     /* Vbi */
1798                 ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
1799                 break;
1800             case 3:                     /* Sliced_cc */
1801                 ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
1802                 break;
1803             case 4:                     /* ts1 */
1804             case 6:                     /* ts1 parallel mode */
1805                 ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
1806                 break;
1807             case 5:                     /* ts2 */
1808                 ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
1809                 break;
1810             }
1811
1812     }
1813
1814     if(start) {
1815         rc = cx231xx_initialize_stream_xfer(dev, media_type);
1816
1817         if(rc < 0) {
1818             return rc;
1819         }
1820
1821         /* enable video capture */
1822         if(ep_mask > 0 )
1823             rc = cx231xx_start_stream(dev, ep_mask);
1824     }
1825     else {
1826         /* disable video capture */
1827         if(ep_mask > 0 )
1828             rc = cx231xx_stop_stream(dev, ep_mask);
1829     }
1830
1831     if (dev->mode == CX231XX_ANALOG_MODE){
1832         /* do any in Analog mode */
1833     }
1834     else {
1835         /* do any in digital mode */
1836     }
1837
1838         return rc;
1839 }
1840 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
1841
1842
1843 /************************************************************************************
1844 *                       G P I O   B I T control functions                           *
1845 *************************************************************************************/
1846 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8* gpio_val)
1847 {
1848     int status = 0;
1849
1850     status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
1851
1852     return status;
1853 }
1854
1855 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8* gpio_val)
1856 {
1857     int status = 0;
1858
1859     status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
1860
1861     return status;
1862 }
1863
1864 /*
1865 * cx231xx_set_gpio_direction
1866 *      Sets the direction of the GPIO pin to input or output
1867 *
1868 * Parameters :
1869 *      pin_number : The GPIO Pin number to program the direction for
1870 *                   from 0 to 31
1871 *      pin_value : The Direction of the GPIO Pin under reference.
1872 *                      0 = Input direction
1873 *                      1 = Output direction
1874 */
1875 int cx231xx_set_gpio_direction(struct cx231xx *dev,
1876         int    pin_number,
1877         int    pin_value)
1878 {
1879         int status = 0;
1880     u32 value = 0;
1881
1882     /* Check for valid pin_number - if 32 , bail out */
1883     if (pin_number >= 32) {
1884         return -EINVAL;
1885     }
1886
1887     if (pin_value == 0) {                           /* input */
1888         value = dev->gpio_dir &(~(1<<pin_number)) ; /* clear */
1889     } else {
1890         value = dev->gpio_dir | (1<<pin_number) ;
1891     }
1892
1893         status = cx231xx_set_gpio_bit(dev, value, (u8*) & dev->gpio_val);
1894
1895     /* cache the value for future */
1896         dev->gpio_dir = value;
1897
1898     return status;
1899 }
1900
1901
1902 /*
1903 * SetGpioPinLogicValue
1904 *      Sets the value of the GPIO pin to Logic high or low. The Pin under
1905 *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
1906 *
1907 * Parameters :
1908 *      pin_number : The GPIO Pin number to program the direction for
1909 *      pin_value : The value of the GPIO Pin under reference.
1910 *                      0 = set it to 0
1911 *                      1 = set it to 1
1912 */
1913 int cx231xx_set_gpio_value(struct cx231xx *dev,
1914         int    pin_number,
1915         int    pin_value)
1916 {
1917     int status = 0;
1918     u32 value = 0;
1919
1920     /* Check for valid pin_number - if 0xFF , bail out */
1921     if (pin_number >= 32)
1922         return -EINVAL;
1923
1924     /* first do a sanity check - if the Pin is not output, make it output */
1925     if ((dev->gpio_dir & (1<<pin_number)) == 0x00)
1926     {
1927         /* It was in input mode */
1928         value = dev->gpio_dir | (1<<pin_number) ;
1929         dev->gpio_dir = value;
1930         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
1931                 value = 0;
1932     }
1933
1934     if (pin_value == 0) {
1935         value = dev->gpio_val & (~(1<<pin_number));
1936     } else {
1937         value = dev->gpio_val | (1<<pin_number);
1938     }
1939
1940     /* store the value */
1941     dev->gpio_val=value;
1942
1943     /* toggle bit0 of GP_IO */
1944     status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
1945
1946     return status;
1947 }
1948
1949
1950 /************************************************************************************
1951 *                          G P I O I2C related functions                            *
1952 *************************************************************************************/
1953 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
1954 {
1955         int status = 0;
1956
1957         /* set SCL to output 1 ; set SDA to output 1 */
1958         dev->gpio_dir |= 1<< dev->board.tuner_scl_gpio;
1959         dev->gpio_dir |= 1<<dev->board.tuner_sda_gpio;
1960         dev->gpio_val |= 1<<dev->board.tuner_scl_gpio;
1961         dev->gpio_val |= 1<<dev->board.tuner_sda_gpio;
1962
1963     status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
1964     if(status < 0){
1965                 return -EINVAL;
1966         }
1967
1968         /* set SCL to output 1; set SDA to output 0 */
1969         dev->gpio_val |= 1<<dev->board.tuner_scl_gpio;
1970         dev->gpio_val &= ~(1<<dev->board.tuner_sda_gpio);
1971
1972     status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
1973     if(status < 0){
1974                 return -EINVAL;
1975         }
1976
1977         /* set SCL to output 0; set SDA to output 0      */
1978         dev->gpio_val &= ~(1<<dev->board.tuner_scl_gpio);
1979         dev->gpio_val &= ~(1<<dev->board.tuner_sda_gpio);
1980
1981     status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
1982     if(status < 0){
1983                 return -EINVAL;
1984         }
1985
1986         return status;
1987 }
1988
1989
1990 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
1991 {
1992     int status = 0;
1993
1994         /* set SCL to output 0; set SDA to output 0      */
1995         dev->gpio_dir |= 1<<dev->board.tuner_scl_gpio;
1996         dev->gpio_dir |= 1<<dev->board.tuner_sda_gpio;
1997
1998         dev->gpio_val &= ~(1<<dev->board.tuner_scl_gpio);
1999         dev->gpio_val &= ~(1<<dev->board.tuner_sda_gpio);
2000
2001     status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2002     if(status < 0){
2003                 return -EINVAL;
2004         }
2005
2006         /* set SCL to output 1; set SDA to output 0      */
2007         dev->gpio_val |= 1<<dev->board.tuner_scl_gpio;
2008         dev->gpio_val &= ~(1<<dev->board.tuner_sda_gpio);
2009
2010         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2011     if(status < 0){
2012                 return -EINVAL;
2013         }
2014
2015         /* set SCL to input ,release SCL cable control
2016            set SDA to input ,release SDA cable control */
2017         dev->gpio_dir &= ~(1<<dev->board.tuner_scl_gpio);
2018         dev->gpio_dir &= ~(1<<dev->board.tuner_sda_gpio);
2019
2020     status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2021     if(status < 0){
2022                 return -EINVAL;
2023         }
2024         return status;
2025 }
2026
2027
2028 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2029 {
2030         int  status = 0;
2031     u8 i;
2032
2033         /* set SCL to output ; set SDA to output */
2034         dev->gpio_dir |= 1<<dev->board.tuner_scl_gpio;
2035         dev->gpio_dir |= 1<<dev->board.tuner_sda_gpio;
2036
2037         for(i = 0;i<8;i++) {
2038                 if(((data<<i) & 0x80) == 0) {
2039                         /* set SCL to output 0; set SDA to output 0     */
2040                         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2041                         dev->gpio_val &= ~(1<<dev->board.tuner_sda_gpio);
2042                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2043
2044                         /* set SCL to output 1; set SDA to output 0     */
2045                         dev->gpio_val  |= 1<<dev->board.tuner_scl_gpio;
2046                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2047
2048                         /* set SCL to output 0; set SDA to output 0     */
2049                         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2050                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2051                 } else {
2052                         /* set SCL to output 0; set SDA to output 1     */
2053                         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2054                         dev->gpio_val |= 1<<dev->board.tuner_sda_gpio;
2055                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2056
2057                         /* set SCL to output 1; set SDA to output 1     */
2058                         dev->gpio_val  |= 1<<dev->board.tuner_scl_gpio;
2059                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2060
2061                         /* set SCL to output 0; set SDA to output 1     */
2062                         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2063                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2064         }
2065         }
2066         return status;
2067 }
2068
2069 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2070 {
2071         u8 value = 0;
2072         int  status = 0;
2073         u32 gpio_logic_value =0;
2074     u8 i;
2075
2076         /* read byte */
2077     for(i=0;i<8;i++) {      /* send write I2c addr */
2078
2079                 /* set SCL to output 0; set SDA to input */
2080                 dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2081                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2082
2083                 /* set SCL to output 1; set SDA to input */
2084                 dev->gpio_val  |= 1<<dev->board.tuner_scl_gpio;
2085                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2086
2087                 /* get SDA data bit */
2088                 gpio_logic_value = dev->gpio_val;
2089                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2090                 if((dev->gpio_val & (1<<dev->board.tuner_sda_gpio)) != 0) {
2091                         value |= (1<<(8-i-1));
2092                 }
2093
2094                 dev->gpio_val = gpio_logic_value;
2095         }
2096
2097         /* set SCL to output 0,finish the read latest SCL signal.
2098            !!!set SDA to input,never to modify SDA direction at the same times */
2099         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2100         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2101
2102     /* store the value */
2103     *buf = value & 0xff;
2104
2105         return status;
2106 }
2107
2108 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2109 {
2110         int  status = 0;
2111         u32 gpio_logic_value = 0;
2112     int nCnt=10;
2113     int nInit=nCnt;
2114
2115         /* clock stretch; set SCL to input; set SDA to input; get SCL value till SCL = 1 */
2116         dev->gpio_dir &= ~(1<<dev->board.tuner_sda_gpio);
2117         dev->gpio_dir &= ~(1<<dev->board.tuner_scl_gpio);
2118
2119         gpio_logic_value = dev->gpio_val;
2120         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2121
2122     do{
2123                 msleep(2);
2124                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2125         nCnt--;
2126         }while(((dev->gpio_val & (1<<dev->board.tuner_scl_gpio)) == 0) && (nCnt>0));
2127
2128     if(nCnt==0) {
2129         cx231xx_info("No ACK after %d msec for clock stretch. GPIO I2C operation failed!",nInit*10);
2130     }
2131
2132         /* readAck
2133            throuth clock stretch ,slave has given a SCL signal,so the SDA data can be directly read.  */
2134         status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2135
2136         if((dev->gpio_val & 1<< dev->board.tuner_sda_gpio) == 0){
2137                 dev->gpio_val = gpio_logic_value;
2138                 dev->gpio_val &= ~(1<< dev->board.tuner_sda_gpio);
2139                 status = 0;
2140         } else {
2141                 dev->gpio_val = gpio_logic_value;
2142                 dev->gpio_val |= (1<< dev->board.tuner_sda_gpio);
2143         }
2144
2145         /* read SDA end, set the SCL to output 0, after this operation, SDA direction can be changed. */
2146         dev->gpio_val = gpio_logic_value;
2147         dev->gpio_dir |= (1<<dev->board.tuner_scl_gpio);
2148         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2149         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2150
2151         return status;
2152 }
2153
2154
2155 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2156 {
2157         int  status = 0;
2158
2159         /* set SDA to ouput */
2160         dev->gpio_dir |= 1<<dev->board.tuner_sda_gpio;
2161         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2162
2163         /* set SCL = 0 (output); set SDA = 0 (output) */
2164         dev->gpio_val &= ~(1<<dev->board.tuner_sda_gpio);
2165         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2166         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2167
2168         /* set SCL = 1 (output); set SDA = 0 (output) */
2169         dev->gpio_val  |= 1<<dev->board.tuner_scl_gpio;
2170         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2171
2172         /* set SCL = 0 (output); set SDA = 0 (output) */
2173         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2174         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2175
2176         /* set SDA to input,and then the slave will read data from SDA. */
2177         dev->gpio_dir  &= ~(1<<dev->board.tuner_sda_gpio);
2178         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2179
2180         return status;
2181 }
2182
2183 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2184 {
2185         int  status = 0;
2186
2187         /* set scl to output ; set sda to input */
2188         dev->gpio_dir |= 1<<dev->board.tuner_scl_gpio;
2189         dev->gpio_dir &= ~(1<<dev->board.tuner_sda_gpio);
2190         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2191
2192         /* set scl to output 0; set sda to input */
2193         dev->gpio_val  &= ~(1<<dev->board.tuner_scl_gpio);
2194         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2195
2196         /* set scl to output 1; set sda to input */
2197         dev->gpio_val  |= 1<<dev->board.tuner_scl_gpio;
2198         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val);
2199
2200         return status;
2201 }
2202
2203
2204
2205 /************************************************************************************
2206 *                          G P I O I2C related functions                            *
2207 *************************************************************************************/
2208 /* cx231xx_gpio_i2c_read
2209  * Function to read data from gpio based I2C interface
2210  */
2211 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf ,u8 len)
2212 {
2213         int  status = 0;
2214     int i = 0;
2215
2216     /* get the lock */
2217         mutex_lock(&dev->gpio_i2c_lock);
2218
2219         /* start */
2220         status = cx231xx_gpio_i2c_start(dev);
2221
2222         /* write dev_addr */
2223         status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) +1);
2224
2225         /* readAck */
2226         status = cx231xx_gpio_i2c_read_ack(dev);
2227
2228     /* read data */
2229     for(i = 0; i < len; i++ ) {
2230         /* read data */
2231         buf[i] = 0;
2232             status = cx231xx_gpio_i2c_read_byte(dev, & buf[i]);
2233
2234         if( (i+1) != len) {
2235                 /* only do write ack if we more length */
2236                 status = cx231xx_gpio_i2c_write_ack(dev);
2237         }
2238     }
2239
2240         /* write NAK - inform reads are complete */
2241         status = cx231xx_gpio_i2c_write_nak(dev);
2242
2243         /* write end */
2244         status = cx231xx_gpio_i2c_end(dev);
2245
2246         /* release the lock */
2247         mutex_unlock(&dev->gpio_i2c_lock);
2248
2249         return status;
2250 }
2251
2252
2253 /* cx231xx_gpio_i2c_write
2254  * Function to write data to gpio based I2C interface
2255  */
2256 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf ,u8 len)
2257 {
2258         int  status = 0;
2259         int i=0;
2260
2261         /* get the lock */
2262         mutex_lock(&dev->gpio_i2c_lock);
2263
2264         /* start */
2265         status = cx231xx_gpio_i2c_start(dev);
2266
2267         /* write dev_addr */
2268         status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2269
2270         /* read Ack */
2271     status = cx231xx_gpio_i2c_read_ack(dev);
2272
2273     for(i = 0; i < len; i++ ) {
2274                 /* Write data */
2275         status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
2276
2277             /* read Ack */
2278         status = cx231xx_gpio_i2c_read_ack(dev);
2279     }
2280
2281     /* write End */
2282         status = cx231xx_gpio_i2c_end(dev);
2283
2284         /* release the lock */
2285         mutex_unlock(&dev->gpio_i2c_lock);
2286
2287         return 0;
2288 }
2289