2 * cx18 ADEC audio functions
4 * Derived from cx25840-core.c
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "cx18-driver.h"
28 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
30 u32 reg = 0xc40000 + (addr & ~3);
32 int shift = (addr & 3) * 8;
33 u32 x = cx18_read_reg(cx, reg);
35 x = (x & ~(mask << shift)) | ((u32)value << shift);
36 cx18_write_reg(cx, x, reg);
40 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
42 u32 reg = 0xc40000 + (addr & ~3);
43 int shift = (addr & 3) * 8;
44 u32 x = cx18_read_reg(cx, reg);
46 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
47 cx18_write_reg_expect(cx, x, reg,
48 ((u32)eval << shift), ((u32)mask << shift));
52 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
54 cx18_write_reg(cx, value, 0xc40000 + addr);
59 cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
61 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
65 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
67 cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
71 u8 cx18_av_read(struct cx18 *cx, u16 addr)
73 u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
74 int shift = (addr & 3) * 8;
76 return (x >> shift) & 0xff;
79 u32 cx18_av_read4(struct cx18 *cx, u16 addr)
81 return cx18_read_reg(cx, 0xc40000 + addr);
84 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
87 return cx18_av_write(cx, addr,
88 (cx18_av_read(cx, addr) & and_mask) |
92 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
95 return cx18_av_write4(cx, addr,
96 (cx18_av_read4(cx, addr) & and_mask) |
100 /* ----------------------------------------------------------------------- */
102 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
103 enum cx18_av_audio_input aud_input);
104 static void log_audio_status(struct cx18 *cx);
105 static void log_video_status(struct cx18 *cx);
107 /* ----------------------------------------------------------------------- */
109 static void cx18_av_initialize(struct cx18 *cx)
111 struct cx18_av_state *state = &cx->av_state;
115 /* Stop 8051 code execution */
116 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
117 0x03000000, 0x13000000);
119 /* initallize the PLL by toggling sleep bit */
120 v = cx18_av_read4(cx, CXADEC_HOST_REG1);
121 /* enable sleep mode - register appears to be read only... */
122 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
123 /* disable sleep mode */
124 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
127 /* initialize DLLs */
128 v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
130 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
132 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
134 v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
136 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
138 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
140 /* set analog bias currents. Set Vreg to 1.20V. */
141 cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
143 v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
144 /* enable TUNE_FIL_RST */
145 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
146 /* disable TUNE_FIL_RST */
147 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
148 v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
150 /* enable 656 output */
151 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
153 /* video output drive strength */
154 cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
157 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
158 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
160 /* set video to auto-detect */
161 /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */
162 /* set the comb notch = 1 */
163 cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
165 /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
166 /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
167 cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
169 /* Set VGA_TRACK_RANGE to 0x20 */
170 cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
174 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
175 * don't clamp raw samples when codes are in use, 1 byte user D-words,
176 * IDID0 has line #, RP code V bit transition on VBLANK, data during
179 cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
181 /* Set the video input.
182 The setting in MODE_CTRL gets lost when we do the above setup */
183 /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
184 /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
186 v = cx18_av_read4(cx, CXADEC_AFE_CTRL);
187 v &= 0xFFFBFFFF; /* turn OFF bit 18 for droop_comp_ch1 */
188 v &= 0xFFFF7FFF; /* turn OFF bit 9 for clamp_sel_ch1 */
189 v &= 0xFFFFFFFE; /* turn OFF bit 0 for 12db_ch1 */
190 /* v |= 0x00000001;*/ /* turn ON bit 0 for 12db_ch1 */
191 cx18_av_write4(cx, CXADEC_AFE_CTRL, v);
193 /* if(dwEnable && dw3DCombAvailable) { */
194 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
196 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
198 cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
199 state->default_volume = 228 - cx18_av_read(cx, 0x8d4);
200 state->default_volume = ((state->default_volume / 2) + 23) << 9;
203 /* ----------------------------------------------------------------------- */
205 void cx18_av_std_setup(struct cx18 *cx)
207 struct cx18_av_state *state = &cx->av_state;
208 v4l2_std_id std = state->std;
209 int hblank, hactive, burst, vblank, vactive, sc;
210 int vblank656, src_decimation;
211 int luma_lpf, uv_lpf, comb;
212 u32 pll_int, pll_frac, pll_post;
214 /* datasheet startup, step 8d */
215 if (std & ~V4L2_STD_NTSC)
216 cx18_av_write(cx, 0x49f, 0x11);
218 cx18_av_write(cx, 0x49f, 0x14);
220 if (std & V4L2_STD_625_50) {
221 /* FIXME - revisit these for Sliced VBI */
228 src_decimation = 0x21f;
231 if (std & V4L2_STD_PAL) {
235 } else if (std == V4L2_STD_PAL_Nc) {
246 * The following relationships of half line counts should hold:
247 * 525 = vsync + vactive + vblank656
248 * 12 = vblank656 - vblank
250 * vsync: always 6 half-lines of vsync pulses
251 * vactive: half lines of active video
252 * vblank656: half lines, after line 3, of blanked video
253 * vblank: half lines, after line 9, of blanked video
255 * vblank656 starts counting from the falling edge of the first
256 * vsync pulse (start of line 4)
257 * vblank starts counting from the after the 6 vsync pulses and
258 * 6 equalization pulses (start of line 10)
260 * For 525 line systems the driver will extract VBI information
261 * from lines 10 through 21. To avoid the EAV RP code from
262 * toggling at the start of hblank at line 22, where sliced VBI
263 * data from line 21 is stuffed, also treat line 22 as blanked.
265 vblank656 = 38; /* lines 4 through 22 */
266 vblank = 26; /* lines 10 through 22 */
267 vactive = 481; /* lines 23 through 262.5 */
274 src_decimation = 0x21f;
275 if (std == V4L2_STD_PAL_60) {
280 } else if (std == V4L2_STD_PAL_M) {
291 /* DEBUG: Displays configured PLL frequency */
292 pll_int = cx18_av_read(cx, 0x108);
293 pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
294 pll_post = cx18_av_read(cx, 0x109);
295 CX18_DEBUG_INFO("PLL regs = int: %u, frac: %u, post: %u\n",
296 pll_int, pll_frac, pll_post);
301 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
303 CX18_DEBUG_INFO("PLL = %d.%06d MHz\n",
304 pll / 1000000, pll % 1000000);
305 CX18_DEBUG_INFO("PLL/8 = %d.%06d MHz\n",
306 pll / 8000000, (pll / 8) % 1000000);
308 fin = ((u64)src_decimation * pll) >> 12;
309 CX18_DEBUG_INFO("ADC Sampling freq = %d.%06d MHz\n",
310 fin / 1000000, fin % 1000000);
312 fsc = (((u64)sc) * pll) >> 24L;
313 CX18_DEBUG_INFO("Chroma sub-carrier freq = %d.%06d MHz\n",
314 fsc / 1000000, fsc % 1000000);
316 CX18_DEBUG_INFO("hblank %i, hactive %i, "
317 "vblank %i , vactive %i, vblank656 %i, src_dec %i,"
318 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x,"
320 hblank, hactive, vblank, vactive, vblank656,
321 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
324 /* Sets horizontal blanking delay and active lines */
325 cx18_av_write(cx, 0x470, hblank);
326 cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) |
328 cx18_av_write(cx, 0x472, hactive >> 4);
330 /* Sets burst gate delay */
331 cx18_av_write(cx, 0x473, burst);
333 /* Sets vertical blanking delay and active duration */
334 cx18_av_write(cx, 0x474, vblank);
335 cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) |
337 cx18_av_write(cx, 0x476, vactive >> 4);
338 cx18_av_write(cx, 0x477, vblank656);
340 /* Sets src decimation rate */
341 cx18_av_write(cx, 0x478, 0xff & src_decimation);
342 cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8));
344 /* Sets Luma and UV Low pass filters */
345 cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
347 /* Enables comb filters */
348 cx18_av_write(cx, 0x47b, comb);
351 cx18_av_write(cx, 0x47c, sc);
352 cx18_av_write(cx, 0x47d, 0xff & sc >> 8);
353 cx18_av_write(cx, 0x47e, 0xff & sc >> 16);
355 if (std & V4L2_STD_625_50) {
356 state->slicer_line_delay = 1;
357 state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
359 state->slicer_line_delay = 0;
360 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
362 cx18_av_write(cx, 0x47f, state->slicer_line_delay);
365 /* ----------------------------------------------------------------------- */
367 static void input_change(struct cx18 *cx)
369 struct cx18_av_state *state = &cx->av_state;
370 v4l2_std_id std = state->std;
373 /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
374 cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
375 cx18_av_and_or(cx, 0x401, ~0x60, 0);
376 cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
378 if (std & V4L2_STD_525_60) {
379 if (std == V4L2_STD_NTSC_M_JP) {
380 /* Japan uses EIAJ audio standard */
381 cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
382 cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
383 } else if (std == V4L2_STD_NTSC_M_KR) {
384 /* South Korea uses A2 audio standard */
385 cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
386 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
388 /* Others use the BTSC audio standard */
389 cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
390 cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
392 } else if (std & V4L2_STD_PAL) {
393 /* Follow tuner change procedure for PAL */
394 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
395 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
396 } else if (std & V4L2_STD_SECAM) {
397 /* Select autodetect for SECAM */
398 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
399 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
402 v = cx18_av_read(cx, 0x803);
404 /* restart audio decoder microcontroller */
406 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
408 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
412 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
413 enum cx18_av_audio_input aud_input)
415 struct cx18_av_state *state = &cx->av_state;
416 u8 is_composite = (vid_input >= CX18_AV_COMPOSITE1 &&
417 vid_input <= CX18_AV_COMPOSITE8);
421 CX18_DEBUG_INFO("decoder set video input %d, audio input %d\n",
422 vid_input, aud_input);
425 reg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
427 int luma = vid_input & 0xf0;
428 int chroma = vid_input & 0xf00;
430 if ((vid_input & ~0xff0) ||
431 luma < CX18_AV_SVIDEO_LUMA1 ||
432 luma > CX18_AV_SVIDEO_LUMA8 ||
433 chroma < CX18_AV_SVIDEO_CHROMA4 ||
434 chroma > CX18_AV_SVIDEO_CHROMA8) {
435 CX18_ERR("0x%04x is not a valid video input!\n",
439 reg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
440 if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
442 reg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
445 reg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
450 case CX18_AV_AUDIO_SERIAL1:
451 case CX18_AV_AUDIO_SERIAL2:
452 /* do nothing, use serial audio input */
454 case CX18_AV_AUDIO4: reg &= ~0x30; break;
455 case CX18_AV_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
456 case CX18_AV_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
457 case CX18_AV_AUDIO7: reg &= ~0xc0; break;
458 case CX18_AV_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
461 CX18_ERR("0x%04x is not a valid audio input!\n", aud_input);
465 cx18_av_write_expect(cx, 0x103, reg, reg, 0xf7);
466 /* Set INPUT_MODE to Composite (0) or S-Video (1) */
467 cx18_av_and_or(cx, 0x401, ~0x6, is_composite ? 0 : 0x02);
469 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
470 v = cx18_av_read(cx, 0x102);
475 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
476 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
480 cx18_av_write_expect(cx, 0x102, v, v, 0x17);
482 /*cx18_av_and_or4(cx, 0x104, ~0x001b4180, 0x00004180);*/
484 state->vid_input = vid_input;
485 state->aud_input = aud_input;
486 cx18_av_audio_set_path(cx);
491 /* ----------------------------------------------------------------------- */
493 static int set_v4lstd(struct cx18 *cx)
495 struct cx18_av_state *state = &cx->av_state;
496 u8 fmt = 0; /* zero is autodetect */
499 /* First tests should be against specific std */
500 if (state->std == V4L2_STD_NTSC_M_JP) {
502 } else if (state->std == V4L2_STD_NTSC_443) {
504 } else if (state->std == V4L2_STD_PAL_M) {
507 } else if (state->std == V4L2_STD_PAL_N) {
509 } else if (state->std == V4L2_STD_PAL_Nc) {
511 } else if (state->std == V4L2_STD_PAL_60) {
514 /* Then, test against generic ones */
515 if (state->std & V4L2_STD_NTSC)
517 else if (state->std & V4L2_STD_PAL)
519 else if (state->std & V4L2_STD_SECAM)
523 CX18_DEBUG_INFO("changing video std to fmt %i\n", fmt);
525 /* Follow step 9 of section 3.16 in the cx18_av datasheet.
526 Without this PAL may display a vertical ghosting effect.
527 This happens for example with the Yuan MPC622. */
528 if (fmt >= 4 && fmt < 8) {
529 /* Set format to NTSC-M */
530 cx18_av_and_or(cx, 0x400, ~0xf, 1);
532 cx18_av_and_or(cx, 0x47b, ~6, 0);
534 cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
535 cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
536 cx18_av_std_setup(cx);
541 /* ----------------------------------------------------------------------- */
543 static int set_v4lctrl(struct cx18 *cx, struct v4l2_control *ctrl)
546 case V4L2_CID_BRIGHTNESS:
547 if (ctrl->value < 0 || ctrl->value > 255) {
548 CX18_ERR("invalid brightness setting %d\n",
553 cx18_av_write(cx, 0x414, ctrl->value - 128);
556 case V4L2_CID_CONTRAST:
557 if (ctrl->value < 0 || ctrl->value > 127) {
558 CX18_ERR("invalid contrast setting %d\n",
563 cx18_av_write(cx, 0x415, ctrl->value << 1);
566 case V4L2_CID_SATURATION:
567 if (ctrl->value < 0 || ctrl->value > 127) {
568 CX18_ERR("invalid saturation setting %d\n",
573 cx18_av_write(cx, 0x420, ctrl->value << 1);
574 cx18_av_write(cx, 0x421, ctrl->value << 1);
578 if (ctrl->value < -128 || ctrl->value > 127) {
579 CX18_ERR("invalid hue setting %d\n", ctrl->value);
583 cx18_av_write(cx, 0x422, ctrl->value);
586 case V4L2_CID_AUDIO_VOLUME:
587 case V4L2_CID_AUDIO_BASS:
588 case V4L2_CID_AUDIO_TREBLE:
589 case V4L2_CID_AUDIO_BALANCE:
590 case V4L2_CID_AUDIO_MUTE:
591 return cx18_av_audio(cx, VIDIOC_S_CTRL, ctrl);
600 static int get_v4lctrl(struct cx18 *cx, struct v4l2_control *ctrl)
603 case V4L2_CID_BRIGHTNESS:
604 ctrl->value = (s8)cx18_av_read(cx, 0x414) + 128;
606 case V4L2_CID_CONTRAST:
607 ctrl->value = cx18_av_read(cx, 0x415) >> 1;
609 case V4L2_CID_SATURATION:
610 ctrl->value = cx18_av_read(cx, 0x420) >> 1;
613 ctrl->value = (s8)cx18_av_read(cx, 0x422);
615 case V4L2_CID_AUDIO_VOLUME:
616 case V4L2_CID_AUDIO_BASS:
617 case V4L2_CID_AUDIO_TREBLE:
618 case V4L2_CID_AUDIO_BALANCE:
619 case V4L2_CID_AUDIO_MUTE:
620 return cx18_av_audio(cx, VIDIOC_G_CTRL, ctrl);
628 /* ----------------------------------------------------------------------- */
630 static int get_v4lfmt(struct cx18 *cx, struct v4l2_format *fmt)
633 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
634 return cx18_av_vbi(cx, VIDIOC_G_FMT, fmt);
642 static int set_v4lfmt(struct cx18 *cx, struct v4l2_format *fmt)
644 struct cx18_av_state *state = &cx->av_state;
645 struct v4l2_pix_format *pix;
646 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
647 int is_50Hz = !(state->std & V4L2_STD_525_60);
650 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
651 pix = &(fmt->fmt.pix);
653 Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
654 Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
656 Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
657 Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
659 Vlines = pix->height + (is_50Hz ? 4 : 7);
661 if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) ||
662 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
663 CX18_ERR("%dx%d is not a valid size!\n",
664 pix->width, pix->height);
668 HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20);
669 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
672 if (pix->width >= 385)
674 else if (pix->width > 192)
676 else if (pix->width > 96)
681 CX18_DEBUG_INFO("decoder set size %dx%d -> scale %ux%u\n",
682 pix->width, pix->height, HSC, VSC);
685 cx18_av_write(cx, 0x418, HSC & 0xff);
686 cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
687 cx18_av_write(cx, 0x41a, HSC >> 16);
689 cx18_av_write(cx, 0x41c, VSC & 0xff);
690 cx18_av_write(cx, 0x41d, VSC >> 8);
691 /* VS_INTRLACE=1 VFILT=filter */
692 cx18_av_write(cx, 0x41e, 0x8 | filter);
695 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
696 return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt);
698 case V4L2_BUF_TYPE_VBI_CAPTURE:
699 return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt);
708 /* ----------------------------------------------------------------------- */
710 static int valid_av_cmd(unsigned int cmd)
713 /* All commands supported by cx18_av_cmd() */
714 case VIDIOC_INT_DECODE_VBI_LINE:
715 case VIDIOC_INT_AUDIO_CLOCK_FREQ:
716 case VIDIOC_STREAMON:
717 case VIDIOC_STREAMOFF:
718 case VIDIOC_LOG_STATUS:
721 case VIDIOC_QUERYCTRL:
725 case VIDIOC_INT_G_VIDEO_ROUTING:
726 case VIDIOC_INT_S_VIDEO_ROUTING:
727 case VIDIOC_INT_G_AUDIO_ROUTING:
728 case VIDIOC_INT_S_AUDIO_ROUTING:
729 case VIDIOC_S_FREQUENCY:
734 case VIDIOC_INT_RESET:
742 int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg)
744 struct cx18_av_state *state = &cx->av_state;
745 struct v4l2_tuner *vt = arg;
746 struct v4l2_routing *route = arg;
748 if (!state->is_initialized && valid_av_cmd(cmd)) {
749 CX18_DEBUG_INFO("cmd %08x triggered fw load\n", cmd);
750 /* initialize on first use */
751 state->is_initialized = 1;
752 cx18_av_initialize(cx);
756 case VIDIOC_INT_DECODE_VBI_LINE:
757 return cx18_av_vbi(cx, cmd, arg);
759 case VIDIOC_INT_AUDIO_CLOCK_FREQ:
760 return cx18_av_audio(cx, cmd, arg);
762 case VIDIOC_STREAMON:
763 CX18_DEBUG_INFO("enable output\n");
764 cx18_av_write(cx, 0x115, 0x8c);
765 cx18_av_write(cx, 0x116, 0x07);
768 case VIDIOC_STREAMOFF:
769 CX18_DEBUG_INFO("disable output\n");
770 cx18_av_write(cx, 0x115, 0x00);
771 cx18_av_write(cx, 0x116, 0x00);
774 case VIDIOC_LOG_STATUS:
775 log_video_status(cx);
776 log_audio_status(cx);
780 return get_v4lctrl(cx, (struct v4l2_control *)arg);
783 return set_v4lctrl(cx, (struct v4l2_control *)arg);
785 case VIDIOC_QUERYCTRL:
787 struct v4l2_queryctrl *qc = arg;
790 case V4L2_CID_BRIGHTNESS:
791 case V4L2_CID_CONTRAST:
792 case V4L2_CID_SATURATION:
794 return v4l2_ctrl_query_fill_std(qc);
800 case V4L2_CID_AUDIO_VOLUME:
801 return v4l2_ctrl_query_fill(qc, 0, 65535,
802 65535 / 100, state->default_volume);
803 case V4L2_CID_AUDIO_MUTE:
804 case V4L2_CID_AUDIO_BALANCE:
805 case V4L2_CID_AUDIO_BASS:
806 case V4L2_CID_AUDIO_TREBLE:
807 return v4l2_ctrl_query_fill_std(qc);
815 *(v4l2_std_id *)arg = state->std;
819 if (state->radio == 0 && state->std == *(v4l2_std_id *)arg)
822 state->std = *(v4l2_std_id *)arg;
823 return set_v4lstd(cx);
829 case VIDIOC_INT_G_VIDEO_ROUTING:
830 route->input = state->vid_input;
834 case VIDIOC_INT_S_VIDEO_ROUTING:
835 return set_input(cx, route->input, state->aud_input);
837 case VIDIOC_INT_G_AUDIO_ROUTING:
838 route->input = state->aud_input;
842 case VIDIOC_INT_S_AUDIO_ROUTING:
843 return set_input(cx, state->vid_input, route->input);
845 case VIDIOC_S_FREQUENCY:
851 u8 vpres = cx18_av_read(cx, 0x40e) & 0x20;
858 vt->signal = vpres ? 0xffff : 0x0;
861 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
862 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
864 mode = cx18_av_read(cx, 0x804);
866 /* get rxsubchans and audmode */
867 if ((mode & 0xf) == 1)
868 val |= V4L2_TUNER_SUB_STEREO;
870 val |= V4L2_TUNER_SUB_MONO;
872 if (mode == 2 || mode == 4)
873 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
876 val |= V4L2_TUNER_SUB_SAP;
878 vt->rxsubchans = val;
879 vt->audmode = state->audmode;
890 v = cx18_av_read(cx, 0x809);
893 switch (vt->audmode) {
894 case V4L2_TUNER_MODE_MONO:
897 bilingual -> lang1 */
899 case V4L2_TUNER_MODE_STEREO:
900 case V4L2_TUNER_MODE_LANG1:
903 bilingual -> lang1 */
906 case V4L2_TUNER_MODE_LANG1_LANG2:
909 bilingual -> lang1/lang2 */
912 case V4L2_TUNER_MODE_LANG2:
915 bilingual -> lang2 */
921 cx18_av_write_expect(cx, 0x809, v, v, 0xff);
922 state->audmode = vt->audmode;
927 return get_v4lfmt(cx, (struct v4l2_format *)arg);
930 return set_v4lfmt(cx, (struct v4l2_format *)arg);
932 case VIDIOC_INT_RESET:
933 cx18_av_initialize(cx);
943 /* ----------------------------------------------------------------------- */
945 /* ----------------------------------------------------------------------- */
947 static void log_video_status(struct cx18 *cx)
949 static const char *const fmt_strs[] = {
951 "NTSC-M", "NTSC-J", "NTSC-4.43",
952 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
958 struct cx18_av_state *state = &cx->av_state;
959 u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
960 u8 gen_stat1 = cx18_av_read(cx, 0x40d);
961 u8 gen_stat2 = cx18_av_read(cx, 0x40e);
962 int vid_input = state->vid_input;
964 CX18_INFO("Video signal: %spresent\n",
965 (gen_stat2 & 0x20) ? "" : "not ");
966 CX18_INFO("Detected format: %s\n",
967 fmt_strs[gen_stat1 & 0xf]);
969 CX18_INFO("Specified standard: %s\n",
970 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
972 if (vid_input >= CX18_AV_COMPOSITE1 &&
973 vid_input <= CX18_AV_COMPOSITE8) {
974 CX18_INFO("Specified video input: Composite %d\n",
975 vid_input - CX18_AV_COMPOSITE1 + 1);
977 CX18_INFO("Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
978 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
981 CX18_INFO("Specified audioclock freq: %d Hz\n", state->audclk_freq);
984 /* ----------------------------------------------------------------------- */
986 static void log_audio_status(struct cx18 *cx)
988 struct cx18_av_state *state = &cx->av_state;
989 u8 download_ctl = cx18_av_read(cx, 0x803);
990 u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
991 u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
992 u8 audio_config = cx18_av_read(cx, 0x808);
993 u8 pref_mode = cx18_av_read(cx, 0x809);
994 u8 afc0 = cx18_av_read(cx, 0x80b);
995 u8 mute_ctl = cx18_av_read(cx, 0x8d3);
996 int aud_input = state->aud_input;
999 switch (mod_det_stat0) {
1000 case 0x00: p = "mono"; break;
1001 case 0x01: p = "stereo"; break;
1002 case 0x02: p = "dual"; break;
1003 case 0x04: p = "tri"; break;
1004 case 0x10: p = "mono with SAP"; break;
1005 case 0x11: p = "stereo with SAP"; break;
1006 case 0x12: p = "dual with SAP"; break;
1007 case 0x14: p = "tri with SAP"; break;
1008 case 0xfe: p = "forced mode"; break;
1009 default: p = "not defined"; break;
1011 CX18_INFO("Detected audio mode: %s\n", p);
1013 switch (mod_det_stat1) {
1014 case 0x00: p = "not defined"; break;
1015 case 0x01: p = "EIAJ"; break;
1016 case 0x02: p = "A2-M"; break;
1017 case 0x03: p = "A2-BG"; break;
1018 case 0x04: p = "A2-DK1"; break;
1019 case 0x05: p = "A2-DK2"; break;
1020 case 0x06: p = "A2-DK3"; break;
1021 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1022 case 0x08: p = "AM-L"; break;
1023 case 0x09: p = "NICAM-BG"; break;
1024 case 0x0a: p = "NICAM-DK"; break;
1025 case 0x0b: p = "NICAM-I"; break;
1026 case 0x0c: p = "NICAM-L"; break;
1027 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1028 case 0x0e: p = "IF FM Radio"; break;
1029 case 0x0f: p = "BTSC"; break;
1030 case 0x10: p = "detected chrominance"; break;
1031 case 0xfd: p = "unknown audio standard"; break;
1032 case 0xfe: p = "forced audio standard"; break;
1033 case 0xff: p = "no detected audio standard"; break;
1034 default: p = "not defined"; break;
1036 CX18_INFO("Detected audio standard: %s\n", p);
1037 CX18_INFO("Audio muted: %s\n",
1038 (mute_ctl & 0x2) ? "yes" : "no");
1039 CX18_INFO("Audio microcontroller: %s\n",
1040 (download_ctl & 0x10) ? "running" : "stopped");
1042 switch (audio_config >> 4) {
1043 case 0x00: p = "undefined"; break;
1044 case 0x01: p = "BTSC"; break;
1045 case 0x02: p = "EIAJ"; break;
1046 case 0x03: p = "A2-M"; break;
1047 case 0x04: p = "A2-BG"; break;
1048 case 0x05: p = "A2-DK1"; break;
1049 case 0x06: p = "A2-DK2"; break;
1050 case 0x07: p = "A2-DK3"; break;
1051 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1052 case 0x09: p = "AM-L"; break;
1053 case 0x0a: p = "NICAM-BG"; break;
1054 case 0x0b: p = "NICAM-DK"; break;
1055 case 0x0c: p = "NICAM-I"; break;
1056 case 0x0d: p = "NICAM-L"; break;
1057 case 0x0e: p = "FM radio"; break;
1058 case 0x0f: p = "automatic detection"; break;
1059 default: p = "undefined"; break;
1061 CX18_INFO("Configured audio standard: %s\n", p);
1063 if ((audio_config >> 4) < 0xF) {
1064 switch (audio_config & 0xF) {
1065 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1066 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1067 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1068 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1069 case 0x04: p = "STEREO"; break;
1070 case 0x05: p = "DUAL1 (AC)"; break;
1071 case 0x06: p = "DUAL2 (BC)"; break;
1072 case 0x07: p = "DUAL3 (AB)"; break;
1073 default: p = "undefined";
1075 CX18_INFO("Configured audio mode: %s\n", p);
1077 switch (audio_config & 0xF) {
1078 case 0x00: p = "BG"; break;
1079 case 0x01: p = "DK1"; break;
1080 case 0x02: p = "DK2"; break;
1081 case 0x03: p = "DK3"; break;
1082 case 0x04: p = "I"; break;
1083 case 0x05: p = "L"; break;
1084 case 0x06: p = "BTSC"; break;
1085 case 0x07: p = "EIAJ"; break;
1086 case 0x08: p = "A2-M"; break;
1087 case 0x09: p = "FM Radio (4.5 MHz)"; break;
1088 case 0x0a: p = "FM Radio (5.5 MHz)"; break;
1089 case 0x0b: p = "S-Video"; break;
1090 case 0x0f: p = "automatic standard and mode detection"; break;
1091 default: p = "undefined"; break;
1093 CX18_INFO("Configured audio system: %s\n", p);
1097 CX18_INFO("Specified audio input: Tuner (In%d)\n",
1100 CX18_INFO("Specified audio input: External\n");
1102 switch (pref_mode & 0xf) {
1103 case 0: p = "mono/language A"; break;
1104 case 1: p = "language B"; break;
1105 case 2: p = "language C"; break;
1106 case 3: p = "analog fallback"; break;
1107 case 4: p = "stereo"; break;
1108 case 5: p = "language AC"; break;
1109 case 6: p = "language BC"; break;
1110 case 7: p = "language AB"; break;
1111 default: p = "undefined"; break;
1113 CX18_INFO("Preferred audio mode: %s\n", p);
1115 if ((audio_config & 0xf) == 0xf) {
1116 switch ((afc0 >> 3) & 0x1) {
1117 case 0: p = "system DK"; break;
1118 case 1: p = "system L"; break;
1120 CX18_INFO("Selected 65 MHz format: %s\n", p);
1122 switch (afc0 & 0x7) {
1123 case 0: p = "Chroma"; break;
1124 case 1: p = "BTSC"; break;
1125 case 2: p = "EIAJ"; break;
1126 case 3: p = "A2-M"; break;
1127 case 4: p = "autodetect"; break;
1128 default: p = "undefined"; break;
1130 CX18_INFO("Selected 45 MHz format: %s\n", p);