2 * cx18 ADEC audio functions
4 * Derived from cx25840-core.c
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 #include <media/v4l2-chip-ident.h>
26 #include "cx18-driver.h"
28 #include "cx18-cards.h"
30 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
32 u32 reg = 0xc40000 + (addr & ~3);
34 int shift = (addr & 3) * 8;
35 u32 x = cx18_read_reg(cx, reg);
37 x = (x & ~(mask << shift)) | ((u32)value << shift);
38 cx18_write_reg(cx, x, reg);
42 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
44 u32 reg = 0xc40000 + (addr & ~3);
45 int shift = (addr & 3) * 8;
46 u32 x = cx18_read_reg(cx, reg);
48 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
49 cx18_write_reg_expect(cx, x, reg,
50 ((u32)eval << shift), ((u32)mask << shift));
54 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
56 cx18_write_reg(cx, value, 0xc40000 + addr);
61 cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
63 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
67 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
69 cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
73 u8 cx18_av_read(struct cx18 *cx, u16 addr)
75 u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
76 int shift = (addr & 3) * 8;
78 return (x >> shift) & 0xff;
81 u32 cx18_av_read4(struct cx18 *cx, u16 addr)
83 return cx18_read_reg(cx, 0xc40000 + addr);
86 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
89 return cx18_av_write(cx, addr,
90 (cx18_av_read(cx, addr) & and_mask) |
94 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
97 return cx18_av_write4(cx, addr,
98 (cx18_av_read4(cx, addr) & and_mask) |
102 static void cx18_av_initialize(struct cx18 *cx)
104 struct cx18_av_state *state = &cx->av_state;
108 /* Stop 8051 code execution */
109 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
110 0x03000000, 0x13000000);
112 /* initallize the PLL by toggling sleep bit */
113 v = cx18_av_read4(cx, CXADEC_HOST_REG1);
114 /* enable sleep mode - register appears to be read only... */
115 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
116 /* disable sleep mode */
117 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
120 /* initialize DLLs */
121 v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
123 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
125 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
127 v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
129 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
131 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
133 /* set analog bias currents. Set Vreg to 1.20V. */
134 cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
136 v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
137 /* enable TUNE_FIL_RST */
138 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
139 /* disable TUNE_FIL_RST */
140 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
141 v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
143 /* enable 656 output */
144 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
146 /* video output drive strength */
147 cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
150 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
151 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
153 /* set video to auto-detect */
154 /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */
155 /* set the comb notch = 1 */
156 cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
158 /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
159 /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
160 cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
162 /* Set VGA_TRACK_RANGE to 0x20 */
163 cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
167 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
168 * don't clamp raw samples when codes are in use, 1 byte user D-words,
169 * IDID0 has line #, RP code V bit transition on VBLANK, data during
172 cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
174 /* Set the video input.
175 The setting in MODE_CTRL gets lost when we do the above setup */
176 /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
177 /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
179 v = cx18_av_read4(cx, CXADEC_AFE_CTRL);
180 v &= 0xFFFBFFFF; /* turn OFF bit 18 for droop_comp_ch1 */
181 v &= 0xFFFF7FFF; /* turn OFF bit 9 for clamp_sel_ch1 */
182 v &= 0xFFFFFFFE; /* turn OFF bit 0 for 12db_ch1 */
183 /* v |= 0x00000001;*/ /* turn ON bit 0 for 12db_ch1 */
184 cx18_av_write4(cx, CXADEC_AFE_CTRL, v);
186 /* if(dwEnable && dw3DCombAvailable) { */
187 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
189 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
191 cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
192 state->default_volume = 228 - cx18_av_read(cx, 0x8d4);
193 state->default_volume = ((state->default_volume / 2) + 23) << 9;
196 static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
198 struct cx18 *cx = v4l2_get_subdevdata(sd);
200 cx18_av_initialize(cx);
204 static int cx18_av_init_hardware(struct v4l2_subdev *sd, u32 val)
206 struct cx18_av_state *state = to_cx18_av_state(sd);
207 struct cx18 *cx = v4l2_get_subdevdata(sd);
209 if (!state->is_initialized) {
210 /* initialize on first use */
211 state->is_initialized = 1;
212 cx18_av_initialize(cx);
217 void cx18_av_std_setup(struct cx18 *cx)
219 struct cx18_av_state *state = &cx->av_state;
220 v4l2_std_id std = state->std;
221 int hblank, hactive, burst, vblank, vactive, sc;
222 int vblank656, src_decimation;
223 int luma_lpf, uv_lpf, comb;
224 u32 pll_int, pll_frac, pll_post;
226 /* datasheet startup, step 8d */
227 if (std & ~V4L2_STD_NTSC)
228 cx18_av_write(cx, 0x49f, 0x11);
230 cx18_av_write(cx, 0x49f, 0x14);
232 if (std & V4L2_STD_625_50) {
233 /* FIXME - revisit these for Sliced VBI */
240 src_decimation = 0x21f;
243 if (std & V4L2_STD_PAL) {
247 } else if (std == V4L2_STD_PAL_Nc) {
258 * The following relationships of half line counts should hold:
259 * 525 = vsync + vactive + vblank656
260 * 12 = vblank656 - vblank
262 * vsync: always 6 half-lines of vsync pulses
263 * vactive: half lines of active video
264 * vblank656: half lines, after line 3, of blanked video
265 * vblank: half lines, after line 9, of blanked video
267 * vblank656 starts counting from the falling edge of the first
268 * vsync pulse (start of line 4)
269 * vblank starts counting from the after the 6 vsync pulses and
270 * 6 equalization pulses (start of line 10)
272 * For 525 line systems the driver will extract VBI information
273 * from lines 10 through 21. To avoid the EAV RP code from
274 * toggling at the start of hblank at line 22, where sliced VBI
275 * data from line 21 is stuffed, also treat line 22 as blanked.
277 vblank656 = 38; /* lines 4 through 22 */
278 vblank = 26; /* lines 10 through 22 */
279 vactive = 481; /* lines 23 through 262.5 */
286 src_decimation = 0x21f;
287 if (std == V4L2_STD_PAL_60) {
292 } else if (std == V4L2_STD_PAL_M) {
303 /* DEBUG: Displays configured PLL frequency */
304 pll_int = cx18_av_read(cx, 0x108);
305 pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
306 pll_post = cx18_av_read(cx, 0x109);
307 CX18_DEBUG_INFO("PLL regs = int: %u, frac: %u, post: %u\n",
308 pll_int, pll_frac, pll_post);
313 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
315 CX18_DEBUG_INFO("PLL = %d.%06d MHz\n",
316 pll / 1000000, pll % 1000000);
317 CX18_DEBUG_INFO("PLL/8 = %d.%06d MHz\n",
318 pll / 8000000, (pll / 8) % 1000000);
320 fin = ((u64)src_decimation * pll) >> 12;
321 CX18_DEBUG_INFO("ADC Sampling freq = %d.%06d MHz\n",
322 fin / 1000000, fin % 1000000);
324 fsc = (((u64)sc) * pll) >> 24L;
325 CX18_DEBUG_INFO("Chroma sub-carrier freq = %d.%06d MHz\n",
326 fsc / 1000000, fsc % 1000000);
328 CX18_DEBUG_INFO("hblank %i, hactive %i, "
329 "vblank %i , vactive %i, vblank656 %i, src_dec %i,"
330 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x,"
332 hblank, hactive, vblank, vactive, vblank656,
333 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
336 /* Sets horizontal blanking delay and active lines */
337 cx18_av_write(cx, 0x470, hblank);
338 cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) |
340 cx18_av_write(cx, 0x472, hactive >> 4);
342 /* Sets burst gate delay */
343 cx18_av_write(cx, 0x473, burst);
345 /* Sets vertical blanking delay and active duration */
346 cx18_av_write(cx, 0x474, vblank);
347 cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) |
349 cx18_av_write(cx, 0x476, vactive >> 4);
350 cx18_av_write(cx, 0x477, vblank656);
352 /* Sets src decimation rate */
353 cx18_av_write(cx, 0x478, 0xff & src_decimation);
354 cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8));
356 /* Sets Luma and UV Low pass filters */
357 cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
359 /* Enables comb filters */
360 cx18_av_write(cx, 0x47b, comb);
363 cx18_av_write(cx, 0x47c, sc);
364 cx18_av_write(cx, 0x47d, 0xff & sc >> 8);
365 cx18_av_write(cx, 0x47e, 0xff & sc >> 16);
367 if (std & V4L2_STD_625_50) {
368 state->slicer_line_delay = 1;
369 state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
371 state->slicer_line_delay = 0;
372 state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
374 cx18_av_write(cx, 0x47f, state->slicer_line_delay);
377 static int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
378 struct v4l2_decode_vbi_line *vbi_line)
380 struct cx18 *cx = v4l2_get_subdevdata(sd);
381 return cx18_av_vbi(cx, VIDIOC_INT_DECODE_VBI_LINE, vbi_line);
384 static int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
386 struct cx18 *cx = v4l2_get_subdevdata(sd);
387 return cx18_av_audio(cx, VIDIOC_INT_AUDIO_CLOCK_FREQ, &freq);
390 static void input_change(struct cx18 *cx)
392 struct cx18_av_state *state = &cx->av_state;
393 v4l2_std_id std = state->std;
396 /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
397 cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
398 cx18_av_and_or(cx, 0x401, ~0x60, 0);
399 cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
401 if (std & V4L2_STD_525_60) {
402 if (std == V4L2_STD_NTSC_M_JP) {
403 /* Japan uses EIAJ audio standard */
404 cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
405 cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
406 } else if (std == V4L2_STD_NTSC_M_KR) {
407 /* South Korea uses A2 audio standard */
408 cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
409 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
411 /* Others use the BTSC audio standard */
412 cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
413 cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
415 } else if (std & V4L2_STD_PAL) {
416 /* Follow tuner change procedure for PAL */
417 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
418 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
419 } else if (std & V4L2_STD_SECAM) {
420 /* Select autodetect for SECAM */
421 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
422 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
425 v = cx18_av_read(cx, 0x803);
427 /* restart audio decoder microcontroller */
429 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
431 cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
435 static int cx18_av_s_frequency(struct v4l2_subdev *sd,
436 struct v4l2_frequency *freq)
438 struct cx18 *cx = v4l2_get_subdevdata(sd);
443 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
444 enum cx18_av_audio_input aud_input)
446 struct cx18_av_state *state = &cx->av_state;
447 u8 is_composite = (vid_input >= CX18_AV_COMPOSITE1 &&
448 vid_input <= CX18_AV_COMPOSITE8);
452 CX18_DEBUG_INFO("decoder set video input %d, audio input %d\n",
453 vid_input, aud_input);
456 reg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
458 int luma = vid_input & 0xf0;
459 int chroma = vid_input & 0xf00;
461 if ((vid_input & ~0xff0) ||
462 luma < CX18_AV_SVIDEO_LUMA1 ||
463 luma > CX18_AV_SVIDEO_LUMA8 ||
464 chroma < CX18_AV_SVIDEO_CHROMA4 ||
465 chroma > CX18_AV_SVIDEO_CHROMA8) {
466 CX18_ERR("0x%04x is not a valid video input!\n",
470 reg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
471 if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
473 reg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
476 reg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
481 case CX18_AV_AUDIO_SERIAL1:
482 case CX18_AV_AUDIO_SERIAL2:
483 /* do nothing, use serial audio input */
485 case CX18_AV_AUDIO4: reg &= ~0x30; break;
486 case CX18_AV_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
487 case CX18_AV_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
488 case CX18_AV_AUDIO7: reg &= ~0xc0; break;
489 case CX18_AV_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
492 CX18_ERR("0x%04x is not a valid audio input!\n", aud_input);
496 cx18_av_write_expect(cx, 0x103, reg, reg, 0xf7);
497 /* Set INPUT_MODE to Composite (0) or S-Video (1) */
498 cx18_av_and_or(cx, 0x401, ~0x6, is_composite ? 0 : 0x02);
500 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
501 v = cx18_av_read(cx, 0x102);
506 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
507 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
511 cx18_av_write_expect(cx, 0x102, v, v, 0x17);
513 /*cx18_av_and_or4(cx, 0x104, ~0x001b4180, 0x00004180);*/
515 state->vid_input = vid_input;
516 state->aud_input = aud_input;
517 cx18_av_audio_set_path(cx);
522 static int cx18_av_s_video_routing(struct v4l2_subdev *sd,
523 const struct v4l2_routing *route)
525 struct cx18_av_state *state = to_cx18_av_state(sd);
526 struct cx18 *cx = v4l2_get_subdevdata(sd);
527 return set_input(cx, route->input, state->aud_input);
530 static int cx18_av_s_audio_routing(struct v4l2_subdev *sd,
531 const struct v4l2_routing *route)
533 struct cx18_av_state *state = to_cx18_av_state(sd);
534 struct cx18 *cx = v4l2_get_subdevdata(sd);
535 return set_input(cx, state->vid_input, route->input);
538 static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
540 struct cx18_av_state *state = to_cx18_av_state(sd);
541 struct cx18 *cx = v4l2_get_subdevdata(sd);
549 vpres = cx18_av_read(cx, 0x40e) & 0x20;
550 vt->signal = vpres ? 0xffff : 0x0;
553 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
554 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
556 mode = cx18_av_read(cx, 0x804);
558 /* get rxsubchans and audmode */
559 if ((mode & 0xf) == 1)
560 val |= V4L2_TUNER_SUB_STEREO;
562 val |= V4L2_TUNER_SUB_MONO;
564 if (mode == 2 || mode == 4)
565 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
568 val |= V4L2_TUNER_SUB_SAP;
570 vt->rxsubchans = val;
571 vt->audmode = state->audmode;
575 static int cx18_av_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
577 struct cx18_av_state *state = to_cx18_av_state(sd);
578 struct cx18 *cx = v4l2_get_subdevdata(sd);
584 v = cx18_av_read(cx, 0x809);
587 switch (vt->audmode) {
588 case V4L2_TUNER_MODE_MONO:
591 bilingual -> lang1 */
593 case V4L2_TUNER_MODE_STEREO:
594 case V4L2_TUNER_MODE_LANG1:
597 bilingual -> lang1 */
600 case V4L2_TUNER_MODE_LANG1_LANG2:
603 bilingual -> lang1/lang2 */
606 case V4L2_TUNER_MODE_LANG2:
609 bilingual -> lang2 */
615 cx18_av_write_expect(cx, 0x809, v, v, 0xff);
616 state->audmode = vt->audmode;
620 static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
622 struct cx18_av_state *state = to_cx18_av_state(sd);
623 struct cx18 *cx = v4l2_get_subdevdata(sd);
625 u8 fmt = 0; /* zero is autodetect */
628 if (state->radio == 0 && state->std == norm)
634 /* First tests should be against specific std */
635 if (state->std == V4L2_STD_NTSC_M_JP) {
637 } else if (state->std == V4L2_STD_NTSC_443) {
639 } else if (state->std == V4L2_STD_PAL_M) {
642 } else if (state->std == V4L2_STD_PAL_N) {
644 } else if (state->std == V4L2_STD_PAL_Nc) {
646 } else if (state->std == V4L2_STD_PAL_60) {
649 /* Then, test against generic ones */
650 if (state->std & V4L2_STD_NTSC)
652 else if (state->std & V4L2_STD_PAL)
654 else if (state->std & V4L2_STD_SECAM)
658 CX18_DEBUG_INFO("changing video std to fmt %i\n", fmt);
660 /* Follow step 9 of section 3.16 in the cx18_av datasheet.
661 Without this PAL may display a vertical ghosting effect.
662 This happens for example with the Yuan MPC622. */
663 if (fmt >= 4 && fmt < 8) {
664 /* Set format to NTSC-M */
665 cx18_av_and_or(cx, 0x400, ~0xf, 1);
667 cx18_av_and_or(cx, 0x47b, ~6, 0);
669 cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
670 cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
671 cx18_av_std_setup(cx);
676 static int cx18_av_s_radio(struct v4l2_subdev *sd)
678 struct cx18_av_state *state = to_cx18_av_state(sd);
683 static int cx18_av_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
685 struct cx18 *cx = v4l2_get_subdevdata(sd);
688 case V4L2_CID_BRIGHTNESS:
689 if (ctrl->value < 0 || ctrl->value > 255) {
690 CX18_ERR("invalid brightness setting %d\n",
695 cx18_av_write(cx, 0x414, ctrl->value - 128);
698 case V4L2_CID_CONTRAST:
699 if (ctrl->value < 0 || ctrl->value > 127) {
700 CX18_ERR("invalid contrast setting %d\n",
705 cx18_av_write(cx, 0x415, ctrl->value << 1);
708 case V4L2_CID_SATURATION:
709 if (ctrl->value < 0 || ctrl->value > 127) {
710 CX18_ERR("invalid saturation setting %d\n",
715 cx18_av_write(cx, 0x420, ctrl->value << 1);
716 cx18_av_write(cx, 0x421, ctrl->value << 1);
720 if (ctrl->value < -128 || ctrl->value > 127) {
721 CX18_ERR("invalid hue setting %d\n", ctrl->value);
725 cx18_av_write(cx, 0x422, ctrl->value);
728 case V4L2_CID_AUDIO_VOLUME:
729 case V4L2_CID_AUDIO_BASS:
730 case V4L2_CID_AUDIO_TREBLE:
731 case V4L2_CID_AUDIO_BALANCE:
732 case V4L2_CID_AUDIO_MUTE:
733 return cx18_av_audio(cx, VIDIOC_S_CTRL, ctrl);
741 static int cx18_av_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
743 struct cx18 *cx = v4l2_get_subdevdata(sd);
746 case V4L2_CID_BRIGHTNESS:
747 ctrl->value = (s8)cx18_av_read(cx, 0x414) + 128;
749 case V4L2_CID_CONTRAST:
750 ctrl->value = cx18_av_read(cx, 0x415) >> 1;
752 case V4L2_CID_SATURATION:
753 ctrl->value = cx18_av_read(cx, 0x420) >> 1;
756 ctrl->value = (s8)cx18_av_read(cx, 0x422);
758 case V4L2_CID_AUDIO_VOLUME:
759 case V4L2_CID_AUDIO_BASS:
760 case V4L2_CID_AUDIO_TREBLE:
761 case V4L2_CID_AUDIO_BALANCE:
762 case V4L2_CID_AUDIO_MUTE:
763 return cx18_av_audio(cx, VIDIOC_G_CTRL, ctrl);
770 static int cx18_av_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
772 struct cx18_av_state *state = to_cx18_av_state(sd);
775 case V4L2_CID_BRIGHTNESS:
776 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
777 case V4L2_CID_CONTRAST:
778 case V4L2_CID_SATURATION:
779 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
781 return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0);
787 case V4L2_CID_AUDIO_VOLUME:
788 return v4l2_ctrl_query_fill(qc, 0, 65535,
789 65535 / 100, state->default_volume);
790 case V4L2_CID_AUDIO_MUTE:
791 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
792 case V4L2_CID_AUDIO_BALANCE:
793 case V4L2_CID_AUDIO_BASS:
794 case V4L2_CID_AUDIO_TREBLE:
795 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
802 static int cx18_av_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
804 struct cx18 *cx = v4l2_get_subdevdata(sd);
807 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
808 return cx18_av_vbi(cx, VIDIOC_G_FMT, fmt);
815 static int cx18_av_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
817 struct cx18_av_state *state = to_cx18_av_state(sd);
818 struct cx18 *cx = v4l2_get_subdevdata(sd);
820 struct v4l2_pix_format *pix;
821 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
822 int is_50Hz = !(state->std & V4L2_STD_525_60);
825 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
826 pix = &(fmt->fmt.pix);
828 Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
829 Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
831 Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
832 Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
834 Vlines = pix->height + (is_50Hz ? 4 : 7);
836 if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) ||
837 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
838 CX18_ERR("%dx%d is not a valid size!\n",
839 pix->width, pix->height);
843 HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20);
844 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
847 if (pix->width >= 385)
849 else if (pix->width > 192)
851 else if (pix->width > 96)
856 CX18_DEBUG_INFO("decoder set size %dx%d -> scale %ux%u\n",
857 pix->width, pix->height, HSC, VSC);
860 cx18_av_write(cx, 0x418, HSC & 0xff);
861 cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
862 cx18_av_write(cx, 0x41a, HSC >> 16);
864 cx18_av_write(cx, 0x41c, VSC & 0xff);
865 cx18_av_write(cx, 0x41d, VSC >> 8);
866 /* VS_INTRLACE=1 VFILT=filter */
867 cx18_av_write(cx, 0x41e, 0x8 | filter);
870 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
871 return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt);
873 case V4L2_BUF_TYPE_VBI_CAPTURE:
874 return cx18_av_vbi(cx, VIDIOC_S_FMT, fmt);
882 static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable)
884 struct cx18 *cx = v4l2_get_subdevdata(sd);
886 CX18_DEBUG_INFO("%s output\n", enable ? "enable" : "disable");
888 cx18_av_write(cx, 0x115, 0x8c);
889 cx18_av_write(cx, 0x116, 0x07);
891 cx18_av_write(cx, 0x115, 0x00);
892 cx18_av_write(cx, 0x116, 0x00);
897 static void log_video_status(struct cx18 *cx)
899 static const char *const fmt_strs[] = {
901 "NTSC-M", "NTSC-J", "NTSC-4.43",
902 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
908 struct cx18_av_state *state = &cx->av_state;
909 u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
910 u8 gen_stat1 = cx18_av_read(cx, 0x40d);
911 u8 gen_stat2 = cx18_av_read(cx, 0x40e);
912 int vid_input = state->vid_input;
914 CX18_INFO("Video signal: %spresent\n",
915 (gen_stat2 & 0x20) ? "" : "not ");
916 CX18_INFO("Detected format: %s\n",
917 fmt_strs[gen_stat1 & 0xf]);
919 CX18_INFO("Specified standard: %s\n",
920 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
922 if (vid_input >= CX18_AV_COMPOSITE1 &&
923 vid_input <= CX18_AV_COMPOSITE8) {
924 CX18_INFO("Specified video input: Composite %d\n",
925 vid_input - CX18_AV_COMPOSITE1 + 1);
927 CX18_INFO("Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
928 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
931 CX18_INFO("Specified audioclock freq: %d Hz\n", state->audclk_freq);
934 static void log_audio_status(struct cx18 *cx)
936 struct cx18_av_state *state = &cx->av_state;
937 u8 download_ctl = cx18_av_read(cx, 0x803);
938 u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
939 u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
940 u8 audio_config = cx18_av_read(cx, 0x808);
941 u8 pref_mode = cx18_av_read(cx, 0x809);
942 u8 afc0 = cx18_av_read(cx, 0x80b);
943 u8 mute_ctl = cx18_av_read(cx, 0x8d3);
944 int aud_input = state->aud_input;
947 switch (mod_det_stat0) {
948 case 0x00: p = "mono"; break;
949 case 0x01: p = "stereo"; break;
950 case 0x02: p = "dual"; break;
951 case 0x04: p = "tri"; break;
952 case 0x10: p = "mono with SAP"; break;
953 case 0x11: p = "stereo with SAP"; break;
954 case 0x12: p = "dual with SAP"; break;
955 case 0x14: p = "tri with SAP"; break;
956 case 0xfe: p = "forced mode"; break;
957 default: p = "not defined"; break;
959 CX18_INFO("Detected audio mode: %s\n", p);
961 switch (mod_det_stat1) {
962 case 0x00: p = "not defined"; break;
963 case 0x01: p = "EIAJ"; break;
964 case 0x02: p = "A2-M"; break;
965 case 0x03: p = "A2-BG"; break;
966 case 0x04: p = "A2-DK1"; break;
967 case 0x05: p = "A2-DK2"; break;
968 case 0x06: p = "A2-DK3"; break;
969 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
970 case 0x08: p = "AM-L"; break;
971 case 0x09: p = "NICAM-BG"; break;
972 case 0x0a: p = "NICAM-DK"; break;
973 case 0x0b: p = "NICAM-I"; break;
974 case 0x0c: p = "NICAM-L"; break;
975 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
976 case 0x0e: p = "IF FM Radio"; break;
977 case 0x0f: p = "BTSC"; break;
978 case 0x10: p = "detected chrominance"; break;
979 case 0xfd: p = "unknown audio standard"; break;
980 case 0xfe: p = "forced audio standard"; break;
981 case 0xff: p = "no detected audio standard"; break;
982 default: p = "not defined"; break;
984 CX18_INFO("Detected audio standard: %s\n", p);
985 CX18_INFO("Audio muted: %s\n",
986 (mute_ctl & 0x2) ? "yes" : "no");
987 CX18_INFO("Audio microcontroller: %s\n",
988 (download_ctl & 0x10) ? "running" : "stopped");
990 switch (audio_config >> 4) {
991 case 0x00: p = "undefined"; break;
992 case 0x01: p = "BTSC"; break;
993 case 0x02: p = "EIAJ"; break;
994 case 0x03: p = "A2-M"; break;
995 case 0x04: p = "A2-BG"; break;
996 case 0x05: p = "A2-DK1"; break;
997 case 0x06: p = "A2-DK2"; break;
998 case 0x07: p = "A2-DK3"; break;
999 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1000 case 0x09: p = "AM-L"; break;
1001 case 0x0a: p = "NICAM-BG"; break;
1002 case 0x0b: p = "NICAM-DK"; break;
1003 case 0x0c: p = "NICAM-I"; break;
1004 case 0x0d: p = "NICAM-L"; break;
1005 case 0x0e: p = "FM radio"; break;
1006 case 0x0f: p = "automatic detection"; break;
1007 default: p = "undefined"; break;
1009 CX18_INFO("Configured audio standard: %s\n", p);
1011 if ((audio_config >> 4) < 0xF) {
1012 switch (audio_config & 0xF) {
1013 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1014 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1015 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1016 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1017 case 0x04: p = "STEREO"; break;
1018 case 0x05: p = "DUAL1 (AC)"; break;
1019 case 0x06: p = "DUAL2 (BC)"; break;
1020 case 0x07: p = "DUAL3 (AB)"; break;
1021 default: p = "undefined";
1023 CX18_INFO("Configured audio mode: %s\n", p);
1025 switch (audio_config & 0xF) {
1026 case 0x00: p = "BG"; break;
1027 case 0x01: p = "DK1"; break;
1028 case 0x02: p = "DK2"; break;
1029 case 0x03: p = "DK3"; break;
1030 case 0x04: p = "I"; break;
1031 case 0x05: p = "L"; break;
1032 case 0x06: p = "BTSC"; break;
1033 case 0x07: p = "EIAJ"; break;
1034 case 0x08: p = "A2-M"; break;
1035 case 0x09: p = "FM Radio (4.5 MHz)"; break;
1036 case 0x0a: p = "FM Radio (5.5 MHz)"; break;
1037 case 0x0b: p = "S-Video"; break;
1038 case 0x0f: p = "automatic standard and mode detection"; break;
1039 default: p = "undefined"; break;
1041 CX18_INFO("Configured audio system: %s\n", p);
1045 CX18_INFO("Specified audio input: Tuner (In%d)\n",
1048 CX18_INFO("Specified audio input: External\n");
1050 switch (pref_mode & 0xf) {
1051 case 0: p = "mono/language A"; break;
1052 case 1: p = "language B"; break;
1053 case 2: p = "language C"; break;
1054 case 3: p = "analog fallback"; break;
1055 case 4: p = "stereo"; break;
1056 case 5: p = "language AC"; break;
1057 case 6: p = "language BC"; break;
1058 case 7: p = "language AB"; break;
1059 default: p = "undefined"; break;
1061 CX18_INFO("Preferred audio mode: %s\n", p);
1063 if ((audio_config & 0xf) == 0xf) {
1064 switch ((afc0 >> 3) & 0x1) {
1065 case 0: p = "system DK"; break;
1066 case 1: p = "system L"; break;
1068 CX18_INFO("Selected 65 MHz format: %s\n", p);
1070 switch (afc0 & 0x7) {
1071 case 0: p = "Chroma"; break;
1072 case 1: p = "BTSC"; break;
1073 case 2: p = "EIAJ"; break;
1074 case 3: p = "A2-M"; break;
1075 case 4: p = "autodetect"; break;
1076 default: p = "undefined"; break;
1078 CX18_INFO("Selected 45 MHz format: %s\n", p);
1082 static int cx18_av_log_status(struct v4l2_subdev *sd)
1084 struct cx18 *cx = v4l2_get_subdevdata(sd);
1085 log_video_status(cx);
1086 log_audio_status(cx);
1090 static inline int cx18_av_dbg_match(const struct v4l2_dbg_match *match)
1092 return match->type == V4L2_CHIP_MATCH_HOST && match->addr == 1;
1095 static int cx18_av_g_chip_ident(struct v4l2_subdev *sd,
1096 struct v4l2_dbg_chip_ident *chip)
1098 if (cx18_av_dbg_match(&chip->match)) {
1100 * Nothing else is going to claim to be this combination,
1101 * and the real host chip revision will be returned by a host
1102 * match on address 0.
1104 chip->ident = V4L2_IDENT_CX25843;
1105 chip->revision = V4L2_IDENT_CX23418; /* Why not */
1110 #ifdef CONFIG_VIDEO_ADV_DEBUG
1111 static int cx18_av_g_register(struct v4l2_subdev *sd,
1112 struct v4l2_dbg_register *reg)
1114 struct cx18 *cx = v4l2_get_subdevdata(sd);
1116 if (!cx18_av_dbg_match(®->match))
1118 if ((reg->reg & 0x3) != 0)
1120 if (!capable(CAP_SYS_ADMIN))
1123 reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
1127 static int cx18_av_s_register(struct v4l2_subdev *sd,
1128 struct v4l2_dbg_register *reg)
1130 struct cx18 *cx = v4l2_get_subdevdata(sd);
1132 if (!cx18_av_dbg_match(®->match))
1134 if ((reg->reg & 0x3) != 0)
1136 if (!capable(CAP_SYS_ADMIN))
1138 cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
1143 static const struct v4l2_subdev_core_ops cx18_av_general_ops = {
1144 .g_chip_ident = cx18_av_g_chip_ident,
1145 .log_status = cx18_av_log_status,
1146 .init = cx18_av_init_hardware,
1147 .reset = cx18_av_reset,
1148 .queryctrl = cx18_av_queryctrl,
1149 .g_ctrl = cx18_av_g_ctrl,
1150 .s_ctrl = cx18_av_s_ctrl,
1151 #ifdef CONFIG_VIDEO_ADV_DEBUG
1152 .g_register = cx18_av_g_register,
1153 .s_register = cx18_av_s_register,
1157 static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = {
1158 .s_radio = cx18_av_s_radio,
1159 .s_frequency = cx18_av_s_frequency,
1160 .g_tuner = cx18_av_g_tuner,
1161 .s_tuner = cx18_av_s_tuner,
1162 .s_std = cx18_av_s_std,
1165 static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = {
1166 .s_clock_freq = cx18_av_s_clock_freq,
1167 .s_routing = cx18_av_s_audio_routing,
1170 static const struct v4l2_subdev_video_ops cx18_av_video_ops = {
1171 .s_routing = cx18_av_s_video_routing,
1172 .decode_vbi_line = cx18_av_decode_vbi_line,
1173 .s_stream = cx18_av_s_stream,
1174 .g_fmt = cx18_av_g_fmt,
1175 .s_fmt = cx18_av_s_fmt,
1178 static const struct v4l2_subdev_ops cx18_av_ops = {
1179 .core = &cx18_av_general_ops,
1180 .tuner = &cx18_av_tuner_ops,
1181 .audio = &cx18_av_audio_ops,
1182 .video = &cx18_av_video_ops,
1185 int cx18_av_init(struct cx18 *cx)
1187 struct v4l2_subdev *sd = &cx->av_state.sd;
1189 v4l2_subdev_init(sd, &cx18_av_ops);
1190 v4l2_set_subdevdata(sd, cx);
1191 snprintf(sd->name, sizeof(sd->name),
1192 "%s-internal A/V decoder", cx->v4l2_dev.name);
1193 sd->grp_id = CX18_HW_CX23418;
1194 return v4l2_device_register_subdev(&cx->v4l2_dev, sd);
1197 void cx18_av_fini(struct cx18 *cx)
1199 v4l2_device_unregister_subdev(&cx->av_state.sd);