2 Samsung S5H1411 VSB/QAM demodulator driver
4 Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/delay.h>
28 #include "dvb_frontend.h"
31 struct s5h1411_state {
33 struct i2c_adapter *i2c;
35 /* configuration settings */
36 const struct s5h1411_config *config;
38 struct dvb_frontend frontend;
40 fe_modulation_t current_modulation;
42 u32 current_frequency;
50 #define dprintk(arg...) do { \
55 /* Register values to initialise the demod, defaults to VSB */
56 static struct init_tab {
61 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
62 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
63 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
64 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
65 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
66 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
67 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
68 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
69 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
70 { S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, },
71 { S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, },
72 { S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, },
73 { S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, },
74 { S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, },
75 { S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, },
76 { S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, },
77 { S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, },
78 { S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, },
79 { S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, },
80 { S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, },
81 { S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, },
82 { S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, },
83 { S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, },
84 { S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, },
85 { S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, },
86 { S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, },
87 { S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, },
88 { S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, },
89 { S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, },
90 { S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, },
91 { S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, },
92 { S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, },
93 { S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, },
94 { S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, },
95 { S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, },
96 { S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, },
97 { S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, },
98 { S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, },
99 { S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, },
100 { S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, },
101 { S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, },
102 { S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, },
103 { S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, },
104 { S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, },
105 { S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, },
106 { S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, },
107 { S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, },
108 { S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, },
109 { S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, },
110 { S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, },
111 { S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, },
112 { S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, },
113 { S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, },
114 { S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, },
115 { S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, },
116 { S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, },
117 { S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, },
118 { S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, },
119 { S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, },
120 { S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, },
121 { S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, },
122 { S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, },
123 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
124 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
125 { S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
126 { S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
127 { S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
128 { S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
129 { S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
130 { S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
131 { S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
132 { S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
133 { S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
134 { S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
135 { S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
136 { S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
137 { S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
138 { S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
139 { S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
140 { S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
143 /* VSB SNR lookup table */
144 static struct vsb_snr_tab {
188 /* QAM64 SNR lookup table */
189 static struct qam64_snr_tab {
192 } qam64_snr_tab[] = {
261 /* QAM256 SNR lookup table */
262 static struct qam256_snr_tab {
265 } qam256_snr_tab[] = {
340 /* 8 bit registers, 16 bit values */
341 static int s5h1411_writereg(struct s5h1411_state *state,
342 u8 addr, u8 reg, u16 data)
345 u8 buf[] = { reg, data >> 8, data & 0xff };
347 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 };
349 ret = i2c_transfer(state->i2c, &msg, 1);
352 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
353 "ret == %i)\n", __func__, addr, reg, data, ret);
355 return (ret != 1) ? -1 : 0;
358 static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
364 struct i2c_msg msg[] = {
365 { .addr = addr, .flags = 0, .buf = b0, .len = 1 },
366 { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } };
368 ret = i2c_transfer(state->i2c, msg, 2);
371 printk(KERN_ERR "%s: readreg error (ret == %i)\n",
373 return (b1[0] << 8) | b1[1];
376 static int s5h1411_softreset(struct dvb_frontend *fe)
378 struct s5h1411_state *state = fe->demodulator_priv;
380 dprintk("%s()\n", __func__);
382 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
383 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
387 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz)
389 struct s5h1411_state *state = fe->demodulator_priv;
391 dprintk("%s(%d KHz)\n", __func__, KHz);
395 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5);
396 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
397 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
400 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
401 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
402 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
405 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
406 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
407 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
410 dprintk("%s(%d KHz) Invalid, defaulting to 5380\n",
412 /* no break, need to continue */
415 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
416 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
417 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
421 state->if_freq = KHz;
426 static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode)
428 struct s5h1411_state *state = fe->demodulator_priv;
431 dprintk("%s(%d)\n", __func__, mode);
433 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
435 case S5H1411_MPEGTIMING_CONTINOUS_INVERTING_CLOCK:
438 case S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK:
439 dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
442 case S5H1411_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK:
445 case S5H1411_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK:
452 /* Configure MPEG Signal Timing charactistics */
453 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
456 static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion)
458 struct s5h1411_state *state = fe->demodulator_priv;
461 dprintk("%s(%d)\n", __func__, inversion);
462 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
465 val |= 0x1000; /* Inverted */
469 state->inversion = inversion;
470 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
473 static int s5h1411_set_serialmode(struct dvb_frontend *fe, int serial)
475 struct s5h1411_state *state = fe->demodulator_priv;
478 dprintk("%s(%d)\n", __func__, serial);
479 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100;
484 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val);
487 static int s5h1411_enable_modulation(struct dvb_frontend *fe,
490 struct s5h1411_state *state = fe->demodulator_priv;
492 dprintk("%s(0x%08x)\n", __func__, m);
496 dprintk("%s() VSB_8\n", __func__);
497 s5h1411_set_if_freq(fe, state->config->vsb_if);
498 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
499 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
500 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
505 dprintk("%s() QAM_AUTO (64/256)\n", __func__);
506 s5h1411_set_if_freq(fe, state->config->qam_if);
507 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
508 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
509 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
510 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
513 dprintk("%s() Invalid modulation\n", __func__);
517 state->current_modulation = m;
518 s5h1411_softreset(fe);
523 static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
525 struct s5h1411_state *state = fe->demodulator_priv;
527 dprintk("%s(%d)\n", __func__, enable);
530 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
532 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
535 static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable)
537 struct s5h1411_state *state = fe->demodulator_priv;
540 dprintk("%s(%d)\n", __func__, enable);
542 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
545 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
548 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
551 static int s5h1411_sleep(struct dvb_frontend *fe, int enable)
553 struct s5h1411_state *state = fe->demodulator_priv;
555 dprintk("%s(%d)\n", __func__, enable);
558 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
560 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
561 s5h1411_softreset(fe);
567 static int s5h1411_register_reset(struct dvb_frontend *fe)
569 struct s5h1411_state *state = fe->demodulator_priv;
571 dprintk("%s()\n", __func__);
573 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
576 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
577 static int s5h1411_set_frontend(struct dvb_frontend *fe,
578 struct dvb_frontend_parameters *p)
580 struct s5h1411_state *state = fe->demodulator_priv;
582 dprintk("%s(frequency=%d)\n", __func__, p->frequency);
584 s5h1411_softreset(fe);
586 state->current_frequency = p->frequency;
588 s5h1411_enable_modulation(fe, p->u.vsb.modulation);
590 /* Allow the demod to settle */
593 if (fe->ops.tuner_ops.set_params) {
594 if (fe->ops.i2c_gate_ctrl)
595 fe->ops.i2c_gate_ctrl(fe, 1);
597 fe->ops.tuner_ops.set_params(fe, p);
599 if (fe->ops.i2c_gate_ctrl)
600 fe->ops.i2c_gate_ctrl(fe, 0);
606 /* Reset the demod hardware and reset all of the configuration registers
607 to a default state. */
608 static int s5h1411_init(struct dvb_frontend *fe)
610 struct s5h1411_state *state = fe->demodulator_priv;
613 dprintk("%s()\n", __func__);
615 s5h1411_sleep(fe, 0);
616 s5h1411_register_reset(fe);
618 for (i = 0; i < ARRAY_SIZE(init_tab); i++)
619 s5h1411_writereg(state, init_tab[i].addr,
623 /* The datasheet says that after initialisation, VSB is default */
624 state->current_modulation = VSB_8;
626 if (state->config->output_mode == S5H1411_SERIAL_OUTPUT)
628 s5h1411_set_serialmode(fe, 1);
631 s5h1411_set_serialmode(fe, 0);
633 s5h1411_set_spectralinversion(fe, state->config->inversion);
634 s5h1411_set_if_freq(fe, state->config->vsb_if);
635 s5h1411_set_gpio(fe, state->config->gpio);
636 s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing);
637 s5h1411_softreset(fe);
639 /* Note: Leaving the I2C gate closed. */
640 s5h1411_i2c_gate_ctrl(fe, 0);
645 static int s5h1411_read_status(struct dvb_frontend *fe, fe_status_t *status)
647 struct s5h1411_state *state = fe->demodulator_priv;
649 u32 tuner_status = 0;
653 /* Register F2 bit 15 = Master Lock, removed */
655 switch (state->current_modulation) {
658 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0);
659 if (reg & 0x10) /* QAM FEC Lock */
660 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
661 if (reg & 0x100) /* QAM EQ Lock */
662 *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
666 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2);
667 if (reg & 0x1000) /* FEC Lock */
668 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
669 if (reg & 0x2000) /* EQ Lock */
670 *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
672 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53);
673 if (reg & 0x1) /* AFC Lock */
674 *status |= FE_HAS_SIGNAL;
681 switch (state->config->status_mode) {
682 case S5H1411_DEMODLOCKING:
683 if (*status & FE_HAS_VITERBI)
684 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
686 case S5H1411_TUNERLOCKING:
687 /* Get the tuner status */
688 if (fe->ops.tuner_ops.get_status) {
689 if (fe->ops.i2c_gate_ctrl)
690 fe->ops.i2c_gate_ctrl(fe, 1);
692 fe->ops.tuner_ops.get_status(fe, &tuner_status);
694 if (fe->ops.i2c_gate_ctrl)
695 fe->ops.i2c_gate_ctrl(fe, 0);
698 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
702 dprintk("%s() status 0x%08x\n", __func__, *status);
707 static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
709 int i, ret = -EINVAL;
710 dprintk("%s()\n", __func__);
712 for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
713 if (v < qam256_snr_tab[i].val) {
714 *snr = qam256_snr_tab[i].data;
722 static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
724 int i, ret = -EINVAL;
725 dprintk("%s()\n", __func__);
727 for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
728 if (v < qam64_snr_tab[i].val) {
729 *snr = qam64_snr_tab[i].data;
737 static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
739 int i, ret = -EINVAL;
740 dprintk("%s()\n", __func__);
742 for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
743 if (v > vsb_snr_tab[i].val) {
744 *snr = vsb_snr_tab[i].data;
749 dprintk("%s() snr=%d\n", __func__, *snr);
753 static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
755 struct s5h1411_state *state = fe->demodulator_priv;
757 dprintk("%s()\n", __func__);
759 switch (state->current_modulation) {
761 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
762 return s5h1411_qam64_lookup_snr(fe, snr, reg);
764 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
765 return s5h1411_qam256_lookup_snr(fe, snr, reg);
767 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR,
769 return s5h1411_vsb_lookup_snr(fe, snr, reg);
777 static int s5h1411_read_signal_strength(struct dvb_frontend *fe,
778 u16 *signal_strength)
780 return s5h1411_read_snr(fe, signal_strength);
783 static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
785 struct s5h1411_state *state = fe->demodulator_priv;
787 *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
792 static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
794 return s5h1411_read_ucblocks(fe, ber);
797 static int s5h1411_get_frontend(struct dvb_frontend *fe,
798 struct dvb_frontend_parameters *p)
800 struct s5h1411_state *state = fe->demodulator_priv;
802 p->frequency = state->current_frequency;
803 p->u.vsb.modulation = state->current_modulation;
808 static int s5h1411_get_tune_settings(struct dvb_frontend *fe,
809 struct dvb_frontend_tune_settings *tune)
811 tune->min_delay_ms = 1000;
815 static void s5h1411_release(struct dvb_frontend *fe)
817 struct s5h1411_state *state = fe->demodulator_priv;
821 static struct dvb_frontend_ops s5h1411_ops;
823 struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config,
824 struct i2c_adapter *i2c)
826 struct s5h1411_state *state = NULL;
829 /* allocate memory for the internal state */
830 state = kmalloc(sizeof(struct s5h1411_state), GFP_KERNEL);
834 /* setup the state */
835 state->config = config;
837 state->current_modulation = VSB_8;
838 state->inversion = state->config->inversion;
840 /* check if the demod exists */
841 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05);
845 /* create dvb_frontend */
846 memcpy(&state->frontend.ops, &s5h1411_ops,
847 sizeof(struct dvb_frontend_ops));
849 state->frontend.demodulator_priv = state;
851 if (s5h1411_init(&state->frontend) != 0) {
852 printk(KERN_ERR "%s: Failed to initialize correctly\n",
857 /* Note: Leaving the I2C gate open here. */
858 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
860 return &state->frontend;
866 EXPORT_SYMBOL(s5h1411_attach);
868 static struct dvb_frontend_ops s5h1411_ops = {
871 .name = "Samsung S5H1411 QAM/8VSB Frontend",
873 .frequency_min = 54000000,
874 .frequency_max = 858000000,
875 .frequency_stepsize = 62500,
876 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
879 .init = s5h1411_init,
880 .i2c_gate_ctrl = s5h1411_i2c_gate_ctrl,
881 .set_frontend = s5h1411_set_frontend,
882 .get_frontend = s5h1411_get_frontend,
883 .get_tune_settings = s5h1411_get_tune_settings,
884 .read_status = s5h1411_read_status,
885 .read_ber = s5h1411_read_ber,
886 .read_signal_strength = s5h1411_read_signal_strength,
887 .read_snr = s5h1411_read_snr,
888 .read_ucblocks = s5h1411_read_ucblocks,
889 .release = s5h1411_release,
892 module_param(debug, int, 0644);
893 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
895 MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver");
896 MODULE_AUTHOR("Steven Toth");
897 MODULE_LICENSE("GPL");